2 * CRIS emulation for qemu: main translation routines.
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 * The condition code translation is in need of attention.
26 #include "qemu/osdep.h"
28 #include "disas/disas.h"
30 #include "exec/helper-proto.h"
32 #include "exec/cpu_ldst.h"
33 #include "crisv32-decode.h"
35 #include "exec/helper-gen.h"
37 #include "trace-tcg.h"
43 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
45 # define LOG_DIS(...) do { } while (0)
49 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
50 #define BUG_ON(x) ({if (x) BUG();})
54 /* Used by the decoder. */
55 #define EXTRACT_FIELD(src, start, end) \
56 (((src) >> start) & ((1 << (end - start + 1)) - 1))
58 #define CC_MASK_NZ 0xc
59 #define CC_MASK_NZV 0xe
60 #define CC_MASK_NZVC 0xf
61 #define CC_MASK_RNZV 0x10e
63 static TCGv_env cpu_env
;
64 static TCGv cpu_R
[16];
65 static TCGv cpu_PR
[16];
69 static TCGv cc_result
;
74 static TCGv env_btaken
;
75 static TCGv env_btarget
;
78 #include "exec/gen-icount.h"
80 /* This is the state at translation time. */
81 typedef struct DisasContext
{
86 unsigned int (*decoder
)(CPUCRISState
*env
, struct DisasContext
*dc
);
91 unsigned int zsize
, zzsize
;
105 int cc_size_uptodate
; /* -1 invalid or last written value. */
107 int cc_x_uptodate
; /* 1 - ccs, 2 - known | X_FLAG. 0 not up-to-date. */
108 int flags_uptodate
; /* Whether or not $ccs is up-to-date. */
109 int flagx_known
; /* Whether or not flags_x has the x flag known at
113 int clear_x
; /* Clear x after this insn? */
114 int clear_prefix
; /* Clear prefix after this insn? */
115 int clear_locked_irq
; /* Clear the irq lockout. */
116 int cpustate_changed
;
117 unsigned int tb_flags
; /* tb dependent flags. */
122 #define JMP_DIRECT_CC 2
123 #define JMP_INDIRECT 3
124 int jmp
; /* 0=nojmp, 1=direct, 2=indirect. */
129 struct TranslationBlock
*tb
;
130 int singlestep_enabled
;
133 static void gen_BUG(DisasContext
*dc
, const char *file
, int line
)
135 fprintf(stderr
, "BUG: pc=%x %s %d\n", dc
->pc
, file
, line
);
136 if (qemu_log_separate()) {
137 qemu_log("BUG: pc=%x %s %d\n", dc
->pc
, file
, line
);
139 cpu_abort(CPU(dc
->cpu
), "%s:%d\n", file
, line
);
142 static const char *regnames
[] =
144 "$r0", "$r1", "$r2", "$r3",
145 "$r4", "$r5", "$r6", "$r7",
146 "$r8", "$r9", "$r10", "$r11",
147 "$r12", "$r13", "$sp", "$acr",
149 static const char *pregnames
[] =
151 "$bz", "$vr", "$pid", "$srs",
152 "$wz", "$exs", "$eda", "$mof",
153 "$dz", "$ebp", "$erp", "$srp",
154 "$nrp", "$ccs", "$usp", "$spc",
157 /* We need this table to handle preg-moves with implicit width. */
158 static int preg_sizes
[] = {
169 #define t_gen_mov_TN_env(tn, member) \
170 tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member))
171 #define t_gen_mov_env_TN(member, tn) \
172 tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
174 static inline void t_gen_mov_TN_preg(TCGv tn
, int r
)
176 assert(r
>= 0 && r
<= 15);
177 if (r
== PR_BZ
|| r
== PR_WZ
|| r
== PR_DZ
) {
178 tcg_gen_mov_tl(tn
, tcg_const_tl(0));
179 } else if (r
== PR_VR
) {
180 tcg_gen_mov_tl(tn
, tcg_const_tl(32));
182 tcg_gen_mov_tl(tn
, cpu_PR
[r
]);
185 static inline void t_gen_mov_preg_TN(DisasContext
*dc
, int r
, TCGv tn
)
187 assert(r
>= 0 && r
<= 15);
188 if (r
== PR_BZ
|| r
== PR_WZ
|| r
== PR_DZ
) {
190 } else if (r
== PR_SRS
) {
191 tcg_gen_andi_tl(cpu_PR
[r
], tn
, 3);
194 gen_helper_tlb_flush_pid(cpu_env
, tn
);
196 if (dc
->tb_flags
& S_FLAG
&& r
== PR_SPC
) {
197 gen_helper_spc_write(cpu_env
, tn
);
198 } else if (r
== PR_CCS
) {
199 dc
->cpustate_changed
= 1;
201 tcg_gen_mov_tl(cpu_PR
[r
], tn
);
205 /* Sign extend at translation time. */
206 static int sign_extend(unsigned int val
, unsigned int width
)
218 static int cris_fetch(CPUCRISState
*env
, DisasContext
*dc
, uint32_t addr
,
219 unsigned int size
, unsigned int sign
)
226 r
= cpu_ldl_code(env
, addr
);
232 r
= cpu_ldsw_code(env
, addr
);
234 r
= cpu_lduw_code(env
, addr
);
241 r
= cpu_ldsb_code(env
, addr
);
243 r
= cpu_ldub_code(env
, addr
);
248 cpu_abort(CPU(dc
->cpu
), "Invalid fetch size %d\n", size
);
254 static void cris_lock_irq(DisasContext
*dc
)
256 dc
->clear_locked_irq
= 0;
257 t_gen_mov_env_TN(locked_irq
, tcg_const_tl(1));
260 static inline void t_gen_raise_exception(uint32_t index
)
262 TCGv_i32 tmp
= tcg_const_i32(index
);
263 gen_helper_raise_exception(cpu_env
, tmp
);
264 tcg_temp_free_i32(tmp
);
267 static void t_gen_lsl(TCGv d
, TCGv a
, TCGv b
)
272 t_31
= tcg_const_tl(31);
273 tcg_gen_shl_tl(d
, a
, b
);
275 tcg_gen_sub_tl(t0
, t_31
, b
);
276 tcg_gen_sar_tl(t0
, t0
, t_31
);
277 tcg_gen_and_tl(t0
, t0
, d
);
278 tcg_gen_xor_tl(d
, d
, t0
);
283 static void t_gen_lsr(TCGv d
, TCGv a
, TCGv b
)
288 t_31
= tcg_temp_new();
289 tcg_gen_shr_tl(d
, a
, b
);
291 tcg_gen_movi_tl(t_31
, 31);
292 tcg_gen_sub_tl(t0
, t_31
, b
);
293 tcg_gen_sar_tl(t0
, t0
, t_31
);
294 tcg_gen_and_tl(t0
, t0
, d
);
295 tcg_gen_xor_tl(d
, d
, t0
);
300 static void t_gen_asr(TCGv d
, TCGv a
, TCGv b
)
305 t_31
= tcg_temp_new();
306 tcg_gen_sar_tl(d
, a
, b
);
308 tcg_gen_movi_tl(t_31
, 31);
309 tcg_gen_sub_tl(t0
, t_31
, b
);
310 tcg_gen_sar_tl(t0
, t0
, t_31
);
311 tcg_gen_or_tl(d
, d
, t0
);
316 static void t_gen_cris_dstep(TCGv d
, TCGv a
, TCGv b
)
318 TCGv t
= tcg_temp_new();
325 tcg_gen_shli_tl(d
, a
, 1);
326 tcg_gen_sub_tl(t
, d
, b
);
327 tcg_gen_movcond_tl(TCG_COND_GEU
, d
, d
, b
, t
, d
);
331 static void t_gen_cris_mstep(TCGv d
, TCGv a
, TCGv b
, TCGv ccs
)
341 tcg_gen_shli_tl(d
, a
, 1);
342 tcg_gen_shli_tl(t
, ccs
, 31 - 3);
343 tcg_gen_sari_tl(t
, t
, 31);
344 tcg_gen_and_tl(t
, t
, b
);
345 tcg_gen_add_tl(d
, d
, t
);
349 /* Extended arithmetics on CRIS. */
350 static inline void t_gen_add_flag(TCGv d
, int flag
)
355 t_gen_mov_TN_preg(c
, PR_CCS
);
356 /* Propagate carry into d. */
357 tcg_gen_andi_tl(c
, c
, 1 << flag
);
359 tcg_gen_shri_tl(c
, c
, flag
);
361 tcg_gen_add_tl(d
, d
, c
);
365 static inline void t_gen_addx_carry(DisasContext
*dc
, TCGv d
)
367 if (dc
->flagx_known
) {
372 t_gen_mov_TN_preg(c
, PR_CCS
);
373 /* C flag is already at bit 0. */
374 tcg_gen_andi_tl(c
, c
, C_FLAG
);
375 tcg_gen_add_tl(d
, d
, c
);
383 t_gen_mov_TN_preg(x
, PR_CCS
);
384 tcg_gen_mov_tl(c
, x
);
386 /* Propagate carry into d if X is set. Branch free. */
387 tcg_gen_andi_tl(c
, c
, C_FLAG
);
388 tcg_gen_andi_tl(x
, x
, X_FLAG
);
389 tcg_gen_shri_tl(x
, x
, 4);
391 tcg_gen_and_tl(x
, x
, c
);
392 tcg_gen_add_tl(d
, d
, x
);
398 static inline void t_gen_subx_carry(DisasContext
*dc
, TCGv d
)
400 if (dc
->flagx_known
) {
405 t_gen_mov_TN_preg(c
, PR_CCS
);
406 /* C flag is already at bit 0. */
407 tcg_gen_andi_tl(c
, c
, C_FLAG
);
408 tcg_gen_sub_tl(d
, d
, c
);
416 t_gen_mov_TN_preg(x
, PR_CCS
);
417 tcg_gen_mov_tl(c
, x
);
419 /* Propagate carry into d if X is set. Branch free. */
420 tcg_gen_andi_tl(c
, c
, C_FLAG
);
421 tcg_gen_andi_tl(x
, x
, X_FLAG
);
422 tcg_gen_shri_tl(x
, x
, 4);
424 tcg_gen_and_tl(x
, x
, c
);
425 tcg_gen_sub_tl(d
, d
, x
);
431 /* Swap the two bytes within each half word of the s operand.
432 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
433 static inline void t_gen_swapb(TCGv d
, TCGv s
)
438 org_s
= tcg_temp_new();
440 /* d and s may refer to the same object. */
441 tcg_gen_mov_tl(org_s
, s
);
442 tcg_gen_shli_tl(t
, org_s
, 8);
443 tcg_gen_andi_tl(d
, t
, 0xff00ff00);
444 tcg_gen_shri_tl(t
, org_s
, 8);
445 tcg_gen_andi_tl(t
, t
, 0x00ff00ff);
446 tcg_gen_or_tl(d
, d
, t
);
448 tcg_temp_free(org_s
);
451 /* Swap the halfwords of the s operand. */
452 static inline void t_gen_swapw(TCGv d
, TCGv s
)
455 /* d and s refer the same object. */
457 tcg_gen_mov_tl(t
, s
);
458 tcg_gen_shli_tl(d
, t
, 16);
459 tcg_gen_shri_tl(t
, t
, 16);
460 tcg_gen_or_tl(d
, d
, t
);
464 /* Reverse the within each byte.
465 T0 = (((T0 << 7) & 0x80808080) |
466 ((T0 << 5) & 0x40404040) |
467 ((T0 << 3) & 0x20202020) |
468 ((T0 << 1) & 0x10101010) |
469 ((T0 >> 1) & 0x08080808) |
470 ((T0 >> 3) & 0x04040404) |
471 ((T0 >> 5) & 0x02020202) |
472 ((T0 >> 7) & 0x01010101));
474 static inline void t_gen_swapr(TCGv d
, TCGv s
)
477 int shift
; /* LSL when positive, LSR when negative. */
492 /* d and s refer the same object. */
494 org_s
= tcg_temp_new();
495 tcg_gen_mov_tl(org_s
, s
);
497 tcg_gen_shli_tl(t
, org_s
, bitrev
[0].shift
);
498 tcg_gen_andi_tl(d
, t
, bitrev
[0].mask
);
499 for (i
= 1; i
< ARRAY_SIZE(bitrev
); i
++) {
500 if (bitrev
[i
].shift
>= 0) {
501 tcg_gen_shli_tl(t
, org_s
, bitrev
[i
].shift
);
503 tcg_gen_shri_tl(t
, org_s
, -bitrev
[i
].shift
);
505 tcg_gen_andi_tl(t
, t
, bitrev
[i
].mask
);
506 tcg_gen_or_tl(d
, d
, t
);
509 tcg_temp_free(org_s
);
512 static void t_gen_cc_jmp(TCGv pc_true
, TCGv pc_false
)
514 TCGLabel
*l1
= gen_new_label();
516 /* Conditional jmp. */
517 tcg_gen_mov_tl(env_pc
, pc_false
);
518 tcg_gen_brcondi_tl(TCG_COND_EQ
, env_btaken
, 0, l1
);
519 tcg_gen_mov_tl(env_pc
, pc_true
);
523 static inline bool use_goto_tb(DisasContext
*dc
, target_ulong dest
)
525 #ifndef CONFIG_USER_ONLY
526 return (dc
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
527 (dc
->ppc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
533 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
535 if (use_goto_tb(dc
, dest
)) {
537 tcg_gen_movi_tl(env_pc
, dest
);
538 tcg_gen_exit_tb((uintptr_t)dc
->tb
+ n
);
540 tcg_gen_movi_tl(env_pc
, dest
);
545 static inline void cris_clear_x_flag(DisasContext
*dc
)
547 if (dc
->flagx_known
&& dc
->flags_x
) {
548 dc
->flags_uptodate
= 0;
555 static void cris_flush_cc_state(DisasContext
*dc
)
557 if (dc
->cc_size_uptodate
!= dc
->cc_size
) {
558 tcg_gen_movi_tl(cc_size
, dc
->cc_size
);
559 dc
->cc_size_uptodate
= dc
->cc_size
;
561 tcg_gen_movi_tl(cc_op
, dc
->cc_op
);
562 tcg_gen_movi_tl(cc_mask
, dc
->cc_mask
);
565 static void cris_evaluate_flags(DisasContext
*dc
)
567 if (dc
->flags_uptodate
) {
571 cris_flush_cc_state(dc
);
575 gen_helper_evaluate_flags_mcp(cpu_PR
[PR_CCS
], cpu_env
,
576 cpu_PR
[PR_CCS
], cc_src
,
580 gen_helper_evaluate_flags_muls(cpu_PR
[PR_CCS
], cpu_env
,
581 cpu_PR
[PR_CCS
], cc_result
,
585 gen_helper_evaluate_flags_mulu(cpu_PR
[PR_CCS
], cpu_env
,
586 cpu_PR
[PR_CCS
], cc_result
,
596 switch (dc
->cc_size
) {
598 gen_helper_evaluate_flags_move_4(cpu_PR
[PR_CCS
],
599 cpu_env
, cpu_PR
[PR_CCS
], cc_result
);
602 gen_helper_evaluate_flags_move_2(cpu_PR
[PR_CCS
],
603 cpu_env
, cpu_PR
[PR_CCS
], cc_result
);
606 gen_helper_evaluate_flags(cpu_env
);
615 if (dc
->cc_size
== 4) {
616 gen_helper_evaluate_flags_sub_4(cpu_PR
[PR_CCS
], cpu_env
,
617 cpu_PR
[PR_CCS
], cc_src
, cc_dest
, cc_result
);
619 gen_helper_evaluate_flags(cpu_env
);
624 switch (dc
->cc_size
) {
626 gen_helper_evaluate_flags_alu_4(cpu_PR
[PR_CCS
], cpu_env
,
627 cpu_PR
[PR_CCS
], cc_src
, cc_dest
, cc_result
);
630 gen_helper_evaluate_flags(cpu_env
);
636 if (dc
->flagx_known
) {
638 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], X_FLAG
);
639 } else if (dc
->cc_op
== CC_OP_FLAGS
) {
640 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~X_FLAG
);
643 dc
->flags_uptodate
= 1;
646 static void cris_cc_mask(DisasContext
*dc
, unsigned int mask
)
655 /* Check if we need to evaluate the condition codes due to
657 ovl
= (dc
->cc_mask
^ mask
) & ~mask
;
659 /* TODO: optimize this case. It trigs all the time. */
660 cris_evaluate_flags(dc
);
666 static void cris_update_cc_op(DisasContext
*dc
, int op
, int size
)
670 dc
->flags_uptodate
= 0;
673 static inline void cris_update_cc_x(DisasContext
*dc
)
675 /* Save the x flag state at the time of the cc snapshot. */
676 if (dc
->flagx_known
) {
677 if (dc
->cc_x_uptodate
== (2 | dc
->flags_x
)) {
680 tcg_gen_movi_tl(cc_x
, dc
->flags_x
);
681 dc
->cc_x_uptodate
= 2 | dc
->flags_x
;
683 tcg_gen_andi_tl(cc_x
, cpu_PR
[PR_CCS
], X_FLAG
);
684 dc
->cc_x_uptodate
= 1;
688 /* Update cc prior to executing ALU op. Needs source operands untouched. */
689 static void cris_pre_alu_update_cc(DisasContext
*dc
, int op
,
690 TCGv dst
, TCGv src
, int size
)
693 cris_update_cc_op(dc
, op
, size
);
694 tcg_gen_mov_tl(cc_src
, src
);
702 && op
!= CC_OP_LSL
) {
703 tcg_gen_mov_tl(cc_dest
, dst
);
706 cris_update_cc_x(dc
);
710 /* Update cc after executing ALU op. needs the result. */
711 static inline void cris_update_result(DisasContext
*dc
, TCGv res
)
714 tcg_gen_mov_tl(cc_result
, res
);
718 /* Returns one if the write back stage should execute. */
719 static void cris_alu_op_exec(DisasContext
*dc
, int op
,
720 TCGv dst
, TCGv a
, TCGv b
, int size
)
722 /* Emit the ALU insns. */
725 tcg_gen_add_tl(dst
, a
, b
);
726 /* Extended arithmetics. */
727 t_gen_addx_carry(dc
, dst
);
730 tcg_gen_add_tl(dst
, a
, b
);
731 t_gen_add_flag(dst
, 0); /* C_FLAG. */
734 tcg_gen_add_tl(dst
, a
, b
);
735 t_gen_add_flag(dst
, 8); /* R_FLAG. */
738 tcg_gen_sub_tl(dst
, a
, b
);
739 /* Extended arithmetics. */
740 t_gen_subx_carry(dc
, dst
);
743 tcg_gen_mov_tl(dst
, b
);
746 tcg_gen_or_tl(dst
, a
, b
);
749 tcg_gen_and_tl(dst
, a
, b
);
752 tcg_gen_xor_tl(dst
, a
, b
);
755 t_gen_lsl(dst
, a
, b
);
758 t_gen_lsr(dst
, a
, b
);
761 t_gen_asr(dst
, a
, b
);
764 tcg_gen_neg_tl(dst
, b
);
765 /* Extended arithmetics. */
766 t_gen_subx_carry(dc
, dst
);
769 gen_helper_lz(dst
, b
);
772 tcg_gen_muls2_tl(dst
, cpu_PR
[PR_MOF
], a
, b
);
775 tcg_gen_mulu2_tl(dst
, cpu_PR
[PR_MOF
], a
, b
);
778 t_gen_cris_dstep(dst
, a
, b
);
781 t_gen_cris_mstep(dst
, a
, b
, cpu_PR
[PR_CCS
]);
784 tcg_gen_movcond_tl(TCG_COND_LEU
, dst
, a
, b
, a
, b
);
787 tcg_gen_sub_tl(dst
, a
, b
);
788 /* Extended arithmetics. */
789 t_gen_subx_carry(dc
, dst
);
792 qemu_log_mask(LOG_GUEST_ERROR
, "illegal ALU op.\n");
798 tcg_gen_andi_tl(dst
, dst
, 0xff);
799 } else if (size
== 2) {
800 tcg_gen_andi_tl(dst
, dst
, 0xffff);
804 static void cris_alu(DisasContext
*dc
, int op
,
805 TCGv d
, TCGv op_a
, TCGv op_b
, int size
)
812 if (op
== CC_OP_CMP
) {
813 tmp
= tcg_temp_new();
815 } else if (size
== 4) {
819 tmp
= tcg_temp_new();
823 cris_pre_alu_update_cc(dc
, op
, op_a
, op_b
, size
);
824 cris_alu_op_exec(dc
, op
, tmp
, op_a
, op_b
, size
);
825 cris_update_result(dc
, tmp
);
830 tcg_gen_andi_tl(d
, d
, ~0xff);
832 tcg_gen_andi_tl(d
, d
, ~0xffff);
834 tcg_gen_or_tl(d
, d
, tmp
);
836 if (!TCGV_EQUAL(tmp
, d
)) {
841 static int arith_cc(DisasContext
*dc
)
845 case CC_OP_ADDC
: return 1;
846 case CC_OP_ADD
: return 1;
847 case CC_OP_SUB
: return 1;
848 case CC_OP_DSTEP
: return 1;
849 case CC_OP_LSL
: return 1;
850 case CC_OP_LSR
: return 1;
851 case CC_OP_ASR
: return 1;
852 case CC_OP_CMP
: return 1;
853 case CC_OP_NEG
: return 1;
854 case CC_OP_OR
: return 1;
855 case CC_OP_AND
: return 1;
856 case CC_OP_XOR
: return 1;
857 case CC_OP_MULU
: return 1;
858 case CC_OP_MULS
: return 1;
866 static void gen_tst_cc (DisasContext
*dc
, TCGv cc
, int cond
)
868 int arith_opt
, move_opt
;
870 /* TODO: optimize more condition codes. */
873 * If the flags are live, we've gotta look into the bits of CCS.
874 * Otherwise, if we just did an arithmetic operation we try to
875 * evaluate the condition code faster.
877 * When this function is done, T0 should be non-zero if the condition
880 arith_opt
= arith_cc(dc
) && !dc
->flags_uptodate
;
881 move_opt
= (dc
->cc_op
== CC_OP_MOVE
);
884 if ((arith_opt
|| move_opt
)
885 && dc
->cc_x_uptodate
!= (2 | X_FLAG
)) {
886 tcg_gen_setcond_tl(TCG_COND_EQ
, cc
,
887 cc_result
, tcg_const_tl(0));
889 cris_evaluate_flags(dc
);
891 cpu_PR
[PR_CCS
], Z_FLAG
);
895 if ((arith_opt
|| move_opt
)
896 && dc
->cc_x_uptodate
!= (2 | X_FLAG
)) {
897 tcg_gen_mov_tl(cc
, cc_result
);
899 cris_evaluate_flags(dc
);
900 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
],
902 tcg_gen_andi_tl(cc
, cc
, Z_FLAG
);
906 cris_evaluate_flags(dc
);
907 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
], C_FLAG
);
910 cris_evaluate_flags(dc
);
911 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
], C_FLAG
);
912 tcg_gen_andi_tl(cc
, cc
, C_FLAG
);
915 cris_evaluate_flags(dc
);
916 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
], V_FLAG
);
919 cris_evaluate_flags(dc
);
920 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
],
922 tcg_gen_andi_tl(cc
, cc
, V_FLAG
);
925 if (arith_opt
|| move_opt
) {
928 if (dc
->cc_size
== 1) {
930 } else if (dc
->cc_size
== 2) {
934 tcg_gen_shri_tl(cc
, cc_result
, bits
);
935 tcg_gen_xori_tl(cc
, cc
, 1);
937 cris_evaluate_flags(dc
);
938 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
],
940 tcg_gen_andi_tl(cc
, cc
, N_FLAG
);
944 if (arith_opt
|| move_opt
) {
947 if (dc
->cc_size
== 1) {
949 } else if (dc
->cc_size
== 2) {
953 tcg_gen_shri_tl(cc
, cc_result
, bits
);
954 tcg_gen_andi_tl(cc
, cc
, 1);
956 cris_evaluate_flags(dc
);
957 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
],
962 cris_evaluate_flags(dc
);
963 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
],
967 cris_evaluate_flags(dc
);
971 tmp
= tcg_temp_new();
972 tcg_gen_xori_tl(tmp
, cpu_PR
[PR_CCS
],
974 /* Overlay the C flag on top of the Z. */
975 tcg_gen_shli_tl(cc
, tmp
, 2);
976 tcg_gen_and_tl(cc
, tmp
, cc
);
977 tcg_gen_andi_tl(cc
, cc
, Z_FLAG
);
983 cris_evaluate_flags(dc
);
984 /* Overlay the V flag on top of the N. */
985 tcg_gen_shli_tl(cc
, cpu_PR
[PR_CCS
], 2);
988 tcg_gen_andi_tl(cc
, cc
, N_FLAG
);
989 tcg_gen_xori_tl(cc
, cc
, N_FLAG
);
992 cris_evaluate_flags(dc
);
993 /* Overlay the V flag on top of the N. */
994 tcg_gen_shli_tl(cc
, cpu_PR
[PR_CCS
], 2);
997 tcg_gen_andi_tl(cc
, cc
, N_FLAG
);
1000 cris_evaluate_flags(dc
);
1007 /* To avoid a shift we overlay everything on
1009 tcg_gen_shri_tl(n
, cpu_PR
[PR_CCS
], 2);
1010 tcg_gen_shri_tl(z
, cpu_PR
[PR_CCS
], 1);
1012 tcg_gen_xori_tl(z
, z
, 2);
1014 tcg_gen_xor_tl(n
, n
, cpu_PR
[PR_CCS
]);
1015 tcg_gen_xori_tl(n
, n
, 2);
1016 tcg_gen_and_tl(cc
, z
, n
);
1017 tcg_gen_andi_tl(cc
, cc
, 2);
1024 cris_evaluate_flags(dc
);
1031 /* To avoid a shift we overlay everything on
1033 tcg_gen_shri_tl(n
, cpu_PR
[PR_CCS
], 2);
1034 tcg_gen_shri_tl(z
, cpu_PR
[PR_CCS
], 1);
1036 tcg_gen_xor_tl(n
, n
, cpu_PR
[PR_CCS
]);
1037 tcg_gen_or_tl(cc
, z
, n
);
1038 tcg_gen_andi_tl(cc
, cc
, 2);
1045 cris_evaluate_flags(dc
);
1046 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
], P_FLAG
);
1049 tcg_gen_movi_tl(cc
, 1);
1057 static void cris_store_direct_jmp(DisasContext
*dc
)
1059 /* Store the direct jmp state into the cpu-state. */
1060 if (dc
->jmp
== JMP_DIRECT
|| dc
->jmp
== JMP_DIRECT_CC
) {
1061 if (dc
->jmp
== JMP_DIRECT
) {
1062 tcg_gen_movi_tl(env_btaken
, 1);
1064 tcg_gen_movi_tl(env_btarget
, dc
->jmp_pc
);
1065 dc
->jmp
= JMP_INDIRECT
;
1069 static void cris_prepare_cc_branch (DisasContext
*dc
,
1070 int offset
, int cond
)
1072 /* This helps us re-schedule the micro-code to insns in delay-slots
1073 before the actual jump. */
1074 dc
->delayed_branch
= 2;
1075 dc
->jmp
= JMP_DIRECT_CC
;
1076 dc
->jmp_pc
= dc
->pc
+ offset
;
1078 gen_tst_cc(dc
, env_btaken
, cond
);
1079 tcg_gen_movi_tl(env_btarget
, dc
->jmp_pc
);
1083 /* jumps, when the dest is in a live reg for example. Direct should be set
1084 when the dest addr is constant to allow tb chaining. */
1085 static inline void cris_prepare_jmp (DisasContext
*dc
, unsigned int type
)
1087 /* This helps us re-schedule the micro-code to insns in delay-slots
1088 before the actual jump. */
1089 dc
->delayed_branch
= 2;
1091 if (type
== JMP_INDIRECT
) {
1092 tcg_gen_movi_tl(env_btaken
, 1);
1096 static void gen_load64(DisasContext
*dc
, TCGv_i64 dst
, TCGv addr
)
1098 int mem_index
= cpu_mmu_index(&dc
->cpu
->env
, false);
1100 /* If we get a fault on a delayslot we must keep the jmp state in
1101 the cpu-state to be able to re-execute the jmp. */
1102 if (dc
->delayed_branch
== 1) {
1103 cris_store_direct_jmp(dc
);
1106 tcg_gen_qemu_ld_i64(dst
, addr
, mem_index
, MO_TEQ
);
1109 static void gen_load(DisasContext
*dc
, TCGv dst
, TCGv addr
,
1110 unsigned int size
, int sign
)
1112 int mem_index
= cpu_mmu_index(&dc
->cpu
->env
, false);
1114 /* If we get a fault on a delayslot we must keep the jmp state in
1115 the cpu-state to be able to re-execute the jmp. */
1116 if (dc
->delayed_branch
== 1) {
1117 cris_store_direct_jmp(dc
);
1120 tcg_gen_qemu_ld_tl(dst
, addr
, mem_index
,
1121 MO_TE
+ ctz32(size
) + (sign
? MO_SIGN
: 0));
1124 static void gen_store (DisasContext
*dc
, TCGv addr
, TCGv val
,
1127 int mem_index
= cpu_mmu_index(&dc
->cpu
->env
, false);
1129 /* If we get a fault on a delayslot we must keep the jmp state in
1130 the cpu-state to be able to re-execute the jmp. */
1131 if (dc
->delayed_branch
== 1) {
1132 cris_store_direct_jmp(dc
);
1136 /* Conditional writes. We only support the kind were X and P are known
1137 at translation time. */
1138 if (dc
->flagx_known
&& dc
->flags_x
&& (dc
->tb_flags
& P_FLAG
)) {
1140 cris_evaluate_flags(dc
);
1141 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], C_FLAG
);
1145 tcg_gen_qemu_st_tl(val
, addr
, mem_index
, MO_TE
+ ctz32(size
));
1147 if (dc
->flagx_known
&& dc
->flags_x
) {
1148 cris_evaluate_flags(dc
);
1149 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~C_FLAG
);
1153 static inline void t_gen_sext(TCGv d
, TCGv s
, int size
)
1156 tcg_gen_ext8s_i32(d
, s
);
1157 } else if (size
== 2) {
1158 tcg_gen_ext16s_i32(d
, s
);
1159 } else if (!TCGV_EQUAL(d
, s
)) {
1160 tcg_gen_mov_tl(d
, s
);
1164 static inline void t_gen_zext(TCGv d
, TCGv s
, int size
)
1167 tcg_gen_ext8u_i32(d
, s
);
1168 } else if (size
== 2) {
1169 tcg_gen_ext16u_i32(d
, s
);
1170 } else if (!TCGV_EQUAL(d
, s
)) {
1171 tcg_gen_mov_tl(d
, s
);
1176 static char memsize_char(int size
)
1179 case 1: return 'b'; break;
1180 case 2: return 'w'; break;
1181 case 4: return 'd'; break;
1189 static inline unsigned int memsize_z(DisasContext
*dc
)
1191 return dc
->zsize
+ 1;
1194 static inline unsigned int memsize_zz(DisasContext
*dc
)
1196 switch (dc
->zzsize
) {
1204 static inline void do_postinc (DisasContext
*dc
, int size
)
1207 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], size
);
1211 static inline void dec_prep_move_r(DisasContext
*dc
, int rs
, int rd
,
1212 int size
, int s_ext
, TCGv dst
)
1215 t_gen_sext(dst
, cpu_R
[rs
], size
);
1217 t_gen_zext(dst
, cpu_R
[rs
], size
);
1221 /* Prepare T0 and T1 for a register alu operation.
1222 s_ext decides if the operand1 should be sign-extended or zero-extended when
1224 static void dec_prep_alu_r(DisasContext
*dc
, int rs
, int rd
,
1225 int size
, int s_ext
, TCGv dst
, TCGv src
)
1227 dec_prep_move_r(dc
, rs
, rd
, size
, s_ext
, src
);
1230 t_gen_sext(dst
, cpu_R
[rd
], size
);
1232 t_gen_zext(dst
, cpu_R
[rd
], size
);
1236 static int dec_prep_move_m(CPUCRISState
*env
, DisasContext
*dc
,
1237 int s_ext
, int memsize
, TCGv dst
)
1245 is_imm
= rs
== 15 && dc
->postinc
;
1247 /* Load [$rs] onto T1. */
1249 insn_len
= 2 + memsize
;
1254 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, memsize
, s_ext
);
1255 tcg_gen_movi_tl(dst
, imm
);
1258 cris_flush_cc_state(dc
);
1259 gen_load(dc
, dst
, cpu_R
[rs
], memsize
, 0);
1261 t_gen_sext(dst
, dst
, memsize
);
1263 t_gen_zext(dst
, dst
, memsize
);
1269 /* Prepare T0 and T1 for a memory + alu operation.
1270 s_ext decides if the operand1 should be sign-extended or zero-extended when
1272 static int dec_prep_alu_m(CPUCRISState
*env
, DisasContext
*dc
,
1273 int s_ext
, int memsize
, TCGv dst
, TCGv src
)
1277 insn_len
= dec_prep_move_m(env
, dc
, s_ext
, memsize
, src
);
1278 tcg_gen_mov_tl(dst
, cpu_R
[dc
->op2
]);
1283 static const char *cc_name(int cc
)
1285 static const char *cc_names
[16] = {
1286 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1287 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1290 return cc_names
[cc
];
1294 /* Start of insn decoders. */
1296 static int dec_bccq(CPUCRISState
*env
, DisasContext
*dc
)
1300 uint32_t cond
= dc
->op2
;
1302 offset
= EXTRACT_FIELD(dc
->ir
, 1, 7);
1303 sign
= EXTRACT_FIELD(dc
->ir
, 0, 0);
1306 offset
|= sign
<< 8;
1307 offset
= sign_extend(offset
, 8);
1309 LOG_DIS("b%s %x\n", cc_name(cond
), dc
->pc
+ offset
);
1311 /* op2 holds the condition-code. */
1312 cris_cc_mask(dc
, 0);
1313 cris_prepare_cc_branch(dc
, offset
, cond
);
1316 static int dec_addoq(CPUCRISState
*env
, DisasContext
*dc
)
1320 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 7);
1321 imm
= sign_extend(dc
->op1
, 7);
1323 LOG_DIS("addoq %d, $r%u\n", imm
, dc
->op2
);
1324 cris_cc_mask(dc
, 0);
1325 /* Fetch register operand, */
1326 tcg_gen_addi_tl(cpu_R
[R_ACR
], cpu_R
[dc
->op2
], imm
);
1330 static int dec_addq(CPUCRISState
*env
, DisasContext
*dc
)
1332 LOG_DIS("addq %u, $r%u\n", dc
->op1
, dc
->op2
);
1334 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1336 cris_cc_mask(dc
, CC_MASK_NZVC
);
1338 cris_alu(dc
, CC_OP_ADD
,
1339 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(dc
->op1
), 4);
1342 static int dec_moveq(CPUCRISState
*env
, DisasContext
*dc
)
1346 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1347 imm
= sign_extend(dc
->op1
, 5);
1348 LOG_DIS("moveq %d, $r%u\n", imm
, dc
->op2
);
1350 tcg_gen_movi_tl(cpu_R
[dc
->op2
], imm
);
1353 static int dec_subq(CPUCRISState
*env
, DisasContext
*dc
)
1355 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1357 LOG_DIS("subq %u, $r%u\n", dc
->op1
, dc
->op2
);
1359 cris_cc_mask(dc
, CC_MASK_NZVC
);
1360 cris_alu(dc
, CC_OP_SUB
,
1361 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(dc
->op1
), 4);
1364 static int dec_cmpq(CPUCRISState
*env
, DisasContext
*dc
)
1367 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1368 imm
= sign_extend(dc
->op1
, 5);
1370 LOG_DIS("cmpq %d, $r%d\n", imm
, dc
->op2
);
1371 cris_cc_mask(dc
, CC_MASK_NZVC
);
1373 cris_alu(dc
, CC_OP_CMP
,
1374 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(imm
), 4);
1377 static int dec_andq(CPUCRISState
*env
, DisasContext
*dc
)
1380 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1381 imm
= sign_extend(dc
->op1
, 5);
1383 LOG_DIS("andq %d, $r%d\n", imm
, dc
->op2
);
1384 cris_cc_mask(dc
, CC_MASK_NZ
);
1386 cris_alu(dc
, CC_OP_AND
,
1387 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(imm
), 4);
1390 static int dec_orq(CPUCRISState
*env
, DisasContext
*dc
)
1393 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1394 imm
= sign_extend(dc
->op1
, 5);
1395 LOG_DIS("orq %d, $r%d\n", imm
, dc
->op2
);
1396 cris_cc_mask(dc
, CC_MASK_NZ
);
1398 cris_alu(dc
, CC_OP_OR
,
1399 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(imm
), 4);
1402 static int dec_btstq(CPUCRISState
*env
, DisasContext
*dc
)
1404 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1405 LOG_DIS("btstq %u, $r%d\n", dc
->op1
, dc
->op2
);
1407 cris_cc_mask(dc
, CC_MASK_NZ
);
1408 cris_evaluate_flags(dc
);
1409 gen_helper_btst(cpu_PR
[PR_CCS
], cpu_env
, cpu_R
[dc
->op2
],
1410 tcg_const_tl(dc
->op1
), cpu_PR
[PR_CCS
]);
1411 cris_alu(dc
, CC_OP_MOVE
,
1412 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1413 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
1414 dc
->flags_uptodate
= 1;
1417 static int dec_asrq(CPUCRISState
*env
, DisasContext
*dc
)
1419 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1420 LOG_DIS("asrq %u, $r%d\n", dc
->op1
, dc
->op2
);
1421 cris_cc_mask(dc
, CC_MASK_NZ
);
1423 tcg_gen_sari_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], dc
->op1
);
1424 cris_alu(dc
, CC_OP_MOVE
,
1426 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1429 static int dec_lslq(CPUCRISState
*env
, DisasContext
*dc
)
1431 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1432 LOG_DIS("lslq %u, $r%d\n", dc
->op1
, dc
->op2
);
1434 cris_cc_mask(dc
, CC_MASK_NZ
);
1436 tcg_gen_shli_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], dc
->op1
);
1438 cris_alu(dc
, CC_OP_MOVE
,
1440 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1443 static int dec_lsrq(CPUCRISState
*env
, DisasContext
*dc
)
1445 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1446 LOG_DIS("lsrq %u, $r%d\n", dc
->op1
, dc
->op2
);
1448 cris_cc_mask(dc
, CC_MASK_NZ
);
1450 tcg_gen_shri_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], dc
->op1
);
1451 cris_alu(dc
, CC_OP_MOVE
,
1453 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1457 static int dec_move_r(CPUCRISState
*env
, DisasContext
*dc
)
1459 int size
= memsize_zz(dc
);
1461 LOG_DIS("move.%c $r%u, $r%u\n",
1462 memsize_char(size
), dc
->op1
, dc
->op2
);
1464 cris_cc_mask(dc
, CC_MASK_NZ
);
1466 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, cpu_R
[dc
->op2
]);
1467 cris_cc_mask(dc
, CC_MASK_NZ
);
1468 cris_update_cc_op(dc
, CC_OP_MOVE
, 4);
1469 cris_update_cc_x(dc
);
1470 cris_update_result(dc
, cpu_R
[dc
->op2
]);
1474 t0
= tcg_temp_new();
1475 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t0
);
1476 cris_alu(dc
, CC_OP_MOVE
,
1478 cpu_R
[dc
->op2
], t0
, size
);
1484 static int dec_scc_r(CPUCRISState
*env
, DisasContext
*dc
)
1488 LOG_DIS("s%s $r%u\n",
1489 cc_name(cond
), dc
->op1
);
1491 gen_tst_cc(dc
, cpu_R
[dc
->op1
], cond
);
1492 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], 0);
1494 cris_cc_mask(dc
, 0);
1498 static inline void cris_alu_alloc_temps(DisasContext
*dc
, int size
, TCGv
*t
)
1501 t
[0] = cpu_R
[dc
->op2
];
1502 t
[1] = cpu_R
[dc
->op1
];
1504 t
[0] = tcg_temp_new();
1505 t
[1] = tcg_temp_new();
1509 static inline void cris_alu_free_temps(DisasContext
*dc
, int size
, TCGv
*t
)
1512 tcg_temp_free(t
[0]);
1513 tcg_temp_free(t
[1]);
1517 static int dec_and_r(CPUCRISState
*env
, DisasContext
*dc
)
1520 int size
= memsize_zz(dc
);
1522 LOG_DIS("and.%c $r%u, $r%u\n",
1523 memsize_char(size
), dc
->op1
, dc
->op2
);
1525 cris_cc_mask(dc
, CC_MASK_NZ
);
1527 cris_alu_alloc_temps(dc
, size
, t
);
1528 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1529 cris_alu(dc
, CC_OP_AND
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1530 cris_alu_free_temps(dc
, size
, t
);
1534 static int dec_lz_r(CPUCRISState
*env
, DisasContext
*dc
)
1537 LOG_DIS("lz $r%u, $r%u\n",
1539 cris_cc_mask(dc
, CC_MASK_NZ
);
1540 t0
= tcg_temp_new();
1541 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0, cpu_R
[dc
->op2
], t0
);
1542 cris_alu(dc
, CC_OP_LZ
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1547 static int dec_lsl_r(CPUCRISState
*env
, DisasContext
*dc
)
1550 int size
= memsize_zz(dc
);
1552 LOG_DIS("lsl.%c $r%u, $r%u\n",
1553 memsize_char(size
), dc
->op1
, dc
->op2
);
1555 cris_cc_mask(dc
, CC_MASK_NZ
);
1556 cris_alu_alloc_temps(dc
, size
, t
);
1557 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1558 tcg_gen_andi_tl(t
[1], t
[1], 63);
1559 cris_alu(dc
, CC_OP_LSL
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1560 cris_alu_alloc_temps(dc
, size
, t
);
1564 static int dec_lsr_r(CPUCRISState
*env
, DisasContext
*dc
)
1567 int size
= memsize_zz(dc
);
1569 LOG_DIS("lsr.%c $r%u, $r%u\n",
1570 memsize_char(size
), dc
->op1
, dc
->op2
);
1572 cris_cc_mask(dc
, CC_MASK_NZ
);
1573 cris_alu_alloc_temps(dc
, size
, t
);
1574 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1575 tcg_gen_andi_tl(t
[1], t
[1], 63);
1576 cris_alu(dc
, CC_OP_LSR
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1577 cris_alu_free_temps(dc
, size
, t
);
1581 static int dec_asr_r(CPUCRISState
*env
, DisasContext
*dc
)
1584 int size
= memsize_zz(dc
);
1586 LOG_DIS("asr.%c $r%u, $r%u\n",
1587 memsize_char(size
), dc
->op1
, dc
->op2
);
1589 cris_cc_mask(dc
, CC_MASK_NZ
);
1590 cris_alu_alloc_temps(dc
, size
, t
);
1591 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 1, t
[0], t
[1]);
1592 tcg_gen_andi_tl(t
[1], t
[1], 63);
1593 cris_alu(dc
, CC_OP_ASR
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1594 cris_alu_free_temps(dc
, size
, t
);
1598 static int dec_muls_r(CPUCRISState
*env
, DisasContext
*dc
)
1601 int size
= memsize_zz(dc
);
1603 LOG_DIS("muls.%c $r%u, $r%u\n",
1604 memsize_char(size
), dc
->op1
, dc
->op2
);
1605 cris_cc_mask(dc
, CC_MASK_NZV
);
1606 cris_alu_alloc_temps(dc
, size
, t
);
1607 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 1, t
[0], t
[1]);
1609 cris_alu(dc
, CC_OP_MULS
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
1610 cris_alu_free_temps(dc
, size
, t
);
1614 static int dec_mulu_r(CPUCRISState
*env
, DisasContext
*dc
)
1617 int size
= memsize_zz(dc
);
1619 LOG_DIS("mulu.%c $r%u, $r%u\n",
1620 memsize_char(size
), dc
->op1
, dc
->op2
);
1621 cris_cc_mask(dc
, CC_MASK_NZV
);
1622 cris_alu_alloc_temps(dc
, size
, t
);
1623 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1625 cris_alu(dc
, CC_OP_MULU
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
1626 cris_alu_alloc_temps(dc
, size
, t
);
1631 static int dec_dstep_r(CPUCRISState
*env
, DisasContext
*dc
)
1633 LOG_DIS("dstep $r%u, $r%u\n", dc
->op1
, dc
->op2
);
1634 cris_cc_mask(dc
, CC_MASK_NZ
);
1635 cris_alu(dc
, CC_OP_DSTEP
,
1636 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], 4);
1640 static int dec_xor_r(CPUCRISState
*env
, DisasContext
*dc
)
1643 int size
= memsize_zz(dc
);
1644 LOG_DIS("xor.%c $r%u, $r%u\n",
1645 memsize_char(size
), dc
->op1
, dc
->op2
);
1646 BUG_ON(size
!= 4); /* xor is dword. */
1647 cris_cc_mask(dc
, CC_MASK_NZ
);
1648 cris_alu_alloc_temps(dc
, size
, t
);
1649 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1651 cris_alu(dc
, CC_OP_XOR
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
1652 cris_alu_free_temps(dc
, size
, t
);
1656 static int dec_bound_r(CPUCRISState
*env
, DisasContext
*dc
)
1659 int size
= memsize_zz(dc
);
1660 LOG_DIS("bound.%c $r%u, $r%u\n",
1661 memsize_char(size
), dc
->op1
, dc
->op2
);
1662 cris_cc_mask(dc
, CC_MASK_NZ
);
1663 l0
= tcg_temp_local_new();
1664 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, l0
);
1665 cris_alu(dc
, CC_OP_BOUND
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], l0
, 4);
1670 static int dec_cmp_r(CPUCRISState
*env
, DisasContext
*dc
)
1673 int size
= memsize_zz(dc
);
1674 LOG_DIS("cmp.%c $r%u, $r%u\n",
1675 memsize_char(size
), dc
->op1
, dc
->op2
);
1676 cris_cc_mask(dc
, CC_MASK_NZVC
);
1677 cris_alu_alloc_temps(dc
, size
, t
);
1678 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1680 cris_alu(dc
, CC_OP_CMP
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1681 cris_alu_free_temps(dc
, size
, t
);
1685 static int dec_abs_r(CPUCRISState
*env
, DisasContext
*dc
)
1689 LOG_DIS("abs $r%u, $r%u\n",
1691 cris_cc_mask(dc
, CC_MASK_NZ
);
1693 t0
= tcg_temp_new();
1694 tcg_gen_sari_tl(t0
, cpu_R
[dc
->op1
], 31);
1695 tcg_gen_xor_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], t0
);
1696 tcg_gen_sub_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
);
1699 cris_alu(dc
, CC_OP_MOVE
,
1700 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1704 static int dec_add_r(CPUCRISState
*env
, DisasContext
*dc
)
1707 int size
= memsize_zz(dc
);
1708 LOG_DIS("add.%c $r%u, $r%u\n",
1709 memsize_char(size
), dc
->op1
, dc
->op2
);
1710 cris_cc_mask(dc
, CC_MASK_NZVC
);
1711 cris_alu_alloc_temps(dc
, size
, t
);
1712 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1714 cris_alu(dc
, CC_OP_ADD
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1715 cris_alu_free_temps(dc
, size
, t
);
1719 static int dec_addc_r(CPUCRISState
*env
, DisasContext
*dc
)
1721 LOG_DIS("addc $r%u, $r%u\n",
1723 cris_evaluate_flags(dc
);
1724 /* Set for this insn. */
1725 dc
->flagx_known
= 1;
1726 dc
->flags_x
= X_FLAG
;
1728 cris_cc_mask(dc
, CC_MASK_NZVC
);
1729 cris_alu(dc
, CC_OP_ADDC
,
1730 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], 4);
1734 static int dec_mcp_r(CPUCRISState
*env
, DisasContext
*dc
)
1736 LOG_DIS("mcp $p%u, $r%u\n",
1738 cris_evaluate_flags(dc
);
1739 cris_cc_mask(dc
, CC_MASK_RNZV
);
1740 cris_alu(dc
, CC_OP_MCP
,
1741 cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], cpu_PR
[dc
->op2
], 4);
1746 static char * swapmode_name(int mode
, char *modename
) {
1749 modename
[i
++] = 'n';
1752 modename
[i
++] = 'w';
1755 modename
[i
++] = 'b';
1758 modename
[i
++] = 'r';
1765 static int dec_swap_r(CPUCRISState
*env
, DisasContext
*dc
)
1771 LOG_DIS("swap%s $r%u\n",
1772 swapmode_name(dc
->op2
, modename
), dc
->op1
);
1774 cris_cc_mask(dc
, CC_MASK_NZ
);
1775 t0
= tcg_temp_new();
1776 tcg_gen_mov_tl(t0
, cpu_R
[dc
->op1
]);
1778 tcg_gen_not_tl(t0
, t0
);
1781 t_gen_swapw(t0
, t0
);
1784 t_gen_swapb(t0
, t0
);
1787 t_gen_swapr(t0
, t0
);
1789 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], t0
, 4);
1794 static int dec_or_r(CPUCRISState
*env
, DisasContext
*dc
)
1797 int size
= memsize_zz(dc
);
1798 LOG_DIS("or.%c $r%u, $r%u\n",
1799 memsize_char(size
), dc
->op1
, dc
->op2
);
1800 cris_cc_mask(dc
, CC_MASK_NZ
);
1801 cris_alu_alloc_temps(dc
, size
, t
);
1802 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1803 cris_alu(dc
, CC_OP_OR
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1804 cris_alu_free_temps(dc
, size
, t
);
1808 static int dec_addi_r(CPUCRISState
*env
, DisasContext
*dc
)
1811 LOG_DIS("addi.%c $r%u, $r%u\n",
1812 memsize_char(memsize_zz(dc
)), dc
->op2
, dc
->op1
);
1813 cris_cc_mask(dc
, 0);
1814 t0
= tcg_temp_new();
1815 tcg_gen_shl_tl(t0
, cpu_R
[dc
->op2
], tcg_const_tl(dc
->zzsize
));
1816 tcg_gen_add_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], t0
);
1821 static int dec_addi_acr(CPUCRISState
*env
, DisasContext
*dc
)
1824 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1825 memsize_char(memsize_zz(dc
)), dc
->op2
, dc
->op1
);
1826 cris_cc_mask(dc
, 0);
1827 t0
= tcg_temp_new();
1828 tcg_gen_shl_tl(t0
, cpu_R
[dc
->op2
], tcg_const_tl(dc
->zzsize
));
1829 tcg_gen_add_tl(cpu_R
[R_ACR
], cpu_R
[dc
->op1
], t0
);
1834 static int dec_neg_r(CPUCRISState
*env
, DisasContext
*dc
)
1837 int size
= memsize_zz(dc
);
1838 LOG_DIS("neg.%c $r%u, $r%u\n",
1839 memsize_char(size
), dc
->op1
, dc
->op2
);
1840 cris_cc_mask(dc
, CC_MASK_NZVC
);
1841 cris_alu_alloc_temps(dc
, size
, t
);
1842 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1844 cris_alu(dc
, CC_OP_NEG
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1845 cris_alu_free_temps(dc
, size
, t
);
1849 static int dec_btst_r(CPUCRISState
*env
, DisasContext
*dc
)
1851 LOG_DIS("btst $r%u, $r%u\n",
1853 cris_cc_mask(dc
, CC_MASK_NZ
);
1854 cris_evaluate_flags(dc
);
1855 gen_helper_btst(cpu_PR
[PR_CCS
], cpu_env
, cpu_R
[dc
->op2
],
1856 cpu_R
[dc
->op1
], cpu_PR
[PR_CCS
]);
1857 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op2
],
1858 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1859 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
1860 dc
->flags_uptodate
= 1;
1864 static int dec_sub_r(CPUCRISState
*env
, DisasContext
*dc
)
1867 int size
= memsize_zz(dc
);
1868 LOG_DIS("sub.%c $r%u, $r%u\n",
1869 memsize_char(size
), dc
->op1
, dc
->op2
);
1870 cris_cc_mask(dc
, CC_MASK_NZVC
);
1871 cris_alu_alloc_temps(dc
, size
, t
);
1872 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1873 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1874 cris_alu_free_temps(dc
, size
, t
);
1878 /* Zero extension. From size to dword. */
1879 static int dec_movu_r(CPUCRISState
*env
, DisasContext
*dc
)
1882 int size
= memsize_z(dc
);
1883 LOG_DIS("movu.%c $r%u, $r%u\n",
1887 cris_cc_mask(dc
, CC_MASK_NZ
);
1888 t0
= tcg_temp_new();
1889 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t0
);
1890 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1895 /* Sign extension. From size to dword. */
1896 static int dec_movs_r(CPUCRISState
*env
, DisasContext
*dc
)
1899 int size
= memsize_z(dc
);
1900 LOG_DIS("movs.%c $r%u, $r%u\n",
1904 cris_cc_mask(dc
, CC_MASK_NZ
);
1905 t0
= tcg_temp_new();
1906 /* Size can only be qi or hi. */
1907 t_gen_sext(t0
, cpu_R
[dc
->op1
], size
);
1908 cris_alu(dc
, CC_OP_MOVE
,
1909 cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], t0
, 4);
1914 /* zero extension. From size to dword. */
1915 static int dec_addu_r(CPUCRISState
*env
, DisasContext
*dc
)
1918 int size
= memsize_z(dc
);
1919 LOG_DIS("addu.%c $r%u, $r%u\n",
1923 cris_cc_mask(dc
, CC_MASK_NZVC
);
1924 t0
= tcg_temp_new();
1925 /* Size can only be qi or hi. */
1926 t_gen_zext(t0
, cpu_R
[dc
->op1
], size
);
1927 cris_alu(dc
, CC_OP_ADD
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1932 /* Sign extension. From size to dword. */
1933 static int dec_adds_r(CPUCRISState
*env
, DisasContext
*dc
)
1936 int size
= memsize_z(dc
);
1937 LOG_DIS("adds.%c $r%u, $r%u\n",
1941 cris_cc_mask(dc
, CC_MASK_NZVC
);
1942 t0
= tcg_temp_new();
1943 /* Size can only be qi or hi. */
1944 t_gen_sext(t0
, cpu_R
[dc
->op1
], size
);
1945 cris_alu(dc
, CC_OP_ADD
,
1946 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1951 /* Zero extension. From size to dword. */
1952 static int dec_subu_r(CPUCRISState
*env
, DisasContext
*dc
)
1955 int size
= memsize_z(dc
);
1956 LOG_DIS("subu.%c $r%u, $r%u\n",
1960 cris_cc_mask(dc
, CC_MASK_NZVC
);
1961 t0
= tcg_temp_new();
1962 /* Size can only be qi or hi. */
1963 t_gen_zext(t0
, cpu_R
[dc
->op1
], size
);
1964 cris_alu(dc
, CC_OP_SUB
,
1965 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1970 /* Sign extension. From size to dword. */
1971 static int dec_subs_r(CPUCRISState
*env
, DisasContext
*dc
)
1974 int size
= memsize_z(dc
);
1975 LOG_DIS("subs.%c $r%u, $r%u\n",
1979 cris_cc_mask(dc
, CC_MASK_NZVC
);
1980 t0
= tcg_temp_new();
1981 /* Size can only be qi or hi. */
1982 t_gen_sext(t0
, cpu_R
[dc
->op1
], size
);
1983 cris_alu(dc
, CC_OP_SUB
,
1984 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1989 static int dec_setclrf(CPUCRISState
*env
, DisasContext
*dc
)
1992 int set
= (~dc
->opcode
>> 2) & 1;
1995 flags
= (EXTRACT_FIELD(dc
->ir
, 12, 15) << 4)
1996 | EXTRACT_FIELD(dc
->ir
, 0, 3);
1997 if (set
&& flags
== 0) {
2000 } else if (!set
&& (flags
& 0x20)) {
2003 LOG_DIS("%sf %x\n", set
? "set" : "clr", flags
);
2006 /* User space is not allowed to touch these. Silently ignore. */
2007 if (dc
->tb_flags
& U_FLAG
) {
2008 flags
&= ~(S_FLAG
| I_FLAG
| U_FLAG
);
2011 if (flags
& X_FLAG
) {
2012 dc
->flagx_known
= 1;
2014 dc
->flags_x
= X_FLAG
;
2020 /* Break the TB if any of the SPI flag changes. */
2021 if (flags
& (P_FLAG
| S_FLAG
)) {
2022 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2023 dc
->is_jmp
= DISAS_UPDATE
;
2024 dc
->cpustate_changed
= 1;
2027 /* For the I flag, only act on posedge. */
2028 if ((flags
& I_FLAG
)) {
2029 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2030 dc
->is_jmp
= DISAS_UPDATE
;
2031 dc
->cpustate_changed
= 1;
2035 /* Simply decode the flags. */
2036 cris_evaluate_flags(dc
);
2037 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
2038 cris_update_cc_x(dc
);
2039 tcg_gen_movi_tl(cc_op
, dc
->cc_op
);
2042 if (!(dc
->tb_flags
& U_FLAG
) && (flags
& U_FLAG
)) {
2043 /* Enter user mode. */
2044 t_gen_mov_env_TN(ksp
, cpu_R
[R_SP
]);
2045 tcg_gen_mov_tl(cpu_R
[R_SP
], cpu_PR
[PR_USP
]);
2046 dc
->cpustate_changed
= 1;
2048 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], flags
);
2050 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~flags
);
2053 dc
->flags_uptodate
= 1;
2058 static int dec_move_rs(CPUCRISState
*env
, DisasContext
*dc
)
2060 LOG_DIS("move $r%u, $s%u\n", dc
->op1
, dc
->op2
);
2061 cris_cc_mask(dc
, 0);
2062 gen_helper_movl_sreg_reg(cpu_env
, tcg_const_tl(dc
->op2
),
2063 tcg_const_tl(dc
->op1
));
2066 static int dec_move_sr(CPUCRISState
*env
, DisasContext
*dc
)
2068 LOG_DIS("move $s%u, $r%u\n", dc
->op2
, dc
->op1
);
2069 cris_cc_mask(dc
, 0);
2070 gen_helper_movl_reg_sreg(cpu_env
, tcg_const_tl(dc
->op1
),
2071 tcg_const_tl(dc
->op2
));
2075 static int dec_move_rp(CPUCRISState
*env
, DisasContext
*dc
)
2078 LOG_DIS("move $r%u, $p%u\n", dc
->op1
, dc
->op2
);
2079 cris_cc_mask(dc
, 0);
2081 t
[0] = tcg_temp_new();
2082 if (dc
->op2
== PR_CCS
) {
2083 cris_evaluate_flags(dc
);
2084 tcg_gen_mov_tl(t
[0], cpu_R
[dc
->op1
]);
2085 if (dc
->tb_flags
& U_FLAG
) {
2086 t
[1] = tcg_temp_new();
2087 /* User space is not allowed to touch all flags. */
2088 tcg_gen_andi_tl(t
[0], t
[0], 0x39f);
2089 tcg_gen_andi_tl(t
[1], cpu_PR
[PR_CCS
], ~0x39f);
2090 tcg_gen_or_tl(t
[0], t
[1], t
[0]);
2091 tcg_temp_free(t
[1]);
2094 tcg_gen_mov_tl(t
[0], cpu_R
[dc
->op1
]);
2097 t_gen_mov_preg_TN(dc
, dc
->op2
, t
[0]);
2098 if (dc
->op2
== PR_CCS
) {
2099 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
2100 dc
->flags_uptodate
= 1;
2102 tcg_temp_free(t
[0]);
2105 static int dec_move_pr(CPUCRISState
*env
, DisasContext
*dc
)
2108 LOG_DIS("move $p%u, $r%u\n", dc
->op2
, dc
->op1
);
2109 cris_cc_mask(dc
, 0);
2111 if (dc
->op2
== PR_CCS
) {
2112 cris_evaluate_flags(dc
);
2115 if (dc
->op2
== PR_DZ
) {
2116 tcg_gen_movi_tl(cpu_R
[dc
->op1
], 0);
2118 t0
= tcg_temp_new();
2119 t_gen_mov_TN_preg(t0
, dc
->op2
);
2120 cris_alu(dc
, CC_OP_MOVE
,
2121 cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], t0
,
2122 preg_sizes
[dc
->op2
]);
2128 static int dec_move_mr(CPUCRISState
*env
, DisasContext
*dc
)
2130 int memsize
= memsize_zz(dc
);
2132 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2133 memsize_char(memsize
),
2134 dc
->op1
, dc
->postinc
? "+]" : "]",
2138 insn_len
= dec_prep_move_m(env
, dc
, 0, 4, cpu_R
[dc
->op2
]);
2139 cris_cc_mask(dc
, CC_MASK_NZ
);
2140 cris_update_cc_op(dc
, CC_OP_MOVE
, 4);
2141 cris_update_cc_x(dc
);
2142 cris_update_result(dc
, cpu_R
[dc
->op2
]);
2146 t0
= tcg_temp_new();
2147 insn_len
= dec_prep_move_m(env
, dc
, 0, memsize
, t0
);
2148 cris_cc_mask(dc
, CC_MASK_NZ
);
2149 cris_alu(dc
, CC_OP_MOVE
,
2150 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, memsize
);
2153 do_postinc(dc
, memsize
);
2157 static inline void cris_alu_m_alloc_temps(TCGv
*t
)
2159 t
[0] = tcg_temp_new();
2160 t
[1] = tcg_temp_new();
2163 static inline void cris_alu_m_free_temps(TCGv
*t
)
2165 tcg_temp_free(t
[0]);
2166 tcg_temp_free(t
[1]);
2169 static int dec_movs_m(CPUCRISState
*env
, DisasContext
*dc
)
2172 int memsize
= memsize_z(dc
);
2174 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2175 memsize_char(memsize
),
2176 dc
->op1
, dc
->postinc
? "+]" : "]",
2179 cris_alu_m_alloc_temps(t
);
2181 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2182 cris_cc_mask(dc
, CC_MASK_NZ
);
2183 cris_alu(dc
, CC_OP_MOVE
,
2184 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2185 do_postinc(dc
, memsize
);
2186 cris_alu_m_free_temps(t
);
2190 static int dec_addu_m(CPUCRISState
*env
, DisasContext
*dc
)
2193 int memsize
= memsize_z(dc
);
2195 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2196 memsize_char(memsize
),
2197 dc
->op1
, dc
->postinc
? "+]" : "]",
2200 cris_alu_m_alloc_temps(t
);
2202 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2203 cris_cc_mask(dc
, CC_MASK_NZVC
);
2204 cris_alu(dc
, CC_OP_ADD
,
2205 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2206 do_postinc(dc
, memsize
);
2207 cris_alu_m_free_temps(t
);
2211 static int dec_adds_m(CPUCRISState
*env
, DisasContext
*dc
)
2214 int memsize
= memsize_z(dc
);
2216 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2217 memsize_char(memsize
),
2218 dc
->op1
, dc
->postinc
? "+]" : "]",
2221 cris_alu_m_alloc_temps(t
);
2223 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2224 cris_cc_mask(dc
, CC_MASK_NZVC
);
2225 cris_alu(dc
, CC_OP_ADD
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2226 do_postinc(dc
, memsize
);
2227 cris_alu_m_free_temps(t
);
2231 static int dec_subu_m(CPUCRISState
*env
, DisasContext
*dc
)
2234 int memsize
= memsize_z(dc
);
2236 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2237 memsize_char(memsize
),
2238 dc
->op1
, dc
->postinc
? "+]" : "]",
2241 cris_alu_m_alloc_temps(t
);
2243 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2244 cris_cc_mask(dc
, CC_MASK_NZVC
);
2245 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2246 do_postinc(dc
, memsize
);
2247 cris_alu_m_free_temps(t
);
2251 static int dec_subs_m(CPUCRISState
*env
, DisasContext
*dc
)
2254 int memsize
= memsize_z(dc
);
2256 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2257 memsize_char(memsize
),
2258 dc
->op1
, dc
->postinc
? "+]" : "]",
2261 cris_alu_m_alloc_temps(t
);
2263 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2264 cris_cc_mask(dc
, CC_MASK_NZVC
);
2265 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2266 do_postinc(dc
, memsize
);
2267 cris_alu_m_free_temps(t
);
2271 static int dec_movu_m(CPUCRISState
*env
, DisasContext
*dc
)
2274 int memsize
= memsize_z(dc
);
2277 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2278 memsize_char(memsize
),
2279 dc
->op1
, dc
->postinc
? "+]" : "]",
2282 cris_alu_m_alloc_temps(t
);
2283 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2284 cris_cc_mask(dc
, CC_MASK_NZ
);
2285 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2286 do_postinc(dc
, memsize
);
2287 cris_alu_m_free_temps(t
);
2291 static int dec_cmpu_m(CPUCRISState
*env
, DisasContext
*dc
)
2294 int memsize
= memsize_z(dc
);
2296 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2297 memsize_char(memsize
),
2298 dc
->op1
, dc
->postinc
? "+]" : "]",
2301 cris_alu_m_alloc_temps(t
);
2302 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2303 cris_cc_mask(dc
, CC_MASK_NZVC
);
2304 cris_alu(dc
, CC_OP_CMP
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2305 do_postinc(dc
, memsize
);
2306 cris_alu_m_free_temps(t
);
2310 static int dec_cmps_m(CPUCRISState
*env
, DisasContext
*dc
)
2313 int memsize
= memsize_z(dc
);
2315 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2316 memsize_char(memsize
),
2317 dc
->op1
, dc
->postinc
? "+]" : "]",
2320 cris_alu_m_alloc_temps(t
);
2321 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2322 cris_cc_mask(dc
, CC_MASK_NZVC
);
2323 cris_alu(dc
, CC_OP_CMP
,
2324 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1],
2326 do_postinc(dc
, memsize
);
2327 cris_alu_m_free_temps(t
);
2331 static int dec_cmp_m(CPUCRISState
*env
, DisasContext
*dc
)
2334 int memsize
= memsize_zz(dc
);
2336 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2337 memsize_char(memsize
),
2338 dc
->op1
, dc
->postinc
? "+]" : "]",
2341 cris_alu_m_alloc_temps(t
);
2342 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2343 cris_cc_mask(dc
, CC_MASK_NZVC
);
2344 cris_alu(dc
, CC_OP_CMP
,
2345 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1],
2347 do_postinc(dc
, memsize
);
2348 cris_alu_m_free_temps(t
);
2352 static int dec_test_m(CPUCRISState
*env
, DisasContext
*dc
)
2355 int memsize
= memsize_zz(dc
);
2357 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2358 memsize_char(memsize
),
2359 dc
->op1
, dc
->postinc
? "+]" : "]",
2362 cris_evaluate_flags(dc
);
2364 cris_alu_m_alloc_temps(t
);
2365 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2366 cris_cc_mask(dc
, CC_MASK_NZ
);
2367 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~3);
2369 cris_alu(dc
, CC_OP_CMP
,
2370 cpu_R
[dc
->op2
], t
[1], tcg_const_tl(0), memsize_zz(dc
));
2371 do_postinc(dc
, memsize
);
2372 cris_alu_m_free_temps(t
);
2376 static int dec_and_m(CPUCRISState
*env
, DisasContext
*dc
)
2379 int memsize
= memsize_zz(dc
);
2381 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2382 memsize_char(memsize
),
2383 dc
->op1
, dc
->postinc
? "+]" : "]",
2386 cris_alu_m_alloc_temps(t
);
2387 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2388 cris_cc_mask(dc
, CC_MASK_NZ
);
2389 cris_alu(dc
, CC_OP_AND
, cpu_R
[dc
->op2
], t
[0], t
[1], memsize_zz(dc
));
2390 do_postinc(dc
, memsize
);
2391 cris_alu_m_free_temps(t
);
2395 static int dec_add_m(CPUCRISState
*env
, DisasContext
*dc
)
2398 int memsize
= memsize_zz(dc
);
2400 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2401 memsize_char(memsize
),
2402 dc
->op1
, dc
->postinc
? "+]" : "]",
2405 cris_alu_m_alloc_temps(t
);
2406 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2407 cris_cc_mask(dc
, CC_MASK_NZVC
);
2408 cris_alu(dc
, CC_OP_ADD
,
2409 cpu_R
[dc
->op2
], t
[0], t
[1], memsize_zz(dc
));
2410 do_postinc(dc
, memsize
);
2411 cris_alu_m_free_temps(t
);
2415 static int dec_addo_m(CPUCRISState
*env
, DisasContext
*dc
)
2418 int memsize
= memsize_zz(dc
);
2420 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2421 memsize_char(memsize
),
2422 dc
->op1
, dc
->postinc
? "+]" : "]",
2425 cris_alu_m_alloc_temps(t
);
2426 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2427 cris_cc_mask(dc
, 0);
2428 cris_alu(dc
, CC_OP_ADD
, cpu_R
[R_ACR
], t
[0], t
[1], 4);
2429 do_postinc(dc
, memsize
);
2430 cris_alu_m_free_temps(t
);
2434 static int dec_bound_m(CPUCRISState
*env
, DisasContext
*dc
)
2437 int memsize
= memsize_zz(dc
);
2439 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2440 memsize_char(memsize
),
2441 dc
->op1
, dc
->postinc
? "+]" : "]",
2444 l
[0] = tcg_temp_local_new();
2445 l
[1] = tcg_temp_local_new();
2446 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, l
[0], l
[1]);
2447 cris_cc_mask(dc
, CC_MASK_NZ
);
2448 cris_alu(dc
, CC_OP_BOUND
, cpu_R
[dc
->op2
], l
[0], l
[1], 4);
2449 do_postinc(dc
, memsize
);
2450 tcg_temp_free(l
[0]);
2451 tcg_temp_free(l
[1]);
2455 static int dec_addc_mr(CPUCRISState
*env
, DisasContext
*dc
)
2459 LOG_DIS("addc [$r%u%s, $r%u\n",
2460 dc
->op1
, dc
->postinc
? "+]" : "]",
2463 cris_evaluate_flags(dc
);
2465 /* Set for this insn. */
2466 dc
->flagx_known
= 1;
2467 dc
->flags_x
= X_FLAG
;
2469 cris_alu_m_alloc_temps(t
);
2470 insn_len
= dec_prep_alu_m(env
, dc
, 0, 4, t
[0], t
[1]);
2471 cris_cc_mask(dc
, CC_MASK_NZVC
);
2472 cris_alu(dc
, CC_OP_ADDC
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
2474 cris_alu_m_free_temps(t
);
2478 static int dec_sub_m(CPUCRISState
*env
, DisasContext
*dc
)
2481 int memsize
= memsize_zz(dc
);
2483 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2484 memsize_char(memsize
),
2485 dc
->op1
, dc
->postinc
? "+]" : "]",
2486 dc
->op2
, dc
->ir
, dc
->zzsize
);
2488 cris_alu_m_alloc_temps(t
);
2489 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2490 cris_cc_mask(dc
, CC_MASK_NZVC
);
2491 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], t
[0], t
[1], memsize
);
2492 do_postinc(dc
, memsize
);
2493 cris_alu_m_free_temps(t
);
2497 static int dec_or_m(CPUCRISState
*env
, DisasContext
*dc
)
2500 int memsize
= memsize_zz(dc
);
2502 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2503 memsize_char(memsize
),
2504 dc
->op1
, dc
->postinc
? "+]" : "]",
2507 cris_alu_m_alloc_temps(t
);
2508 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2509 cris_cc_mask(dc
, CC_MASK_NZ
);
2510 cris_alu(dc
, CC_OP_OR
,
2511 cpu_R
[dc
->op2
], t
[0], t
[1], memsize_zz(dc
));
2512 do_postinc(dc
, memsize
);
2513 cris_alu_m_free_temps(t
);
2517 static int dec_move_mp(CPUCRISState
*env
, DisasContext
*dc
)
2520 int memsize
= memsize_zz(dc
);
2523 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2524 memsize_char(memsize
),
2526 dc
->postinc
? "+]" : "]",
2529 cris_alu_m_alloc_temps(t
);
2530 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2531 cris_cc_mask(dc
, 0);
2532 if (dc
->op2
== PR_CCS
) {
2533 cris_evaluate_flags(dc
);
2534 if (dc
->tb_flags
& U_FLAG
) {
2535 /* User space is not allowed to touch all flags. */
2536 tcg_gen_andi_tl(t
[1], t
[1], 0x39f);
2537 tcg_gen_andi_tl(t
[0], cpu_PR
[PR_CCS
], ~0x39f);
2538 tcg_gen_or_tl(t
[1], t
[0], t
[1]);
2542 t_gen_mov_preg_TN(dc
, dc
->op2
, t
[1]);
2544 do_postinc(dc
, memsize
);
2545 cris_alu_m_free_temps(t
);
2549 static int dec_move_pm(CPUCRISState
*env
, DisasContext
*dc
)
2554 memsize
= preg_sizes
[dc
->op2
];
2556 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2557 memsize_char(memsize
),
2558 dc
->op2
, dc
->op1
, dc
->postinc
? "+]" : "]");
2560 /* prepare store. Address in T0, value in T1. */
2561 if (dc
->op2
== PR_CCS
) {
2562 cris_evaluate_flags(dc
);
2564 t0
= tcg_temp_new();
2565 t_gen_mov_TN_preg(t0
, dc
->op2
);
2566 cris_flush_cc_state(dc
);
2567 gen_store(dc
, cpu_R
[dc
->op1
], t0
, memsize
);
2570 cris_cc_mask(dc
, 0);
2572 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], memsize
);
2577 static int dec_movem_mr(CPUCRISState
*env
, DisasContext
*dc
)
2583 int nr
= dc
->op2
+ 1;
2585 LOG_DIS("movem [$r%u%s, $r%u\n", dc
->op1
,
2586 dc
->postinc
? "+]" : "]", dc
->op2
);
2588 addr
= tcg_temp_new();
2589 /* There are probably better ways of doing this. */
2590 cris_flush_cc_state(dc
);
2591 for (i
= 0; i
< (nr
>> 1); i
++) {
2592 tmp
[i
] = tcg_temp_new_i64();
2593 tcg_gen_addi_tl(addr
, cpu_R
[dc
->op1
], i
* 8);
2594 gen_load64(dc
, tmp
[i
], addr
);
2597 tmp32
= tcg_temp_new_i32();
2598 tcg_gen_addi_tl(addr
, cpu_R
[dc
->op1
], i
* 8);
2599 gen_load(dc
, tmp32
, addr
, 4, 0);
2603 tcg_temp_free(addr
);
2605 for (i
= 0; i
< (nr
>> 1); i
++) {
2606 tcg_gen_extrl_i64_i32(cpu_R
[i
* 2], tmp
[i
]);
2607 tcg_gen_shri_i64(tmp
[i
], tmp
[i
], 32);
2608 tcg_gen_extrl_i64_i32(cpu_R
[i
* 2 + 1], tmp
[i
]);
2609 tcg_temp_free_i64(tmp
[i
]);
2612 tcg_gen_mov_tl(cpu_R
[dc
->op2
], tmp32
);
2613 tcg_temp_free(tmp32
);
2616 /* writeback the updated pointer value. */
2618 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], nr
* 4);
2621 /* gen_load might want to evaluate the previous insns flags. */
2622 cris_cc_mask(dc
, 0);
2626 static int dec_movem_rm(CPUCRISState
*env
, DisasContext
*dc
)
2632 LOG_DIS("movem $r%u, [$r%u%s\n", dc
->op2
, dc
->op1
,
2633 dc
->postinc
? "+]" : "]");
2635 cris_flush_cc_state(dc
);
2637 tmp
= tcg_temp_new();
2638 addr
= tcg_temp_new();
2639 tcg_gen_movi_tl(tmp
, 4);
2640 tcg_gen_mov_tl(addr
, cpu_R
[dc
->op1
]);
2641 for (i
= 0; i
<= dc
->op2
; i
++) {
2642 /* Displace addr. */
2643 /* Perform the store. */
2644 gen_store(dc
, addr
, cpu_R
[i
], 4);
2645 tcg_gen_add_tl(addr
, addr
, tmp
);
2648 tcg_gen_mov_tl(cpu_R
[dc
->op1
], addr
);
2650 cris_cc_mask(dc
, 0);
2652 tcg_temp_free(addr
);
2656 static int dec_move_rm(CPUCRISState
*env
, DisasContext
*dc
)
2660 memsize
= memsize_zz(dc
);
2662 LOG_DIS("move.%c $r%u, [$r%u]\n",
2663 memsize_char(memsize
), dc
->op2
, dc
->op1
);
2665 /* prepare store. */
2666 cris_flush_cc_state(dc
);
2667 gen_store(dc
, cpu_R
[dc
->op1
], cpu_R
[dc
->op2
], memsize
);
2670 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], memsize
);
2672 cris_cc_mask(dc
, 0);
2676 static int dec_lapcq(CPUCRISState
*env
, DisasContext
*dc
)
2678 LOG_DIS("lapcq %x, $r%u\n",
2679 dc
->pc
+ dc
->op1
*2, dc
->op2
);
2680 cris_cc_mask(dc
, 0);
2681 tcg_gen_movi_tl(cpu_R
[dc
->op2
], dc
->pc
+ dc
->op1
* 2);
2685 static int dec_lapc_im(CPUCRISState
*env
, DisasContext
*dc
)
2693 cris_cc_mask(dc
, 0);
2694 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2695 LOG_DIS("lapc 0x%x, $r%u\n", imm
+ dc
->pc
, dc
->op2
);
2699 tcg_gen_movi_tl(cpu_R
[rd
], pc
);
2703 /* Jump to special reg. */
2704 static int dec_jump_p(CPUCRISState
*env
, DisasContext
*dc
)
2706 LOG_DIS("jump $p%u\n", dc
->op2
);
2708 if (dc
->op2
== PR_CCS
) {
2709 cris_evaluate_flags(dc
);
2711 t_gen_mov_TN_preg(env_btarget
, dc
->op2
);
2712 /* rete will often have low bit set to indicate delayslot. */
2713 tcg_gen_andi_tl(env_btarget
, env_btarget
, ~1);
2714 cris_cc_mask(dc
, 0);
2715 cris_prepare_jmp(dc
, JMP_INDIRECT
);
2719 /* Jump and save. */
2720 static int dec_jas_r(CPUCRISState
*env
, DisasContext
*dc
)
2722 LOG_DIS("jas $r%u, $p%u\n", dc
->op1
, dc
->op2
);
2723 cris_cc_mask(dc
, 0);
2724 /* Store the return address in Pd. */
2725 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->op1
]);
2729 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 4));
2731 cris_prepare_jmp(dc
, JMP_INDIRECT
);
2735 static int dec_jas_im(CPUCRISState
*env
, DisasContext
*dc
)
2739 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2741 LOG_DIS("jas 0x%x\n", imm
);
2742 cris_cc_mask(dc
, 0);
2743 /* Store the return address in Pd. */
2744 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 8));
2747 cris_prepare_jmp(dc
, JMP_DIRECT
);
2751 static int dec_jasc_im(CPUCRISState
*env
, DisasContext
*dc
)
2755 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2757 LOG_DIS("jasc 0x%x\n", imm
);
2758 cris_cc_mask(dc
, 0);
2759 /* Store the return address in Pd. */
2760 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 8 + 4));
2763 cris_prepare_jmp(dc
, JMP_DIRECT
);
2767 static int dec_jasc_r(CPUCRISState
*env
, DisasContext
*dc
)
2769 LOG_DIS("jasc_r $r%u, $p%u\n", dc
->op1
, dc
->op2
);
2770 cris_cc_mask(dc
, 0);
2771 /* Store the return address in Pd. */
2772 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->op1
]);
2773 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 4 + 4));
2774 cris_prepare_jmp(dc
, JMP_INDIRECT
);
2778 static int dec_bcc_im(CPUCRISState
*env
, DisasContext
*dc
)
2781 uint32_t cond
= dc
->op2
;
2783 offset
= cris_fetch(env
, dc
, dc
->pc
+ 2, 2, 1);
2785 LOG_DIS("b%s %d pc=%x dst=%x\n",
2786 cc_name(cond
), offset
,
2787 dc
->pc
, dc
->pc
+ offset
);
2789 cris_cc_mask(dc
, 0);
2790 /* op2 holds the condition-code. */
2791 cris_prepare_cc_branch(dc
, offset
, cond
);
2795 static int dec_bas_im(CPUCRISState
*env
, DisasContext
*dc
)
2799 simm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2801 LOG_DIS("bas 0x%x, $p%u\n", dc
->pc
+ simm
, dc
->op2
);
2802 cris_cc_mask(dc
, 0);
2803 /* Store the return address in Pd. */
2804 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 8));
2806 dc
->jmp_pc
= dc
->pc
+ simm
;
2807 cris_prepare_jmp(dc
, JMP_DIRECT
);
2811 static int dec_basc_im(CPUCRISState
*env
, DisasContext
*dc
)
2814 simm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2816 LOG_DIS("basc 0x%x, $p%u\n", dc
->pc
+ simm
, dc
->op2
);
2817 cris_cc_mask(dc
, 0);
2818 /* Store the return address in Pd. */
2819 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 12));
2821 dc
->jmp_pc
= dc
->pc
+ simm
;
2822 cris_prepare_jmp(dc
, JMP_DIRECT
);
2826 static int dec_rfe_etc(CPUCRISState
*env
, DisasContext
*dc
)
2828 cris_cc_mask(dc
, 0);
2830 if (dc
->op2
== 15) {
2831 tcg_gen_st_i32(tcg_const_i32(1), cpu_env
,
2832 -offsetof(CRISCPU
, env
) + offsetof(CPUState
, halted
));
2833 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2834 t_gen_raise_exception(EXCP_HLT
);
2838 switch (dc
->op2
& 7) {
2842 cris_evaluate_flags(dc
);
2843 gen_helper_rfe(cpu_env
);
2844 dc
->is_jmp
= DISAS_UPDATE
;
2849 cris_evaluate_flags(dc
);
2850 gen_helper_rfn(cpu_env
);
2851 dc
->is_jmp
= DISAS_UPDATE
;
2854 LOG_DIS("break %d\n", dc
->op1
);
2855 cris_evaluate_flags(dc
);
2857 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2859 /* Breaks start at 16 in the exception vector. */
2860 t_gen_mov_env_TN(trap_vector
,
2861 tcg_const_tl(dc
->op1
+ 16));
2862 t_gen_raise_exception(EXCP_BREAK
);
2863 dc
->is_jmp
= DISAS_UPDATE
;
2866 printf("op2=%x\n", dc
->op2
);
2874 static int dec_ftag_fidx_d_m(CPUCRISState
*env
, DisasContext
*dc
)
2879 static int dec_ftag_fidx_i_m(CPUCRISState
*env
, DisasContext
*dc
)
2884 static int dec_null(CPUCRISState
*env
, DisasContext
*dc
)
2886 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2887 dc
->pc
, dc
->opcode
, dc
->op1
, dc
->op2
);
2893 static struct decoder_info
{
2898 int (*dec
)(CPUCRISState
*env
, DisasContext
*dc
);
2900 /* Order matters here. */
2901 {DEC_MOVEQ
, dec_moveq
},
2902 {DEC_BTSTQ
, dec_btstq
},
2903 {DEC_CMPQ
, dec_cmpq
},
2904 {DEC_ADDOQ
, dec_addoq
},
2905 {DEC_ADDQ
, dec_addq
},
2906 {DEC_SUBQ
, dec_subq
},
2907 {DEC_ANDQ
, dec_andq
},
2909 {DEC_ASRQ
, dec_asrq
},
2910 {DEC_LSLQ
, dec_lslq
},
2911 {DEC_LSRQ
, dec_lsrq
},
2912 {DEC_BCCQ
, dec_bccq
},
2914 {DEC_BCC_IM
, dec_bcc_im
},
2915 {DEC_JAS_IM
, dec_jas_im
},
2916 {DEC_JAS_R
, dec_jas_r
},
2917 {DEC_JASC_IM
, dec_jasc_im
},
2918 {DEC_JASC_R
, dec_jasc_r
},
2919 {DEC_BAS_IM
, dec_bas_im
},
2920 {DEC_BASC_IM
, dec_basc_im
},
2921 {DEC_JUMP_P
, dec_jump_p
},
2922 {DEC_LAPC_IM
, dec_lapc_im
},
2923 {DEC_LAPCQ
, dec_lapcq
},
2925 {DEC_RFE_ETC
, dec_rfe_etc
},
2926 {DEC_ADDC_MR
, dec_addc_mr
},
2928 {DEC_MOVE_MP
, dec_move_mp
},
2929 {DEC_MOVE_PM
, dec_move_pm
},
2930 {DEC_MOVEM_MR
, dec_movem_mr
},
2931 {DEC_MOVEM_RM
, dec_movem_rm
},
2932 {DEC_MOVE_PR
, dec_move_pr
},
2933 {DEC_SCC_R
, dec_scc_r
},
2934 {DEC_SETF
, dec_setclrf
},
2935 {DEC_CLEARF
, dec_setclrf
},
2937 {DEC_MOVE_SR
, dec_move_sr
},
2938 {DEC_MOVE_RP
, dec_move_rp
},
2939 {DEC_SWAP_R
, dec_swap_r
},
2940 {DEC_ABS_R
, dec_abs_r
},
2941 {DEC_LZ_R
, dec_lz_r
},
2942 {DEC_MOVE_RS
, dec_move_rs
},
2943 {DEC_BTST_R
, dec_btst_r
},
2944 {DEC_ADDC_R
, dec_addc_r
},
2946 {DEC_DSTEP_R
, dec_dstep_r
},
2947 {DEC_XOR_R
, dec_xor_r
},
2948 {DEC_MCP_R
, dec_mcp_r
},
2949 {DEC_CMP_R
, dec_cmp_r
},
2951 {DEC_ADDI_R
, dec_addi_r
},
2952 {DEC_ADDI_ACR
, dec_addi_acr
},
2954 {DEC_ADD_R
, dec_add_r
},
2955 {DEC_SUB_R
, dec_sub_r
},
2957 {DEC_ADDU_R
, dec_addu_r
},
2958 {DEC_ADDS_R
, dec_adds_r
},
2959 {DEC_SUBU_R
, dec_subu_r
},
2960 {DEC_SUBS_R
, dec_subs_r
},
2961 {DEC_LSL_R
, dec_lsl_r
},
2963 {DEC_AND_R
, dec_and_r
},
2964 {DEC_OR_R
, dec_or_r
},
2965 {DEC_BOUND_R
, dec_bound_r
},
2966 {DEC_ASR_R
, dec_asr_r
},
2967 {DEC_LSR_R
, dec_lsr_r
},
2969 {DEC_MOVU_R
, dec_movu_r
},
2970 {DEC_MOVS_R
, dec_movs_r
},
2971 {DEC_NEG_R
, dec_neg_r
},
2972 {DEC_MOVE_R
, dec_move_r
},
2974 {DEC_FTAG_FIDX_I_M
, dec_ftag_fidx_i_m
},
2975 {DEC_FTAG_FIDX_D_M
, dec_ftag_fidx_d_m
},
2977 {DEC_MULS_R
, dec_muls_r
},
2978 {DEC_MULU_R
, dec_mulu_r
},
2980 {DEC_ADDU_M
, dec_addu_m
},
2981 {DEC_ADDS_M
, dec_adds_m
},
2982 {DEC_SUBU_M
, dec_subu_m
},
2983 {DEC_SUBS_M
, dec_subs_m
},
2985 {DEC_CMPU_M
, dec_cmpu_m
},
2986 {DEC_CMPS_M
, dec_cmps_m
},
2987 {DEC_MOVU_M
, dec_movu_m
},
2988 {DEC_MOVS_M
, dec_movs_m
},
2990 {DEC_CMP_M
, dec_cmp_m
},
2991 {DEC_ADDO_M
, dec_addo_m
},
2992 {DEC_BOUND_M
, dec_bound_m
},
2993 {DEC_ADD_M
, dec_add_m
},
2994 {DEC_SUB_M
, dec_sub_m
},
2995 {DEC_AND_M
, dec_and_m
},
2996 {DEC_OR_M
, dec_or_m
},
2997 {DEC_MOVE_RM
, dec_move_rm
},
2998 {DEC_TEST_M
, dec_test_m
},
2999 {DEC_MOVE_MR
, dec_move_mr
},
3004 static unsigned int crisv32_decoder(CPUCRISState
*env
, DisasContext
*dc
)
3009 /* Load a halfword onto the instruction register. */
3010 dc
->ir
= cris_fetch(env
, dc
, dc
->pc
, 2, 0);
3012 /* Now decode it. */
3013 dc
->opcode
= EXTRACT_FIELD(dc
->ir
, 4, 11);
3014 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 3);
3015 dc
->op2
= EXTRACT_FIELD(dc
->ir
, 12, 15);
3016 dc
->zsize
= EXTRACT_FIELD(dc
->ir
, 4, 4);
3017 dc
->zzsize
= EXTRACT_FIELD(dc
->ir
, 4, 5);
3018 dc
->postinc
= EXTRACT_FIELD(dc
->ir
, 10, 10);
3020 /* Large switch for all insns. */
3021 for (i
= 0; i
< ARRAY_SIZE(decinfo
); i
++) {
3022 if ((dc
->opcode
& decinfo
[i
].mask
) == decinfo
[i
].bits
) {
3023 insn_len
= decinfo
[i
].dec(env
, dc
);
3028 #if !defined(CONFIG_USER_ONLY)
3029 /* Single-stepping ? */
3030 if (dc
->tb_flags
& S_FLAG
) {
3031 TCGLabel
*l1
= gen_new_label();
3032 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_PR
[PR_SPC
], dc
->pc
, l1
);
3033 /* We treat SPC as a break with an odd trap vector. */
3034 cris_evaluate_flags(dc
);
3035 t_gen_mov_env_TN(trap_vector
, tcg_const_tl(3));
3036 tcg_gen_movi_tl(env_pc
, dc
->pc
+ insn_len
);
3037 tcg_gen_movi_tl(cpu_PR
[PR_SPC
], dc
->pc
+ insn_len
);
3038 t_gen_raise_exception(EXCP_BREAK
);
3045 #include "translate_v10.c"
3048 * Delay slots on QEMU/CRIS.
3050 * If an exception hits on a delayslot, the core will let ERP (the Exception
3051 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3052 * to give SW a hint that the exception actually hit on the dslot.
3054 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3055 * the core and any jmp to an odd addresses will mask off that lsb. It is
3056 * simply there to let sw know there was an exception on a dslot.
3058 * When the software returns from an exception, the branch will re-execute.
3059 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3060 * and the branch and delayslot don't share pages.
3062 * The TB contaning the branch insn will set up env->btarget and evaluate
3063 * env->btaken. When the translation loop exits we will note that the branch
3064 * sequence is broken and let env->dslot be the size of the branch insn (those
3067 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3068 * set). It will also expect to have env->dslot setup with the size of the
3069 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3070 * will execute the dslot and take the branch, either to btarget or just one
3073 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3074 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3075 * branch and set lsb). Then env->dslot gets cleared so that the exception
3076 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3077 * masked off and we will reexecute the branch insn.
3081 /* generate intermediate code for basic block 'tb'. */
3082 void gen_intermediate_code(CPUCRISState
*env
, struct TranslationBlock
*tb
)
3084 CRISCPU
*cpu
= cris_env_get_cpu(env
);
3085 CPUState
*cs
= CPU(cpu
);
3087 unsigned int insn_len
;
3088 struct DisasContext ctx
;
3089 struct DisasContext
*dc
= &ctx
;
3090 uint32_t next_page_start
;
3095 if (env
->pregs
[PR_VR
] == 32) {
3096 dc
->decoder
= crisv32_decoder
;
3097 dc
->clear_locked_irq
= 0;
3099 dc
->decoder
= crisv10_decoder
;
3100 dc
->clear_locked_irq
= 1;
3103 /* Odd PC indicates that branch is rexecuting due to exception in the
3104 * delayslot, like in real hw.
3106 pc_start
= tb
->pc
& ~1;
3110 dc
->is_jmp
= DISAS_NEXT
;
3113 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
3114 dc
->flags_uptodate
= 1;
3115 dc
->flagx_known
= 1;
3116 dc
->flags_x
= tb
->flags
& X_FLAG
;
3117 dc
->cc_x_uptodate
= 0;
3120 dc
->clear_prefix
= 0;
3122 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
3123 dc
->cc_size_uptodate
= -1;
3125 /* Decode TB flags. */
3126 dc
->tb_flags
= tb
->flags
& (S_FLAG
| P_FLAG
| U_FLAG \
3127 | X_FLAG
| PFIX_FLAG
);
3128 dc
->delayed_branch
= !!(tb
->flags
& 7);
3129 if (dc
->delayed_branch
) {
3130 dc
->jmp
= JMP_INDIRECT
;
3132 dc
->jmp
= JMP_NOJMP
;
3135 dc
->cpustate_changed
= 0;
3137 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
3139 "pc=%x %x flg=%" PRIx64
" bt=%x ds=%u ccs=%x\n"
3146 (uint64_t)tb
->flags
,
3147 env
->btarget
, (unsigned)tb
->flags
& 7,
3149 env
->pregs
[PR_PID
], env
->pregs
[PR_USP
],
3150 env
->regs
[0], env
->regs
[1], env
->regs
[2], env
->regs
[3],
3151 env
->regs
[4], env
->regs
[5], env
->regs
[6], env
->regs
[7],
3152 env
->regs
[8], env
->regs
[9],
3153 env
->regs
[10], env
->regs
[11],
3154 env
->regs
[12], env
->regs
[13],
3155 env
->regs
[14], env
->regs
[15]);
3156 qemu_log("--------------\n");
3157 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
3160 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
3162 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
3163 if (max_insns
== 0) {
3164 max_insns
= CF_COUNT_MASK
;
3166 if (max_insns
> TCG_MAX_INSNS
) {
3167 max_insns
= TCG_MAX_INSNS
;
3172 tcg_gen_insn_start(dc
->delayed_branch
== 1
3173 ? dc
->ppc
| 1 : dc
->pc
);
3176 if (unlikely(cpu_breakpoint_test(cs
, dc
->pc
, BP_ANY
))) {
3177 cris_evaluate_flags(dc
);
3178 tcg_gen_movi_tl(env_pc
, dc
->pc
);
3179 t_gen_raise_exception(EXCP_DEBUG
);
3180 dc
->is_jmp
= DISAS_UPDATE
;
3181 /* The address covered by the breakpoint must be included in
3182 [tb->pc, tb->pc + tb->size) in order to for it to be
3183 properly cleared -- thus we increment the PC here so that
3184 the logic setting tb->size below does the right thing. */
3190 LOG_DIS("%8.8x:\t", dc
->pc
);
3192 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
3197 insn_len
= dc
->decoder(env
, dc
);
3201 cris_clear_x_flag(dc
);
3204 /* Check for delayed branches here. If we do it before
3205 actually generating any host code, the simulator will just
3206 loop doing nothing for on this program location. */
3207 if (dc
->delayed_branch
) {
3208 dc
->delayed_branch
--;
3209 if (dc
->delayed_branch
== 0) {
3210 if (tb
->flags
& 7) {
3211 t_gen_mov_env_TN(dslot
, tcg_const_tl(0));
3213 if (dc
->cpustate_changed
|| !dc
->flagx_known
3214 || (dc
->flags_x
!= (tb
->flags
& X_FLAG
))) {
3215 cris_store_direct_jmp(dc
);
3218 if (dc
->clear_locked_irq
) {
3219 dc
->clear_locked_irq
= 0;
3220 t_gen_mov_env_TN(locked_irq
, tcg_const_tl(0));
3223 if (dc
->jmp
== JMP_DIRECT_CC
) {
3224 TCGLabel
*l1
= gen_new_label();
3225 cris_evaluate_flags(dc
);
3227 /* Conditional jmp. */
3228 tcg_gen_brcondi_tl(TCG_COND_EQ
,
3230 gen_goto_tb(dc
, 1, dc
->jmp_pc
);
3232 gen_goto_tb(dc
, 0, dc
->pc
);
3233 dc
->is_jmp
= DISAS_TB_JUMP
;
3234 dc
->jmp
= JMP_NOJMP
;
3235 } else if (dc
->jmp
== JMP_DIRECT
) {
3236 cris_evaluate_flags(dc
);
3237 gen_goto_tb(dc
, 0, dc
->jmp_pc
);
3238 dc
->is_jmp
= DISAS_TB_JUMP
;
3239 dc
->jmp
= JMP_NOJMP
;
3241 t_gen_cc_jmp(env_btarget
, tcg_const_tl(dc
->pc
));
3242 dc
->is_jmp
= DISAS_JUMP
;
3248 /* If we are rexecuting a branch due to exceptions on
3249 delay slots don't break. */
3250 if (!(tb
->pc
& 1) && cs
->singlestep_enabled
) {
3253 } while (!dc
->is_jmp
&& !dc
->cpustate_changed
3254 && !tcg_op_buf_full()
3256 && (dc
->pc
< next_page_start
)
3257 && num_insns
< max_insns
);
3259 if (dc
->clear_locked_irq
) {
3260 t_gen_mov_env_TN(locked_irq
, tcg_const_tl(0));
3265 if (tb
->cflags
& CF_LAST_IO
)
3267 /* Force an update if the per-tb cpu state has changed. */
3268 if (dc
->is_jmp
== DISAS_NEXT
3269 && (dc
->cpustate_changed
|| !dc
->flagx_known
3270 || (dc
->flags_x
!= (tb
->flags
& X_FLAG
)))) {
3271 dc
->is_jmp
= DISAS_UPDATE
;
3272 tcg_gen_movi_tl(env_pc
, npc
);
3274 /* Broken branch+delayslot sequence. */
3275 if (dc
->delayed_branch
== 1) {
3276 /* Set env->dslot to the size of the branch insn. */
3277 t_gen_mov_env_TN(dslot
, tcg_const_tl(dc
->pc
- dc
->ppc
));
3278 cris_store_direct_jmp(dc
);
3281 cris_evaluate_flags(dc
);
3283 if (unlikely(cs
->singlestep_enabled
)) {
3284 if (dc
->is_jmp
== DISAS_NEXT
) {
3285 tcg_gen_movi_tl(env_pc
, npc
);
3287 t_gen_raise_exception(EXCP_DEBUG
);
3289 switch (dc
->is_jmp
) {
3291 gen_goto_tb(dc
, 1, npc
);
3296 /* indicate that the hash table must be used
3297 to find the next TB */
3302 /* nothing more to generate */
3306 gen_tb_end(tb
, num_insns
);
3308 tb
->size
= dc
->pc
- pc_start
;
3309 tb
->icount
= num_insns
;
3313 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
3314 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
,
3316 qemu_log("\nisize=%d osize=%d\n",
3317 dc
->pc
- pc_start
, tcg_op_buf_count());
3323 void cris_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
3326 CRISCPU
*cpu
= CRIS_CPU(cs
);
3327 CPUCRISState
*env
= &cpu
->env
;
3335 cpu_fprintf(f
, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3336 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3337 env
->pc
, env
->pregs
[PR_CCS
], env
->btaken
, env
->btarget
,
3339 env
->cc_src
, env
->cc_dest
, env
->cc_result
, env
->cc_mask
);
3342 for (i
= 0; i
< 16; i
++) {
3343 cpu_fprintf(f
, "%s=%8.8x ", regnames
[i
], env
->regs
[i
]);
3344 if ((i
+ 1) % 4 == 0) {
3345 cpu_fprintf(f
, "\n");
3348 cpu_fprintf(f
, "\nspecial regs:\n");
3349 for (i
= 0; i
< 16; i
++) {
3350 cpu_fprintf(f
, "%s=%8.8x ", pregnames
[i
], env
->pregs
[i
]);
3351 if ((i
+ 1) % 4 == 0) {
3352 cpu_fprintf(f
, "\n");
3355 srs
= env
->pregs
[PR_SRS
];
3356 cpu_fprintf(f
, "\nsupport function regs bank %x:\n", srs
);
3357 if (srs
< ARRAY_SIZE(env
->sregs
)) {
3358 for (i
= 0; i
< 16; i
++) {
3359 cpu_fprintf(f
, "s%2.2d=%8.8x ",
3360 i
, env
->sregs
[srs
][i
]);
3361 if ((i
+ 1) % 4 == 0) {
3362 cpu_fprintf(f
, "\n");
3366 cpu_fprintf(f
, "\n\n");
3370 void cris_initialize_tcg(void)
3374 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
3375 cc_x
= tcg_global_mem_new(cpu_env
,
3376 offsetof(CPUCRISState
, cc_x
), "cc_x");
3377 cc_src
= tcg_global_mem_new(cpu_env
,
3378 offsetof(CPUCRISState
, cc_src
), "cc_src");
3379 cc_dest
= tcg_global_mem_new(cpu_env
,
3380 offsetof(CPUCRISState
, cc_dest
),
3382 cc_result
= tcg_global_mem_new(cpu_env
,
3383 offsetof(CPUCRISState
, cc_result
),
3385 cc_op
= tcg_global_mem_new(cpu_env
,
3386 offsetof(CPUCRISState
, cc_op
), "cc_op");
3387 cc_size
= tcg_global_mem_new(cpu_env
,
3388 offsetof(CPUCRISState
, cc_size
),
3390 cc_mask
= tcg_global_mem_new(cpu_env
,
3391 offsetof(CPUCRISState
, cc_mask
),
3394 env_pc
= tcg_global_mem_new(cpu_env
,
3395 offsetof(CPUCRISState
, pc
),
3397 env_btarget
= tcg_global_mem_new(cpu_env
,
3398 offsetof(CPUCRISState
, btarget
),
3400 env_btaken
= tcg_global_mem_new(cpu_env
,
3401 offsetof(CPUCRISState
, btaken
),
3403 for (i
= 0; i
< 16; i
++) {
3404 cpu_R
[i
] = tcg_global_mem_new(cpu_env
,
3405 offsetof(CPUCRISState
, regs
[i
]),
3408 for (i
= 0; i
< 16; i
++) {
3409 cpu_PR
[i
] = tcg_global_mem_new(cpu_env
,
3410 offsetof(CPUCRISState
, pregs
[i
]),
3415 void restore_state_to_opc(CPUCRISState
*env
, TranslationBlock
*tb
,