target-sh4/helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20
  21 #include "cpu.h"
  22 #include "exec/exec-all.h"
  23 #include "exec/log.h"
  24
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "hw/sh4/sh_intc.h"
  27 #endif
  28
  29 #if defined(CONFIG_USER_ONLY)
  30
  31 void superh_cpu_do_interrupt(CPUState *cs)
  32 {
  33     cs->exception_index = -1;
  34 }
  35
  36 int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  37                                 int mmu_idx)
  38 {
  39     SuperHCPU *cpu = SUPERH_CPU(cs);
  40     CPUSH4State *env = &cpu->env;
  41
  42     env->tea = address;
  43     cs->exception_index = -1;
  44     switch (rw) {
  45     case 0:
  46         cs->exception_index = 0x0a0;
  47         break;
  48     case 1:
  49         cs->exception_index = 0x0c0;
  50         break;
  51     case 2:
  52         cs->exception_index = 0x0a0;
  53         break;
  54     }
  55     return 1;
  56 }
  57
  58 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
  59 {
  60     /* For user mode, only U0 area is cacheable. */
  61     return !(addr & 0x80000000);
  62 }
  63
  64 #else /* !CONFIG_USER_ONLY */
  65
  66 #define MMU_OK                   0
  67 #define MMU_ITLB_MISS            (-1)
  68 #define MMU_ITLB_MULTIPLE        (-2)
  69 #define MMU_ITLB_VIOLATION       (-3)
  70 #define MMU_DTLB_MISS_READ       (-4)
  71 #define MMU_DTLB_MISS_WRITE      (-5)
  72 #define MMU_DTLB_INITIAL_WRITE   (-6)
  73 #define MMU_DTLB_VIOLATION_READ  (-7)
  74 #define MMU_DTLB_VIOLATION_WRITE (-8)
  75 #define MMU_DTLB_MULTIPLE        (-9)
  76 #define MMU_DTLB_MISS            (-10)
  77 #define MMU_IADDR_ERROR          (-11)
  78 #define MMU_DADDR_ERROR_READ     (-12)
  79 #define MMU_DADDR_ERROR_WRITE    (-13)
  80
  81 void superh_cpu_do_interrupt(CPUState *cs)
  82 {
  83     SuperHCPU *cpu = SUPERH_CPU(cs);
  84     CPUSH4State *env = &cpu->env;
  85     int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
  86     int do_exp, irq_vector = cs->exception_index;
  87
  88     /* prioritize exceptions over interrupts */
  89
  90     do_exp = cs->exception_index != -1;
  91     do_irq = do_irq && (cs->exception_index == -1);
  92
  93     if (env->sr & (1u << SR_BL)) {
  94         if (do_exp && cs->exception_index != 0x1e0) {
  95             cs->exception_index = 0x000; /* masked exception -> reset */
  96         }
  97         if (do_irq && !env->in_sleep) {
  98             return; /* masked */
  99         }
 100     }
 101     env->in_sleep = 0;
 102
 103     if (do_irq) {
 104         irq_vector = sh_intc_get_pending_vector(env->intc_handle,
 105                                                 (env->sr >> 4) & 0xf);
 106         if (irq_vector == -1) {
 107             return; /* masked */
 108         }
 109     }
 110
 111     if (qemu_loglevel_mask(CPU_LOG_INT)) {
 112         const char *expname;
 113         switch (cs->exception_index) {
 114         case 0x0e0:
 115             expname = "addr_error";
 116             break;
 117         case 0x040:
 118             expname = "tlb_miss";
 119             break;
 120         case 0x0a0:
 121             expname = "tlb_violation";
 122             break;
 123         case 0x180:
 124             expname = "illegal_instruction";
 125             break;
 126         case 0x1a0:
 127             expname = "slot_illegal_instruction";
 128             break;
 129         case 0x800:
 130             expname = "fpu_disable";
 131             break;
 132         case 0x820:
 133             expname = "slot_fpu";
 134             break;
 135         case 0x100:
 136             expname = "data_write";
 137             break;
 138         case 0x060:
 139             expname = "dtlb_miss_write";
 140             break;
 141         case 0x0c0:
 142             expname = "dtlb_violation_write";
 143             break;
 144         case 0x120:
 145             expname = "fpu_exception";
 146             break;
 147         case 0x080:
 148             expname = "initial_page_write";
 149             break;
 150         case 0x160:
 151             expname = "trapa";
 152             break;
 153         default:
 154             expname = do_irq ? "interrupt" : "???";
 155             break;
 156         }
 157         qemu_log("exception 0x%03x [%s] raised\n",
 158                   irq_vector, expname);
 159         log_cpu_state(cs, 0);
 160     }
 161
 162     env->ssr = cpu_read_sr(env);
 163     env->spc = env->pc;
 164     env->sgr = env->gregs[15];
 165     env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB);
 166
 167     if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
 168         /* Branch instruction should be executed again before delay slot. */
 169         env->spc -= 2;
 170         /* Clear flags for exception/interrupt routine. */
 171         env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
 172     }
 173     if (env->flags & DELAY_SLOT_CLEARME)
 174         env->flags = 0;
 175
 176     if (do_exp) {
 177         env->expevt = cs->exception_index;
 178         switch (cs->exception_index) {
 179         case 0x000:
 180         case 0x020:
 181         case 0x140:
 182             env->sr &= ~(1u << SR_FD);
 183             env->sr |= 0xf << 4; /* IMASK */
 184             env->pc = 0xa0000000;
 185             break;
 186         case 0x040:
 187         case 0x060:
 188             env->pc = env->vbr + 0x400;
 189             break;
 190         case 0x160:
 191             env->spc += 2; /* special case for TRAPA */
 192             /* fall through */
 193         default:
 194             env->pc = env->vbr + 0x100;
 195             break;
 196         }
 197         return;
 198     }
 199
 200     if (do_irq) {
 201         env->intevt = irq_vector;
 202         env->pc = env->vbr + 0x600;
 203         return;
 204     }
 205 }
 206
 207 static void update_itlb_use(CPUSH4State * env, int itlbnb)
 208 {
 209     uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
 210
 211     switch (itlbnb) {
 212     case 0:
 213         and_mask = 0x1f;
 214         break;
 215     case 1:
 216         and_mask = 0xe7;
 217         or_mask = 0x80;
 218         break;
 219     case 2:
 220         and_mask = 0xfb;
 221         or_mask = 0x50;
 222         break;
 223     case 3:
 224         or_mask = 0x2c;
 225         break;
 226     }
 227
 228     env->mmucr &= (and_mask << 24) | 0x00ffffff;
 229     env->mmucr |= (or_mask << 24);
 230 }
 231
 232 static int itlb_replacement(CPUSH4State * env)
 233 {
 234     SuperHCPU *cpu = sh_env_get_cpu(env);
 235
 236     if ((env->mmucr & 0xe0000000) == 0xe0000000) {
 237         return 0;
 238     }
 239     if ((env->mmucr & 0x98000000) == 0x18000000) {
 240         return 1;
 241     }
 242     if ((env->mmucr & 0x54000000) == 0x04000000) {
 243         return 2;
 244     }
 245     if ((env->mmucr & 0x2c000000) == 0x00000000) {
 246         return 3;
 247     }
 248     cpu_abort(CPU(cpu), "Unhandled itlb_replacement");
 249 }
 250
 251 /* Find the corresponding entry in the right TLB
 252    Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
 253 */
 254 static int find_tlb_entry(CPUSH4State * env, target_ulong address,
 255                           tlb_t * entries, uint8_t nbtlb, int use_asid)
 256 {
 257     int match = MMU_DTLB_MISS;
 258     uint32_t start, end;
 259     uint8_t asid;
 260     int i;
 261
 262     asid = env->pteh & 0xff;
 263
 264     for (i = 0; i < nbtlb; i++) {
 265         if (!entries[i].v)
 266             continue;           /* Invalid entry */
 267         if (!entries[i].sh && use_asid && entries[i].asid != asid)
 268             continue;           /* Bad ASID */
 269         start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
 270         end = start + entries[i].size - 1;
 271         if (address >= start && address <= end) {       /* Match */
 272             if (match != MMU_DTLB_MISS)
 273                 return MMU_DTLB_MULTIPLE;       /* Multiple match */
 274             match = i;
 275         }
 276     }
 277     return match;
 278 }
 279
 280 static void increment_urc(CPUSH4State * env)
 281 {
 282     uint8_t urb, urc;
 283
 284     /* Increment URC */
 285     urb = ((env->mmucr) >> 18) & 0x3f;
 286     urc = ((env->mmucr) >> 10) & 0x3f;
 287     urc++;
 288     if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
 289         urc = 0;
 290     env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
 291 }
 292
 293 /* Copy and utlb entry into itlb
 294    Return entry
 295 */
 296 static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
 297 {
 298     int itlb;
 299
 300     tlb_t * ientry;
 301     itlb = itlb_replacement(env);
 302     ientry = &env->itlb[itlb];
 303     if (ientry->v) {
 304         tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10);
 305     }
 306     *ientry = env->utlb[utlb];
 307     update_itlb_use(env, itlb);
 308     return itlb;
 309 }
 310
 311 /* Find itlb entry
 312    Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
 313 */
 314 static int find_itlb_entry(CPUSH4State * env, target_ulong address,
 315                            int use_asid)
 316 {
 317     int e;
 318
 319     e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
 320     if (e == MMU_DTLB_MULTIPLE) {
 321         e = MMU_ITLB_MULTIPLE;
 322     } else if (e == MMU_DTLB_MISS) {
 323         e = MMU_ITLB_MISS;
 324     } else if (e >= 0) {
 325         update_itlb_use(env, e);
 326     }
 327     return e;
 328 }
 329
 330 /* Find utlb entry
 331    Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
 332 static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
 333 {
 334     /* per utlb access */
 335     increment_urc(env);
 336
 337     /* Return entry */
 338     return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
 339 }
 340
 341 /* Match address against MMU
 342    Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
 343    MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
 344    MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
 345    MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
 346    MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
 347 */
 348 static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
 349                            int *prot, target_ulong address,
 350                            int rw, int access_type)
 351 {
 352     int use_asid, n;
 353     tlb_t *matching = NULL;
 354
 355     use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
 356
 357     if (rw == 2) {
 358         n = find_itlb_entry(env, address, use_asid);
 359         if (n >= 0) {
 360             matching = &env->itlb[n];
 361             if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
 362                 n = MMU_ITLB_VIOLATION;
 363             } else {
 364                 *prot = PAGE_EXEC;
 365             }
 366         } else {
 367             n = find_utlb_entry(env, address, use_asid);
 368             if (n >= 0) {
 369                 n = copy_utlb_entry_itlb(env, n);
 370                 matching = &env->itlb[n];
 371                 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
 372                     n = MMU_ITLB_VIOLATION;
 373                 } else {
 374                     *prot = PAGE_READ | PAGE_EXEC;
 375                     if ((matching->pr & 1) && matching->d) {
 376                         *prot |= PAGE_WRITE;
 377                     }
 378                 }
 379             } else if (n == MMU_DTLB_MULTIPLE) {
 380                 n = MMU_ITLB_MULTIPLE;
 381             } else if (n == MMU_DTLB_MISS) {
 382                 n = MMU_ITLB_MISS;
 383             }
 384         }
 385     } else {
 386         n = find_utlb_entry(env, address, use_asid);
 387         if (n >= 0) {
 388             matching = &env->utlb[n];
 389             if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
 390                 n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
 391                     MMU_DTLB_VIOLATION_READ;
 392             } else if ((rw == 1) && !(matching->pr & 1)) {
 393                 n = MMU_DTLB_VIOLATION_WRITE;
 394             } else if ((rw == 1) && !matching->d) {
 395                 n = MMU_DTLB_INITIAL_WRITE;
 396             } else {
 397                 *prot = PAGE_READ;
 398                 if ((matching->pr & 1) && matching->d) {
 399                     *prot |= PAGE_WRITE;
 400                 }
 401             }
 402         } else if (n == MMU_DTLB_MISS) {
 403             n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
 404                 MMU_DTLB_MISS_READ;
 405         }
 406     }
 407     if (n >= 0) {
 408         n = MMU_OK;
 409         *physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
 410             (address & (matching->size - 1));
 411     }
 412     return n;
 413 }
 414
 415 static int get_physical_address(CPUSH4State * env, target_ulong * physical,
 416                                 int *prot, target_ulong address,
 417                                 int rw, int access_type)
 418 {
 419     /* P1, P2 and P4 areas do not use translation */
 420     if ((address >= 0x80000000 && address < 0xc0000000) ||
 421         address >= 0xe0000000) {
 422         if (!(env->sr & (1u << SR_MD))
 423             && (address < 0xe0000000 || address >= 0xe4000000)) {
 424             /* Unauthorized access in user mode (only store queues are available) */
 425             fprintf(stderr, "Unauthorized access\n");
 426             if (rw == 0)
 427                 return MMU_DADDR_ERROR_READ;
 428             else if (rw == 1)
 429                 return MMU_DADDR_ERROR_WRITE;
 430             else
 431                 return MMU_IADDR_ERROR;
 432         }
 433         if (address >= 0x80000000 && address < 0xc0000000) {
 434             /* Mask upper 3 bits for P1 and P2 areas */
 435             *physical = address & 0x1fffffff;
 436         } else {
 437             *physical = address;
 438         }
 439         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 440         return MMU_OK;
 441     }
 442
 443     /* If MMU is disabled, return the corresponding physical page */
 444     if (!(env->mmucr & MMUCR_AT)) {
 445         *physical = address & 0x1FFFFFFF;
 446         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 447         return MMU_OK;
 448     }
 449
 450     /* We need to resort to the MMU */
 451     return get_mmu_address(env, physical, prot, address, rw, access_type);
 452 }
 453
 454 int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
 455                                 int mmu_idx)
 456 {
 457     SuperHCPU *cpu = SUPERH_CPU(cs);
 458     CPUSH4State *env = &cpu->env;
 459     target_ulong physical;
 460     int prot, ret, access_type;
 461
 462     access_type = ACCESS_INT;
 463     ret =
 464         get_physical_address(env, &physical, &prot, address, rw,
 465                              access_type);
 466
 467     if (ret != MMU_OK) {
 468         env->tea = address;
 469         if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) {
 470             env->pteh = (env->pteh & PTEH_ASID_MASK) |
 471                     (address & PTEH_VPN_MASK);
 472         }
 473         switch (ret) {
 474         case MMU_ITLB_MISS:
 475         case MMU_DTLB_MISS_READ:
 476             cs->exception_index = 0x040;
 477             break;
 478         case MMU_DTLB_MULTIPLE:
 479         case MMU_ITLB_MULTIPLE:
 480             cs->exception_index = 0x140;
 481             break;
 482         case MMU_ITLB_VIOLATION:
 483             cs->exception_index = 0x0a0;
 484             break;
 485         case MMU_DTLB_MISS_WRITE:
 486             cs->exception_index = 0x060;
 487             break;
 488         case MMU_DTLB_INITIAL_WRITE:
 489             cs->exception_index = 0x080;
 490             break;
 491         case MMU_DTLB_VIOLATION_READ:
 492             cs->exception_index = 0x0a0;
 493             break;
 494         case MMU_DTLB_VIOLATION_WRITE:
 495             cs->exception_index = 0x0c0;
 496             break;
 497         case MMU_IADDR_ERROR:
 498         case MMU_DADDR_ERROR_READ:
 499             cs->exception_index = 0x0e0;
 500             break;
 501         case MMU_DADDR_ERROR_WRITE:
 502             cs->exception_index = 0x100;
 503             break;
 504         default:
 505             cpu_abort(cs, "Unhandled MMU fault");
 506         }
 507         return 1;
 508     }
 509
 510     address &= TARGET_PAGE_MASK;
 511     physical &= TARGET_PAGE_MASK;
 512
 513     tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
 514     return 0;
 515 }
 516
 517 hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 518 {
 519     SuperHCPU *cpu = SUPERH_CPU(cs);
 520     target_ulong physical;
 521     int prot;
 522
 523     get_physical_address(&cpu->env, &physical, &prot, addr, 0, 0);
 524     return physical;
 525 }
 526
 527 void cpu_load_tlb(CPUSH4State * env)
 528 {
 529     SuperHCPU *cpu = sh_env_get_cpu(env);
 530     int n = cpu_mmucr_urc(env->mmucr);
 531     tlb_t * entry = &env->utlb[n];
 532
 533     if (entry->v) {
 534         /* Overwriting valid entry in utlb. */
 535         target_ulong address = entry->vpn << 10;
 536         tlb_flush_page(CPU(cpu), address);
 537     }
 538
 539     /* Take values into cpu status from registers. */
 540     entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
 541     entry->vpn  = cpu_pteh_vpn(env->pteh);
 542     entry->v    = (uint8_t)cpu_ptel_v(env->ptel);
 543     entry->ppn  = cpu_ptel_ppn(env->ptel);
 544     entry->sz   = (uint8_t)cpu_ptel_sz(env->ptel);
 545     switch (entry->sz) {
 546     case 0: /* 00 */
 547         entry->size = 1024; /* 1K */
 548         break;
 549     case 1: /* 01 */
 550         entry->size = 1024 * 4; /* 4K */
 551         break;
 552     case 2: /* 10 */
 553         entry->size = 1024 * 64; /* 64K */
 554         break;
 555     case 3: /* 11 */
 556         entry->size = 1024 * 1024; /* 1M */
 557         break;
 558     default:
 559         cpu_abort(CPU(cpu), "Unhandled load_tlb");
 560         break;
 561     }
 562     entry->sh   = (uint8_t)cpu_ptel_sh(env->ptel);
 563     entry->c    = (uint8_t)cpu_ptel_c(env->ptel);
 564     entry->pr   = (uint8_t)cpu_ptel_pr(env->ptel);
 565     entry->d    = (uint8_t)cpu_ptel_d(env->ptel);
 566     entry->wt   = (uint8_t)cpu_ptel_wt(env->ptel);
 567     entry->sa   = (uint8_t)cpu_ptea_sa(env->ptea);
 568     entry->tc   = (uint8_t)cpu_ptea_tc(env->ptea);
 569 }
 570
 571  void cpu_sh4_invalidate_tlb(CPUSH4State *s)
 572 {
 573     int i;
 574
 575     /* UTLB */
 576     for (i = 0; i < UTLB_SIZE; i++) {
 577         tlb_t * entry = &s->utlb[i];
 578         entry->v = 0;
 579     }
 580     /* ITLB */
 581     for (i = 0; i < ITLB_SIZE; i++) {
 582         tlb_t * entry = &s->itlb[i];
 583         entry->v = 0;
 584     }
 585
 586     tlb_flush(CPU(sh_env_get_cpu(s)), 1);
 587 }
 588
 589 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
 590                                        hwaddr addr)
 591 {
 592     int index = (addr & 0x00000300) >> 8;
 593     tlb_t * entry = &s->itlb[index];
 594
 595     return (entry->vpn  << 10) |
 596            (entry->v    <<  8) |
 597            (entry->asid);
 598 }
 599
 600 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
 601                                     uint32_t mem_value)
 602 {
 603     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
 604     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
 605     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
 606
 607     int index = (addr & 0x00000300) >> 8;
 608     tlb_t * entry = &s->itlb[index];
 609     if (entry->v) {
 610         /* Overwriting valid entry in itlb. */
 611         target_ulong address = entry->vpn << 10;
 612         tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
 613     }
 614     entry->asid = asid;
 615     entry->vpn = vpn;
 616     entry->v = v;
 617 }
 618
 619 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
 620                                        hwaddr addr)
 621 {
 622     int array = (addr & 0x00800000) >> 23;
 623     int index = (addr & 0x00000300) >> 8;
 624     tlb_t * entry = &s->itlb[index];
 625
 626     if (array == 0) {
 627         /* ITLB Data Array 1 */
 628         return (entry->ppn << 10) |
 629                (entry->v   <<  8) |
 630                (entry->pr  <<  5) |
 631                ((entry->sz & 1) <<  6) |
 632                ((entry->sz & 2) <<  4) |
 633                (entry->c   <<  3) |
 634                (entry->sh  <<  1);
 635     } else {
 636         /* ITLB Data Array 2 */
 637         return (entry->tc << 1) |
 638                (entry->sa);
 639     }
 640 }
 641
 642 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
 643                                     uint32_t mem_value)
 644 {
 645     int array = (addr & 0x00800000) >> 23;
 646     int index = (addr & 0x00000300) >> 8;
 647     tlb_t * entry = &s->itlb[index];
 648
 649     if (array == 0) {
 650         /* ITLB Data Array 1 */
 651         if (entry->v) {
 652             /* Overwriting valid entry in utlb. */
 653             target_ulong address = entry->vpn << 10;
 654             tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
 655         }
 656         entry->ppn = (mem_value & 0x1ffffc00) >> 10;
 657         entry->v   = (mem_value & 0x00000100) >> 8;
 658         entry->sz  = (mem_value & 0x00000080) >> 6 |
 659                      (mem_value & 0x00000010) >> 4;
 660         entry->pr  = (mem_value & 0x00000040) >> 5;
 661         entry->c   = (mem_value & 0x00000008) >> 3;
 662         entry->sh  = (mem_value & 0x00000002) >> 1;
 663     } else {
 664         /* ITLB Data Array 2 */
 665         entry->tc  = (mem_value & 0x00000008) >> 3;
 666         entry->sa  = (mem_value & 0x00000007);
 667     }
 668 }
 669
 670 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
 671                                        hwaddr addr)
 672 {
 673     int index = (addr & 0x00003f00) >> 8;
 674     tlb_t * entry = &s->utlb[index];
 675
 676     increment_urc(s); /* per utlb access */
 677
 678     return (entry->vpn  << 10) |
 679            (entry->v    <<  8) |
 680            (entry->asid);
 681 }
 682
 683 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
 684                                     uint32_t mem_value)
 685 {
 686     int associate = addr & 0x0000080;
 687     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
 688     uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
 689     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
 690     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
 691     int use_asid = !(s->mmucr & MMUCR_SV) || !(s->sr & (1u << SR_MD));
 692
 693     if (associate) {
 694         int i;
 695         tlb_t * utlb_match_entry = NULL;
 696         int needs_tlb_flush = 0;
 697
 698         /* search UTLB */
 699         for (i = 0; i < UTLB_SIZE; i++) {
 700             tlb_t * entry = &s->utlb[i];
 701             if (!entry->v)
 702                 continue;
 703
 704             if (entry->vpn == vpn
 705                 && (!use_asid || entry->asid == asid || entry->sh)) {
 706                 if (utlb_match_entry) {
 707                     CPUState *cs = CPU(sh_env_get_cpu(s));
 708
 709                     /* Multiple TLB Exception */
 710                     cs->exception_index = 0x140;
 711                     s->tea = addr;
 712                     break;
 713                 }
 714                 if (entry->v && !v)
 715                     needs_tlb_flush = 1;
 716                 entry->v = v;
 717                 entry->d = d;
 718                 utlb_match_entry = entry;
 719             }
 720             increment_urc(s); /* per utlb access */
 721         }
 722
 723         /* search ITLB */
 724         for (i = 0; i < ITLB_SIZE; i++) {
 725             tlb_t * entry = &s->itlb[i];
 726             if (entry->vpn == vpn
 727                 && (!use_asid || entry->asid == asid || entry->sh)) {
 728                 if (entry->v && !v)
 729                     needs_tlb_flush = 1;
 730                 if (utlb_match_entry)
 731                     *entry = *utlb_match_entry;
 732                 else
 733                     entry->v = v;
 734                 break;
 735             }
 736         }
 737
 738         if (needs_tlb_flush) {
 739             tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10);
 740         }
 741
 742     } else {
 743         int index = (addr & 0x00003f00) >> 8;
 744         tlb_t * entry = &s->utlb[index];
 745         if (entry->v) {
 746             CPUState *cs = CPU(sh_env_get_cpu(s));
 747
 748             /* Overwriting valid entry in utlb. */
 749             target_ulong address = entry->vpn << 10;
 750             tlb_flush_page(cs, address);
 751         }
 752         entry->asid = asid;
 753         entry->vpn = vpn;
 754         entry->d = d;
 755         entry->v = v;
 756         increment_urc(s);
 757     }
 758 }
 759
 760 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
 761                                        hwaddr addr)
 762 {
 763     int array = (addr & 0x00800000) >> 23;
 764     int index = (addr & 0x00003f00) >> 8;
 765     tlb_t * entry = &s->utlb[index];
 766
 767     increment_urc(s); /* per utlb access */
 768
 769     if (array == 0) {
 770         /* ITLB Data Array 1 */
 771         return (entry->ppn << 10) |
 772                (entry->v   <<  8) |
 773                (entry->pr  <<  5) |
 774                ((entry->sz & 1) <<  6) |
 775                ((entry->sz & 2) <<  4) |
 776                (entry->c   <<  3) |
 777                (entry->d   <<  2) |
 778                (entry->sh  <<  1) |
 779                (entry->wt);
 780     } else {
 781         /* ITLB Data Array 2 */
 782         return (entry->tc << 1) |
 783                (entry->sa);
 784     }
 785 }
 786
 787 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
 788                                     uint32_t mem_value)
 789 {
 790     int array = (addr & 0x00800000) >> 23;
 791     int index = (addr & 0x00003f00) >> 8;
 792     tlb_t * entry = &s->utlb[index];
 793
 794     increment_urc(s); /* per utlb access */
 795
 796     if (array == 0) {
 797         /* UTLB Data Array 1 */
 798         if (entry->v) {
 799             /* Overwriting valid entry in utlb. */
 800             target_ulong address = entry->vpn << 10;
 801             tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
 802         }
 803         entry->ppn = (mem_value & 0x1ffffc00) >> 10;
 804         entry->v   = (mem_value & 0x00000100) >> 8;
 805         entry->sz  = (mem_value & 0x00000080) >> 6 |
 806                      (mem_value & 0x00000010) >> 4;
 807         entry->pr  = (mem_value & 0x00000060) >> 5;
 808         entry->c   = (mem_value & 0x00000008) >> 3;
 809         entry->d   = (mem_value & 0x00000004) >> 2;
 810         entry->sh  = (mem_value & 0x00000002) >> 1;
 811         entry->wt  = (mem_value & 0x00000001);
 812     } else {
 813         /* UTLB Data Array 2 */
 814         entry->tc = (mem_value & 0x00000008) >> 3;
 815         entry->sa = (mem_value & 0x00000007);
 816     }
 817 }
 818
 819 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
 820 {
 821     int n;
 822     int use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
 823
 824     /* check area */
 825     if (env->sr & (1u << SR_MD)) {
 826         /* For privileged mode, P2 and P4 area is not cacheable. */
 827         if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
 828             return 0;
 829     } else {
 830         /* For user mode, only U0 area is cacheable. */
 831         if (0x80000000 <= addr)
 832             return 0;
 833     }
 834
 835     /*
 836      * TODO : Evaluate CCR and check if the cache is on or off.
 837      *        Now CCR is not in CPUSH4State, but in SH7750State.
 838      *        When you move the ccr into CPUSH4State, the code will be
 839      *        as follows.
 840      */
 841 #if 0
 842     /* check if operand cache is enabled or not. */
 843     if (!(env->ccr & 1))
 844         return 0;
 845 #endif
 846
 847     /* if MMU is off, no check for TLB. */
 848     if (env->mmucr & MMUCR_AT)
 849         return 1;
 850
 851     /* check TLB */
 852     n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
 853     if (n >= 0)
 854         return env->itlb[n].c;
 855
 856     n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
 857     if (n >= 0)
 858         return env->utlb[n].c;
 859
 860     return 0;
 861 }
 862
 863 #endif
 864
 865 bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 866 {
 867     if (interrupt_request & CPU_INTERRUPT_HARD) {
 868         superh_cpu_do_interrupt(cs);
 869         return true;
 870     }
 871     return false;
 872 }