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[qemu/kevin.git] / target-sparc / op_helper.c
blob5890f2902d7ff5448b75bc86b26a0655e91d0912
1 #include "exec.h"
2 #include "host-utils.h"
3 #include "helper.h"
4 #if !defined(CONFIG_USER_ONLY)
5 #include "softmmu_exec.h"
6 #endif /* !defined(CONFIG_USER_ONLY) */
7
8 //#define DEBUG_MMU
9 //#define DEBUG_MXCC
10 //#define DEBUG_UNALIGNED
11 //#define DEBUG_UNASSIGNED
12 //#define DEBUG_ASI
13 //#define DEBUG_PCALL
14
15 #ifdef DEBUG_MMU
16 #define DPRINTF_MMU(fmt, args...) \
17 do { printf("MMU: " fmt , ##args); } while (0)
18 #else
19 #define DPRINTF_MMU(fmt, args...) do {} while (0)
20 #endif
21
22 #ifdef DEBUG_MXCC
23 #define DPRINTF_MXCC(fmt, args...) \
24 do { printf("MXCC: " fmt , ##args); } while (0)
25 #else
26 #define DPRINTF_MXCC(fmt, args...) do {} while (0)
27 #endif
28
29 #ifdef DEBUG_ASI
30 #define DPRINTF_ASI(fmt, args...) \
31 do { printf("ASI: " fmt , ##args); } while (0)
32 #endif
33
34 #ifdef TARGET_SPARC64
35 #ifndef TARGET_ABI32
36 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
37 #else
38 #define AM_CHECK(env1) (1)
39 #endif
40 #endif
41
42 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
43 // Calculates TSB pointer value for fault page size 8k or 64k
44 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
45 uint64_t tag_access_register,
46 int page_size)
47 {
48 uint64_t tsb_base = tsb_register & ~0x1fffULL;
49 int tsb_split = (env->dmmuregs[5] & 0x1000ULL) ? 1 : 0;
50 int tsb_size = env->dmmuregs[5] & 0xf;
51
52 // discard lower 13 bits which hold tag access context
53 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
54
55 // now reorder bits
56 uint64_t tsb_base_mask = ~0x1fffULL;
57 uint64_t va = tag_access_va;
58
59 // move va bits to correct position
60 if (page_size == 8*1024) {
61 va >>= 9;
62 } else if (page_size == 64*1024) {
63 va >>= 12;
64 }
65
66 if (tsb_size) {
67 tsb_base_mask <<= tsb_size;
68 }
69
70 // calculate tsb_base mask and adjust va if split is in use
71 if (tsb_split) {
72 if (page_size == 8*1024) {
73 va &= ~(1ULL << (13 + tsb_size));
74 } else if (page_size == 64*1024) {
75 va |= (1ULL << (13 + tsb_size));
76 }
77 tsb_base_mask <<= 1;
78 }
79
80 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
81 }
82
83 // Calculates tag target register value by reordering bits
84 // in tag access register
85 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
86 {
87 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
88 }
89
90 #endif
91
92 static inline void address_mask(CPUState *env1, target_ulong *addr)
93 {
94 #ifdef TARGET_SPARC64
95 if (AM_CHECK(env1))
96 *addr &= 0xffffffffULL;
97 #endif
98 }
99
100 static void raise_exception(int tt)
101 {
102 env->exception_index = tt;
103 cpu_loop_exit();
104 }
105
106 void HELPER(raise_exception)(int tt)
107 {
108 raise_exception(tt);
109 }
110
111 static inline void set_cwp(int new_cwp)
112 {
113 cpu_set_cwp(env, new_cwp);
114 }
115
116 void helper_check_align(target_ulong addr, uint32_t align)
117 {
118 if (addr & align) {
119 #ifdef DEBUG_UNALIGNED
120 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
121 "\n", addr, env->pc);
122 #endif
123 raise_exception(TT_UNALIGNED);
124 }
125 }
126
127 #define F_HELPER(name, p) void helper_f##name##p(void)
128
129 #define F_BINOP(name) \
130 float32 helper_f ## name ## s (float32 src1, float32 src2) \
131 { \
132 return float32_ ## name (src1, src2, &env->fp_status); \
133 } \
134 F_HELPER(name, d) \
135 { \
136 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
137 } \
138 F_HELPER(name, q) \
139 { \
140 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
141 }
142
143 F_BINOP(add);
144 F_BINOP(sub);
145 F_BINOP(mul);
146 F_BINOP(div);
147 #undef F_BINOP
148
149 void helper_fsmuld(float32 src1, float32 src2)
150 {
151 DT0 = float64_mul(float32_to_float64(src1, &env->fp_status),
152 float32_to_float64(src2, &env->fp_status),
153 &env->fp_status);
154 }
155
156 void helper_fdmulq(void)
157 {
158 QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
159 float64_to_float128(DT1, &env->fp_status),
160 &env->fp_status);
161 }
162
163 float32 helper_fnegs(float32 src)
164 {
165 return float32_chs(src);
166 }
167
168 #ifdef TARGET_SPARC64
169 F_HELPER(neg, d)
170 {
171 DT0 = float64_chs(DT1);
172 }
173
174 F_HELPER(neg, q)
175 {
176 QT0 = float128_chs(QT1);
177 }
178 #endif
179
180 /* Integer to float conversion. */
181 float32 helper_fitos(int32_t src)
182 {
183 return int32_to_float32(src, &env->fp_status);
184 }
185
186 void helper_fitod(int32_t src)
187 {
188 DT0 = int32_to_float64(src, &env->fp_status);
189 }
190
191 void helper_fitoq(int32_t src)
192 {
193 QT0 = int32_to_float128(src, &env->fp_status);
194 }
195
196 #ifdef TARGET_SPARC64
197 float32 helper_fxtos(void)
198 {
199 return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
200 }
201
202 F_HELPER(xto, d)
203 {
204 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
205 }
206
207 F_HELPER(xto, q)
208 {
209 QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
210 }
211 #endif
212 #undef F_HELPER
213
214 /* floating point conversion */
215 float32 helper_fdtos(void)
216 {
217 return float64_to_float32(DT1, &env->fp_status);
218 }
219
220 void helper_fstod(float32 src)
221 {
222 DT0 = float32_to_float64(src, &env->fp_status);
223 }
224
225 float32 helper_fqtos(void)
226 {
227 return float128_to_float32(QT1, &env->fp_status);
228 }
229
230 void helper_fstoq(float32 src)
231 {
232 QT0 = float32_to_float128(src, &env->fp_status);
233 }
234
235 void helper_fqtod(void)
236 {
237 DT0 = float128_to_float64(QT1, &env->fp_status);
238 }
239
240 void helper_fdtoq(void)
241 {
242 QT0 = float64_to_float128(DT1, &env->fp_status);
243 }
244
245 /* Float to integer conversion. */
246 int32_t helper_fstoi(float32 src)
247 {
248 return float32_to_int32_round_to_zero(src, &env->fp_status);
249 }
250
251 int32_t helper_fdtoi(void)
252 {
253 return float64_to_int32_round_to_zero(DT1, &env->fp_status);
254 }
255
256 int32_t helper_fqtoi(void)
257 {
258 return float128_to_int32_round_to_zero(QT1, &env->fp_status);
259 }
260
261 #ifdef TARGET_SPARC64
262 void helper_fstox(float32 src)
263 {
264 *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status);
265 }
266
267 void helper_fdtox(void)
268 {
269 *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
270 }
271
272 void helper_fqtox(void)
273 {
274 *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
275 }
276
277 void helper_faligndata(void)
278 {
279 uint64_t tmp;
280
281 tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
282 /* on many architectures a shift of 64 does nothing */
283 if ((env->gsr & 7) != 0) {
284 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
285 }
286 *((uint64_t *)&DT0) = tmp;
287 }
288
289 #ifdef WORDS_BIGENDIAN
290 #define VIS_B64(n) b[7 - (n)]
291 #define VIS_W64(n) w[3 - (n)]
292 #define VIS_SW64(n) sw[3 - (n)]
293 #define VIS_L64(n) l[1 - (n)]
294 #define VIS_B32(n) b[3 - (n)]
295 #define VIS_W32(n) w[1 - (n)]
296 #else
297 #define VIS_B64(n) b[n]
298 #define VIS_W64(n) w[n]
299 #define VIS_SW64(n) sw[n]
300 #define VIS_L64(n) l[n]
301 #define VIS_B32(n) b[n]
302 #define VIS_W32(n) w[n]
303 #endif
304
305 typedef union {
306 uint8_t b[8];
307 uint16_t w[4];
308 int16_t sw[4];
309 uint32_t l[2];
310 float64 d;
311 } vis64;
312
313 typedef union {
314 uint8_t b[4];
315 uint16_t w[2];
316 uint32_t l;
317 float32 f;
318 } vis32;
319
320 void helper_fpmerge(void)
321 {
322 vis64 s, d;
323
324 s.d = DT0;
325 d.d = DT1;
326
327 // Reverse calculation order to handle overlap
328 d.VIS_B64(7) = s.VIS_B64(3);
329 d.VIS_B64(6) = d.VIS_B64(3);
330 d.VIS_B64(5) = s.VIS_B64(2);
331 d.VIS_B64(4) = d.VIS_B64(2);
332 d.VIS_B64(3) = s.VIS_B64(1);
333 d.VIS_B64(2) = d.VIS_B64(1);
334 d.VIS_B64(1) = s.VIS_B64(0);
335 //d.VIS_B64(0) = d.VIS_B64(0);
336
337 DT0 = d.d;
338 }
339
340 void helper_fmul8x16(void)
341 {
342 vis64 s, d;
343 uint32_t tmp;
344
345 s.d = DT0;
346 d.d = DT1;
347
348 #define PMUL(r) \
349 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
350 if ((tmp & 0xff) > 0x7f) \
351 tmp += 0x100; \
352 d.VIS_W64(r) = tmp >> 8;
353
354 PMUL(0);
355 PMUL(1);
356 PMUL(2);
357 PMUL(3);
358 #undef PMUL
359
360 DT0 = d.d;
361 }
362
363 void helper_fmul8x16al(void)
364 {
365 vis64 s, d;
366 uint32_t tmp;
367
368 s.d = DT0;
369 d.d = DT1;
370
371 #define PMUL(r) \
372 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
373 if ((tmp & 0xff) > 0x7f) \
374 tmp += 0x100; \
375 d.VIS_W64(r) = tmp >> 8;
376
377 PMUL(0);
378 PMUL(1);
379 PMUL(2);
380 PMUL(3);
381 #undef PMUL
382
383 DT0 = d.d;
384 }
385
386 void helper_fmul8x16au(void)
387 {
388 vis64 s, d;
389 uint32_t tmp;
390
391 s.d = DT0;
392 d.d = DT1;
393
394 #define PMUL(r) \
395 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
396 if ((tmp & 0xff) > 0x7f) \
397 tmp += 0x100; \
398 d.VIS_W64(r) = tmp >> 8;
399
400 PMUL(0);
401 PMUL(1);
402 PMUL(2);
403 PMUL(3);
404 #undef PMUL
405
406 DT0 = d.d;
407 }
408
409 void helper_fmul8sux16(void)
410 {
411 vis64 s, d;
412 uint32_t tmp;
413
414 s.d = DT0;
415 d.d = DT1;
416
417 #define PMUL(r) \
418 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
419 if ((tmp & 0xff) > 0x7f) \
420 tmp += 0x100; \
421 d.VIS_W64(r) = tmp >> 8;
422
423 PMUL(0);
424 PMUL(1);
425 PMUL(2);
426 PMUL(3);
427 #undef PMUL
428
429 DT0 = d.d;
430 }
431
432 void helper_fmul8ulx16(void)
433 {
434 vis64 s, d;
435 uint32_t tmp;
436
437 s.d = DT0;
438 d.d = DT1;
439
440 #define PMUL(r) \
441 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
442 if ((tmp & 0xff) > 0x7f) \
443 tmp += 0x100; \
444 d.VIS_W64(r) = tmp >> 8;
445
446 PMUL(0);
447 PMUL(1);
448 PMUL(2);
449 PMUL(3);
450 #undef PMUL
451
452 DT0 = d.d;
453 }
454
455 void helper_fmuld8sux16(void)
456 {
457 vis64 s, d;
458 uint32_t tmp;
459
460 s.d = DT0;
461 d.d = DT1;
462
463 #define PMUL(r) \
464 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
465 if ((tmp & 0xff) > 0x7f) \
466 tmp += 0x100; \
467 d.VIS_L64(r) = tmp;
468
469 // Reverse calculation order to handle overlap
470 PMUL(1);
471 PMUL(0);
472 #undef PMUL
473
474 DT0 = d.d;
475 }
476
477 void helper_fmuld8ulx16(void)
478 {
479 vis64 s, d;
480 uint32_t tmp;
481
482 s.d = DT0;
483 d.d = DT1;
484
485 #define PMUL(r) \
486 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
487 if ((tmp & 0xff) > 0x7f) \
488 tmp += 0x100; \
489 d.VIS_L64(r) = tmp;
490
491 // Reverse calculation order to handle overlap
492 PMUL(1);
493 PMUL(0);
494 #undef PMUL
495
496 DT0 = d.d;
497 }
498
499 void helper_fexpand(void)
500 {
501 vis32 s;
502 vis64 d;
503
504 s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
505 d.d = DT1;
506 d.VIS_W64(0) = s.VIS_B32(0) << 4;
507 d.VIS_W64(1) = s.VIS_B32(1) << 4;
508 d.VIS_W64(2) = s.VIS_B32(2) << 4;
509 d.VIS_W64(3) = s.VIS_B32(3) << 4;
510
511 DT0 = d.d;
512 }
513
514 #define VIS_HELPER(name, F) \
515 void name##16(void) \
516 { \
517 vis64 s, d; \
518 \
519 s.d = DT0; \
520 d.d = DT1; \
521 \
522 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
523 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
524 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
525 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
526 \
527 DT0 = d.d; \
528 } \
529 \
530 uint32_t name##16s(uint32_t src1, uint32_t src2) \
531 { \
532 vis32 s, d; \
533 \
534 s.l = src1; \
535 d.l = src2; \
536 \
537 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
538 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
539 \
540 return d.l; \
541 } \
542 \
543 void name##32(void) \
544 { \
545 vis64 s, d; \
546 \
547 s.d = DT0; \
548 d.d = DT1; \
549 \
550 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
551 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
552 \
553 DT0 = d.d; \
554 } \
555 \
556 uint32_t name##32s(uint32_t src1, uint32_t src2) \
557 { \
558 vis32 s, d; \
559 \
560 s.l = src1; \
561 d.l = src2; \
562 \
563 d.l = F(d.l, s.l); \
564 \
565 return d.l; \
566 }
567
568 #define FADD(a, b) ((a) + (b))
569 #define FSUB(a, b) ((a) - (b))
570 VIS_HELPER(helper_fpadd, FADD)
571 VIS_HELPER(helper_fpsub, FSUB)
572
573 #define VIS_CMPHELPER(name, F) \
574 void name##16(void) \
575 { \
576 vis64 s, d; \
577 \
578 s.d = DT0; \
579 d.d = DT1; \
580 \
581 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
582 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
583 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
584 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
585 \
586 DT0 = d.d; \
587 } \
588 \
589 void name##32(void) \
590 { \
591 vis64 s, d; \
592 \
593 s.d = DT0; \
594 d.d = DT1; \
595 \
596 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
597 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
598 \
599 DT0 = d.d; \
600 }
601
602 #define FCMPGT(a, b) ((a) > (b))
603 #define FCMPEQ(a, b) ((a) == (b))
604 #define FCMPLE(a, b) ((a) <= (b))
605 #define FCMPNE(a, b) ((a) != (b))
606
607 VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
608 VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
609 VIS_CMPHELPER(helper_fcmple, FCMPLE)
610 VIS_CMPHELPER(helper_fcmpne, FCMPNE)
611 #endif
612
613 void helper_check_ieee_exceptions(void)
614 {
615 target_ulong status;
616
617 status = get_float_exception_flags(&env->fp_status);
618 if (status) {
619 /* Copy IEEE 754 flags into FSR */
620 if (status & float_flag_invalid)
621 env->fsr |= FSR_NVC;
622 if (status & float_flag_overflow)
623 env->fsr |= FSR_OFC;
624 if (status & float_flag_underflow)
625 env->fsr |= FSR_UFC;
626 if (status & float_flag_divbyzero)
627 env->fsr |= FSR_DZC;
628 if (status & float_flag_inexact)
629 env->fsr |= FSR_NXC;
630
631 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
632 /* Unmasked exception, generate a trap */
633 env->fsr |= FSR_FTT_IEEE_EXCP;
634 raise_exception(TT_FP_EXCP);
635 } else {
636 /* Accumulate exceptions */
637 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
638 }
639 }
640 }
641
642 void helper_clear_float_exceptions(void)
643 {
644 set_float_exception_flags(0, &env->fp_status);
645 }
646
647 float32 helper_fabss(float32 src)
648 {
649 return float32_abs(src);
650 }
651
652 #ifdef TARGET_SPARC64
653 void helper_fabsd(void)
654 {
655 DT0 = float64_abs(DT1);
656 }
657
658 void helper_fabsq(void)
659 {
660 QT0 = float128_abs(QT1);
661 }
662 #endif
663
664 float32 helper_fsqrts(float32 src)
665 {
666 return float32_sqrt(src, &env->fp_status);
667 }
668
669 void helper_fsqrtd(void)
670 {
671 DT0 = float64_sqrt(DT1, &env->fp_status);
672 }
673
674 void helper_fsqrtq(void)
675 {
676 QT0 = float128_sqrt(QT1, &env->fp_status);
677 }
678
679 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
680 void glue(helper_, name) (void) \
681 { \
682 target_ulong new_fsr; \
683 \
684 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
685 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
686 case float_relation_unordered: \
687 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
688 if ((env->fsr & FSR_NVM) || TRAP) { \
689 env->fsr |= new_fsr; \
690 env->fsr |= FSR_NVC; \
691 env->fsr |= FSR_FTT_IEEE_EXCP; \
692 raise_exception(TT_FP_EXCP); \
693 } else { \
694 env->fsr |= FSR_NVA; \
695 } \
696 break; \
697 case float_relation_less: \
698 new_fsr = FSR_FCC0 << FS; \
699 break; \
700 case float_relation_greater: \
701 new_fsr = FSR_FCC1 << FS; \
702 break; \
703 default: \
704 new_fsr = 0; \
705 break; \
706 } \
707 env->fsr |= new_fsr; \
708 }
709 #define GEN_FCMPS(name, size, FS, TRAP) \
710 void glue(helper_, name)(float32 src1, float32 src2) \
711 { \
712 target_ulong new_fsr; \
713 \
714 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
715 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
716 case float_relation_unordered: \
717 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
718 if ((env->fsr & FSR_NVM) || TRAP) { \
719 env->fsr |= new_fsr; \
720 env->fsr |= FSR_NVC; \
721 env->fsr |= FSR_FTT_IEEE_EXCP; \
722 raise_exception(TT_FP_EXCP); \
723 } else { \
724 env->fsr |= FSR_NVA; \
725 } \
726 break; \
727 case float_relation_less: \
728 new_fsr = FSR_FCC0 << FS; \
729 break; \
730 case float_relation_greater: \
731 new_fsr = FSR_FCC1 << FS; \
732 break; \
733 default: \
734 new_fsr = 0; \
735 break; \
736 } \
737 env->fsr |= new_fsr; \
738 }
739
740 GEN_FCMPS(fcmps, float32, 0, 0);
741 GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
742
743 GEN_FCMPS(fcmpes, float32, 0, 1);
744 GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
745
746 GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
747 GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
748
749 static uint32_t compute_all_flags(void)
750 {
751 return env->psr & PSR_ICC;
752 }
753
754 static uint32_t compute_C_flags(void)
755 {
756 return env->psr & PSR_CARRY;
757 }
758
759 static inline uint32_t get_NZ_icc(target_ulong dst)
760 {
761 uint32_t ret = 0;
762
763 if (!(dst & 0xffffffffULL))
764 ret |= PSR_ZERO;
765 if ((int32_t) (dst & 0xffffffffULL) < 0)
766 ret |= PSR_NEG;
767 return ret;
768 }
769
770 #ifdef TARGET_SPARC64
771 static uint32_t compute_all_flags_xcc(void)
772 {
773 return env->xcc & PSR_ICC;
774 }
775
776 static uint32_t compute_C_flags_xcc(void)
777 {
778 return env->xcc & PSR_CARRY;
779 }
780
781 static inline uint32_t get_NZ_xcc(target_ulong dst)
782 {
783 uint32_t ret = 0;
784
785 if (!dst)
786 ret |= PSR_ZERO;
787 if ((int64_t)dst < 0)
788 ret |= PSR_NEG;
789 return ret;
790 }
791 #endif
792
793 static inline uint32_t get_C_add_icc(target_ulong dst, target_ulong src1)
794 {
795 uint32_t ret = 0;
796
797 if ((dst & 0xffffffffULL) < (src1 & 0xffffffffULL))
798 ret |= PSR_CARRY;
799 return ret;
800 }
801
802 static inline uint32_t get_V_add_icc(target_ulong dst, target_ulong src1,
803 target_ulong src2)
804 {
805 uint32_t ret = 0;
806
807 if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1ULL << 31))
808 ret |= PSR_OVF;
809 return ret;
810 }
811
812 static uint32_t compute_all_add(void)
813 {
814 uint32_t ret;
815
816 ret = get_NZ_icc(CC_DST);
817 ret |= get_C_add_icc(CC_DST, CC_SRC);
818 ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2);
819 return ret;
820 }
821
822 static uint32_t compute_C_add(void)
823 {
824 return get_C_add_icc(CC_DST, CC_SRC);
825 }
826
827 #ifdef TARGET_SPARC64
828 static inline uint32_t get_C_add_xcc(target_ulong dst, target_ulong src1)
829 {
830 uint32_t ret = 0;
831
832 if (dst < src1)
833 ret |= PSR_CARRY;
834 return ret;
835 }
836
837 static inline uint32_t get_V_add_xcc(target_ulong dst, target_ulong src1,
838 target_ulong src2)
839 {
840 uint32_t ret = 0;
841
842 if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1ULL << 63))
843 ret |= PSR_OVF;
844 return ret;
845 }
846
847 static uint32_t compute_all_add_xcc(void)
848 {
849 uint32_t ret;
850
851 ret = get_NZ_xcc(CC_DST);
852 ret |= get_C_add_xcc(CC_DST, CC_SRC);
853 ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2);
854 return ret;
855 }
856
857 static uint32_t compute_C_add_xcc(void)
858 {
859 return get_C_add_xcc(CC_DST, CC_SRC);
860 }
861 #endif
862
863 static uint32_t compute_all_addx(void)
864 {
865 uint32_t ret;
866
867 ret = get_NZ_icc(CC_DST);
868 ret |= get_C_add_icc(CC_DST - CC_SRC2, CC_SRC);
869 ret |= get_C_add_icc(CC_DST, CC_SRC);
870 ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2);
871 return ret;
872 }
873
874 static uint32_t compute_C_addx(void)
875 {
876 uint32_t ret;
877
878 ret = get_C_add_icc(CC_DST - CC_SRC2, CC_SRC);
879 ret |= get_C_add_icc(CC_DST, CC_SRC);
880 return ret;
881 }
882
883 #ifdef TARGET_SPARC64
884 static uint32_t compute_all_addx_xcc(void)
885 {
886 uint32_t ret;
887
888 ret = get_NZ_xcc(CC_DST);
889 ret |= get_C_add_xcc(CC_DST - CC_SRC2, CC_SRC);
890 ret |= get_C_add_xcc(CC_DST, CC_SRC);
891 ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2);
892 return ret;
893 }
894
895 static uint32_t compute_C_addx_xcc(void)
896 {
897 uint32_t ret;
898
899 ret = get_C_add_xcc(CC_DST - CC_SRC2, CC_SRC);
900 ret |= get_C_add_xcc(CC_DST, CC_SRC);
901 return ret;
902 }
903 #endif
904
905 static inline uint32_t get_C_sub_icc(target_ulong src1, target_ulong src2)
906 {
907 uint32_t ret = 0;
908
909 if ((src1 & 0xffffffffULL) < (src2 & 0xffffffffULL))
910 ret |= PSR_CARRY;
911 return ret;
912 }
913
914 static inline uint32_t get_V_sub_icc(target_ulong dst, target_ulong src1,
915 target_ulong src2)
916 {
917 uint32_t ret = 0;
918
919 if (((src1 ^ src2) & (src1 ^ dst)) & (1ULL << 31))
920 ret |= PSR_OVF;
921 return ret;
922 }
923
924 static uint32_t compute_all_sub(void)
925 {
926 uint32_t ret;
927
928 ret = get_NZ_icc(CC_DST);
929 ret |= get_C_sub_icc(CC_SRC, CC_SRC2);
930 ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2);
931 return ret;
932 }
933
934 static uint32_t compute_C_sub(void)
935 {
936 return get_C_sub_icc(CC_SRC, CC_SRC2);
937 }
938
939 #ifdef TARGET_SPARC64
940 static inline uint32_t get_C_sub_xcc(target_ulong src1, target_ulong src2)
941 {
942 uint32_t ret = 0;
943
944 if (src1 < src2)
945 ret |= PSR_CARRY;
946 return ret;
947 }
948
949 static inline uint32_t get_V_sub_xcc(target_ulong dst, target_ulong src1,
950 target_ulong src2)
951 {
952 uint32_t ret = 0;
953
954 if (((src1 ^ src2) & (src1 ^ dst)) & (1ULL << 63))
955 ret |= PSR_OVF;
956 return ret;
957 }
958
959 static uint32_t compute_all_sub_xcc(void)
960 {
961 uint32_t ret;
962
963 ret = get_NZ_xcc(CC_DST);
964 ret |= get_C_sub_xcc(CC_SRC, CC_SRC2);
965 ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2);
966 return ret;
967 }
968
969 static uint32_t compute_C_sub_xcc(void)
970 {
971 return get_C_sub_xcc(CC_SRC, CC_SRC2);
972 }
973 #endif
974
975 static uint32_t compute_all_logic(void)
976 {
977 return get_NZ_icc(CC_DST);
978 }
979
980 static uint32_t compute_C_logic(void)
981 {
982 return 0;
983 }
984
985 #ifdef TARGET_SPARC64
986 static uint32_t compute_all_logic_xcc(void)
987 {
988 return get_NZ_xcc(CC_DST);
989 }
990 #endif
991
992 typedef struct CCTable {
993 uint32_t (*compute_all)(void); /* return all the flags */
994 uint32_t (*compute_c)(void); /* return the C flag */
995 } CCTable;
996
997 static const CCTable icc_table[CC_OP_NB] = {
998 /* CC_OP_DYNAMIC should never happen */
999 [CC_OP_FLAGS] = { compute_all_flags, compute_C_flags },
1000 [CC_OP_ADD] = { compute_all_add, compute_C_add },
1001 [CC_OP_ADDX] = { compute_all_addx, compute_C_addx },
1002 [CC_OP_SUB] = { compute_all_sub, compute_C_sub },
1003 [CC_OP_LOGIC] = { compute_all_logic, compute_C_logic },
1004 };
1005
1006 #ifdef TARGET_SPARC64
1007 static const CCTable xcc_table[CC_OP_NB] = {
1008 /* CC_OP_DYNAMIC should never happen */
1009 [CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc },
1010 [CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc },
1011 [CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc },
1012 [CC_OP_SUB] = { compute_all_sub_xcc, compute_C_sub_xcc },
1013 [CC_OP_LOGIC] = { compute_all_logic_xcc, compute_C_logic },
1014 };
1015 #endif
1016
1017 void helper_compute_psr(void)
1018 {
1019 uint32_t new_psr;
1020
1021 new_psr = icc_table[CC_OP].compute_all();
1022 env->psr = new_psr;
1023 #ifdef TARGET_SPARC64
1024 new_psr = xcc_table[CC_OP].compute_all();
1025 env->xcc = new_psr;
1026 #endif
1027 CC_OP = CC_OP_FLAGS;
1028 }
1029
1030 uint32_t helper_compute_C_icc(void)
1031 {
1032 uint32_t ret;
1033
1034 ret = icc_table[CC_OP].compute_c() >> PSR_CARRY_SHIFT;
1035 return ret;
1036 }
1037
1038 #ifdef TARGET_SPARC64
1039 GEN_FCMPS(fcmps_fcc1, float32, 22, 0);
1040 GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
1041 GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
1042
1043 GEN_FCMPS(fcmps_fcc2, float32, 24, 0);
1044 GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
1045 GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
1046
1047 GEN_FCMPS(fcmps_fcc3, float32, 26, 0);
1048 GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
1049 GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
1050
1051 GEN_FCMPS(fcmpes_fcc1, float32, 22, 1);
1052 GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
1053 GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
1054
1055 GEN_FCMPS(fcmpes_fcc2, float32, 24, 1);
1056 GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
1057 GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
1058
1059 GEN_FCMPS(fcmpes_fcc3, float32, 26, 1);
1060 GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
1061 GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
1062 #endif
1063 #undef GEN_FCMPS
1064
1065 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
1066 defined(DEBUG_MXCC)
1067 static void dump_mxcc(CPUState *env)
1068 {
1069 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
1070 env->mxccdata[0], env->mxccdata[1],
1071 env->mxccdata[2], env->mxccdata[3]);
1072 printf("mxccregs: %016llx %016llx %016llx %016llx\n"
1073 " %016llx %016llx %016llx %016llx\n",
1074 env->mxccregs[0], env->mxccregs[1],
1075 env->mxccregs[2], env->mxccregs[3],
1076 env->mxccregs[4], env->mxccregs[5],
1077 env->mxccregs[6], env->mxccregs[7]);
1078 }
1079 #endif
1080
1081 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
1082 && defined(DEBUG_ASI)
1083 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
1084 uint64_t r1)
1085 {
1086 switch (size)
1087 {
1088 case 1:
1089 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
1090 addr, asi, r1 & 0xff);
1091 break;
1092 case 2:
1093 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
1094 addr, asi, r1 & 0xffff);
1095 break;
1096 case 4:
1097 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
1098 addr, asi, r1 & 0xffffffff);
1099 break;
1100 case 8:
1101 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
1102 addr, asi, r1);
1103 break;
1104 }
1105 }
1106 #endif
1107
1108 #ifndef TARGET_SPARC64
1109 #ifndef CONFIG_USER_ONLY
1110 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1111 {
1112 uint64_t ret = 0;
1113 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1114 uint32_t last_addr = addr;
1115 #endif
1116
1117 helper_check_align(addr, size - 1);
1118 switch (asi) {
1119 case 2: /* SuperSparc MXCC registers */
1120 switch (addr) {
1121 case 0x01c00a00: /* MXCC control register */
1122 if (size == 8)
1123 ret = env->mxccregs[3];
1124 else
1125 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1126 size);
1127 break;
1128 case 0x01c00a04: /* MXCC control register */
1129 if (size == 4)
1130 ret = env->mxccregs[3];
1131 else
1132 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1133 size);
1134 break;
1135 case 0x01c00c00: /* Module reset register */
1136 if (size == 8) {
1137 ret = env->mxccregs[5];
1138 // should we do something here?
1139 } else
1140 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1141 size);
1142 break;
1143 case 0x01c00f00: /* MBus port address register */
1144 if (size == 8)
1145 ret = env->mxccregs[7];
1146 else
1147 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1148 size);
1149 break;
1150 default:
1151 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
1152 size);
1153 break;
1154 }
1155 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
1156 "addr = %08x -> ret = %" PRIx64 ","
1157 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
1158 #ifdef DEBUG_MXCC
1159 dump_mxcc(env);
1160 #endif
1161 break;
1162 case 3: /* MMU probe */
1163 {
1164 int mmulev;
1165
1166 mmulev = (addr >> 8) & 15;
1167 if (mmulev > 4)
1168 ret = 0;
1169 else
1170 ret = mmu_probe(env, addr, mmulev);
1171 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
1172 addr, mmulev, ret);
1173 }
1174 break;
1175 case 4: /* read MMU regs */
1176 {
1177 int reg = (addr >> 8) & 0x1f;
1178
1179 ret = env->mmuregs[reg];
1180 if (reg == 3) /* Fault status cleared on read */
1181 env->mmuregs[3] = 0;
1182 else if (reg == 0x13) /* Fault status read */
1183 ret = env->mmuregs[3];
1184 else if (reg == 0x14) /* Fault address read */
1185 ret = env->mmuregs[4];
1186 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
1187 }
1188 break;
1189 case 5: // Turbosparc ITLB Diagnostic
1190 case 6: // Turbosparc DTLB Diagnostic
1191 case 7: // Turbosparc IOTLB Diagnostic
1192 break;
1193 case 9: /* Supervisor code access */
1194 switch(size) {
1195 case 1:
1196 ret = ldub_code(addr);
1197 break;
1198 case 2:
1199 ret = lduw_code(addr);
1200 break;
1201 default:
1202 case 4:
1203 ret = ldl_code(addr);
1204 break;
1205 case 8:
1206 ret = ldq_code(addr);
1207 break;
1208 }
1209 break;
1210 case 0xa: /* User data access */
1211 switch(size) {
1212 case 1:
1213 ret = ldub_user(addr);
1214 break;
1215 case 2:
1216 ret = lduw_user(addr);
1217 break;
1218 default:
1219 case 4:
1220 ret = ldl_user(addr);
1221 break;
1222 case 8:
1223 ret = ldq_user(addr);
1224 break;
1225 }
1226 break;
1227 case 0xb: /* Supervisor data access */
1228 switch(size) {
1229 case 1:
1230 ret = ldub_kernel(addr);
1231 break;
1232 case 2:
1233 ret = lduw_kernel(addr);
1234 break;
1235 default:
1236 case 4:
1237 ret = ldl_kernel(addr);
1238 break;
1239 case 8:
1240 ret = ldq_kernel(addr);
1241 break;
1242 }
1243 break;
1244 case 0xc: /* I-cache tag */
1245 case 0xd: /* I-cache data */
1246 case 0xe: /* D-cache tag */
1247 case 0xf: /* D-cache data */
1248 break;
1249 case 0x20: /* MMU passthrough */
1250 switch(size) {
1251 case 1:
1252 ret = ldub_phys(addr);
1253 break;
1254 case 2:
1255 ret = lduw_phys(addr);
1256 break;
1257 default:
1258 case 4:
1259 ret = ldl_phys(addr);
1260 break;
1261 case 8:
1262 ret = ldq_phys(addr);
1263 break;
1264 }
1265 break;
1266 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1267 switch(size) {
1268 case 1:
1269 ret = ldub_phys((target_phys_addr_t)addr
1270 | ((target_phys_addr_t)(asi & 0xf) << 32));
1271 break;
1272 case 2:
1273 ret = lduw_phys((target_phys_addr_t)addr
1274 | ((target_phys_addr_t)(asi & 0xf) << 32));
1275 break;
1276 default:
1277 case 4:
1278 ret = ldl_phys((target_phys_addr_t)addr
1279 | ((target_phys_addr_t)(asi & 0xf) << 32));
1280 break;
1281 case 8:
1282 ret = ldq_phys((target_phys_addr_t)addr
1283 | ((target_phys_addr_t)(asi & 0xf) << 32));
1284 break;
1285 }
1286 break;
1287 case 0x30: // Turbosparc secondary cache diagnostic
1288 case 0x31: // Turbosparc RAM snoop
1289 case 0x32: // Turbosparc page table descriptor diagnostic
1290 case 0x39: /* data cache diagnostic register */
1291 ret = 0;
1292 break;
1293 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
1294 {
1295 int reg = (addr >> 8) & 3;
1296
1297 switch(reg) {
1298 case 0: /* Breakpoint Value (Addr) */
1299 ret = env->mmubpregs[reg];
1300 break;
1301 case 1: /* Breakpoint Mask */
1302 ret = env->mmubpregs[reg];
1303 break;
1304 case 2: /* Breakpoint Control */
1305 ret = env->mmubpregs[reg];
1306 break;
1307 case 3: /* Breakpoint Status */
1308 ret = env->mmubpregs[reg];
1309 env->mmubpregs[reg] = 0ULL;
1310 break;
1311 }
1312 DPRINTF_MMU("read breakpoint reg[%d] 0x%016llx\n", reg, ret);
1313 }
1314 break;
1315 case 8: /* User code access, XXX */
1316 default:
1317 do_unassigned_access(addr, 0, 0, asi, size);
1318 ret = 0;
1319 break;
1320 }
1321 if (sign) {
1322 switch(size) {
1323 case 1:
1324 ret = (int8_t) ret;
1325 break;
1326 case 2:
1327 ret = (int16_t) ret;
1328 break;
1329 case 4:
1330 ret = (int32_t) ret;
1331 break;
1332 default:
1333 break;
1334 }
1335 }
1336 #ifdef DEBUG_ASI
1337 dump_asi("read ", last_addr, asi, size, ret);
1338 #endif
1339 return ret;
1340 }
1341
1342 void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
1343 {
1344 helper_check_align(addr, size - 1);
1345 switch(asi) {
1346 case 2: /* SuperSparc MXCC registers */
1347 switch (addr) {
1348 case 0x01c00000: /* MXCC stream data register 0 */
1349 if (size == 8)
1350 env->mxccdata[0] = val;
1351 else
1352 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1353 size);
1354 break;
1355 case 0x01c00008: /* MXCC stream data register 1 */
1356 if (size == 8)
1357 env->mxccdata[1] = val;
1358 else
1359 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1360 size);
1361 break;
1362 case 0x01c00010: /* MXCC stream data register 2 */
1363 if (size == 8)
1364 env->mxccdata[2] = val;
1365 else
1366 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1367 size);
1368 break;
1369 case 0x01c00018: /* MXCC stream data register 3 */
1370 if (size == 8)
1371 env->mxccdata[3] = val;
1372 else
1373 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1374 size);
1375 break;
1376 case 0x01c00100: /* MXCC stream source */
1377 if (size == 8)
1378 env->mxccregs[0] = val;
1379 else
1380 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1381 size);
1382 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1383 0);
1384 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1385 8);
1386 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1387 16);
1388 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1389 24);
1390 break;
1391 case 0x01c00200: /* MXCC stream destination */
1392 if (size == 8)
1393 env->mxccregs[1] = val;
1394 else
1395 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1396 size);
1397 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
1398 env->mxccdata[0]);
1399 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
1400 env->mxccdata[1]);
1401 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
1402 env->mxccdata[2]);
1403 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
1404 env->mxccdata[3]);
1405 break;
1406 case 0x01c00a00: /* MXCC control register */
1407 if (size == 8)
1408 env->mxccregs[3] = val;
1409 else
1410 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1411 size);
1412 break;
1413 case 0x01c00a04: /* MXCC control register */
1414 if (size == 4)
1415 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
1416 | val;
1417 else
1418 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1419 size);
1420 break;
1421 case 0x01c00e00: /* MXCC error register */
1422 // writing a 1 bit clears the error
1423 if (size == 8)
1424 env->mxccregs[6] &= ~val;
1425 else
1426 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1427 size);
1428 break;
1429 case 0x01c00f00: /* MBus port address register */
1430 if (size == 8)
1431 env->mxccregs[7] = val;
1432 else
1433 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1434 size);
1435 break;
1436 default:
1437 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
1438 size);
1439 break;
1440 }
1441 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
1442 asi, size, addr, val);
1443 #ifdef DEBUG_MXCC
1444 dump_mxcc(env);
1445 #endif
1446 break;
1447 case 3: /* MMU flush */
1448 {
1449 int mmulev;
1450
1451 mmulev = (addr >> 8) & 15;
1452 DPRINTF_MMU("mmu flush level %d\n", mmulev);
1453 switch (mmulev) {
1454 case 0: // flush page
1455 tlb_flush_page(env, addr & 0xfffff000);
1456 break;
1457 case 1: // flush segment (256k)
1458 case 2: // flush region (16M)
1459 case 3: // flush context (4G)
1460 case 4: // flush entire
1461 tlb_flush(env, 1);
1462 break;
1463 default:
1464 break;
1465 }
1466 #ifdef DEBUG_MMU
1467 dump_mmu(env);
1468 #endif
1469 }
1470 break;
1471 case 4: /* write MMU regs */
1472 {
1473 int reg = (addr >> 8) & 0x1f;
1474 uint32_t oldreg;
1475
1476 oldreg = env->mmuregs[reg];
1477 switch(reg) {
1478 case 0: // Control Register
1479 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1480 (val & 0x00ffffff);
1481 // Mappings generated during no-fault mode or MMU
1482 // disabled mode are invalid in normal mode
1483 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
1484 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm)))
1485 tlb_flush(env, 1);
1486 break;
1487 case 1: // Context Table Pointer Register
1488 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
1489 break;
1490 case 2: // Context Register
1491 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
1492 if (oldreg != env->mmuregs[reg]) {
1493 /* we flush when the MMU context changes because
1494 QEMU has no MMU context support */
1495 tlb_flush(env, 1);
1496 }
1497 break;
1498 case 3: // Synchronous Fault Status Register with Clear
1499 case 4: // Synchronous Fault Address Register
1500 break;
1501 case 0x10: // TLB Replacement Control Register
1502 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
1503 break;
1504 case 0x13: // Synchronous Fault Status Register with Read and Clear
1505 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
1506 break;
1507 case 0x14: // Synchronous Fault Address Register
1508 env->mmuregs[4] = val;
1509 break;
1510 default:
1511 env->mmuregs[reg] = val;
1512 break;
1513 }
1514 if (oldreg != env->mmuregs[reg]) {
1515 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1516 reg, oldreg, env->mmuregs[reg]);
1517 }
1518 #ifdef DEBUG_MMU
1519 dump_mmu(env);
1520 #endif
1521 }
1522 break;
1523 case 5: // Turbosparc ITLB Diagnostic
1524 case 6: // Turbosparc DTLB Diagnostic
1525 case 7: // Turbosparc IOTLB Diagnostic
1526 break;
1527 case 0xa: /* User data access */
1528 switch(size) {
1529 case 1:
1530 stb_user(addr, val);
1531 break;
1532 case 2:
1533 stw_user(addr, val);
1534 break;
1535 default:
1536 case 4:
1537 stl_user(addr, val);
1538 break;
1539 case 8:
1540 stq_user(addr, val);
1541 break;
1542 }
1543 break;
1544 case 0xb: /* Supervisor data access */
1545 switch(size) {
1546 case 1:
1547 stb_kernel(addr, val);
1548 break;
1549 case 2:
1550 stw_kernel(addr, val);
1551 break;
1552 default:
1553 case 4:
1554 stl_kernel(addr, val);
1555 break;
1556 case 8:
1557 stq_kernel(addr, val);
1558 break;
1559 }
1560 break;
1561 case 0xc: /* I-cache tag */
1562 case 0xd: /* I-cache data */
1563 case 0xe: /* D-cache tag */
1564 case 0xf: /* D-cache data */
1565 case 0x10: /* I/D-cache flush page */
1566 case 0x11: /* I/D-cache flush segment */
1567 case 0x12: /* I/D-cache flush region */
1568 case 0x13: /* I/D-cache flush context */
1569 case 0x14: /* I/D-cache flush user */
1570 break;
1571 case 0x17: /* Block copy, sta access */
1572 {
1573 // val = src
1574 // addr = dst
1575 // copy 32 bytes
1576 unsigned int i;
1577 uint32_t src = val & ~3, dst = addr & ~3, temp;
1578
1579 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
1580 temp = ldl_kernel(src);
1581 stl_kernel(dst, temp);
1582 }
1583 }
1584 break;
1585 case 0x1f: /* Block fill, stda access */
1586 {
1587 // addr = dst
1588 // fill 32 bytes with val
1589 unsigned int i;
1590 uint32_t dst = addr & 7;
1591
1592 for (i = 0; i < 32; i += 8, dst += 8)
1593 stq_kernel(dst, val);
1594 }
1595 break;
1596 case 0x20: /* MMU passthrough */
1597 {
1598 switch(size) {
1599 case 1:
1600 stb_phys(addr, val);
1601 break;
1602 case 2:
1603 stw_phys(addr, val);
1604 break;
1605 case 4:
1606 default:
1607 stl_phys(addr, val);
1608 break;
1609 case 8:
1610 stq_phys(addr, val);
1611 break;
1612 }
1613 }
1614 break;
1615 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1616 {
1617 switch(size) {
1618 case 1:
1619 stb_phys((target_phys_addr_t)addr
1620 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1621 break;
1622 case 2:
1623 stw_phys((target_phys_addr_t)addr
1624 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1625 break;
1626 case 4:
1627 default:
1628 stl_phys((target_phys_addr_t)addr
1629 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1630 break;
1631 case 8:
1632 stq_phys((target_phys_addr_t)addr
1633 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1634 break;
1635 }
1636 }
1637 break;
1638 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1639 case 0x31: // store buffer data, Ross RT620 I-cache flush or
1640 // Turbosparc snoop RAM
1641 case 0x32: // store buffer control or Turbosparc page table
1642 // descriptor diagnostic
1643 case 0x36: /* I-cache flash clear */
1644 case 0x37: /* D-cache flash clear */
1645 case 0x4c: /* breakpoint action */
1646 break;
1647 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1648 {
1649 int reg = (addr >> 8) & 3;
1650
1651 switch(reg) {
1652 case 0: /* Breakpoint Value (Addr) */
1653 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1654 break;
1655 case 1: /* Breakpoint Mask */
1656 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1657 break;
1658 case 2: /* Breakpoint Control */
1659 env->mmubpregs[reg] = (val & 0x7fULL);
1660 break;
1661 case 3: /* Breakpoint Status */
1662 env->mmubpregs[reg] = (val & 0xfULL);
1663 break;
1664 }
1665 DPRINTF_MMU("write breakpoint reg[%d] 0x%016llx\n", reg,
1666 env->mmuregs[reg]);
1667 }
1668 break;
1669 case 8: /* User code access, XXX */
1670 case 9: /* Supervisor code access, XXX */
1671 default:
1672 do_unassigned_access(addr, 1, 0, asi, size);
1673 break;
1674 }
1675 #ifdef DEBUG_ASI
1676 dump_asi("write", addr, asi, size, val);
1677 #endif
1678 }
1679
1680 #endif /* CONFIG_USER_ONLY */
1681 #else /* TARGET_SPARC64 */
1682
1683 #ifdef CONFIG_USER_ONLY
1684 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1685 {
1686 uint64_t ret = 0;
1687 #if defined(DEBUG_ASI)
1688 target_ulong last_addr = addr;
1689 #endif
1690
1691 if (asi < 0x80)
1692 raise_exception(TT_PRIV_ACT);
1693
1694 helper_check_align(addr, size - 1);
1695 address_mask(env, &addr);
1696
1697 switch (asi) {
1698 case 0x82: // Primary no-fault
1699 case 0x8a: // Primary no-fault LE
1700 if (page_check_range(addr, size, PAGE_READ) == -1) {
1701 #ifdef DEBUG_ASI
1702 dump_asi("read ", last_addr, asi, size, ret);
1703 #endif
1704 return 0;
1705 }
1706 // Fall through
1707 case 0x80: // Primary
1708 case 0x88: // Primary LE
1709 {
1710 switch(size) {
1711 case 1:
1712 ret = ldub_raw(addr);
1713 break;
1714 case 2:
1715 ret = lduw_raw(addr);
1716 break;
1717 case 4:
1718 ret = ldl_raw(addr);
1719 break;
1720 default:
1721 case 8:
1722 ret = ldq_raw(addr);
1723 break;
1724 }
1725 }
1726 break;
1727 case 0x83: // Secondary no-fault
1728 case 0x8b: // Secondary no-fault LE
1729 if (page_check_range(addr, size, PAGE_READ) == -1) {
1730 #ifdef DEBUG_ASI
1731 dump_asi("read ", last_addr, asi, size, ret);
1732 #endif
1733 return 0;
1734 }
1735 // Fall through
1736 case 0x81: // Secondary
1737 case 0x89: // Secondary LE
1738 // XXX
1739 break;
1740 default:
1741 break;
1742 }
1743
1744 /* Convert from little endian */
1745 switch (asi) {
1746 case 0x88: // Primary LE
1747 case 0x89: // Secondary LE
1748 case 0x8a: // Primary no-fault LE
1749 case 0x8b: // Secondary no-fault LE
1750 switch(size) {
1751 case 2:
1752 ret = bswap16(ret);
1753 break;
1754 case 4:
1755 ret = bswap32(ret);
1756 break;
1757 case 8:
1758 ret = bswap64(ret);
1759 break;
1760 default:
1761 break;
1762 }
1763 default:
1764 break;
1765 }
1766
1767 /* Convert to signed number */
1768 if (sign) {
1769 switch(size) {
1770 case 1:
1771 ret = (int8_t) ret;
1772 break;
1773 case 2:
1774 ret = (int16_t) ret;
1775 break;
1776 case 4:
1777 ret = (int32_t) ret;
1778 break;
1779 default:
1780 break;
1781 }
1782 }
1783 #ifdef DEBUG_ASI
1784 dump_asi("read ", last_addr, asi, size, ret);
1785 #endif
1786 return ret;
1787 }
1788
1789 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1790 {
1791 #ifdef DEBUG_ASI
1792 dump_asi("write", addr, asi, size, val);
1793 #endif
1794 if (asi < 0x80)
1795 raise_exception(TT_PRIV_ACT);
1796
1797 helper_check_align(addr, size - 1);
1798 address_mask(env, &addr);
1799
1800 /* Convert to little endian */
1801 switch (asi) {
1802 case 0x88: // Primary LE
1803 case 0x89: // Secondary LE
1804 switch(size) {
1805 case 2:
1806 addr = bswap16(addr);
1807 break;
1808 case 4:
1809 addr = bswap32(addr);
1810 break;
1811 case 8:
1812 addr = bswap64(addr);
1813 break;
1814 default:
1815 break;
1816 }
1817 default:
1818 break;
1819 }
1820
1821 switch(asi) {
1822 case 0x80: // Primary
1823 case 0x88: // Primary LE
1824 {
1825 switch(size) {
1826 case 1:
1827 stb_raw(addr, val);
1828 break;
1829 case 2:
1830 stw_raw(addr, val);
1831 break;
1832 case 4:
1833 stl_raw(addr, val);
1834 break;
1835 case 8:
1836 default:
1837 stq_raw(addr, val);
1838 break;
1839 }
1840 }
1841 break;
1842 case 0x81: // Secondary
1843 case 0x89: // Secondary LE
1844 // XXX
1845 return;
1846
1847 case 0x82: // Primary no-fault, RO
1848 case 0x83: // Secondary no-fault, RO
1849 case 0x8a: // Primary no-fault LE, RO
1850 case 0x8b: // Secondary no-fault LE, RO
1851 default:
1852 do_unassigned_access(addr, 1, 0, 1, size);
1853 return;
1854 }
1855 }
1856
1857 #else /* CONFIG_USER_ONLY */
1858
1859 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1860 {
1861 uint64_t ret = 0;
1862 #if defined(DEBUG_ASI)
1863 target_ulong last_addr = addr;
1864 #endif
1865
1866 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1867 || ((env->def->features & CPU_FEATURE_HYPV)
1868 && asi >= 0x30 && asi < 0x80
1869 && !(env->hpstate & HS_PRIV)))
1870 raise_exception(TT_PRIV_ACT);
1871
1872 helper_check_align(addr, size - 1);
1873 switch (asi) {
1874 case 0x82: // Primary no-fault
1875 case 0x8a: // Primary no-fault LE
1876 if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
1877 #ifdef DEBUG_ASI
1878 dump_asi("read ", last_addr, asi, size, ret);
1879 #endif
1880 return 0;
1881 }
1882 // Fall through
1883 case 0x10: // As if user primary
1884 case 0x18: // As if user primary LE
1885 case 0x80: // Primary
1886 case 0x88: // Primary LE
1887 case 0xe2: // UA2007 Primary block init
1888 case 0xe3: // UA2007 Secondary block init
1889 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1890 if ((env->def->features & CPU_FEATURE_HYPV)
1891 && env->hpstate & HS_PRIV) {
1892 switch(size) {
1893 case 1:
1894 ret = ldub_hypv(addr);
1895 break;
1896 case 2:
1897 ret = lduw_hypv(addr);
1898 break;
1899 case 4:
1900 ret = ldl_hypv(addr);
1901 break;
1902 default:
1903 case 8:
1904 ret = ldq_hypv(addr);
1905 break;
1906 }
1907 } else {
1908 switch(size) {
1909 case 1:
1910 ret = ldub_kernel(addr);
1911 break;
1912 case 2:
1913 ret = lduw_kernel(addr);
1914 break;
1915 case 4:
1916 ret = ldl_kernel(addr);
1917 break;
1918 default:
1919 case 8:
1920 ret = ldq_kernel(addr);
1921 break;
1922 }
1923 }
1924 } else {
1925 switch(size) {
1926 case 1:
1927 ret = ldub_user(addr);
1928 break;
1929 case 2:
1930 ret = lduw_user(addr);
1931 break;
1932 case 4:
1933 ret = ldl_user(addr);
1934 break;
1935 default:
1936 case 8:
1937 ret = ldq_user(addr);
1938 break;
1939 }
1940 }
1941 break;
1942 case 0x14: // Bypass
1943 case 0x15: // Bypass, non-cacheable
1944 case 0x1c: // Bypass LE
1945 case 0x1d: // Bypass, non-cacheable LE
1946 {
1947 switch(size) {
1948 case 1:
1949 ret = ldub_phys(addr);
1950 break;
1951 case 2:
1952 ret = lduw_phys(addr);
1953 break;
1954 case 4:
1955 ret = ldl_phys(addr);
1956 break;
1957 default:
1958 case 8:
1959 ret = ldq_phys(addr);
1960 break;
1961 }
1962 break;
1963 }
1964 case 0x24: // Nucleus quad LDD 128 bit atomic
1965 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
1966 // Only ldda allowed
1967 raise_exception(TT_ILL_INSN);
1968 return 0;
1969 case 0x83: // Secondary no-fault
1970 case 0x8b: // Secondary no-fault LE
1971 if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
1972 #ifdef DEBUG_ASI
1973 dump_asi("read ", last_addr, asi, size, ret);
1974 #endif
1975 return 0;
1976 }
1977 // Fall through
1978 case 0x04: // Nucleus
1979 case 0x0c: // Nucleus Little Endian (LE)
1980 case 0x11: // As if user secondary
1981 case 0x19: // As if user secondary LE
1982 case 0x4a: // UPA config
1983 case 0x81: // Secondary
1984 case 0x89: // Secondary LE
1985 // XXX
1986 break;
1987 case 0x45: // LSU
1988 ret = env->lsu;
1989 break;
1990 case 0x50: // I-MMU regs
1991 {
1992 int reg = (addr >> 3) & 0xf;
1993
1994 if (reg == 0) {
1995 // I-TSB Tag Target register
1996 ret = ultrasparc_tag_target(env->immuregs[6]);
1997 } else {
1998 ret = env->immuregs[reg];
1999 }
2000
2001 break;
2002 }
2003 case 0x51: // I-MMU 8k TSB pointer
2004 {
2005 // env->immuregs[5] holds I-MMU TSB register value
2006 // env->immuregs[6] holds I-MMU Tag Access register value
2007 ret = ultrasparc_tsb_pointer(env->immuregs[5], env->immuregs[6],
2008 8*1024);
2009 break;
2010 }
2011 case 0x52: // I-MMU 64k TSB pointer
2012 {
2013 // env->immuregs[5] holds I-MMU TSB register value
2014 // env->immuregs[6] holds I-MMU Tag Access register value
2015 ret = ultrasparc_tsb_pointer(env->immuregs[5], env->immuregs[6],
2016 64*1024);
2017 break;
2018 }
2019 case 0x55: // I-MMU data access
2020 {
2021 int reg = (addr >> 3) & 0x3f;
2022
2023 ret = env->itlb_tte[reg];
2024 break;
2025 }
2026 case 0x56: // I-MMU tag read
2027 {
2028 int reg = (addr >> 3) & 0x3f;
2029
2030 ret = env->itlb_tag[reg];
2031 break;
2032 }
2033 case 0x58: // D-MMU regs
2034 {
2035 int reg = (addr >> 3) & 0xf;
2036
2037 if (reg == 0) {
2038 // D-TSB Tag Target register
2039 ret = ultrasparc_tag_target(env->dmmuregs[6]);
2040 } else {
2041 ret = env->dmmuregs[reg];
2042 }
2043 break;
2044 }
2045 case 0x59: // D-MMU 8k TSB pointer
2046 {
2047 // env->dmmuregs[5] holds D-MMU TSB register value
2048 // env->dmmuregs[6] holds D-MMU Tag Access register value
2049 ret = ultrasparc_tsb_pointer(env->dmmuregs[5], env->dmmuregs[6],
2050 8*1024);
2051 break;
2052 }
2053 case 0x5a: // D-MMU 64k TSB pointer
2054 {
2055 // env->dmmuregs[5] holds D-MMU TSB register value
2056 // env->dmmuregs[6] holds D-MMU Tag Access register value
2057 ret = ultrasparc_tsb_pointer(env->dmmuregs[5], env->dmmuregs[6],
2058 64*1024);
2059 break;
2060 }
2061 case 0x5d: // D-MMU data access
2062 {
2063 int reg = (addr >> 3) & 0x3f;
2064
2065 ret = env->dtlb_tte[reg];
2066 break;
2067 }
2068 case 0x5e: // D-MMU tag read
2069 {
2070 int reg = (addr >> 3) & 0x3f;
2071
2072 ret = env->dtlb_tag[reg];
2073 break;
2074 }
2075 case 0x46: // D-cache data
2076 case 0x47: // D-cache tag access
2077 case 0x4b: // E-cache error enable
2078 case 0x4c: // E-cache asynchronous fault status
2079 case 0x4d: // E-cache asynchronous fault address
2080 case 0x4e: // E-cache tag data
2081 case 0x66: // I-cache instruction access
2082 case 0x67: // I-cache tag access
2083 case 0x6e: // I-cache predecode
2084 case 0x6f: // I-cache LRU etc.
2085 case 0x76: // E-cache tag
2086 case 0x7e: // E-cache tag
2087 break;
2088 case 0x5b: // D-MMU data pointer
2089 case 0x48: // Interrupt dispatch, RO
2090 case 0x49: // Interrupt data receive
2091 case 0x7f: // Incoming interrupt vector, RO
2092 // XXX
2093 break;
2094 case 0x54: // I-MMU data in, WO
2095 case 0x57: // I-MMU demap, WO
2096 case 0x5c: // D-MMU data in, WO
2097 case 0x5f: // D-MMU demap, WO
2098 case 0x77: // Interrupt vector, WO
2099 default:
2100 do_unassigned_access(addr, 0, 0, 1, size);
2101 ret = 0;
2102 break;
2103 }
2104
2105 /* Convert from little endian */
2106 switch (asi) {
2107 case 0x0c: // Nucleus Little Endian (LE)
2108 case 0x18: // As if user primary LE
2109 case 0x19: // As if user secondary LE
2110 case 0x1c: // Bypass LE
2111 case 0x1d: // Bypass, non-cacheable LE
2112 case 0x88: // Primary LE
2113 case 0x89: // Secondary LE
2114 case 0x8a: // Primary no-fault LE
2115 case 0x8b: // Secondary no-fault LE
2116 switch(size) {
2117 case 2:
2118 ret = bswap16(ret);
2119 break;
2120 case 4:
2121 ret = bswap32(ret);
2122 break;
2123 case 8:
2124 ret = bswap64(ret);
2125 break;
2126 default:
2127 break;
2128 }
2129 default:
2130 break;
2131 }
2132
2133 /* Convert to signed number */
2134 if (sign) {
2135 switch(size) {
2136 case 1:
2137 ret = (int8_t) ret;
2138 break;
2139 case 2:
2140 ret = (int16_t) ret;
2141 break;
2142 case 4:
2143 ret = (int32_t) ret;
2144 break;
2145 default:
2146 break;
2147 }
2148 }
2149 #ifdef DEBUG_ASI
2150 dump_asi("read ", last_addr, asi, size, ret);
2151 #endif
2152 return ret;
2153 }
2154
2155 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
2156 {
2157 #ifdef DEBUG_ASI
2158 dump_asi("write", addr, asi, size, val);
2159 #endif
2160 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2161 || ((env->def->features & CPU_FEATURE_HYPV)
2162 && asi >= 0x30 && asi < 0x80
2163 && !(env->hpstate & HS_PRIV)))
2164 raise_exception(TT_PRIV_ACT);
2165
2166 helper_check_align(addr, size - 1);
2167 /* Convert to little endian */
2168 switch (asi) {
2169 case 0x0c: // Nucleus Little Endian (LE)
2170 case 0x18: // As if user primary LE
2171 case 0x19: // As if user secondary LE
2172 case 0x1c: // Bypass LE
2173 case 0x1d: // Bypass, non-cacheable LE
2174 case 0x88: // Primary LE
2175 case 0x89: // Secondary LE
2176 switch(size) {
2177 case 2:
2178 addr = bswap16(addr);
2179 break;
2180 case 4:
2181 addr = bswap32(addr);
2182 break;
2183 case 8:
2184 addr = bswap64(addr);
2185 break;
2186 default:
2187 break;
2188 }
2189 default:
2190 break;
2191 }
2192
2193 switch(asi) {
2194 case 0x10: // As if user primary
2195 case 0x18: // As if user primary LE
2196 case 0x80: // Primary
2197 case 0x88: // Primary LE
2198 case 0xe2: // UA2007 Primary block init
2199 case 0xe3: // UA2007 Secondary block init
2200 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
2201 if ((env->def->features & CPU_FEATURE_HYPV)
2202 && env->hpstate & HS_PRIV) {
2203 switch(size) {
2204 case 1:
2205 stb_hypv(addr, val);
2206 break;
2207 case 2:
2208 stw_hypv(addr, val);
2209 break;
2210 case 4:
2211 stl_hypv(addr, val);
2212 break;
2213 case 8:
2214 default:
2215 stq_hypv(addr, val);
2216 break;
2217 }
2218 } else {
2219 switch(size) {
2220 case 1:
2221 stb_kernel(addr, val);
2222 break;
2223 case 2:
2224 stw_kernel(addr, val);
2225 break;
2226 case 4:
2227 stl_kernel(addr, val);
2228 break;
2229 case 8:
2230 default:
2231 stq_kernel(addr, val);
2232 break;
2233 }
2234 }
2235 } else {
2236 switch(size) {
2237 case 1:
2238 stb_user(addr, val);
2239 break;
2240 case 2:
2241 stw_user(addr, val);
2242 break;
2243 case 4:
2244 stl_user(addr, val);
2245 break;
2246 case 8:
2247 default:
2248 stq_user(addr, val);
2249 break;
2250 }
2251 }
2252 break;
2253 case 0x14: // Bypass
2254 case 0x15: // Bypass, non-cacheable
2255 case 0x1c: // Bypass LE
2256 case 0x1d: // Bypass, non-cacheable LE
2257 {
2258 switch(size) {
2259 case 1:
2260 stb_phys(addr, val);
2261 break;
2262 case 2:
2263 stw_phys(addr, val);
2264 break;
2265 case 4:
2266 stl_phys(addr, val);
2267 break;
2268 case 8:
2269 default:
2270 stq_phys(addr, val);
2271 break;
2272 }
2273 }
2274 return;
2275 case 0x24: // Nucleus quad LDD 128 bit atomic
2276 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2277 // Only ldda allowed
2278 raise_exception(TT_ILL_INSN);
2279 return;
2280 case 0x04: // Nucleus
2281 case 0x0c: // Nucleus Little Endian (LE)
2282 case 0x11: // As if user secondary
2283 case 0x19: // As if user secondary LE
2284 case 0x4a: // UPA config
2285 case 0x81: // Secondary
2286 case 0x89: // Secondary LE
2287 // XXX
2288 return;
2289 case 0x45: // LSU
2290 {
2291 uint64_t oldreg;
2292
2293 oldreg = env->lsu;
2294 env->lsu = val & (DMMU_E | IMMU_E);
2295 // Mappings generated during D/I MMU disabled mode are
2296 // invalid in normal mode
2297 if (oldreg != env->lsu) {
2298 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
2299 oldreg, env->lsu);
2300 #ifdef DEBUG_MMU
2301 dump_mmu(env);
2302 #endif
2303 tlb_flush(env, 1);
2304 }
2305 return;
2306 }
2307 case 0x50: // I-MMU regs
2308 {
2309 int reg = (addr >> 3) & 0xf;
2310 uint64_t oldreg;
2311
2312 oldreg = env->immuregs[reg];
2313 switch(reg) {
2314 case 0: // RO
2315 case 4:
2316 return;
2317 case 1: // Not in I-MMU
2318 case 2:
2319 case 7:
2320 case 8:
2321 return;
2322 case 3: // SFSR
2323 if ((val & 1) == 0)
2324 val = 0; // Clear SFSR
2325 break;
2326 case 5: // TSB access
2327 case 6: // Tag access
2328 default:
2329 break;
2330 }
2331 env->immuregs[reg] = val;
2332 if (oldreg != env->immuregs[reg]) {
2333 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
2334 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
2335 }
2336 #ifdef DEBUG_MMU
2337 dump_mmu(env);
2338 #endif
2339 return;
2340 }
2341 case 0x54: // I-MMU data in
2342 {
2343 unsigned int i;
2344
2345 // Try finding an invalid entry
2346 for (i = 0; i < 64; i++) {
2347 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
2348 env->itlb_tag[i] = env->immuregs[6];
2349 env->itlb_tte[i] = val;
2350 return;
2351 }
2352 }
2353 // Try finding an unlocked entry
2354 for (i = 0; i < 64; i++) {
2355 if ((env->itlb_tte[i] & 0x40) == 0) {
2356 env->itlb_tag[i] = env->immuregs[6];
2357 env->itlb_tte[i] = val;
2358 return;
2359 }
2360 }
2361 // error state?
2362 return;
2363 }
2364 case 0x55: // I-MMU data access
2365 {
2366 // TODO: auto demap
2367
2368 unsigned int i = (addr >> 3) & 0x3f;
2369
2370 env->itlb_tag[i] = env->immuregs[6];
2371 env->itlb_tte[i] = val;
2372 return;
2373 }
2374 case 0x57: // I-MMU demap
2375 {
2376 unsigned int i;
2377
2378 for (i = 0; i < 64; i++) {
2379 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
2380 target_ulong mask = 0xffffffffffffe000ULL;
2381
2382 mask <<= 3 * ((env->itlb_tte[i] >> 61) & 3);
2383 if ((val & mask) == (env->itlb_tag[i] & mask)) {
2384 env->itlb_tag[i] = 0;
2385 env->itlb_tte[i] = 0;
2386 }
2387 return;
2388 }
2389 }
2390 }
2391 return;
2392 case 0x58: // D-MMU regs
2393 {
2394 int reg = (addr >> 3) & 0xf;
2395 uint64_t oldreg;
2396
2397 oldreg = env->dmmuregs[reg];
2398 switch(reg) {
2399 case 0: // RO
2400 case 4:
2401 return;
2402 case 3: // SFSR
2403 if ((val & 1) == 0) {
2404 val = 0; // Clear SFSR, Fault address
2405 env->dmmuregs[4] = 0;
2406 }
2407 env->dmmuregs[reg] = val;
2408 break;
2409 case 1: // Primary context
2410 case 2: // Secondary context
2411 case 5: // TSB access
2412 case 6: // Tag access
2413 case 7: // Virtual Watchpoint
2414 case 8: // Physical Watchpoint
2415 default:
2416 break;
2417 }
2418 env->dmmuregs[reg] = val;
2419 if (oldreg != env->dmmuregs[reg]) {
2420 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
2421 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
2422 }
2423 #ifdef DEBUG_MMU
2424 dump_mmu(env);
2425 #endif
2426 return;
2427 }
2428 case 0x5c: // D-MMU data in
2429 {
2430 unsigned int i;
2431
2432 // Try finding an invalid entry
2433 for (i = 0; i < 64; i++) {
2434 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
2435 env->dtlb_tag[i] = env->dmmuregs[6];
2436 env->dtlb_tte[i] = val;
2437 return;
2438 }
2439 }
2440 // Try finding an unlocked entry
2441 for (i = 0; i < 64; i++) {
2442 if ((env->dtlb_tte[i] & 0x40) == 0) {
2443 env->dtlb_tag[i] = env->dmmuregs[6];
2444 env->dtlb_tte[i] = val;
2445 return;
2446 }
2447 }
2448 // error state?
2449 return;
2450 }
2451 case 0x5d: // D-MMU data access
2452 {
2453 unsigned int i = (addr >> 3) & 0x3f;
2454
2455 env->dtlb_tag[i] = env->dmmuregs[6];
2456 env->dtlb_tte[i] = val;
2457 return;
2458 }
2459 case 0x5f: // D-MMU demap
2460 {
2461 unsigned int i;
2462
2463 for (i = 0; i < 64; i++) {
2464 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
2465 target_ulong mask = 0xffffffffffffe000ULL;
2466
2467 mask <<= 3 * ((env->dtlb_tte[i] >> 61) & 3);
2468 if ((val & mask) == (env->dtlb_tag[i] & mask)) {
2469 env->dtlb_tag[i] = 0;
2470 env->dtlb_tte[i] = 0;
2471 }
2472 return;
2473 }
2474 }
2475 }
2476 return;
2477 case 0x49: // Interrupt data receive
2478 // XXX
2479 return;
2480 case 0x46: // D-cache data
2481 case 0x47: // D-cache tag access
2482 case 0x4b: // E-cache error enable
2483 case 0x4c: // E-cache asynchronous fault status
2484 case 0x4d: // E-cache asynchronous fault address
2485 case 0x4e: // E-cache tag data
2486 case 0x66: // I-cache instruction access
2487 case 0x67: // I-cache tag access
2488 case 0x6e: // I-cache predecode
2489 case 0x6f: // I-cache LRU etc.
2490 case 0x76: // E-cache tag
2491 case 0x7e: // E-cache tag
2492 return;
2493 case 0x51: // I-MMU 8k TSB pointer, RO
2494 case 0x52: // I-MMU 64k TSB pointer, RO
2495 case 0x56: // I-MMU tag read, RO
2496 case 0x59: // D-MMU 8k TSB pointer, RO
2497 case 0x5a: // D-MMU 64k TSB pointer, RO
2498 case 0x5b: // D-MMU data pointer, RO
2499 case 0x5e: // D-MMU tag read, RO
2500 case 0x48: // Interrupt dispatch, RO
2501 case 0x7f: // Incoming interrupt vector, RO
2502 case 0x82: // Primary no-fault, RO
2503 case 0x83: // Secondary no-fault, RO
2504 case 0x8a: // Primary no-fault LE, RO
2505 case 0x8b: // Secondary no-fault LE, RO
2506 default:
2507 do_unassigned_access(addr, 1, 0, 1, size);
2508 return;
2509 }
2510 }
2511 #endif /* CONFIG_USER_ONLY */
2512
2513 void helper_ldda_asi(target_ulong addr, int asi, int rd)
2514 {
2515 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2516 || ((env->def->features & CPU_FEATURE_HYPV)
2517 && asi >= 0x30 && asi < 0x80
2518 && !(env->hpstate & HS_PRIV)))
2519 raise_exception(TT_PRIV_ACT);
2520
2521 switch (asi) {
2522 case 0x24: // Nucleus quad LDD 128 bit atomic
2523 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2524 helper_check_align(addr, 0xf);
2525 if (rd == 0) {
2526 env->gregs[1] = ldq_kernel(addr + 8);
2527 if (asi == 0x2c)
2528 bswap64s(&env->gregs[1]);
2529 } else if (rd < 8) {
2530 env->gregs[rd] = ldq_kernel(addr);
2531 env->gregs[rd + 1] = ldq_kernel(addr + 8);
2532 if (asi == 0x2c) {
2533 bswap64s(&env->gregs[rd]);
2534 bswap64s(&env->gregs[rd + 1]);
2535 }
2536 } else {
2537 env->regwptr[rd] = ldq_kernel(addr);
2538 env->regwptr[rd + 1] = ldq_kernel(addr + 8);
2539 if (asi == 0x2c) {
2540 bswap64s(&env->regwptr[rd]);
2541 bswap64s(&env->regwptr[rd + 1]);
2542 }
2543 }
2544 break;
2545 default:
2546 helper_check_align(addr, 0x3);
2547 if (rd == 0)
2548 env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0);
2549 else if (rd < 8) {
2550 env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0);
2551 env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2552 } else {
2553 env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0);
2554 env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2555 }
2556 break;
2557 }
2558 }
2559
2560 void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
2561 {
2562 unsigned int i;
2563 target_ulong val;
2564
2565 helper_check_align(addr, 3);
2566 switch (asi) {
2567 case 0xf0: // Block load primary
2568 case 0xf1: // Block load secondary
2569 case 0xf8: // Block load primary LE
2570 case 0xf9: // Block load secondary LE
2571 if (rd & 7) {
2572 raise_exception(TT_ILL_INSN);
2573 return;
2574 }
2575 helper_check_align(addr, 0x3f);
2576 for (i = 0; i < 16; i++) {
2577 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4,
2578 0);
2579 addr += 4;
2580 }
2581
2582 return;
2583 default:
2584 break;
2585 }
2586
2587 val = helper_ld_asi(addr, asi, size, 0);
2588 switch(size) {
2589 default:
2590 case 4:
2591 *((uint32_t *)&env->fpr[rd]) = val;
2592 break;
2593 case 8:
2594 *((int64_t *)&DT0) = val;
2595 break;
2596 case 16:
2597 // XXX
2598 break;
2599 }
2600 }
2601
2602 void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
2603 {
2604 unsigned int i;
2605 target_ulong val = 0;
2606
2607 helper_check_align(addr, 3);
2608 switch (asi) {
2609 case 0xe0: // UA2007 Block commit store primary (cache flush)
2610 case 0xe1: // UA2007 Block commit store secondary (cache flush)
2611 case 0xf0: // Block store primary
2612 case 0xf1: // Block store secondary
2613 case 0xf8: // Block store primary LE
2614 case 0xf9: // Block store secondary LE
2615 if (rd & 7) {
2616 raise_exception(TT_ILL_INSN);
2617 return;
2618 }
2619 helper_check_align(addr, 0x3f);
2620 for (i = 0; i < 16; i++) {
2621 val = *(uint32_t *)&env->fpr[rd++];
2622 helper_st_asi(addr, val, asi & 0x8f, 4);
2623 addr += 4;
2624 }
2625
2626 return;
2627 default:
2628 break;
2629 }
2630
2631 switch(size) {
2632 default:
2633 case 4:
2634 val = *((uint32_t *)&env->fpr[rd]);
2635 break;
2636 case 8:
2637 val = *((int64_t *)&DT0);
2638 break;
2639 case 16:
2640 // XXX
2641 break;
2642 }
2643 helper_st_asi(addr, val, asi, size);
2644 }
2645
2646 target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
2647 target_ulong val2, uint32_t asi)
2648 {
2649 target_ulong ret;
2650
2651 val2 &= 0xffffffffUL;
2652 ret = helper_ld_asi(addr, asi, 4, 0);
2653 ret &= 0xffffffffUL;
2654 if (val2 == ret)
2655 helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4);
2656 return ret;
2657 }
2658
2659 target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
2660 target_ulong val2, uint32_t asi)
2661 {
2662 target_ulong ret;
2663
2664 ret = helper_ld_asi(addr, asi, 8, 0);
2665 if (val2 == ret)
2666 helper_st_asi(addr, val1, asi, 8);
2667 return ret;
2668 }
2669 #endif /* TARGET_SPARC64 */
2670
2671 #ifndef TARGET_SPARC64
2672 void helper_rett(void)
2673 {
2674 unsigned int cwp;
2675
2676 if (env->psret == 1)
2677 raise_exception(TT_ILL_INSN);
2678
2679 env->psret = 1;
2680 cwp = cpu_cwp_inc(env, env->cwp + 1) ;
2681 if (env->wim & (1 << cwp)) {
2682 raise_exception(TT_WIN_UNF);
2683 }
2684 set_cwp(cwp);
2685 env->psrs = env->psrps;
2686 }
2687 #endif
2688
2689 target_ulong helper_udiv(target_ulong a, target_ulong b)
2690 {
2691 uint64_t x0;
2692 uint32_t x1;
2693
2694 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
2695 x1 = b;
2696
2697 if (x1 == 0) {
2698 raise_exception(TT_DIV_ZERO);
2699 }
2700
2701 x0 = x0 / x1;
2702 if (x0 > 0xffffffff) {
2703 env->cc_src2 = 1;
2704 return 0xffffffff;
2705 } else {
2706 env->cc_src2 = 0;
2707 return x0;
2708 }
2709 }
2710
2711 target_ulong helper_sdiv(target_ulong a, target_ulong b)
2712 {
2713 int64_t x0;
2714 int32_t x1;
2715
2716 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
2717 x1 = b;
2718
2719 if (x1 == 0) {
2720 raise_exception(TT_DIV_ZERO);
2721 }
2722
2723 x0 = x0 / x1;
2724 if ((int32_t) x0 != x0) {
2725 env->cc_src2 = 1;
2726 return x0 < 0? 0x80000000: 0x7fffffff;
2727 } else {
2728 env->cc_src2 = 0;
2729 return x0;
2730 }
2731 }
2732
2733 void helper_stdf(target_ulong addr, int mem_idx)
2734 {
2735 helper_check_align(addr, 7);
2736 #if !defined(CONFIG_USER_ONLY)
2737 switch (mem_idx) {
2738 case 0:
2739 stfq_user(addr, DT0);
2740 break;
2741 case 1:
2742 stfq_kernel(addr, DT0);
2743 break;
2744 #ifdef TARGET_SPARC64
2745 case 2:
2746 stfq_hypv(addr, DT0);
2747 break;
2748 #endif
2749 default:
2750 break;
2751 }
2752 #else
2753 address_mask(env, &addr);
2754 stfq_raw(addr, DT0);
2755 #endif
2756 }
2757
2758 void helper_lddf(target_ulong addr, int mem_idx)
2759 {
2760 helper_check_align(addr, 7);
2761 #if !defined(CONFIG_USER_ONLY)
2762 switch (mem_idx) {
2763 case 0:
2764 DT0 = ldfq_user(addr);
2765 break;
2766 case 1:
2767 DT0 = ldfq_kernel(addr);
2768 break;
2769 #ifdef TARGET_SPARC64
2770 case 2:
2771 DT0 = ldfq_hypv(addr);
2772 break;
2773 #endif
2774 default:
2775 break;
2776 }
2777 #else
2778 address_mask(env, &addr);
2779 DT0 = ldfq_raw(addr);
2780 #endif
2781 }
2782
2783 void helper_ldqf(target_ulong addr, int mem_idx)
2784 {
2785 // XXX add 128 bit load
2786 CPU_QuadU u;
2787
2788 helper_check_align(addr, 7);
2789 #if !defined(CONFIG_USER_ONLY)
2790 switch (mem_idx) {
2791 case 0:
2792 u.ll.upper = ldq_user(addr);
2793 u.ll.lower = ldq_user(addr + 8);
2794 QT0 = u.q;
2795 break;
2796 case 1:
2797 u.ll.upper = ldq_kernel(addr);
2798 u.ll.lower = ldq_kernel(addr + 8);
2799 QT0 = u.q;
2800 break;
2801 #ifdef TARGET_SPARC64
2802 case 2:
2803 u.ll.upper = ldq_hypv(addr);
2804 u.ll.lower = ldq_hypv(addr + 8);
2805 QT0 = u.q;
2806 break;
2807 #endif
2808 default:
2809 break;
2810 }
2811 #else
2812 address_mask(env, &addr);
2813 u.ll.upper = ldq_raw(addr);
2814 u.ll.lower = ldq_raw((addr + 8) & 0xffffffffULL);
2815 QT0 = u.q;
2816 #endif
2817 }
2818
2819 void helper_stqf(target_ulong addr, int mem_idx)
2820 {
2821 // XXX add 128 bit store
2822 CPU_QuadU u;
2823
2824 helper_check_align(addr, 7);
2825 #if !defined(CONFIG_USER_ONLY)
2826 switch (mem_idx) {
2827 case 0:
2828 u.q = QT0;
2829 stq_user(addr, u.ll.upper);
2830 stq_user(addr + 8, u.ll.lower);
2831 break;
2832 case 1:
2833 u.q = QT0;
2834 stq_kernel(addr, u.ll.upper);
2835 stq_kernel(addr + 8, u.ll.lower);
2836 break;
2837 #ifdef TARGET_SPARC64
2838 case 2:
2839 u.q = QT0;
2840 stq_hypv(addr, u.ll.upper);
2841 stq_hypv(addr + 8, u.ll.lower);
2842 break;
2843 #endif
2844 default:
2845 break;
2846 }
2847 #else
2848 u.q = QT0;
2849 address_mask(env, &addr);
2850 stq_raw(addr, u.ll.upper);
2851 stq_raw((addr + 8) & 0xffffffffULL, u.ll.lower);
2852 #endif
2853 }
2854
2855 static inline void set_fsr(void)
2856 {
2857 int rnd_mode;
2858
2859 switch (env->fsr & FSR_RD_MASK) {
2860 case FSR_RD_NEAREST:
2861 rnd_mode = float_round_nearest_even;
2862 break;
2863 default:
2864 case FSR_RD_ZERO:
2865 rnd_mode = float_round_to_zero;
2866 break;
2867 case FSR_RD_POS:
2868 rnd_mode = float_round_up;
2869 break;
2870 case FSR_RD_NEG:
2871 rnd_mode = float_round_down;
2872 break;
2873 }
2874 set_float_rounding_mode(rnd_mode, &env->fp_status);
2875 }
2876
2877 void helper_ldfsr(uint32_t new_fsr)
2878 {
2879 env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
2880 set_fsr();
2881 }
2882
2883 #ifdef TARGET_SPARC64
2884 void helper_ldxfsr(uint64_t new_fsr)
2885 {
2886 env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
2887 set_fsr();
2888 }
2889 #endif
2890
2891 void helper_debug(void)
2892 {
2893 env->exception_index = EXCP_DEBUG;
2894 cpu_loop_exit();
2895 }
2896
2897 #ifndef TARGET_SPARC64
2898 /* XXX: use another pointer for %iN registers to avoid slow wrapping
2899 handling ? */
2900 void helper_save(void)
2901 {
2902 uint32_t cwp;
2903
2904 cwp = cpu_cwp_dec(env, env->cwp - 1);
2905 if (env->wim & (1 << cwp)) {
2906 raise_exception(TT_WIN_OVF);
2907 }
2908 set_cwp(cwp);
2909 }
2910
2911 void helper_restore(void)
2912 {
2913 uint32_t cwp;
2914
2915 cwp = cpu_cwp_inc(env, env->cwp + 1);
2916 if (env->wim & (1 << cwp)) {
2917 raise_exception(TT_WIN_UNF);
2918 }
2919 set_cwp(cwp);
2920 }
2921
2922 void helper_wrpsr(target_ulong new_psr)
2923 {
2924 if ((new_psr & PSR_CWP) >= env->nwindows)
2925 raise_exception(TT_ILL_INSN);
2926 else
2927 PUT_PSR(env, new_psr);
2928 }
2929
2930 target_ulong helper_rdpsr(void)
2931 {
2932 return GET_PSR(env);
2933 }
2934
2935 #else
2936 /* XXX: use another pointer for %iN registers to avoid slow wrapping
2937 handling ? */
2938 void helper_save(void)
2939 {
2940 uint32_t cwp;
2941
2942 cwp = cpu_cwp_dec(env, env->cwp - 1);
2943 if (env->cansave == 0) {
2944 raise_exception(TT_SPILL | (env->otherwin != 0 ?
2945 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2946 ((env->wstate & 0x7) << 2)));
2947 } else {
2948 if (env->cleanwin - env->canrestore == 0) {
2949 // XXX Clean windows without trap
2950 raise_exception(TT_CLRWIN);
2951 } else {
2952 env->cansave--;
2953 env->canrestore++;
2954 set_cwp(cwp);
2955 }
2956 }
2957 }
2958
2959 void helper_restore(void)
2960 {
2961 uint32_t cwp;
2962
2963 cwp = cpu_cwp_inc(env, env->cwp + 1);
2964 if (env->canrestore == 0) {
2965 raise_exception(TT_FILL | (env->otherwin != 0 ?
2966 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2967 ((env->wstate & 0x7) << 2)));
2968 } else {
2969 env->cansave++;
2970 env->canrestore--;
2971 set_cwp(cwp);
2972 }
2973 }
2974
2975 void helper_flushw(void)
2976 {
2977 if (env->cansave != env->nwindows - 2) {
2978 raise_exception(TT_SPILL | (env->otherwin != 0 ?
2979 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2980 ((env->wstate & 0x7) << 2)));
2981 }
2982 }
2983
2984 void helper_saved(void)
2985 {
2986 env->cansave++;
2987 if (env->otherwin == 0)
2988 env->canrestore--;
2989 else
2990 env->otherwin--;
2991 }
2992
2993 void helper_restored(void)
2994 {
2995 env->canrestore++;
2996 if (env->cleanwin < env->nwindows - 1)
2997 env->cleanwin++;
2998 if (env->otherwin == 0)
2999 env->cansave--;
3000 else
3001 env->otherwin--;
3002 }
3003
3004 target_ulong helper_rdccr(void)
3005 {
3006 return GET_CCR(env);
3007 }
3008
3009 void helper_wrccr(target_ulong new_ccr)
3010 {
3011 PUT_CCR(env, new_ccr);
3012 }
3013
3014 // CWP handling is reversed in V9, but we still use the V8 register
3015 // order.
3016 target_ulong helper_rdcwp(void)
3017 {
3018 return GET_CWP64(env);
3019 }
3020
3021 void helper_wrcwp(target_ulong new_cwp)
3022 {
3023 PUT_CWP64(env, new_cwp);
3024 }
3025
3026 // This function uses non-native bit order
3027 #define GET_FIELD(X, FROM, TO) \
3028 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
3029
3030 // This function uses the order in the manuals, i.e. bit 0 is 2^0
3031 #define GET_FIELD_SP(X, FROM, TO) \
3032 GET_FIELD(X, 63 - (TO), 63 - (FROM))
3033
3034 target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
3035 {
3036 return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
3037 (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
3038 (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
3039 (GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
3040 (GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
3041 (GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
3042 (((pixel_addr >> 55) & 1) << 4) |
3043 (GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
3044 GET_FIELD_SP(pixel_addr, 11, 12);
3045 }
3046
3047 target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
3048 {
3049 uint64_t tmp;
3050
3051 tmp = addr + offset;
3052 env->gsr &= ~7ULL;
3053 env->gsr |= tmp & 7ULL;
3054 return tmp & ~7ULL;
3055 }
3056
3057 target_ulong helper_popc(target_ulong val)
3058 {
3059 return ctpop64(val);
3060 }
3061
3062 static inline uint64_t *get_gregset(uint64_t pstate)
3063 {
3064 switch (pstate) {
3065 default:
3066 case 0:
3067 return env->bgregs;
3068 case PS_AG:
3069 return env->agregs;
3070 case PS_MG:
3071 return env->mgregs;
3072 case PS_IG:
3073 return env->igregs;
3074 }
3075 }
3076
3077 static inline void change_pstate(uint64_t new_pstate)
3078 {
3079 uint64_t pstate_regs, new_pstate_regs;
3080 uint64_t *src, *dst;
3081
3082 pstate_regs = env->pstate & 0xc01;
3083 new_pstate_regs = new_pstate & 0xc01;
3084 if (new_pstate_regs != pstate_regs) {
3085 // Switch global register bank
3086 src = get_gregset(new_pstate_regs);
3087 dst = get_gregset(pstate_regs);
3088 memcpy32(dst, env->gregs);
3089 memcpy32(env->gregs, src);
3090 }
3091 env->pstate = new_pstate;
3092 }
3093
3094 void helper_wrpstate(target_ulong new_state)
3095 {
3096 if (!(env->def->features & CPU_FEATURE_GL))
3097 change_pstate(new_state & 0xf3f);
3098 }
3099
3100 void helper_done(void)
3101 {
3102 env->pc = env->tsptr->tpc;
3103 env->npc = env->tsptr->tnpc + 4;
3104 PUT_CCR(env, env->tsptr->tstate >> 32);
3105 env->asi = (env->tsptr->tstate >> 24) & 0xff;
3106 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
3107 PUT_CWP64(env, env->tsptr->tstate & 0xff);
3108 env->tl--;
3109 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
3110 }
3111
3112 void helper_retry(void)
3113 {
3114 env->pc = env->tsptr->tpc;
3115 env->npc = env->tsptr->tnpc;
3116 PUT_CCR(env, env->tsptr->tstate >> 32);
3117 env->asi = (env->tsptr->tstate >> 24) & 0xff;
3118 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
3119 PUT_CWP64(env, env->tsptr->tstate & 0xff);
3120 env->tl--;
3121 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
3122 }
3123
3124 void helper_set_softint(uint64_t value)
3125 {
3126 env->softint |= (uint32_t)value;
3127 }
3128
3129 void helper_clear_softint(uint64_t value)
3130 {
3131 env->softint &= (uint32_t)~value;
3132 }
3133
3134 void helper_write_softint(uint64_t value)
3135 {
3136 env->softint = (uint32_t)value;
3137 }
3138 #endif
3139
3140 void helper_flush(target_ulong addr)
3141 {
3142 addr &= ~7;
3143 tb_invalidate_page_range(addr, addr + 8);
3144 }
3145
3146 #ifdef TARGET_SPARC64
3147 #ifdef DEBUG_PCALL
3148 static const char * const excp_names[0x80] = {
3149 [TT_TFAULT] = "Instruction Access Fault",
3150 [TT_TMISS] = "Instruction Access MMU Miss",
3151 [TT_CODE_ACCESS] = "Instruction Access Error",
3152 [TT_ILL_INSN] = "Illegal Instruction",
3153 [TT_PRIV_INSN] = "Privileged Instruction",
3154 [TT_NFPU_INSN] = "FPU Disabled",
3155 [TT_FP_EXCP] = "FPU Exception",
3156 [TT_TOVF] = "Tag Overflow",
3157 [TT_CLRWIN] = "Clean Windows",
3158 [TT_DIV_ZERO] = "Division By Zero",
3159 [TT_DFAULT] = "Data Access Fault",
3160 [TT_DMISS] = "Data Access MMU Miss",
3161 [TT_DATA_ACCESS] = "Data Access Error",
3162 [TT_DPROT] = "Data Protection Error",
3163 [TT_UNALIGNED] = "Unaligned Memory Access",
3164 [TT_PRIV_ACT] = "Privileged Action",
3165 [TT_EXTINT | 0x1] = "External Interrupt 1",
3166 [TT_EXTINT | 0x2] = "External Interrupt 2",
3167 [TT_EXTINT | 0x3] = "External Interrupt 3",
3168 [TT_EXTINT | 0x4] = "External Interrupt 4",
3169 [TT_EXTINT | 0x5] = "External Interrupt 5",
3170 [TT_EXTINT | 0x6] = "External Interrupt 6",
3171 [TT_EXTINT | 0x7] = "External Interrupt 7",
3172 [TT_EXTINT | 0x8] = "External Interrupt 8",
3173 [TT_EXTINT | 0x9] = "External Interrupt 9",
3174 [TT_EXTINT | 0xa] = "External Interrupt 10",
3175 [TT_EXTINT | 0xb] = "External Interrupt 11",
3176 [TT_EXTINT | 0xc] = "External Interrupt 12",
3177 [TT_EXTINT | 0xd] = "External Interrupt 13",
3178 [TT_EXTINT | 0xe] = "External Interrupt 14",
3179 [TT_EXTINT | 0xf] = "External Interrupt 15",
3180 };
3181 #endif
3182
3183 void do_interrupt(CPUState *env)
3184 {
3185 int intno = env->exception_index;
3186
3187 #ifdef DEBUG_PCALL
3188 if (qemu_loglevel_mask(CPU_LOG_INT)) {
3189 static int count;
3190 const char *name;
3191
3192 if (intno < 0 || intno >= 0x180)
3193 name = "Unknown";
3194 else if (intno >= 0x100)
3195 name = "Trap Instruction";
3196 else if (intno >= 0xc0)
3197 name = "Window Fill";
3198 else if (intno >= 0x80)
3199 name = "Window Spill";
3200 else {
3201 name = excp_names[intno];
3202 if (!name)
3203 name = "Unknown";
3204 }
3205
3206 qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
3207 " SP=%016" PRIx64 "\n",
3208 count, name, intno,
3209 env->pc,
3210 env->npc, env->regwptr[6]);
3211 log_cpu_state(env, 0);
3212 #if 0
3213 {
3214 int i;
3215 uint8_t *ptr;
3216
3217 qemu_log(" code=");
3218 ptr = (uint8_t *)env->pc;
3219 for(i = 0; i < 16; i++) {
3220 qemu_log(" %02x", ldub(ptr + i));
3221 }
3222 qemu_log("\n");
3223 }
3224 #endif
3225 count++;
3226 }
3227 #endif
3228 #if !defined(CONFIG_USER_ONLY)
3229 if (env->tl >= env->maxtl) {
3230 cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
3231 " Error state", env->exception_index, env->tl, env->maxtl);
3232 return;
3233 }
3234 #endif
3235 if (env->tl < env->maxtl - 1) {
3236 env->tl++;
3237 } else {
3238 env->pstate |= PS_RED;
3239 if (env->tl < env->maxtl)
3240 env->tl++;
3241 }
3242 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
3243 env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
3244 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
3245 GET_CWP64(env);
3246 env->tsptr->tpc = env->pc;
3247 env->tsptr->tnpc = env->npc;
3248 env->tsptr->tt = intno;
3249 if (!(env->def->features & CPU_FEATURE_GL)) {
3250 switch (intno) {
3251 case TT_IVEC:
3252 change_pstate(PS_PEF | PS_PRIV | PS_IG);
3253 break;
3254 case TT_TFAULT:
3255 case TT_TMISS:
3256 case TT_DFAULT:
3257 case TT_DMISS:
3258 case TT_DPROT:
3259 change_pstate(PS_PEF | PS_PRIV | PS_MG);
3260 break;
3261 default:
3262 change_pstate(PS_PEF | PS_PRIV | PS_AG);
3263 break;
3264 }
3265 }
3266 if (intno == TT_CLRWIN)
3267 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
3268 else if ((intno & 0x1c0) == TT_SPILL)
3269 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
3270 else if ((intno & 0x1c0) == TT_FILL)
3271 cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
3272 env->tbr &= ~0x7fffULL;
3273 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
3274 env->pc = env->tbr;
3275 env->npc = env->pc + 4;
3276 env->exception_index = 0;
3277 }
3278 #else
3279 #ifdef DEBUG_PCALL
3280 static const char * const excp_names[0x80] = {
3281 [TT_TFAULT] = "Instruction Access Fault",
3282 [TT_ILL_INSN] = "Illegal Instruction",
3283 [TT_PRIV_INSN] = "Privileged Instruction",
3284 [TT_NFPU_INSN] = "FPU Disabled",
3285 [TT_WIN_OVF] = "Window Overflow",
3286 [TT_WIN_UNF] = "Window Underflow",
3287 [TT_UNALIGNED] = "Unaligned Memory Access",
3288 [TT_FP_EXCP] = "FPU Exception",
3289 [TT_DFAULT] = "Data Access Fault",
3290 [TT_TOVF] = "Tag Overflow",
3291 [TT_EXTINT | 0x1] = "External Interrupt 1",
3292 [TT_EXTINT | 0x2] = "External Interrupt 2",
3293 [TT_EXTINT | 0x3] = "External Interrupt 3",
3294 [TT_EXTINT | 0x4] = "External Interrupt 4",
3295 [TT_EXTINT | 0x5] = "External Interrupt 5",
3296 [TT_EXTINT | 0x6] = "External Interrupt 6",
3297 [TT_EXTINT | 0x7] = "External Interrupt 7",
3298 [TT_EXTINT | 0x8] = "External Interrupt 8",
3299 [TT_EXTINT | 0x9] = "External Interrupt 9",
3300 [TT_EXTINT | 0xa] = "External Interrupt 10",
3301 [TT_EXTINT | 0xb] = "External Interrupt 11",
3302 [TT_EXTINT | 0xc] = "External Interrupt 12",
3303 [TT_EXTINT | 0xd] = "External Interrupt 13",
3304 [TT_EXTINT | 0xe] = "External Interrupt 14",
3305 [TT_EXTINT | 0xf] = "External Interrupt 15",
3306 [TT_TOVF] = "Tag Overflow",
3307 [TT_CODE_ACCESS] = "Instruction Access Error",
3308 [TT_DATA_ACCESS] = "Data Access Error",
3309 [TT_DIV_ZERO] = "Division By Zero",
3310 [TT_NCP_INSN] = "Coprocessor Disabled",
3311 };
3312 #endif
3313
3314 void do_interrupt(CPUState *env)
3315 {
3316 int cwp, intno = env->exception_index;
3317
3318 #ifdef DEBUG_PCALL
3319 if (qemu_loglevel_mask(CPU_LOG_INT)) {
3320 static int count;
3321 const char *name;
3322
3323 if (intno < 0 || intno >= 0x100)
3324 name = "Unknown";
3325 else if (intno >= 0x80)
3326 name = "Trap Instruction";
3327 else {
3328 name = excp_names[intno];
3329 if (!name)
3330 name = "Unknown";
3331 }
3332
3333 qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
3334 count, name, intno,
3335 env->pc,
3336 env->npc, env->regwptr[6]);
3337 log_cpu_state(env, 0);
3338 #if 0
3339 {
3340 int i;
3341 uint8_t *ptr;
3342
3343 qemu_log(" code=");
3344 ptr = (uint8_t *)env->pc;
3345 for(i = 0; i < 16; i++) {
3346 qemu_log(" %02x", ldub(ptr + i));
3347 }
3348 qemu_log("\n");
3349 }
3350 #endif
3351 count++;
3352 }
3353 #endif
3354 #if !defined(CONFIG_USER_ONLY)
3355 if (env->psret == 0) {
3356 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
3357 env->exception_index);
3358 return;
3359 }
3360 #endif
3361 env->psret = 0;
3362 cwp = cpu_cwp_dec(env, env->cwp - 1);
3363 cpu_set_cwp(env, cwp);
3364 env->regwptr[9] = env->pc;
3365 env->regwptr[10] = env->npc;
3366 env->psrps = env->psrs;
3367 env->psrs = 1;
3368 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
3369 env->pc = env->tbr;
3370 env->npc = env->pc + 4;
3371 env->exception_index = 0;
3372 }
3373 #endif
3374
3375 #if !defined(CONFIG_USER_ONLY)
3376
3377 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
3378 void *retaddr);
3379
3380 #define MMUSUFFIX _mmu
3381 #define ALIGNED_ONLY
3382
3383 #define SHIFT 0
3384 #include "softmmu_template.h"
3385
3386 #define SHIFT 1
3387 #include "softmmu_template.h"
3388
3389 #define SHIFT 2
3390 #include "softmmu_template.h"
3391
3392 #define SHIFT 3
3393 #include "softmmu_template.h"
3394
3395 /* XXX: make it generic ? */
3396 static void cpu_restore_state2(void *retaddr)
3397 {
3398 TranslationBlock *tb;
3399 unsigned long pc;
3400
3401 if (retaddr) {
3402 /* now we have a real cpu fault */
3403 pc = (unsigned long)retaddr;
3404 tb = tb_find_pc(pc);
3405 if (tb) {
3406 /* the PC is inside the translated code. It means that we have
3407 a virtual CPU fault */
3408 cpu_restore_state(tb, env, pc, (void *)(long)env->cond);
3409 }
3410 }
3411 }
3412
3413 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
3414 void *retaddr)
3415 {
3416 #ifdef DEBUG_UNALIGNED
3417 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
3418 "\n", addr, env->pc);
3419 #endif
3420 cpu_restore_state2(retaddr);
3421 raise_exception(TT_UNALIGNED);
3422 }
3423
3424 /* try to fill the TLB and return an exception if error. If retaddr is
3425 NULL, it means that the function was called in C code (i.e. not
3426 from generated code or from helper.c) */
3427 /* XXX: fix it to restore all registers */
3428 void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
3429 {
3430 int ret;
3431 CPUState *saved_env;
3432
3433 /* XXX: hack to restore env in all cases, even if not called from
3434 generated code */
3435 saved_env = env;
3436 env = cpu_single_env;
3437
3438 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
3439 if (ret) {
3440 cpu_restore_state2(retaddr);
3441 cpu_loop_exit();
3442 }
3443 env = saved_env;
3444 }
3445
3446 #endif
3447
3448 #ifndef TARGET_SPARC64
3449 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
3450 int is_asi, int size)
3451 {
3452 CPUState *saved_env;
3453
3454 /* XXX: hack to restore env in all cases, even if not called from
3455 generated code */
3456 saved_env = env;
3457 env = cpu_single_env;
3458 #ifdef DEBUG_UNASSIGNED
3459 if (is_asi)
3460 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
3461 " asi 0x%02x from " TARGET_FMT_lx "\n",
3462 is_exec ? "exec" : is_write ? "write" : "read", size,
3463 size == 1 ? "" : "s", addr, is_asi, env->pc);
3464 else
3465 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
3466 " from " TARGET_FMT_lx "\n",
3467 is_exec ? "exec" : is_write ? "write" : "read", size,
3468 size == 1 ? "" : "s", addr, env->pc);
3469 #endif
3470 if (env->mmuregs[3]) /* Fault status register */
3471 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
3472 if (is_asi)
3473 env->mmuregs[3] |= 1 << 16;
3474 if (env->psrs)
3475 env->mmuregs[3] |= 1 << 5;
3476 if (is_exec)
3477 env->mmuregs[3] |= 1 << 6;
3478 if (is_write)
3479 env->mmuregs[3] |= 1 << 7;
3480 env->mmuregs[3] |= (5 << 2) | 2;
3481 env->mmuregs[4] = addr; /* Fault address register */
3482 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
3483 if (is_exec)
3484 raise_exception(TT_CODE_ACCESS);
3485 else
3486 raise_exception(TT_DATA_ACCESS);
3487 }
3488 env = saved_env;
3489 }
3490 #else
3491 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
3492 int is_asi, int size)
3493 {
3494 #ifdef DEBUG_UNASSIGNED
3495 CPUState *saved_env;
3496
3497 /* XXX: hack to restore env in all cases, even if not called from
3498 generated code */
3499 saved_env = env;
3500 env = cpu_single_env;
3501 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
3502 "\n", addr, env->pc);
3503 env = saved_env;
3504 #endif
3505 if (is_exec)
3506 raise_exception(TT_CODE_ACCESS);
3507 else
3508 raise_exception(TT_DATA_ACCESS);
3509 }
3510 #endif
3511
3512 #ifdef TARGET_SPARC64
3513 void helper_tick_set_count(void *opaque, uint64_t count)
3514 {
3515 #if !defined(CONFIG_USER_ONLY)
3516 cpu_tick_set_count(opaque, count);
3517 #endif
3518 }
3519
3520 uint64_t helper_tick_get_count(void *opaque)
3521 {
3522 #if !defined(CONFIG_USER_ONLY)
3523 return cpu_tick_get_count(opaque);
3524 #else
3525 return 0;
3526 #endif
3527 }
3528
3529 void helper_tick_set_limit(void *opaque, uint64_t limit)
3530 {
3531 #if !defined(CONFIG_USER_ONLY)
3532 cpu_tick_set_limit(opaque, limit);
3533 #endif
3534 }
3535 #endif
Random patches