2 * User emulator execution
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "disas/disas.h"
22 #include "exec/exec-all.h"
24 #include "qemu/bitops.h"
25 #include "exec/cpu_ldst.h"
26 #include "translate-all.h"
27 #include "exec/helper-proto.h"
28 #include "qemu/atomic128.h"
40 #include <sys/ucontext.h>
43 __thread
uintptr_t helper_retaddr
;
45 //#define DEBUG_SIGNAL
47 /* exit the current TB from a signal handler. The host registers are
48 restored in a state compatible with the CPU emulator
50 static void cpu_exit_tb_from_sighandler(CPUState
*cpu
, sigset_t
*old_set
)
52 /* XXX: use siglongjmp ? */
53 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
54 cpu_loop_exit_noexc(cpu
);
57 /* 'pc' is the host PC at which the exception was raised. 'address' is
58 the effective address of the memory exception. 'is_write' is 1 if a
59 write caused the exception and otherwise 0'. 'old_set' is the
60 signal set which should be restored */
61 static inline int handle_cpu_signal(uintptr_t pc
, siginfo_t
*info
,
62 int is_write
, sigset_t
*old_set
)
64 CPUState
*cpu
= current_cpu
;
67 unsigned long address
= (unsigned long)info
->si_addr
;
69 /* We must handle PC addresses from two different sources:
70 * a call return address and a signal frame address.
72 * Within cpu_restore_state_from_tb we assume the former and adjust
73 * the address by -GETPC_ADJ so that the address is within the call
74 * insn so that addr does not accidentally match the beginning of the
77 * However, when the PC comes from the signal frame, it points to
78 * the actual faulting host insn and not a call insn. Subtracting
79 * GETPC_ADJ in that case may accidentally match the previous guest insn.
81 * So for the later case, adjust forward to compensate for what
82 * will be done later by cpu_restore_state_from_tb.
90 /* For synchronous signals we expect to be coming from the vCPU
91 * thread (so current_cpu should be valid) and either from running
92 * code or during translation which can fault as we cross pages.
94 * If neither is true then something has gone wrong and we should
95 * abort rather than try and restart the vCPU execution.
97 if (!cpu
|| !cpu
->running
) {
98 printf("qemu:%s received signal outside vCPU context @ pc=0x%"
99 PRIxPTR
"\n", __func__
, pc
);
103 #if defined(DEBUG_SIGNAL)
104 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
105 pc
, address
, is_write
, *(unsigned long *)old_set
);
107 /* XXX: locking issue */
108 /* Note that it is important that we don't call page_unprotect() unless
109 * this is really a "write to nonwriteable page" fault, because
110 * page_unprotect() assumes that if it is called for an access to
111 * a page that's writeable this means we had two threads racing and
112 * another thread got there first and already made the page writeable;
113 * so we will retry the access. If we were to call page_unprotect()
114 * for some other kind of fault that should really be passed to the
115 * guest, we'd end up in an infinite loop of retrying the faulting
118 if (is_write
&& info
->si_signo
== SIGSEGV
&& info
->si_code
== SEGV_ACCERR
&&
119 h2g_valid(address
)) {
120 switch (page_unprotect(h2g(address
), pc
)) {
122 /* Fault not caused by a page marked unwritable to protect
123 * cached translations, must be the guest binary's problem.
127 /* Fault caused by protection of cached translation; TBs
128 * invalidated, so resume execution. Retain helper_retaddr
129 * for a possible second fault.
133 /* Fault caused by protection of cached translation, and the
134 * currently executing TB was modified and must be exited
135 * immediately. Clear helper_retaddr for next execution.
138 cpu_exit_tb_from_sighandler(cpu
, old_set
);
142 g_assert_not_reached();
146 /* Convert forcefully to guest address space, invalid addresses
147 are still valid segv ones */
148 address
= h2g_nocheck(address
);
150 cc
= CPU_GET_CLASS(cpu
);
151 /* see if it is an MMU fault */
152 g_assert(cc
->handle_mmu_fault
);
153 ret
= cc
->handle_mmu_fault(cpu
, address
, 0, is_write
, MMU_USER_IDX
);
156 /* The MMU fault was handled without causing real CPU fault.
157 * Retain helper_retaddr for a possible second fault.
162 /* All other paths lead to cpu_exit; clear helper_retaddr
163 * for next execution.
168 return 0; /* not an MMU fault */
171 /* Now we have a real cpu fault. */
172 cpu_restore_state(cpu
, pc
, true);
174 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
177 /* never comes here */
181 #if defined(__i386__)
183 #if defined(__NetBSD__)
184 #include <ucontext.h>
186 #define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
187 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
188 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
189 #define MASK_sig(context) ((context)->uc_sigmask)
190 #elif defined(__FreeBSD__) || defined(__DragonFly__)
191 #include <ucontext.h>
193 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
194 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
195 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
196 #define MASK_sig(context) ((context)->uc_sigmask)
197 #elif defined(__OpenBSD__)
198 #define EIP_sig(context) ((context)->sc_eip)
199 #define TRAP_sig(context) ((context)->sc_trapno)
200 #define ERROR_sig(context) ((context)->sc_err)
201 #define MASK_sig(context) ((context)->sc_mask)
203 #define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
204 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
205 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
206 #define MASK_sig(context) ((context)->uc_sigmask)
209 int cpu_signal_handler(int host_signum
, void *pinfo
,
212 siginfo_t
*info
= pinfo
;
213 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
214 ucontext_t
*uc
= puc
;
215 #elif defined(__OpenBSD__)
216 struct sigcontext
*uc
= puc
;
218 ucontext_t
*uc
= puc
;
227 #define REG_TRAPNO TRAPNO
230 trapno
= TRAP_sig(uc
);
231 return handle_cpu_signal(pc
, info
,
232 trapno
== 0xe ? (ERROR_sig(uc
) >> 1) & 1 : 0,
236 #elif defined(__x86_64__)
239 #define PC_sig(context) _UC_MACHINE_PC(context)
240 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
241 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
242 #define MASK_sig(context) ((context)->uc_sigmask)
243 #elif defined(__OpenBSD__)
244 #define PC_sig(context) ((context)->sc_rip)
245 #define TRAP_sig(context) ((context)->sc_trapno)
246 #define ERROR_sig(context) ((context)->sc_err)
247 #define MASK_sig(context) ((context)->sc_mask)
248 #elif defined(__FreeBSD__) || defined(__DragonFly__)
249 #include <ucontext.h>
251 #define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
252 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
253 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
254 #define MASK_sig(context) ((context)->uc_sigmask)
256 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
257 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
258 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
259 #define MASK_sig(context) ((context)->uc_sigmask)
262 int cpu_signal_handler(int host_signum
, void *pinfo
,
265 siginfo_t
*info
= pinfo
;
267 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
268 ucontext_t
*uc
= puc
;
269 #elif defined(__OpenBSD__)
270 struct sigcontext
*uc
= puc
;
272 ucontext_t
*uc
= puc
;
276 return handle_cpu_signal(pc
, info
,
277 TRAP_sig(uc
) == 0xe ? (ERROR_sig(uc
) >> 1) & 1 : 0,
281 #elif defined(_ARCH_PPC)
283 /***********************************************************************
284 * signal context platform-specific definitions
288 /* All Registers access - only for local access */
289 #define REG_sig(reg_name, context) \
290 ((context)->uc_mcontext.regs->reg_name)
291 /* Gpr Registers access */
292 #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
293 /* Program counter */
294 #define IAR_sig(context) REG_sig(nip, context)
295 /* Machine State Register (Supervisor) */
296 #define MSR_sig(context) REG_sig(msr, context)
298 #define CTR_sig(context) REG_sig(ctr, context)
299 /* User's integer exception register */
300 #define XER_sig(context) REG_sig(xer, context)
302 #define LR_sig(context) REG_sig(link, context)
303 /* Condition register */
304 #define CR_sig(context) REG_sig(ccr, context)
306 /* Float Registers access */
307 #define FLOAT_sig(reg_num, context) \
308 (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
309 #define FPSCR_sig(context) \
310 (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
311 /* Exception Registers access */
312 #define DAR_sig(context) REG_sig(dar, context)
313 #define DSISR_sig(context) REG_sig(dsisr, context)
314 #define TRAP_sig(context) REG_sig(trap, context)
317 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
318 #include <ucontext.h>
319 #define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
320 #define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
321 #define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
322 #define XER_sig(context) ((context)->uc_mcontext.mc_xer)
323 #define LR_sig(context) ((context)->uc_mcontext.mc_lr)
324 #define CR_sig(context) ((context)->uc_mcontext.mc_cr)
325 /* Exception Registers access */
326 #define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
327 #define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
328 #define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
329 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
331 int cpu_signal_handler(int host_signum
, void *pinfo
,
334 siginfo_t
*info
= pinfo
;
335 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
336 ucontext_t
*uc
= puc
;
338 ucontext_t
*uc
= puc
;
347 if (DSISR_sig(uc
) & 0x00800000) {
351 if (TRAP_sig(uc
) != 0x400 && (DSISR_sig(uc
) & 0x02000000)) {
355 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
358 #elif defined(__alpha__)
360 int cpu_signal_handler(int host_signum
, void *pinfo
,
363 siginfo_t
*info
= pinfo
;
364 ucontext_t
*uc
= puc
;
365 uint32_t *pc
= uc
->uc_mcontext
.sc_pc
;
369 /* XXX: need kernel patch to get write flag faster */
370 switch (insn
>> 26) {
373 case 0x0f: /* stq_u */
380 case 0x2e: /* stl_c */
381 case 0x2f: /* stq_c */
385 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
387 #elif defined(__sparc__)
389 int cpu_signal_handler(int host_signum
, void *pinfo
,
392 siginfo_t
*info
= pinfo
;
395 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
396 uint32_t *regs
= (uint32_t *)(info
+ 1);
397 void *sigmask
= (regs
+ 20);
398 /* XXX: is there a standard glibc define ? */
399 unsigned long pc
= regs
[1];
402 struct sigcontext
*sc
= puc
;
403 unsigned long pc
= sc
->sigc_regs
.tpc
;
404 void *sigmask
= (void *)sc
->sigc_mask
;
405 #elif defined(__OpenBSD__)
406 struct sigcontext
*uc
= puc
;
407 unsigned long pc
= uc
->sc_pc
;
408 void *sigmask
= (void *)(long)uc
->sc_mask
;
409 #elif defined(__NetBSD__)
410 ucontext_t
*uc
= puc
;
411 unsigned long pc
= _UC_MACHINE_PC(uc
);
412 void *sigmask
= (void *)&uc
->uc_sigmask
;
416 /* XXX: need kernel patch to get write flag faster */
418 insn
= *(uint32_t *)pc
;
419 if ((insn
>> 30) == 3) {
420 switch ((insn
>> 19) & 0x3f) {
422 case 0x15: /* stba */
424 case 0x16: /* stha */
428 case 0x17: /* stda */
430 case 0x1e: /* stxa */
432 case 0x34: /* stfa */
433 case 0x27: /* stdf */
434 case 0x37: /* stdfa */
435 case 0x26: /* stqf */
436 case 0x36: /* stqfa */
437 case 0x25: /* stfsr */
438 case 0x3c: /* casa */
439 case 0x3e: /* casxa */
444 return handle_cpu_signal(pc
, info
, is_write
, sigmask
);
447 #elif defined(__arm__)
449 #if defined(__NetBSD__)
450 #include <ucontext.h>
453 int cpu_signal_handler(int host_signum
, void *pinfo
,
456 siginfo_t
*info
= pinfo
;
457 #if defined(__NetBSD__)
458 ucontext_t
*uc
= puc
;
460 ucontext_t
*uc
= puc
;
465 #if defined(__NetBSD__)
466 pc
= uc
->uc_mcontext
.__gregs
[_REG_R15
];
467 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
468 pc
= uc
->uc_mcontext
.gregs
[R15
];
470 pc
= uc
->uc_mcontext
.arm_pc
;
473 /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
474 * later processor; on v5 we will always report this as a read).
476 is_write
= extract32(uc
->uc_mcontext
.error_code
, 11, 1);
477 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
480 #elif defined(__aarch64__)
482 int cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
)
484 siginfo_t
*info
= pinfo
;
485 ucontext_t
*uc
= puc
;
486 uintptr_t pc
= uc
->uc_mcontext
.pc
;
487 uint32_t insn
= *(uint32_t *)pc
;
490 /* XXX: need kernel patch to get write flag faster. */
491 is_write
= ( (insn
& 0xbfff0000) == 0x0c000000 /* C3.3.1 */
492 || (insn
& 0xbfe00000) == 0x0c800000 /* C3.3.2 */
493 || (insn
& 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
494 || (insn
& 0xbfc00000) == 0x0d800000 /* C3.3.4 */
495 || (insn
& 0x3f400000) == 0x08000000 /* C3.3.6 */
496 || (insn
& 0x3bc00000) == 0x39000000 /* C3.3.13 */
497 || (insn
& 0x3fc00000) == 0x3d800000 /* ... 128bit */
498 /* Ingore bits 10, 11 & 21, controlling indexing. */
499 || (insn
& 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
500 || (insn
& 0x3fe00000) == 0x3c800000 /* ... 128bit */
501 /* Ignore bits 23 & 24, controlling indexing. */
502 || (insn
& 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
504 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
507 #elif defined(__s390__)
509 int cpu_signal_handler(int host_signum
, void *pinfo
,
512 siginfo_t
*info
= pinfo
;
513 ucontext_t
*uc
= puc
;
518 pc
= uc
->uc_mcontext
.psw
.addr
;
520 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
521 of the normal 2 arguments. The 3rd argument contains the "int_code"
522 from the hardware which does in fact contain the is_write value.
523 The rt signal handler, as far as I can tell, does not give this value
524 at all. Not that we could get to it from here even if it were. */
525 /* ??? This is not even close to complete, since it ignores all
526 of the read-modify-write instructions. */
527 pinsn
= (uint16_t *)pc
;
528 switch (pinsn
[0] >> 8) {
534 case 0xc4: /* RIL format insns */
535 switch (pinsn
[0] & 0xf) {
537 case 0xb: /* STGRL */
538 case 0x7: /* STHRL */
542 case 0xe3: /* RXY format insns */
543 switch (pinsn
[2] & 0xff) {
546 case 0x72: /* STCY */
547 case 0x70: /* STHY */
548 case 0x8e: /* STPQ */
549 case 0x3f: /* STRVH */
550 case 0x3e: /* STRV */
551 case 0x2f: /* STRVG */
556 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
559 #elif defined(__mips__)
561 int cpu_signal_handler(int host_signum
, void *pinfo
,
564 siginfo_t
*info
= pinfo
;
565 ucontext_t
*uc
= puc
;
566 greg_t pc
= uc
->uc_mcontext
.pc
;
569 /* XXX: compute is_write */
571 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
576 #error host CPU specific signal handler needed
580 /* The softmmu versions of these helpers are in cputlb.c. */
582 /* Do not allow unaligned operations to proceed. Return the host address. */
583 static void *atomic_mmu_lookup(CPUArchState
*env
, target_ulong addr
,
584 int size
, uintptr_t retaddr
)
586 /* Enforce qemu required alignment. */
587 if (unlikely(addr
& (size
- 1))) {
588 cpu_loop_exit_atomic(ENV_GET_CPU(env
), retaddr
);
590 helper_retaddr
= retaddr
;
594 /* Macro to call the above, with local variables from the use context. */
595 #define ATOMIC_MMU_DECLS do {} while (0)
596 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC())
597 #define ATOMIC_MMU_CLEANUP do { helper_retaddr = 0; } while (0)
599 #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
603 #include "atomic_template.h"
606 #include "atomic_template.h"
609 #include "atomic_template.h"
611 #ifdef CONFIG_ATOMIC64
613 #include "atomic_template.h"
616 /* The following is only callable from other helpers, and matches up
617 with the softmmu version. */
619 #if HAVE_ATOMIC128 || HAVE_CMPXCHG128
623 #undef ATOMIC_MMU_LOOKUP
625 #define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr
626 #define ATOMIC_NAME(X) \
627 HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu))
628 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, retaddr)
631 #include "atomic_template.h"