hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "pci_host.h"
  29 #include "isa.h"
  30 #include "sysbus.h"
  31 #include "range.h"
  32 #include "xen.h"
  33
  34 /*
  35  * I440FX chipset data sheet.
  36  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  37  */
  38
  39 typedef PCIHostState I440FXState;
  40
  41 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  42 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  43 #define XEN_PIIX_NUM_PIRQS      128ULL
  44 #define PIIX_PIRQC              0x60
  45
  46 typedef struct PIIX3State {
  47     PCIDevice dev;
  48
  49     /*
  50      * bitmap to track pic levels.
  51      * The pic level is the logical OR of all the PCI irqs mapped to it
  52      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  53      *
  54      * PIRQ is mapped to PIC pins, we track it by
  55      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  56      * pic_irq * PIIX_NUM_PIRQS + pirq
  57      */
  58 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  59 #error "unable to encode pic state in 64bit in pic_levels."
  60 #endif
  61     uint64_t pic_levels;
  62
  63     qemu_irq *pic;
  64
  65     /* This member isn't used. Just for save/load compatibility */
  66     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  67 } PIIX3State;
  68
  69 typedef struct PAMMemoryRegion {
  70     MemoryRegion mem;
  71     bool initialized;
  72 } PAMMemoryRegion;
  73
  74 struct PCII440FXState {
  75     PCIDevice dev;
  76     MemoryRegion *system_memory;
  77     MemoryRegion *pci_address_space;
  78     MemoryRegion *ram_memory;
  79     MemoryRegion pci_hole;
  80     MemoryRegion pci_hole_64bit;
  81     PAMMemoryRegion pam_regions[13];
  82     MemoryRegion smram_region;
  83     uint8_t smm_enabled;
  84     bool smram_enabled;
  85     PIIX3State *piix3;
  86 };
  87
  88
  89 #define I440FX_PAM      0x59
  90 #define I440FX_PAM_SIZE 7
  91 #define I440FX_SMRAM    0x72
  92
  93 static void piix3_set_irq(void *opaque, int pirq, int level);
  94 static void piix3_write_config_xen(PCIDevice *dev,
  95                                uint32_t address, uint32_t val, int len);
  96
  97 /* return the global irq number corresponding to a given device irq
  98    pin. We could also use the bus number to have a more precise
  99    mapping. */
 100 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
 101 {
 102     int slot_addend;
 103     slot_addend = (pci_dev->devfn >> 3) - 1;
 104     return (pci_intx + slot_addend) & 3;
 105 }
 106
 107 static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r,
 108                        PAMMemoryRegion *mem)
 109 {
 110     if (mem->initialized) {
 111         memory_region_del_subregion(d->system_memory, &mem->mem);
 112         memory_region_destroy(&mem->mem);
 113     }
 114
 115     //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
 116     switch(r) {
 117     case 3:
 118         /* RAM */
 119         memory_region_init_alias(&mem->mem, "pam-ram", d->ram_memory,
 120                                  start, end - start);
 121         break;
 122     case 1:
 123         /* ROM (XXX: not quite correct) */
 124         memory_region_init_alias(&mem->mem, "pam-rom", d->ram_memory,
 125                                  start, end - start);
 126         memory_region_set_readonly(&mem->mem, true);
 127         break;
 128     case 2:
 129     case 0:
 130         /* XXX: should distinguish read/write cases */
 131         memory_region_init_alias(&mem->mem, "pam-pci", d->pci_address_space,
 132                                  start, end - start);
 133         break;
 134     }
 135     memory_region_add_subregion_overlap(d->system_memory,
 136                                         start, &mem->mem, 1);
 137     mem->initialized = true;
 138 }
 139
 140 static void i440fx_update_memory_mappings(PCII440FXState *d)
 141 {
 142     int i, r;
 143     uint32_t smram;
 144
 145     update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
 146                &d->pam_regions[0]);
 147     for(i = 0; i < 12; i++) {
 148         r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
 149         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r,
 150                    &d->pam_regions[i+1]);
 151     }
 152     smram = d->dev.config[I440FX_SMRAM];
 153     if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
 154         if (!d->smram_enabled) {
 155             memory_region_del_subregion(d->system_memory, &d->smram_region);
 156             d->smram_enabled = true;
 157         }
 158     } else {
 159         if (d->smram_enabled) {
 160             memory_region_add_subregion_overlap(d->system_memory, 0xa0000,
 161                                                 &d->smram_region, 1);
 162             d->smram_enabled = false;
 163         }
 164     }
 165 }
 166
 167 static void i440fx_set_smm(int val, void *arg)
 168 {
 169     PCII440FXState *d = arg;
 170
 171     val = (val != 0);
 172     if (d->smm_enabled != val) {
 173         d->smm_enabled = val;
 174         i440fx_update_memory_mappings(d);
 175     }
 176 }
 177
 178
 179 static void i440fx_write_config(PCIDevice *dev,
 180                                 uint32_t address, uint32_t val, int len)
 181 {
 182     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 183
 184     /* XXX: implement SMRAM.D_LOCK */
 185     pci_default_write_config(dev, address, val, len);
 186     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 187         range_covers_byte(address, len, I440FX_SMRAM)) {
 188         i440fx_update_memory_mappings(d);
 189     }
 190 }
 191
 192 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 193 {
 194     PCII440FXState *d = opaque;
 195     int ret, i;
 196
 197     ret = pci_device_load(&d->dev, f);
 198     if (ret < 0)
 199         return ret;
 200     i440fx_update_memory_mappings(d);
 201     qemu_get_8s(f, &d->smm_enabled);
 202
 203     if (version_id == 2) {
 204         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
 205             qemu_get_be32(f); /* dummy load for compatibility */
 206         }
 207     }
 208
 209     return 0;
 210 }
 211
 212 static int i440fx_post_load(void *opaque, int version_id)
 213 {
 214     PCII440FXState *d = opaque;
 215
 216     i440fx_update_memory_mappings(d);
 217     return 0;
 218 }
 219
 220 static const VMStateDescription vmstate_i440fx = {
 221     .name = "I440FX",
 222     .version_id = 3,
 223     .minimum_version_id = 3,
 224     .minimum_version_id_old = 1,
 225     .load_state_old = i440fx_load_old,
 226     .post_load = i440fx_post_load,
 227     .fields      = (VMStateField []) {
 228         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 229         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 230         VMSTATE_END_OF_LIST()
 231     }
 232 };
 233
 234 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 235 {
 236     I440FXState *s = FROM_SYSBUS(I440FXState, dev);
 237
 238     memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
 239                           "pci-conf-idx", 4);
 240     sysbus_add_io(dev, 0xcf8, &s->conf_mem);
 241     sysbus_init_ioports(&s->busdev, 0xcf8, 4);
 242
 243     memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s,
 244                           "pci-conf-data", 4);
 245     sysbus_add_io(dev, 0xcfc, &s->data_mem);
 246     sysbus_init_ioports(&s->busdev, 0xcfc, 4);
 247
 248     return 0;
 249 }
 250
 251 static int i440fx_initfn(PCIDevice *dev)
 252 {
 253     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 254
 255     d->dev.config[I440FX_SMRAM] = 0x02;
 256
 257     cpu_smm_register(&i440fx_set_smm, d);
 258     return 0;
 259 }
 260
 261 static PCIBus *i440fx_common_init(const char *device_name,
 262                                   PCII440FXState **pi440fx_state,
 263                                   int *piix3_devfn,
 264                                   qemu_irq *pic,
 265                                   MemoryRegion *address_space_mem,
 266                                   MemoryRegion *address_space_io,
 267                                   ram_addr_t ram_size,
 268                                   target_phys_addr_t pci_hole_start,
 269                                   target_phys_addr_t pci_hole_size,
 270                                   target_phys_addr_t pci_hole64_start,
 271                                   target_phys_addr_t pci_hole64_size,
 272                                   MemoryRegion *pci_address_space,
 273                                   MemoryRegion *ram_memory)
 274 {
 275     DeviceState *dev;
 276     PCIBus *b;
 277     PCIDevice *d;
 278     I440FXState *s;
 279     PIIX3State *piix3;
 280     PCII440FXState *f;
 281
 282     dev = qdev_create(NULL, "i440FX-pcihost");
 283     s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
 284     s->address_space = address_space_mem;
 285     b = pci_bus_new(&s->busdev.qdev, NULL, pci_address_space,
 286                     address_space_io, 0);
 287     s->bus = b;
 288     qdev_init_nofail(dev);
 289
 290     d = pci_create_simple(b, 0, device_name);
 291     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 292     f = *pi440fx_state;
 293     f->system_memory = address_space_mem;
 294     f->pci_address_space = pci_address_space;
 295     f->ram_memory = ram_memory;
 296     memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
 297                              pci_hole_start, pci_hole_size);
 298     memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
 299     memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
 300                              f->pci_address_space,
 301                              pci_hole64_start, pci_hole64_size);
 302     if (pci_hole64_size) {
 303         memory_region_add_subregion(f->system_memory, pci_hole64_start,
 304                                     &f->pci_hole_64bit);
 305     }
 306     memory_region_init_alias(&f->smram_region, "smram-region",
 307                              f->pci_address_space, 0xa0000, 0x20000);
 308     f->smram_enabled = true;
 309
 310     /* Xen supports additional interrupt routes from the PCI devices to
 311      * the IOAPIC: the four pins of each PCI device on the bus are also
 312      * connected to the IOAPIC directly.
 313      * These additional routes can be discovered through ACPI. */
 314     if (xen_enabled()) {
 315         piix3 = DO_UPCAST(PIIX3State, dev,
 316                 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
 317         pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 318                 piix3, XEN_PIIX_NUM_PIRQS);
 319     } else {
 320         piix3 = DO_UPCAST(PIIX3State, dev,
 321                 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
 322         pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
 323                 PIIX_NUM_PIRQS);
 324     }
 325     piix3->pic = pic;
 326
 327     (*pi440fx_state)->piix3 = piix3;
 328
 329     *piix3_devfn = piix3->dev.devfn;
 330
 331     ram_size = ram_size / 8 / 1024 / 1024;
 332     if (ram_size > 255)
 333         ram_size = 255;
 334     (*pi440fx_state)->dev.config[0x57]=ram_size;
 335
 336     i440fx_update_memory_mappings(f);
 337
 338     return b;
 339 }
 340
 341 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
 342                     qemu_irq *pic,
 343                     MemoryRegion *address_space_mem,
 344                     MemoryRegion *address_space_io,
 345                     ram_addr_t ram_size,
 346                     target_phys_addr_t pci_hole_start,
 347                     target_phys_addr_t pci_hole_size,
 348                     target_phys_addr_t pci_hole64_start,
 349                     target_phys_addr_t pci_hole64_size,
 350                     MemoryRegion *pci_memory, MemoryRegion *ram_memory)
 351
 352 {
 353     PCIBus *b;
 354
 355     b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic,
 356                            address_space_mem, address_space_io, ram_size,
 357                            pci_hole_start, pci_hole_size,
 358                            pci_hole64_size, pci_hole64_size,
 359                            pci_memory, ram_memory);
 360     return b;
 361 }
 362
 363 /* PIIX3 PCI to ISA bridge */
 364 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 365 {
 366     qemu_set_irq(piix3->pic[pic_irq],
 367                  !!(piix3->pic_levels &
 368                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
 369                      (pic_irq * PIIX_NUM_PIRQS))));
 370 }
 371
 372 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 373 {
 374     int pic_irq;
 375     uint64_t mask;
 376
 377     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 378     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 379         return;
 380     }
 381
 382     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
 383     piix3->pic_levels &= ~mask;
 384     piix3->pic_levels |= mask * !!level;
 385
 386     piix3_set_irq_pic(piix3, pic_irq);
 387 }
 388
 389 static void piix3_set_irq(void *opaque, int pirq, int level)
 390 {
 391     PIIX3State *piix3 = opaque;
 392     piix3_set_irq_level(piix3, pirq, level);
 393 }
 394
 395 /* irq routing is changed. so rebuild bitmap */
 396 static void piix3_update_irq_levels(PIIX3State *piix3)
 397 {
 398     int pirq;
 399
 400     piix3->pic_levels = 0;
 401     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 402         piix3_set_irq_level(piix3, pirq,
 403                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 404     }
 405 }
 406
 407 static void piix3_write_config(PCIDevice *dev,
 408                                uint32_t address, uint32_t val, int len)
 409 {
 410     pci_default_write_config(dev, address, val, len);
 411     if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
 412         PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
 413         int pic_irq;
 414         piix3_update_irq_levels(piix3);
 415         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 416             piix3_set_irq_pic(piix3, pic_irq);
 417         }
 418     }
 419 }
 420
 421 static void piix3_write_config_xen(PCIDevice *dev,
 422                                uint32_t address, uint32_t val, int len)
 423 {
 424     xen_piix_pci_write_config_client(address, val, len);
 425     piix3_write_config(dev, address, val, len);
 426 }
 427
 428 static void piix3_reset(void *opaque)
 429 {
 430     PIIX3State *d = opaque;
 431     uint8_t *pci_conf = d->dev.config;
 432
 433     pci_conf[0x04] = 0x07; // master, memory and I/O
 434     pci_conf[0x05] = 0x00;
 435     pci_conf[0x06] = 0x00;
 436     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 437     pci_conf[0x4c] = 0x4d;
 438     pci_conf[0x4e] = 0x03;
 439     pci_conf[0x4f] = 0x00;
 440     pci_conf[0x60] = 0x80;
 441     pci_conf[0x61] = 0x80;
 442     pci_conf[0x62] = 0x80;
 443     pci_conf[0x63] = 0x80;
 444     pci_conf[0x69] = 0x02;
 445     pci_conf[0x70] = 0x80;
 446     pci_conf[0x76] = 0x0c;
 447     pci_conf[0x77] = 0x0c;
 448     pci_conf[0x78] = 0x02;
 449     pci_conf[0x79] = 0x00;
 450     pci_conf[0x80] = 0x00;
 451     pci_conf[0x82] = 0x00;
 452     pci_conf[0xa0] = 0x08;
 453     pci_conf[0xa2] = 0x00;
 454     pci_conf[0xa3] = 0x00;
 455     pci_conf[0xa4] = 0x00;
 456     pci_conf[0xa5] = 0x00;
 457     pci_conf[0xa6] = 0x00;
 458     pci_conf[0xa7] = 0x00;
 459     pci_conf[0xa8] = 0x0f;
 460     pci_conf[0xaa] = 0x00;
 461     pci_conf[0xab] = 0x00;
 462     pci_conf[0xac] = 0x00;
 463     pci_conf[0xae] = 0x00;
 464
 465     d->pic_levels = 0;
 466 }
 467
 468 static int piix3_post_load(void *opaque, int version_id)
 469 {
 470     PIIX3State *piix3 = opaque;
 471     piix3_update_irq_levels(piix3);
 472     return 0;
 473 }
 474
 475 static void piix3_pre_save(void *opaque)
 476 {
 477     int i;
 478     PIIX3State *piix3 = opaque;
 479
 480     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 481         piix3->pci_irq_levels_vmstate[i] =
 482             pci_bus_get_irq_level(piix3->dev.bus, i);
 483     }
 484 }
 485
 486 static const VMStateDescription vmstate_piix3 = {
 487     .name = "PIIX3",
 488     .version_id = 3,
 489     .minimum_version_id = 2,
 490     .minimum_version_id_old = 2,
 491     .post_load = piix3_post_load,
 492     .pre_save = piix3_pre_save,
 493     .fields      = (VMStateField []) {
 494         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 495         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 496                               PIIX_NUM_PIRQS, 3),
 497         VMSTATE_END_OF_LIST()
 498     }
 499 };
 500
 501 static int piix3_initfn(PCIDevice *dev)
 502 {
 503     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 504
 505     isa_bus_new(&d->dev.qdev);
 506     qemu_register_reset(piix3_reset, d);
 507     return 0;
 508 }
 509
 510 static PCIDeviceInfo i440fx_info[] = {
 511     {
 512         .qdev.name    = "i440FX",
 513         .qdev.desc    = "Host bridge",
 514         .qdev.size    = sizeof(PCII440FXState),
 515         .qdev.vmsd    = &vmstate_i440fx,
 516         .qdev.no_user = 1,
 517         .no_hotplug   = 1,
 518         .init         = i440fx_initfn,
 519         .config_write = i440fx_write_config,
 520         .vendor_id    = PCI_VENDOR_ID_INTEL,
 521         .device_id    = PCI_DEVICE_ID_INTEL_82441,
 522         .revision     = 0x02,
 523         .class_id     = PCI_CLASS_BRIDGE_HOST,
 524     },{
 525         .qdev.name    = "PIIX3",
 526         .qdev.desc    = "ISA bridge",
 527         .qdev.size    = sizeof(PIIX3State),
 528         .qdev.vmsd    = &vmstate_piix3,
 529         .qdev.no_user = 1,
 530         .no_hotplug   = 1,
 531         .init         = piix3_initfn,
 532         .config_write = piix3_write_config,
 533         .vendor_id    = PCI_VENDOR_ID_INTEL,
 534         .device_id    = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 535         .class_id     = PCI_CLASS_BRIDGE_ISA,
 536     },{
 537         .qdev.name    = "PIIX3-xen",
 538         .qdev.desc    = "ISA bridge",
 539         .qdev.size    = sizeof(PIIX3State),
 540         .qdev.vmsd    = &vmstate_piix3,
 541         .qdev.no_user = 1,
 542         .no_hotplug   = 1,
 543         .init         = piix3_initfn,
 544         .config_write = piix3_write_config_xen,
 545         .vendor_id    = PCI_VENDOR_ID_INTEL,
 546         .device_id    = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 547         .class_id     = PCI_CLASS_BRIDGE_ISA,
 548     },{
 549         /* end of list */
 550     }
 551 };
 552
 553 static SysBusDeviceInfo i440fx_pcihost_info = {
 554     .init         = i440fx_pcihost_initfn,
 555     .qdev.name    = "i440FX-pcihost",
 556     .qdev.fw_name = "pci",
 557     .qdev.size    = sizeof(I440FXState),
 558     .qdev.no_user = 1,
 559 };
 560
 561 static void i440fx_register(void)
 562 {
 563     sysbus_register_withprop(&i440fx_pcihost_info);
 564     pci_qdev_register_many(i440fx_info);
 565 }
 566 device_init(i440fx_register);