?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sysemu.h: Document what MAX_CPUMASK_BITS really limits
[qemu/kevin.git] / hw / usb / hcd-xhci.c
blobef3177aee96c76f6254b21351b4dc1832d3daaa8
1 /*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include "hw/hw.h"
22 #include "qemu/timer.h"
23 #include "hw/usb.h"
24 #include "hw/pci/pci.h"
25 #include "hw/pci/msi.h"
26 #include "hw/pci/msix.h"
27 #include "trace.h"
28
29 //#define DEBUG_XHCI
30 //#define DEBUG_DATA
31
32 #ifdef DEBUG_XHCI
33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
34 #else
35 #define DPRINTF(...) do {} while (0)
36 #endif
37 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
38 __func__, __LINE__, _msg); abort(); } while (0)
39
40 #define MAXPORTS_2 15
41 #define MAXPORTS_3 15
42
43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
44 #define MAXSLOTS 64
45 #define MAXINTRS 16
46
47 #define TD_QUEUE 24
48
49 /* Very pessimistic, let's hope it's enough for all cases */
50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
51 /* Do not deliver ER Full events. NEC's driver does some things not bound
52 * to the specs when it gets them */
53 #define ER_FULL_HACK
54
55 #define LEN_CAP 0x40
56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
59
60 #define OFF_OPER LEN_CAP
61 #define OFF_RUNTIME 0x1000
62 #define OFF_DOORBELL 0x2000
63 #define OFF_MSIX_TABLE 0x3000
64 #define OFF_MSIX_PBA 0x3800
65 /* must be power of 2 */
66 #define LEN_REGS 0x4000
67
68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
69 #error Increase OFF_RUNTIME
70 #endif
71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
72 #error Increase OFF_DOORBELL
73 #endif
74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
75 # error Increase LEN_REGS
76 #endif
77
78 /* bit definitions */
79 #define USBCMD_RS (1<<0)
80 #define USBCMD_HCRST (1<<1)
81 #define USBCMD_INTE (1<<2)
82 #define USBCMD_HSEE (1<<3)
83 #define USBCMD_LHCRST (1<<7)
84 #define USBCMD_CSS (1<<8)
85 #define USBCMD_CRS (1<<9)
86 #define USBCMD_EWE (1<<10)
87 #define USBCMD_EU3S (1<<11)
88
89 #define USBSTS_HCH (1<<0)
90 #define USBSTS_HSE (1<<2)
91 #define USBSTS_EINT (1<<3)
92 #define USBSTS_PCD (1<<4)
93 #define USBSTS_SSS (1<<8)
94 #define USBSTS_RSS (1<<9)
95 #define USBSTS_SRE (1<<10)
96 #define USBSTS_CNR (1<<11)
97 #define USBSTS_HCE (1<<12)
98
99
100 #define PORTSC_CCS (1<<0)
101 #define PORTSC_PED (1<<1)
102 #define PORTSC_OCA (1<<3)
103 #define PORTSC_PR (1<<4)
104 #define PORTSC_PLS_SHIFT 5
105 #define PORTSC_PLS_MASK 0xf
106 #define PORTSC_PP (1<<9)
107 #define PORTSC_SPEED_SHIFT 10
108 #define PORTSC_SPEED_MASK 0xf
109 #define PORTSC_SPEED_FULL (1<<10)
110 #define PORTSC_SPEED_LOW (2<<10)
111 #define PORTSC_SPEED_HIGH (3<<10)
112 #define PORTSC_SPEED_SUPER (4<<10)
113 #define PORTSC_PIC_SHIFT 14
114 #define PORTSC_PIC_MASK 0x3
115 #define PORTSC_LWS (1<<16)
116 #define PORTSC_CSC (1<<17)
117 #define PORTSC_PEC (1<<18)
118 #define PORTSC_WRC (1<<19)
119 #define PORTSC_OCC (1<<20)
120 #define PORTSC_PRC (1<<21)
121 #define PORTSC_PLC (1<<22)
122 #define PORTSC_CEC (1<<23)
123 #define PORTSC_CAS (1<<24)
124 #define PORTSC_WCE (1<<25)
125 #define PORTSC_WDE (1<<26)
126 #define PORTSC_WOE (1<<27)
127 #define PORTSC_DR (1<<30)
128 #define PORTSC_WPR (1<<31)
129
130 #define CRCR_RCS (1<<0)
131 #define CRCR_CS (1<<1)
132 #define CRCR_CA (1<<2)
133 #define CRCR_CRR (1<<3)
134
135 #define IMAN_IP (1<<0)
136 #define IMAN_IE (1<<1)
137
138 #define ERDP_EHB (1<<3)
139
140 #define TRB_SIZE 16
141 typedef struct XHCITRB {
142 uint64_t parameter;
143 uint32_t status;
144 uint32_t control;
145 dma_addr_t addr;
146 bool ccs;
147 } XHCITRB;
148
149 enum {
150 PLS_U0 = 0,
151 PLS_U1 = 1,
152 PLS_U2 = 2,
153 PLS_U3 = 3,
154 PLS_DISABLED = 4,
155 PLS_RX_DETECT = 5,
156 PLS_INACTIVE = 6,
157 PLS_POLLING = 7,
158 PLS_RECOVERY = 8,
159 PLS_HOT_RESET = 9,
160 PLS_COMPILANCE_MODE = 10,
161 PLS_TEST_MODE = 11,
162 PLS_RESUME = 15,
163 };
164
165 typedef enum TRBType {
166 TRB_RESERVED = 0,
167 TR_NORMAL,
168 TR_SETUP,
169 TR_DATA,
170 TR_STATUS,
171 TR_ISOCH,
172 TR_LINK,
173 TR_EVDATA,
174 TR_NOOP,
175 CR_ENABLE_SLOT,
176 CR_DISABLE_SLOT,
177 CR_ADDRESS_DEVICE,
178 CR_CONFIGURE_ENDPOINT,
179 CR_EVALUATE_CONTEXT,
180 CR_RESET_ENDPOINT,
181 CR_STOP_ENDPOINT,
182 CR_SET_TR_DEQUEUE,
183 CR_RESET_DEVICE,
184 CR_FORCE_EVENT,
185 CR_NEGOTIATE_BW,
186 CR_SET_LATENCY_TOLERANCE,
187 CR_GET_PORT_BANDWIDTH,
188 CR_FORCE_HEADER,
189 CR_NOOP,
190 ER_TRANSFER = 32,
191 ER_COMMAND_COMPLETE,
192 ER_PORT_STATUS_CHANGE,
193 ER_BANDWIDTH_REQUEST,
194 ER_DOORBELL,
195 ER_HOST_CONTROLLER,
196 ER_DEVICE_NOTIFICATION,
197 ER_MFINDEX_WRAP,
198 /* vendor specific bits */
199 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
200 CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
201 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
202 } TRBType;
203
204 #define CR_LINK TR_LINK
205
206 typedef enum TRBCCode {
207 CC_INVALID = 0,
208 CC_SUCCESS,
209 CC_DATA_BUFFER_ERROR,
210 CC_BABBLE_DETECTED,
211 CC_USB_TRANSACTION_ERROR,
212 CC_TRB_ERROR,
213 CC_STALL_ERROR,
214 CC_RESOURCE_ERROR,
215 CC_BANDWIDTH_ERROR,
216 CC_NO_SLOTS_ERROR,
217 CC_INVALID_STREAM_TYPE_ERROR,
218 CC_SLOT_NOT_ENABLED_ERROR,
219 CC_EP_NOT_ENABLED_ERROR,
220 CC_SHORT_PACKET,
221 CC_RING_UNDERRUN,
222 CC_RING_OVERRUN,
223 CC_VF_ER_FULL,
224 CC_PARAMETER_ERROR,
225 CC_BANDWIDTH_OVERRUN,
226 CC_CONTEXT_STATE_ERROR,
227 CC_NO_PING_RESPONSE_ERROR,
228 CC_EVENT_RING_FULL_ERROR,
229 CC_INCOMPATIBLE_DEVICE_ERROR,
230 CC_MISSED_SERVICE_ERROR,
231 CC_COMMAND_RING_STOPPED,
232 CC_COMMAND_ABORTED,
233 CC_STOPPED,
234 CC_STOPPED_LENGTH_INVALID,
235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
236 CC_ISOCH_BUFFER_OVERRUN = 31,
237 CC_EVENT_LOST_ERROR,
238 CC_UNDEFINED_ERROR,
239 CC_INVALID_STREAM_ID_ERROR,
240 CC_SECONDARY_BANDWIDTH_ERROR,
241 CC_SPLIT_TRANSACTION_ERROR
242 } TRBCCode;
243
244 #define TRB_C (1<<0)
245 #define TRB_TYPE_SHIFT 10
246 #define TRB_TYPE_MASK 0x3f
247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
248
249 #define TRB_EV_ED (1<<2)
250
251 #define TRB_TR_ENT (1<<1)
252 #define TRB_TR_ISP (1<<2)
253 #define TRB_TR_NS (1<<3)
254 #define TRB_TR_CH (1<<4)
255 #define TRB_TR_IOC (1<<5)
256 #define TRB_TR_IDT (1<<6)
257 #define TRB_TR_TBC_SHIFT 7
258 #define TRB_TR_TBC_MASK 0x3
259 #define TRB_TR_BEI (1<<9)
260 #define TRB_TR_TLBPC_SHIFT 16
261 #define TRB_TR_TLBPC_MASK 0xf
262 #define TRB_TR_FRAMEID_SHIFT 20
263 #define TRB_TR_FRAMEID_MASK 0x7ff
264 #define TRB_TR_SIA (1<<31)
265
266 #define TRB_TR_DIR (1<<16)
267
268 #define TRB_CR_SLOTID_SHIFT 24
269 #define TRB_CR_SLOTID_MASK 0xff
270 #define TRB_CR_EPID_SHIFT 16
271 #define TRB_CR_EPID_MASK 0x1f
272
273 #define TRB_CR_BSR (1<<9)
274 #define TRB_CR_DC (1<<9)
275
276 #define TRB_LK_TC (1<<1)
277
278 #define TRB_INTR_SHIFT 22
279 #define TRB_INTR_MASK 0x3ff
280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
281
282 #define EP_TYPE_MASK 0x7
283 #define EP_TYPE_SHIFT 3
284
285 #define EP_STATE_MASK 0x7
286 #define EP_DISABLED (0<<0)
287 #define EP_RUNNING (1<<0)
288 #define EP_HALTED (2<<0)
289 #define EP_STOPPED (3<<0)
290 #define EP_ERROR (4<<0)
291
292 #define SLOT_STATE_MASK 0x1f
293 #define SLOT_STATE_SHIFT 27
294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
295 #define SLOT_ENABLED 0
296 #define SLOT_DEFAULT 1
297 #define SLOT_ADDRESSED 2
298 #define SLOT_CONFIGURED 3
299
300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
302
303 typedef struct XHCIState XHCIState;
304 typedef struct XHCIStreamContext XHCIStreamContext;
305 typedef struct XHCIEPContext XHCIEPContext;
306
307 #define get_field(data, field) \
308 (((data) >> field##_SHIFT) & field##_MASK)
309
310 #define set_field(data, newval, field) do { \
311 uint32_t val = *data; \
312 val &= ~(field##_MASK << field##_SHIFT); \
313 val |= ((newval) & field##_MASK) << field##_SHIFT; \
314 *data = val; \
315 } while (0)
316
317 typedef enum EPType {
318 ET_INVALID = 0,
319 ET_ISO_OUT,
320 ET_BULK_OUT,
321 ET_INTR_OUT,
322 ET_CONTROL,
323 ET_ISO_IN,
324 ET_BULK_IN,
325 ET_INTR_IN,
326 } EPType;
327
328 typedef struct XHCIRing {
329 dma_addr_t dequeue;
330 bool ccs;
331 } XHCIRing;
332
333 typedef struct XHCIPort {
334 XHCIState *xhci;
335 uint32_t portsc;
336 uint32_t portnr;
337 USBPort *uport;
338 uint32_t speedmask;
339 char name[16];
340 MemoryRegion mem;
341 } XHCIPort;
342
343 typedef struct XHCITransfer {
344 XHCIState *xhci;
345 USBPacket packet;
346 QEMUSGList sgl;
347 bool running_async;
348 bool running_retry;
349 bool complete;
350 bool int_req;
351 unsigned int iso_pkts;
352 unsigned int slotid;
353 unsigned int epid;
354 unsigned int streamid;
355 bool in_xfer;
356 bool iso_xfer;
357 bool timed_xfer;
358
359 unsigned int trb_count;
360 unsigned int trb_alloced;
361 XHCITRB *trbs;
362
363 TRBCCode status;
364
365 unsigned int pkts;
366 unsigned int pktsize;
367 unsigned int cur_pkt;
368
369 uint64_t mfindex_kick;
370 } XHCITransfer;
371
372 struct XHCIStreamContext {
373 dma_addr_t pctx;
374 unsigned int sct;
375 XHCIRing ring;
376 };
377
378 struct XHCIEPContext {
379 XHCIState *xhci;
380 unsigned int slotid;
381 unsigned int epid;
382
383 XHCIRing ring;
384 unsigned int next_xfer;
385 unsigned int comp_xfer;
386 XHCITransfer transfers[TD_QUEUE];
387 XHCITransfer *retry;
388 EPType type;
389 dma_addr_t pctx;
390 unsigned int max_psize;
391 uint32_t state;
392
393 /* streams */
394 unsigned int max_pstreams;
395 bool lsa;
396 unsigned int nr_pstreams;
397 XHCIStreamContext *pstreams;
398
399 /* iso xfer scheduling */
400 unsigned int interval;
401 int64_t mfindex_last;
402 QEMUTimer *kick_timer;
403 };
404
405 typedef struct XHCISlot {
406 bool enabled;
407 bool addressed;
408 dma_addr_t ctx;
409 USBPort *uport;
410 XHCIEPContext * eps[31];
411 } XHCISlot;
412
413 typedef struct XHCIEvent {
414 TRBType type;
415 TRBCCode ccode;
416 uint64_t ptr;
417 uint32_t length;
418 uint32_t flags;
419 uint8_t slotid;
420 uint8_t epid;
421 } XHCIEvent;
422
423 typedef struct XHCIInterrupter {
424 uint32_t iman;
425 uint32_t imod;
426 uint32_t erstsz;
427 uint32_t erstba_low;
428 uint32_t erstba_high;
429 uint32_t erdp_low;
430 uint32_t erdp_high;
431
432 bool msix_used, er_pcs, er_full;
433
434 dma_addr_t er_start;
435 uint32_t er_size;
436 unsigned int er_ep_idx;
437
438 XHCIEvent ev_buffer[EV_QUEUE];
439 unsigned int ev_buffer_put;
440 unsigned int ev_buffer_get;
441
442 } XHCIInterrupter;
443
444 struct XHCIState {
445 /*< private >*/
446 PCIDevice parent_obj;
447 /*< public >*/
448
449 USBBus bus;
450 MemoryRegion mem;
451 MemoryRegion mem_cap;
452 MemoryRegion mem_oper;
453 MemoryRegion mem_runtime;
454 MemoryRegion mem_doorbell;
455
456 /* properties */
457 uint32_t numports_2;
458 uint32_t numports_3;
459 uint32_t numintrs;
460 uint32_t numslots;
461 uint32_t flags;
462
463 /* Operational Registers */
464 uint32_t usbcmd;
465 uint32_t usbsts;
466 uint32_t dnctrl;
467 uint32_t crcr_low;
468 uint32_t crcr_high;
469 uint32_t dcbaap_low;
470 uint32_t dcbaap_high;
471 uint32_t config;
472
473 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)];
474 XHCIPort ports[MAXPORTS];
475 XHCISlot slots[MAXSLOTS];
476 uint32_t numports;
477
478 /* Runtime Registers */
479 int64_t mfindex_start;
480 QEMUTimer *mfwrap_timer;
481 XHCIInterrupter intr[MAXINTRS];
482
483 XHCIRing cmd_ring;
484 };
485
486 #define TYPE_XHCI "nec-usb-xhci"
487
488 #define XHCI(obj) \
489 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI)
490
491 typedef struct XHCIEvRingSeg {
492 uint32_t addr_low;
493 uint32_t addr_high;
494 uint32_t size;
495 uint32_t rsvd;
496 } XHCIEvRingSeg;
497
498 enum xhci_flags {
499 XHCI_FLAG_USE_MSI = 1,
500 XHCI_FLAG_USE_MSI_X,
501 };
502
503 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
504 unsigned int epid, unsigned int streamid);
505 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
506 unsigned int epid);
507 static void xhci_xfer_report(XHCITransfer *xfer);
508 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v);
509 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v);
510 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci,
511 unsigned int slotid, unsigned int epid);
512
513 static const char *TRBType_names[] = {
514 [TRB_RESERVED] = "TRB_RESERVED",
515 [TR_NORMAL] = "TR_NORMAL",
516 [TR_SETUP] = "TR_SETUP",
517 [TR_DATA] = "TR_DATA",
518 [TR_STATUS] = "TR_STATUS",
519 [TR_ISOCH] = "TR_ISOCH",
520 [TR_LINK] = "TR_LINK",
521 [TR_EVDATA] = "TR_EVDATA",
522 [TR_NOOP] = "TR_NOOP",
523 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
524 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
525 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
526 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
527 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
528 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
529 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
530 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
531 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
532 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
533 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
534 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
535 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
536 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
537 [CR_NOOP] = "CR_NOOP",
538 [ER_TRANSFER] = "ER_TRANSFER",
539 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
540 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
541 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
542 [ER_DOORBELL] = "ER_DOORBELL",
543 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
544 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
545 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
546 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
547 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
548 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
549 };
550
551 static const char *TRBCCode_names[] = {
552 [CC_INVALID] = "CC_INVALID",
553 [CC_SUCCESS] = "CC_SUCCESS",
554 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
555 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
556 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
557 [CC_TRB_ERROR] = "CC_TRB_ERROR",
558 [CC_STALL_ERROR] = "CC_STALL_ERROR",
559 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
560 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
561 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
562 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
563 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
564 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
565 [CC_SHORT_PACKET] = "CC_SHORT_PACKET",
566 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
567 [CC_RING_OVERRUN] = "CC_RING_OVERRUN",
568 [CC_VF_ER_FULL] = "CC_VF_ER_FULL",
569 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
570 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
571 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
572 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
573 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
574 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
575 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
576 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
577 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
578 [CC_STOPPED] = "CC_STOPPED",
579 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
580 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR]
581 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
582 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
583 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
584 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
585 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
586 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
587 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
588 };
589
590 static const char *ep_state_names[] = {
591 [EP_DISABLED] = "disabled",
592 [EP_RUNNING] = "running",
593 [EP_HALTED] = "halted",
594 [EP_STOPPED] = "stopped",
595 [EP_ERROR] = "error",
596 };
597
598 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
599 {
600 if (index >= llen || list[index] == NULL) {
601 return "???";
602 }
603 return list[index];
604 }
605
606 static const char *trb_name(XHCITRB *trb)
607 {
608 return lookup_name(TRB_TYPE(*trb), TRBType_names,
609 ARRAY_SIZE(TRBType_names));
610 }
611
612 static const char *event_name(XHCIEvent *event)
613 {
614 return lookup_name(event->ccode, TRBCCode_names,
615 ARRAY_SIZE(TRBCCode_names));
616 }
617
618 static const char *ep_state_name(uint32_t state)
619 {
620 return lookup_name(state, ep_state_names,
621 ARRAY_SIZE(ep_state_names));
622 }
623
624 static uint64_t xhci_mfindex_get(XHCIState *xhci)
625 {
626 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
627 return (now - xhci->mfindex_start) / 125000;
628 }
629
630 static void xhci_mfwrap_update(XHCIState *xhci)
631 {
632 const uint32_t bits = USBCMD_RS | USBCMD_EWE;
633 uint32_t mfindex, left;
634 int64_t now;
635
636 if ((xhci->usbcmd & bits) == bits) {
637 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
638 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
639 left = 0x4000 - mfindex;
640 timer_mod(xhci->mfwrap_timer, now + left * 125000);
641 } else {
642 timer_del(xhci->mfwrap_timer);
643 }
644 }
645
646 static void xhci_mfwrap_timer(void *opaque)
647 {
648 XHCIState *xhci = opaque;
649 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
650
651 xhci_event(xhci, &wrap, 0);
652 xhci_mfwrap_update(xhci);
653 }
654
655 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
656 {
657 if (sizeof(dma_addr_t) == 4) {
658 return low;
659 } else {
660 return low | (((dma_addr_t)high << 16) << 16);
661 }
662 }
663
664 static inline dma_addr_t xhci_mask64(uint64_t addr)
665 {
666 if (sizeof(dma_addr_t) == 4) {
667 return addr & 0xffffffff;
668 } else {
669 return addr;
670 }
671 }
672
673 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
674 uint32_t *buf, size_t len)
675 {
676 int i;
677
678 assert((len % sizeof(uint32_t)) == 0);
679
680 pci_dma_read(PCI_DEVICE(xhci), addr, buf, len);
681
682 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
683 buf[i] = le32_to_cpu(buf[i]);
684 }
685 }
686
687 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
688 uint32_t *buf, size_t len)
689 {
690 int i;
691 uint32_t tmp[len / sizeof(uint32_t)];
692
693 assert((len % sizeof(uint32_t)) == 0);
694
695 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
696 tmp[i] = cpu_to_le32(buf[i]);
697 }
698 pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len);
699 }
700
701 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
702 {
703 int index;
704
705 if (!uport->dev) {
706 return NULL;
707 }
708 switch (uport->dev->speed) {
709 case USB_SPEED_LOW:
710 case USB_SPEED_FULL:
711 case USB_SPEED_HIGH:
712 index = uport->index;
713 break;
714 case USB_SPEED_SUPER:
715 index = uport->index + xhci->numports_2;
716 break;
717 default:
718 return NULL;
719 }
720 return &xhci->ports[index];
721 }
722
723 static void xhci_intx_update(XHCIState *xhci)
724 {
725 PCIDevice *pci_dev = PCI_DEVICE(xhci);
726 int level = 0;
727
728 if (msix_enabled(pci_dev) ||
729 msi_enabled(pci_dev)) {
730 return;
731 }
732
733 if (xhci->intr[0].iman & IMAN_IP &&
734 xhci->intr[0].iman & IMAN_IE &&
735 xhci->usbcmd & USBCMD_INTE) {
736 level = 1;
737 }
738
739 trace_usb_xhci_irq_intx(level);
740 pci_set_irq(pci_dev, level);
741 }
742
743 static void xhci_msix_update(XHCIState *xhci, int v)
744 {
745 PCIDevice *pci_dev = PCI_DEVICE(xhci);
746 bool enabled;
747
748 if (!msix_enabled(pci_dev)) {
749 return;
750 }
751
752 enabled = xhci->intr[v].iman & IMAN_IE;
753 if (enabled == xhci->intr[v].msix_used) {
754 return;
755 }
756
757 if (enabled) {
758 trace_usb_xhci_irq_msix_use(v);
759 msix_vector_use(pci_dev, v);
760 xhci->intr[v].msix_used = true;
761 } else {
762 trace_usb_xhci_irq_msix_unuse(v);
763 msix_vector_unuse(pci_dev, v);
764 xhci->intr[v].msix_used = false;
765 }
766 }
767
768 static void xhci_intr_raise(XHCIState *xhci, int v)
769 {
770 PCIDevice *pci_dev = PCI_DEVICE(xhci);
771
772 xhci->intr[v].erdp_low |= ERDP_EHB;
773 xhci->intr[v].iman |= IMAN_IP;
774 xhci->usbsts |= USBSTS_EINT;
775
776 if (!(xhci->intr[v].iman & IMAN_IE)) {
777 return;
778 }
779
780 if (!(xhci->usbcmd & USBCMD_INTE)) {
781 return;
782 }
783
784 if (msix_enabled(pci_dev)) {
785 trace_usb_xhci_irq_msix(v);
786 msix_notify(pci_dev, v);
787 return;
788 }
789
790 if (msi_enabled(pci_dev)) {
791 trace_usb_xhci_irq_msi(v);
792 msi_notify(pci_dev, v);
793 return;
794 }
795
796 if (v == 0) {
797 trace_usb_xhci_irq_intx(1);
798 pci_irq_assert(pci_dev);
799 }
800 }
801
802 static inline int xhci_running(XHCIState *xhci)
803 {
804 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full;
805 }
806
807 static void xhci_die(XHCIState *xhci)
808 {
809 xhci->usbsts |= USBSTS_HCE;
810 DPRINTF("xhci: asserted controller error\n");
811 }
812
813 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
814 {
815 PCIDevice *pci_dev = PCI_DEVICE(xhci);
816 XHCIInterrupter *intr = &xhci->intr[v];
817 XHCITRB ev_trb;
818 dma_addr_t addr;
819
820 ev_trb.parameter = cpu_to_le64(event->ptr);
821 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
822 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
823 event->flags | (event->type << TRB_TYPE_SHIFT);
824 if (intr->er_pcs) {
825 ev_trb.control |= TRB_C;
826 }
827 ev_trb.control = cpu_to_le32(ev_trb.control);
828
829 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb),
830 event_name(event), ev_trb.parameter,
831 ev_trb.status, ev_trb.control);
832
833 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
834 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE);
835
836 intr->er_ep_idx++;
837 if (intr->er_ep_idx >= intr->er_size) {
838 intr->er_ep_idx = 0;
839 intr->er_pcs = !intr->er_pcs;
840 }
841 }
842
843 static void xhci_events_update(XHCIState *xhci, int v)
844 {
845 XHCIInterrupter *intr = &xhci->intr[v];
846 dma_addr_t erdp;
847 unsigned int dp_idx;
848 bool do_irq = 0;
849
850 if (xhci->usbsts & USBSTS_HCH) {
851 return;
852 }
853
854 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
855 if (erdp < intr->er_start ||
856 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
857 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
858 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
859 v, intr->er_start, intr->er_size);
860 xhci_die(xhci);
861 return;
862 }
863 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
864 assert(dp_idx < intr->er_size);
865
866 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
867 * deadlocks when the ER is full. Hack it by holding off events until
868 * the driver decides to free at least half of the ring */
869 if (intr->er_full) {
870 int er_free = dp_idx - intr->er_ep_idx;
871 if (er_free <= 0) {
872 er_free += intr->er_size;
873 }
874 if (er_free < (intr->er_size/2)) {
875 DPRINTF("xhci_events_update(): event ring still "
876 "more than half full (hack)\n");
877 return;
878 }
879 }
880
881 while (intr->ev_buffer_put != intr->ev_buffer_get) {
882 assert(intr->er_full);
883 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) {
884 DPRINTF("xhci_events_update(): event ring full again\n");
885 #ifndef ER_FULL_HACK
886 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
887 xhci_write_event(xhci, &full, v);
888 #endif
889 do_irq = 1;
890 break;
891 }
892 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get];
893 xhci_write_event(xhci, event, v);
894 intr->ev_buffer_get++;
895 do_irq = 1;
896 if (intr->ev_buffer_get == EV_QUEUE) {
897 intr->ev_buffer_get = 0;
898 }
899 }
900
901 if (do_irq) {
902 xhci_intr_raise(xhci, v);
903 }
904
905 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) {
906 DPRINTF("xhci_events_update(): event ring no longer full\n");
907 intr->er_full = 0;
908 }
909 }
910
911 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v)
912 {
913 XHCIInterrupter *intr;
914 dma_addr_t erdp;
915 unsigned int dp_idx;
916
917 if (v >= xhci->numintrs) {
918 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs);
919 return;
920 }
921 intr = &xhci->intr[v];
922
923 if (intr->er_full) {
924 DPRINTF("xhci_event(): ER full, queueing\n");
925 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) {
926 DPRINTF("xhci: event queue full, dropping event!\n");
927 return;
928 }
929 intr->ev_buffer[intr->ev_buffer_put++] = *event;
930 if (intr->ev_buffer_put == EV_QUEUE) {
931 intr->ev_buffer_put = 0;
932 }
933 return;
934 }
935
936 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
937 if (erdp < intr->er_start ||
938 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
939 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
940 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
941 v, intr->er_start, intr->er_size);
942 xhci_die(xhci);
943 return;
944 }
945
946 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
947 assert(dp_idx < intr->er_size);
948
949 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) {
950 DPRINTF("xhci_event(): ER full, queueing\n");
951 #ifndef ER_FULL_HACK
952 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
953 xhci_write_event(xhci, &full);
954 #endif
955 intr->er_full = 1;
956 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) {
957 DPRINTF("xhci: event queue full, dropping event!\n");
958 return;
959 }
960 intr->ev_buffer[intr->ev_buffer_put++] = *event;
961 if (intr->ev_buffer_put == EV_QUEUE) {
962 intr->ev_buffer_put = 0;
963 }
964 } else {
965 xhci_write_event(xhci, event, v);
966 }
967
968 xhci_intr_raise(xhci, v);
969 }
970
971 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
972 dma_addr_t base)
973 {
974 ring->dequeue = base;
975 ring->ccs = 1;
976 }
977
978 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
979 dma_addr_t *addr)
980 {
981 PCIDevice *pci_dev = PCI_DEVICE(xhci);
982
983 while (1) {
984 TRBType type;
985 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE);
986 trb->addr = ring->dequeue;
987 trb->ccs = ring->ccs;
988 le64_to_cpus(&trb->parameter);
989 le32_to_cpus(&trb->status);
990 le32_to_cpus(&trb->control);
991
992 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
993 trb->parameter, trb->status, trb->control);
994
995 if ((trb->control & TRB_C) != ring->ccs) {
996 return 0;
997 }
998
999 type = TRB_TYPE(*trb);
1000
1001 if (type != TR_LINK) {
1002 if (addr) {
1003 *addr = ring->dequeue;
1004 }
1005 ring->dequeue += TRB_SIZE;
1006 return type;
1007 } else {
1008 ring->dequeue = xhci_mask64(trb->parameter);
1009 if (trb->control & TRB_LK_TC) {
1010 ring->ccs = !ring->ccs;
1011 }
1012 }
1013 }
1014 }
1015
1016 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
1017 {
1018 PCIDevice *pci_dev = PCI_DEVICE(xhci);
1019 XHCITRB trb;
1020 int length = 0;
1021 dma_addr_t dequeue = ring->dequeue;
1022 bool ccs = ring->ccs;
1023 /* hack to bundle together the two/three TDs that make a setup transfer */
1024 bool control_td_set = 0;
1025
1026 while (1) {
1027 TRBType type;
1028 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE);
1029 le64_to_cpus(&trb.parameter);
1030 le32_to_cpus(&trb.status);
1031 le32_to_cpus(&trb.control);
1032
1033 if ((trb.control & TRB_C) != ccs) {
1034 return -length;
1035 }
1036
1037 type = TRB_TYPE(trb);
1038
1039 if (type == TR_LINK) {
1040 dequeue = xhci_mask64(trb.parameter);
1041 if (trb.control & TRB_LK_TC) {
1042 ccs = !ccs;
1043 }
1044 continue;
1045 }
1046
1047 length += 1;
1048 dequeue += TRB_SIZE;
1049
1050 if (type == TR_SETUP) {
1051 control_td_set = 1;
1052 } else if (type == TR_STATUS) {
1053 control_td_set = 0;
1054 }
1055
1056 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
1057 return length;
1058 }
1059 }
1060 }
1061
1062 static void xhci_er_reset(XHCIState *xhci, int v)
1063 {
1064 XHCIInterrupter *intr = &xhci->intr[v];
1065 XHCIEvRingSeg seg;
1066
1067 if (intr->erstsz == 0) {
1068 /* disabled */
1069 intr->er_start = 0;
1070 intr->er_size = 0;
1071 return;
1072 }
1073 /* cache the (sole) event ring segment location */
1074 if (intr->erstsz != 1) {
1075 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz);
1076 xhci_die(xhci);
1077 return;
1078 }
1079 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
1080 pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg));
1081 le32_to_cpus(&seg.addr_low);
1082 le32_to_cpus(&seg.addr_high);
1083 le32_to_cpus(&seg.size);
1084 if (seg.size < 16 || seg.size > 4096) {
1085 DPRINTF("xhci: invalid value for segment size: %d\n", seg.size);
1086 xhci_die(xhci);
1087 return;
1088 }
1089 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
1090 intr->er_size = seg.size;
1091
1092 intr->er_ep_idx = 0;
1093 intr->er_pcs = 1;
1094 intr->er_full = 0;
1095
1096 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n",
1097 v, intr->er_start, intr->er_size);
1098 }
1099
1100 static void xhci_run(XHCIState *xhci)
1101 {
1102 trace_usb_xhci_run();
1103 xhci->usbsts &= ~USBSTS_HCH;
1104 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1105 }
1106
1107 static void xhci_stop(XHCIState *xhci)
1108 {
1109 trace_usb_xhci_stop();
1110 xhci->usbsts |= USBSTS_HCH;
1111 xhci->crcr_low &= ~CRCR_CRR;
1112 }
1113
1114 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count,
1115 dma_addr_t base)
1116 {
1117 XHCIStreamContext *stctx;
1118 unsigned int i;
1119
1120 stctx = g_new0(XHCIStreamContext, count);
1121 for (i = 0; i < count; i++) {
1122 stctx[i].pctx = base + i * 16;
1123 stctx[i].sct = -1;
1124 }
1125 return stctx;
1126 }
1127
1128 static void xhci_reset_streams(XHCIEPContext *epctx)
1129 {
1130 unsigned int i;
1131
1132 for (i = 0; i < epctx->nr_pstreams; i++) {
1133 epctx->pstreams[i].sct = -1;
1134 }
1135 }
1136
1137 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base)
1138 {
1139 assert(epctx->pstreams == NULL);
1140 epctx->nr_pstreams = 2 << (epctx->max_pstreams + 1);
1141 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base);
1142 }
1143
1144 static void xhci_free_streams(XHCIEPContext *epctx)
1145 {
1146 assert(epctx->pstreams != NULL);
1147
1148 g_free(epctx->pstreams);
1149 epctx->pstreams = NULL;
1150 epctx->nr_pstreams = 0;
1151 }
1152
1153 static int xhci_epmask_to_eps_with_streams(XHCIState *xhci,
1154 unsigned int slotid,
1155 uint32_t epmask,
1156 XHCIEPContext **epctxs,
1157 USBEndpoint **eps)
1158 {
1159 XHCISlot *slot;
1160 XHCIEPContext *epctx;
1161 USBEndpoint *ep;
1162 int i, j;
1163
1164 assert(slotid >= 1 && slotid <= xhci->numslots);
1165
1166 slot = &xhci->slots[slotid - 1];
1167
1168 for (i = 2, j = 0; i <= 31; i++) {
1169 if (!(epmask & (1 << i))) {
1170 continue;
1171 }
1172
1173 epctx = slot->eps[i - 1];
1174 ep = xhci_epid_to_usbep(xhci, slotid, i);
1175 if (!epctx || !epctx->nr_pstreams || !ep) {
1176 continue;
1177 }
1178
1179 if (epctxs) {
1180 epctxs[j] = epctx;
1181 }
1182 eps[j++] = ep;
1183 }
1184 return j;
1185 }
1186
1187 static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid,
1188 uint32_t epmask)
1189 {
1190 USBEndpoint *eps[30];
1191 int nr_eps;
1192
1193 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps);
1194 if (nr_eps) {
1195 usb_device_free_streams(eps[0]->dev, eps, nr_eps);
1196 }
1197 }
1198
1199 static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid,
1200 uint32_t epmask)
1201 {
1202 XHCIEPContext *epctxs[30];
1203 USBEndpoint *eps[30];
1204 int i, r, nr_eps, req_nr_streams, dev_max_streams;
1205
1206 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs,
1207 eps);
1208 if (nr_eps == 0) {
1209 return CC_SUCCESS;
1210 }
1211
1212 req_nr_streams = epctxs[0]->nr_pstreams;
1213 dev_max_streams = eps[0]->max_streams;
1214
1215 for (i = 1; i < nr_eps; i++) {
1216 /*
1217 * HdG: I don't expect these to ever trigger, but if they do we need
1218 * to come up with another solution, ie group identical endpoints
1219 * together and make an usb_device_alloc_streams call per group.
1220 */
1221 if (epctxs[i]->nr_pstreams != req_nr_streams) {
1222 FIXME("guest streams config not identical for all eps");
1223 return CC_RESOURCE_ERROR;
1224 }
1225 if (eps[i]->max_streams != dev_max_streams) {
1226 FIXME("device streams config not identical for all eps");
1227 return CC_RESOURCE_ERROR;
1228 }
1229 }
1230
1231 /*
1232 * max-streams in both the device descriptor and in the controller is a
1233 * power of 2. But stream id 0 is reserved, so if a device can do up to 4
1234 * streams the guest will ask for 5 rounded up to the next power of 2 which
1235 * becomes 8. For emulated devices usb_device_alloc_streams is a nop.
1236 *
1237 * For redirected devices however this is an issue, as there we must ask
1238 * the real xhci controller to alloc streams, and the host driver for the
1239 * real xhci controller will likely disallow allocating more streams then
1240 * the device can handle.
1241 *
1242 * So we limit the requested nr_streams to the maximum number the device
1243 * can handle.
1244 */
1245 if (req_nr_streams > dev_max_streams) {
1246 req_nr_streams = dev_max_streams;
1247 }
1248
1249 r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams);
1250 if (r != 0) {
1251 DPRINTF("xhci: alloc streams failed\n");
1252 return CC_RESOURCE_ERROR;
1253 }
1254
1255 return CC_SUCCESS;
1256 }
1257
1258 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx,
1259 unsigned int streamid,
1260 uint32_t *cc_error)
1261 {
1262 XHCIStreamContext *sctx;
1263 dma_addr_t base;
1264 uint32_t ctx[2], sct;
1265
1266 assert(streamid != 0);
1267 if (epctx->lsa) {
1268 if (streamid >= epctx->nr_pstreams) {
1269 *cc_error = CC_INVALID_STREAM_ID_ERROR;
1270 return NULL;
1271 }
1272 sctx = epctx->pstreams + streamid;
1273 } else {
1274 FIXME("secondary streams not implemented yet");
1275 }
1276
1277 if (sctx->sct == -1) {
1278 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx));
1279 sct = (ctx[0] >> 1) & 0x07;
1280 if (epctx->lsa && sct != 1) {
1281 *cc_error = CC_INVALID_STREAM_TYPE_ERROR;
1282 return NULL;
1283 }
1284 sctx->sct = sct;
1285 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]);
1286 xhci_ring_init(epctx->xhci, &sctx->ring, base);
1287 }
1288 return sctx;
1289 }
1290
1291 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
1292 XHCIStreamContext *sctx, uint32_t state)
1293 {
1294 XHCIRing *ring = NULL;
1295 uint32_t ctx[5];
1296 uint32_t ctx2[2];
1297
1298 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1299 ctx[0] &= ~EP_STATE_MASK;
1300 ctx[0] |= state;
1301
1302 /* update ring dequeue ptr */
1303 if (epctx->nr_pstreams) {
1304 if (sctx != NULL) {
1305 ring = &sctx->ring;
1306 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1307 ctx2[0] &= 0xe;
1308 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs;
1309 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16;
1310 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1311 }
1312 } else {
1313 ring = &epctx->ring;
1314 }
1315 if (ring) {
1316 ctx[2] = ring->dequeue | ring->ccs;
1317 ctx[3] = (ring->dequeue >> 16) >> 16;
1318
1319 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
1320 epctx->pctx, state, ctx[3], ctx[2]);
1321 }
1322
1323 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1324 if (epctx->state != state) {
1325 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid,
1326 ep_state_name(epctx->state),
1327 ep_state_name(state));
1328 }
1329 epctx->state = state;
1330 }
1331
1332 static void xhci_ep_kick_timer(void *opaque)
1333 {
1334 XHCIEPContext *epctx = opaque;
1335 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid, 0);
1336 }
1337
1338 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci,
1339 unsigned int slotid,
1340 unsigned int epid)
1341 {
1342 XHCIEPContext *epctx;
1343 int i;
1344
1345 epctx = g_new0(XHCIEPContext, 1);
1346 epctx->xhci = xhci;
1347 epctx->slotid = slotid;
1348 epctx->epid = epid;
1349
1350 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
1351 epctx->transfers[i].xhci = xhci;
1352 epctx->transfers[i].slotid = slotid;
1353 epctx->transfers[i].epid = epid;
1354 usb_packet_init(&epctx->transfers[i].packet);
1355 }
1356 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx);
1357
1358 return epctx;
1359 }
1360
1361 static void xhci_init_epctx(XHCIEPContext *epctx,
1362 dma_addr_t pctx, uint32_t *ctx)
1363 {
1364 dma_addr_t dequeue;
1365
1366 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
1367
1368 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
1369 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type);
1370 epctx->pctx = pctx;
1371 epctx->max_psize = ctx[1]>>16;
1372 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
1373 epctx->max_pstreams = (ctx[0] >> 10) & 0xf;
1374 epctx->lsa = (ctx[0] >> 15) & 1;
1375 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
1376 epid/2, epid%2, epctx->max_psize);
1377 if (epctx->max_pstreams) {
1378 xhci_alloc_streams(epctx, dequeue);
1379 } else {
1380 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue);
1381 epctx->ring.ccs = ctx[2] & 1;
1382 }
1383
1384 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff);
1385 }
1386
1387 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
1388 unsigned int epid, dma_addr_t pctx,
1389 uint32_t *ctx)
1390 {
1391 XHCISlot *slot;
1392 XHCIEPContext *epctx;
1393
1394 trace_usb_xhci_ep_enable(slotid, epid);
1395 assert(slotid >= 1 && slotid <= xhci->numslots);
1396 assert(epid >= 1 && epid <= 31);
1397
1398 slot = &xhci->slots[slotid-1];
1399 if (slot->eps[epid-1]) {
1400 xhci_disable_ep(xhci, slotid, epid);
1401 }
1402
1403 epctx = xhci_alloc_epctx(xhci, slotid, epid);
1404 slot->eps[epid-1] = epctx;
1405 xhci_init_epctx(epctx, pctx, ctx);
1406
1407 epctx->mfindex_last = 0;
1408
1409 epctx->state = EP_RUNNING;
1410 ctx[0] &= ~EP_STATE_MASK;
1411 ctx[0] |= EP_RUNNING;
1412
1413 return CC_SUCCESS;
1414 }
1415
1416 static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report)
1417 {
1418 int killed = 0;
1419
1420 if (report && (t->running_async || t->running_retry)) {
1421 t->status = report;
1422 xhci_xfer_report(t);
1423 }
1424
1425 if (t->running_async) {
1426 usb_cancel_packet(&t->packet);
1427 t->running_async = 0;
1428 killed = 1;
1429 }
1430 if (t->running_retry) {
1431 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1];
1432 if (epctx) {
1433 epctx->retry = NULL;
1434 timer_del(epctx->kick_timer);
1435 }
1436 t->running_retry = 0;
1437 killed = 1;
1438 }
1439 if (t->trbs) {
1440 g_free(t->trbs);
1441 }
1442
1443 t->trbs = NULL;
1444 t->trb_count = t->trb_alloced = 0;
1445
1446 return killed;
1447 }
1448
1449 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
1450 unsigned int epid, TRBCCode report)
1451 {
1452 XHCISlot *slot;
1453 XHCIEPContext *epctx;
1454 int i, xferi, killed = 0;
1455 USBEndpoint *ep = NULL;
1456 assert(slotid >= 1 && slotid <= xhci->numslots);
1457 assert(epid >= 1 && epid <= 31);
1458
1459 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
1460
1461 slot = &xhci->slots[slotid-1];
1462
1463 if (!slot->eps[epid-1]) {
1464 return 0;
1465 }
1466
1467 epctx = slot->eps[epid-1];
1468
1469 xferi = epctx->next_xfer;
1470 for (i = 0; i < TD_QUEUE; i++) {
1471 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi], report);
1472 if (killed) {
1473 report = 0; /* Only report once */
1474 }
1475 epctx->transfers[xferi].packet.ep = NULL;
1476 xferi = (xferi + 1) % TD_QUEUE;
1477 }
1478
1479 ep = xhci_epid_to_usbep(xhci, slotid, epid);
1480 if (ep) {
1481 usb_device_ep_stopped(ep->dev, ep);
1482 }
1483 return killed;
1484 }
1485
1486 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
1487 unsigned int epid)
1488 {
1489 XHCISlot *slot;
1490 XHCIEPContext *epctx;
1491 int i;
1492
1493 trace_usb_xhci_ep_disable(slotid, epid);
1494 assert(slotid >= 1 && slotid <= xhci->numslots);
1495 assert(epid >= 1 && epid <= 31);
1496
1497 slot = &xhci->slots[slotid-1];
1498
1499 if (!slot->eps[epid-1]) {
1500 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
1501 return CC_SUCCESS;
1502 }
1503
1504 xhci_ep_nuke_xfers(xhci, slotid, epid, 0);
1505
1506 epctx = slot->eps[epid-1];
1507
1508 if (epctx->nr_pstreams) {
1509 xhci_free_streams(epctx);
1510 }
1511
1512 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
1513 usb_packet_cleanup(&epctx->transfers[i].packet);
1514 }
1515
1516 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED);
1517
1518 timer_free(epctx->kick_timer);
1519 g_free(epctx);
1520 slot->eps[epid-1] = NULL;
1521
1522 return CC_SUCCESS;
1523 }
1524
1525 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
1526 unsigned int epid)
1527 {
1528 XHCISlot *slot;
1529 XHCIEPContext *epctx;
1530
1531 trace_usb_xhci_ep_stop(slotid, epid);
1532 assert(slotid >= 1 && slotid <= xhci->numslots);
1533
1534 if (epid < 1 || epid > 31) {
1535 DPRINTF("xhci: bad ep %d\n", epid);
1536 return CC_TRB_ERROR;
1537 }
1538
1539 slot = &xhci->slots[slotid-1];
1540
1541 if (!slot->eps[epid-1]) {
1542 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1543 return CC_EP_NOT_ENABLED_ERROR;
1544 }
1545
1546 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) {
1547 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, "
1548 "data might be lost\n");
1549 }
1550
1551 epctx = slot->eps[epid-1];
1552
1553 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1554
1555 if (epctx->nr_pstreams) {
1556 xhci_reset_streams(epctx);
1557 }
1558
1559 return CC_SUCCESS;
1560 }
1561
1562 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1563 unsigned int epid)
1564 {
1565 XHCISlot *slot;
1566 XHCIEPContext *epctx;
1567
1568 trace_usb_xhci_ep_reset(slotid, epid);
1569 assert(slotid >= 1 && slotid <= xhci->numslots);
1570
1571 if (epid < 1 || epid > 31) {
1572 DPRINTF("xhci: bad ep %d\n", epid);
1573 return CC_TRB_ERROR;
1574 }
1575
1576 slot = &xhci->slots[slotid-1];
1577
1578 if (!slot->eps[epid-1]) {
1579 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1580 return CC_EP_NOT_ENABLED_ERROR;
1581 }
1582
1583 epctx = slot->eps[epid-1];
1584
1585 if (epctx->state != EP_HALTED) {
1586 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n",
1587 epid, epctx->state);
1588 return CC_CONTEXT_STATE_ERROR;
1589 }
1590
1591 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) {
1592 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, "
1593 "data might be lost\n");
1594 }
1595
1596 uint8_t ep = epid>>1;
1597
1598 if (epid & 1) {
1599 ep |= 0x80;
1600 }
1601
1602 if (!xhci->slots[slotid-1].uport ||
1603 !xhci->slots[slotid-1].uport->dev ||
1604 !xhci->slots[slotid-1].uport->dev->attached) {
1605 return CC_USB_TRANSACTION_ERROR;
1606 }
1607
1608 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1609
1610 if (epctx->nr_pstreams) {
1611 xhci_reset_streams(epctx);
1612 }
1613
1614 return CC_SUCCESS;
1615 }
1616
1617 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1618 unsigned int epid, unsigned int streamid,
1619 uint64_t pdequeue)
1620 {
1621 XHCISlot *slot;
1622 XHCIEPContext *epctx;
1623 XHCIStreamContext *sctx;
1624 dma_addr_t dequeue;
1625
1626 assert(slotid >= 1 && slotid <= xhci->numslots);
1627
1628 if (epid < 1 || epid > 31) {
1629 DPRINTF("xhci: bad ep %d\n", epid);
1630 return CC_TRB_ERROR;
1631 }
1632
1633 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue);
1634 dequeue = xhci_mask64(pdequeue);
1635
1636 slot = &xhci->slots[slotid-1];
1637
1638 if (!slot->eps[epid-1]) {
1639 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1640 return CC_EP_NOT_ENABLED_ERROR;
1641 }
1642
1643 epctx = slot->eps[epid-1];
1644
1645 if (epctx->state != EP_STOPPED) {
1646 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1647 return CC_CONTEXT_STATE_ERROR;
1648 }
1649
1650 if (epctx->nr_pstreams) {
1651 uint32_t err;
1652 sctx = xhci_find_stream(epctx, streamid, &err);
1653 if (sctx == NULL) {
1654 return err;
1655 }
1656 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf);
1657 sctx->ring.ccs = dequeue & 1;
1658 } else {
1659 sctx = NULL;
1660 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1661 epctx->ring.ccs = dequeue & 1;
1662 }
1663
1664 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED);
1665
1666 return CC_SUCCESS;
1667 }
1668
1669 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
1670 {
1671 XHCIState *xhci = xfer->xhci;
1672 int i;
1673
1674 xfer->int_req = false;
1675 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count);
1676 for (i = 0; i < xfer->trb_count; i++) {
1677 XHCITRB *trb = &xfer->trbs[i];
1678 dma_addr_t addr;
1679 unsigned int chunk = 0;
1680
1681 if (trb->control & TRB_TR_IOC) {
1682 xfer->int_req = true;
1683 }
1684
1685 switch (TRB_TYPE(*trb)) {
1686 case TR_DATA:
1687 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1688 DPRINTF("xhci: data direction mismatch for TR_DATA\n");
1689 goto err;
1690 }
1691 /* fallthrough */
1692 case TR_NORMAL:
1693 case TR_ISOCH:
1694 addr = xhci_mask64(trb->parameter);
1695 chunk = trb->status & 0x1ffff;
1696 if (trb->control & TRB_TR_IDT) {
1697 if (chunk > 8 || in_xfer) {
1698 DPRINTF("xhci: invalid immediate data TRB\n");
1699 goto err;
1700 }
1701 qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1702 } else {
1703 qemu_sglist_add(&xfer->sgl, addr, chunk);
1704 }
1705 break;
1706 }
1707 }
1708
1709 return 0;
1710
1711 err:
1712 qemu_sglist_destroy(&xfer->sgl);
1713 xhci_die(xhci);
1714 return -1;
1715 }
1716
1717 static void xhci_xfer_unmap(XHCITransfer *xfer)
1718 {
1719 usb_packet_unmap(&xfer->packet, &xfer->sgl);
1720 qemu_sglist_destroy(&xfer->sgl);
1721 }
1722
1723 static void xhci_xfer_report(XHCITransfer *xfer)
1724 {
1725 uint32_t edtla = 0;
1726 unsigned int left;
1727 bool reported = 0;
1728 bool shortpkt = 0;
1729 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1730 XHCIState *xhci = xfer->xhci;
1731 int i;
1732
1733 left = xfer->packet.actual_length;
1734
1735 for (i = 0; i < xfer->trb_count; i++) {
1736 XHCITRB *trb = &xfer->trbs[i];
1737 unsigned int chunk = 0;
1738
1739 switch (TRB_TYPE(*trb)) {
1740 case TR_DATA:
1741 case TR_NORMAL:
1742 case TR_ISOCH:
1743 chunk = trb->status & 0x1ffff;
1744 if (chunk > left) {
1745 chunk = left;
1746 if (xfer->status == CC_SUCCESS) {
1747 shortpkt = 1;
1748 }
1749 }
1750 left -= chunk;
1751 edtla += chunk;
1752 break;
1753 case TR_STATUS:
1754 reported = 0;
1755 shortpkt = 0;
1756 break;
1757 }
1758
1759 if (!reported && ((trb->control & TRB_TR_IOC) ||
1760 (shortpkt && (trb->control & TRB_TR_ISP)) ||
1761 (xfer->status != CC_SUCCESS && left == 0))) {
1762 event.slotid = xfer->slotid;
1763 event.epid = xfer->epid;
1764 event.length = (trb->status & 0x1ffff) - chunk;
1765 event.flags = 0;
1766 event.ptr = trb->addr;
1767 if (xfer->status == CC_SUCCESS) {
1768 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1769 } else {
1770 event.ccode = xfer->status;
1771 }
1772 if (TRB_TYPE(*trb) == TR_EVDATA) {
1773 event.ptr = trb->parameter;
1774 event.flags |= TRB_EV_ED;
1775 event.length = edtla & 0xffffff;
1776 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1777 edtla = 0;
1778 }
1779 xhci_event(xhci, &event, TRB_INTR(*trb));
1780 reported = 1;
1781 if (xfer->status != CC_SUCCESS) {
1782 return;
1783 }
1784 }
1785 }
1786 }
1787
1788 static void xhci_stall_ep(XHCITransfer *xfer)
1789 {
1790 XHCIState *xhci = xfer->xhci;
1791 XHCISlot *slot = &xhci->slots[xfer->slotid-1];
1792 XHCIEPContext *epctx = slot->eps[xfer->epid-1];
1793 uint32_t err;
1794 XHCIStreamContext *sctx;
1795
1796 if (epctx->nr_pstreams) {
1797 sctx = xhci_find_stream(epctx, xfer->streamid, &err);
1798 if (sctx == NULL) {
1799 return;
1800 }
1801 sctx->ring.dequeue = xfer->trbs[0].addr;
1802 sctx->ring.ccs = xfer->trbs[0].ccs;
1803 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED);
1804 } else {
1805 epctx->ring.dequeue = xfer->trbs[0].addr;
1806 epctx->ring.ccs = xfer->trbs[0].ccs;
1807 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED);
1808 }
1809 }
1810
1811 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer,
1812 XHCIEPContext *epctx);
1813
1814 static int xhci_setup_packet(XHCITransfer *xfer)
1815 {
1816 XHCIState *xhci = xfer->xhci;
1817 USBEndpoint *ep;
1818 int dir;
1819
1820 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
1821
1822 if (xfer->packet.ep) {
1823 ep = xfer->packet.ep;
1824 } else {
1825 ep = xhci_epid_to_usbep(xhci, xfer->slotid, xfer->epid);
1826 if (!ep) {
1827 DPRINTF("xhci: slot %d has no device\n",
1828 xfer->slotid);
1829 return -1;
1830 }
1831 }
1832
1833 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */
1834 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid,
1835 xfer->trbs[0].addr, false, xfer->int_req);
1836 usb_packet_map(&xfer->packet, &xfer->sgl);
1837 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1838 xfer->packet.pid, ep->dev->addr, ep->nr);
1839 return 0;
1840 }
1841
1842 static int xhci_complete_packet(XHCITransfer *xfer)
1843 {
1844 if (xfer->packet.status == USB_RET_ASYNC) {
1845 trace_usb_xhci_xfer_async(xfer);
1846 xfer->running_async = 1;
1847 xfer->running_retry = 0;
1848 xfer->complete = 0;
1849 return 0;
1850 } else if (xfer->packet.status == USB_RET_NAK) {
1851 trace_usb_xhci_xfer_nak(xfer);
1852 xfer->running_async = 0;
1853 xfer->running_retry = 1;
1854 xfer->complete = 0;
1855 return 0;
1856 } else {
1857 xfer->running_async = 0;
1858 xfer->running_retry = 0;
1859 xfer->complete = 1;
1860 xhci_xfer_unmap(xfer);
1861 }
1862
1863 if (xfer->packet.status == USB_RET_SUCCESS) {
1864 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length);
1865 xfer->status = CC_SUCCESS;
1866 xhci_xfer_report(xfer);
1867 return 0;
1868 }
1869
1870 /* error */
1871 trace_usb_xhci_xfer_error(xfer, xfer->packet.status);
1872 switch (xfer->packet.status) {
1873 case USB_RET_NODEV:
1874 case USB_RET_IOERROR:
1875 xfer->status = CC_USB_TRANSACTION_ERROR;
1876 xhci_xfer_report(xfer);
1877 xhci_stall_ep(xfer);
1878 break;
1879 case USB_RET_STALL:
1880 xfer->status = CC_STALL_ERROR;
1881 xhci_xfer_report(xfer);
1882 xhci_stall_ep(xfer);
1883 break;
1884 case USB_RET_BABBLE:
1885 xfer->status = CC_BABBLE_DETECTED;
1886 xhci_xfer_report(xfer);
1887 xhci_stall_ep(xfer);
1888 break;
1889 default:
1890 DPRINTF("%s: FIXME: status = %d\n", __func__,
1891 xfer->packet.status);
1892 FIXME("unhandled USB_RET_*");
1893 }
1894 return 0;
1895 }
1896
1897 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1898 {
1899 XHCITRB *trb_setup, *trb_status;
1900 uint8_t bmRequestType;
1901
1902 trb_setup = &xfer->trbs[0];
1903 trb_status = &xfer->trbs[xfer->trb_count-1];
1904
1905 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid);
1906
1907 /* at most one Event Data TRB allowed after STATUS */
1908 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1909 trb_status--;
1910 }
1911
1912 /* do some sanity checks */
1913 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1914 DPRINTF("xhci: ep0 first TD not SETUP: %d\n",
1915 TRB_TYPE(*trb_setup));
1916 return -1;
1917 }
1918 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1919 DPRINTF("xhci: ep0 last TD not STATUS: %d\n",
1920 TRB_TYPE(*trb_status));
1921 return -1;
1922 }
1923 if (!(trb_setup->control & TRB_TR_IDT)) {
1924 DPRINTF("xhci: Setup TRB doesn't have IDT set\n");
1925 return -1;
1926 }
1927 if ((trb_setup->status & 0x1ffff) != 8) {
1928 DPRINTF("xhci: Setup TRB has bad length (%d)\n",
1929 (trb_setup->status & 0x1ffff));
1930 return -1;
1931 }
1932
1933 bmRequestType = trb_setup->parameter;
1934
1935 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1936 xfer->iso_xfer = false;
1937 xfer->timed_xfer = false;
1938
1939 if (xhci_setup_packet(xfer) < 0) {
1940 return -1;
1941 }
1942 xfer->packet.parameter = trb_setup->parameter;
1943
1944 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1945
1946 xhci_complete_packet(xfer);
1947 if (!xfer->running_async && !xfer->running_retry) {
1948 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, 0);
1949 }
1950 return 0;
1951 }
1952
1953 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer,
1954 XHCIEPContext *epctx, uint64_t mfindex)
1955 {
1956 uint64_t asap = ((mfindex + epctx->interval - 1) &
1957 ~(epctx->interval-1));
1958 uint64_t kick = epctx->mfindex_last + epctx->interval;
1959
1960 assert(epctx->interval != 0);
1961 xfer->mfindex_kick = MAX(asap, kick);
1962 }
1963
1964 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1965 XHCIEPContext *epctx, uint64_t mfindex)
1966 {
1967 if (xfer->trbs[0].control & TRB_TR_SIA) {
1968 uint64_t asap = ((mfindex + epctx->interval - 1) &
1969 ~(epctx->interval-1));
1970 if (asap >= epctx->mfindex_last &&
1971 asap <= epctx->mfindex_last + epctx->interval * 4) {
1972 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval;
1973 } else {
1974 xfer->mfindex_kick = asap;
1975 }
1976 } else {
1977 xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
1978 & TRB_TR_FRAMEID_MASK) << 3;
1979 xfer->mfindex_kick |= mfindex & ~0x3fff;
1980 if (xfer->mfindex_kick + 0x100 < mfindex) {
1981 xfer->mfindex_kick += 0x4000;
1982 }
1983 }
1984 }
1985
1986 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1987 XHCIEPContext *epctx, uint64_t mfindex)
1988 {
1989 if (xfer->mfindex_kick > mfindex) {
1990 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1991 (xfer->mfindex_kick - mfindex) * 125000);
1992 xfer->running_retry = 1;
1993 } else {
1994 epctx->mfindex_last = xfer->mfindex_kick;
1995 timer_del(epctx->kick_timer);
1996 xfer->running_retry = 0;
1997 }
1998 }
1999
2000
2001 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
2002 {
2003 uint64_t mfindex;
2004
2005 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
2006
2007 xfer->in_xfer = epctx->type>>2;
2008
2009 switch(epctx->type) {
2010 case ET_INTR_OUT:
2011 case ET_INTR_IN:
2012 xfer->pkts = 0;
2013 xfer->iso_xfer = false;
2014 xfer->timed_xfer = true;
2015 mfindex = xhci_mfindex_get(xhci);
2016 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex);
2017 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
2018 if (xfer->running_retry) {
2019 return -1;
2020 }
2021 break;
2022 case ET_BULK_OUT:
2023 case ET_BULK_IN:
2024 xfer->pkts = 0;
2025 xfer->iso_xfer = false;
2026 xfer->timed_xfer = false;
2027 break;
2028 case ET_ISO_OUT:
2029 case ET_ISO_IN:
2030 xfer->pkts = 1;
2031 xfer->iso_xfer = true;
2032 xfer->timed_xfer = true;
2033 mfindex = xhci_mfindex_get(xhci);
2034 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex);
2035 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
2036 if (xfer->running_retry) {
2037 return -1;
2038 }
2039 break;
2040 default:
2041 trace_usb_xhci_unimplemented("endpoint type", epctx->type);
2042 return -1;
2043 }
2044
2045 if (xhci_setup_packet(xfer) < 0) {
2046 return -1;
2047 }
2048 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2049
2050 xhci_complete_packet(xfer);
2051 if (!xfer->running_async && !xfer->running_retry) {
2052 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, xfer->streamid);
2053 }
2054 return 0;
2055 }
2056
2057 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
2058 {
2059 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid);
2060 return xhci_submit(xhci, xfer, epctx);
2061 }
2062
2063 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
2064 unsigned int epid, unsigned int streamid)
2065 {
2066 XHCIStreamContext *stctx;
2067 XHCIEPContext *epctx;
2068 XHCIRing *ring;
2069 USBEndpoint *ep = NULL;
2070 uint64_t mfindex;
2071 int length;
2072 int i;
2073
2074 trace_usb_xhci_ep_kick(slotid, epid, streamid);
2075 assert(slotid >= 1 && slotid <= xhci->numslots);
2076 assert(epid >= 1 && epid <= 31);
2077
2078 if (!xhci->slots[slotid-1].enabled) {
2079 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid);
2080 return;
2081 }
2082 epctx = xhci->slots[slotid-1].eps[epid-1];
2083 if (!epctx) {
2084 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
2085 epid, slotid);
2086 return;
2087 }
2088
2089 /* If the device has been detached, but the guest has not noticed this
2090 yet the 2 above checks will succeed, but we must NOT continue */
2091 if (!xhci->slots[slotid - 1].uport ||
2092 !xhci->slots[slotid - 1].uport->dev ||
2093 !xhci->slots[slotid - 1].uport->dev->attached) {
2094 return;
2095 }
2096
2097 if (epctx->retry) {
2098 XHCITransfer *xfer = epctx->retry;
2099
2100 trace_usb_xhci_xfer_retry(xfer);
2101 assert(xfer->running_retry);
2102 if (xfer->timed_xfer) {
2103 /* time to kick the transfer? */
2104 mfindex = xhci_mfindex_get(xhci);
2105 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
2106 if (xfer->running_retry) {
2107 return;
2108 }
2109 xfer->timed_xfer = 0;
2110 xfer->running_retry = 1;
2111 }
2112 if (xfer->iso_xfer) {
2113 /* retry iso transfer */
2114 if (xhci_setup_packet(xfer) < 0) {
2115 return;
2116 }
2117 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2118 assert(xfer->packet.status != USB_RET_NAK);
2119 xhci_complete_packet(xfer);
2120 } else {
2121 /* retry nak'ed transfer */
2122 if (xhci_setup_packet(xfer) < 0) {
2123 return;
2124 }
2125 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2126 if (xfer->packet.status == USB_RET_NAK) {
2127 return;
2128 }
2129 xhci_complete_packet(xfer);
2130 }
2131 assert(!xfer->running_retry);
2132 epctx->retry = NULL;
2133 }
2134
2135 if (epctx->state == EP_HALTED) {
2136 DPRINTF("xhci: ep halted, not running schedule\n");
2137 return;
2138 }
2139
2140
2141 if (epctx->nr_pstreams) {
2142 uint32_t err;
2143 stctx = xhci_find_stream(epctx, streamid, &err);
2144 if (stctx == NULL) {
2145 return;
2146 }
2147 ring = &stctx->ring;
2148 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING);
2149 } else {
2150 ring = &epctx->ring;
2151 streamid = 0;
2152 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING);
2153 }
2154 assert(ring->dequeue != 0);
2155
2156 while (1) {
2157 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer];
2158 if (xfer->running_async || xfer->running_retry) {
2159 break;
2160 }
2161 length = xhci_ring_chain_length(xhci, ring);
2162 if (length < 0) {
2163 break;
2164 } else if (length == 0) {
2165 break;
2166 }
2167 if (xfer->trbs && xfer->trb_alloced < length) {
2168 xfer->trb_count = 0;
2169 xfer->trb_alloced = 0;
2170 g_free(xfer->trbs);
2171 xfer->trbs = NULL;
2172 }
2173 if (!xfer->trbs) {
2174 xfer->trbs = g_malloc(sizeof(XHCITRB) * length);
2175 xfer->trb_alloced = length;
2176 }
2177 xfer->trb_count = length;
2178
2179 for (i = 0; i < length; i++) {
2180 assert(xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL));
2181 }
2182 xfer->streamid = streamid;
2183
2184 if (epid == 1) {
2185 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) {
2186 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
2187 ep = xfer->packet.ep;
2188 } else {
2189 DPRINTF("xhci: error firing CTL transfer\n");
2190 }
2191 } else {
2192 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) {
2193 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
2194 } else {
2195 if (!xfer->timed_xfer) {
2196 DPRINTF("xhci: error firing data transfer\n");
2197 }
2198 }
2199 }
2200
2201 if (epctx->state == EP_HALTED) {
2202 break;
2203 }
2204 if (xfer->running_retry) {
2205 DPRINTF("xhci: xfer nacked, stopping schedule\n");
2206 epctx->retry = xfer;
2207 break;
2208 }
2209 }
2210
2211 ep = xhci_epid_to_usbep(xhci, slotid, epid);
2212 if (ep) {
2213 usb_device_flush_ep_queue(ep->dev, ep);
2214 }
2215 }
2216
2217 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
2218 {
2219 trace_usb_xhci_slot_enable(slotid);
2220 assert(slotid >= 1 && slotid <= xhci->numslots);
2221 xhci->slots[slotid-1].enabled = 1;
2222 xhci->slots[slotid-1].uport = NULL;
2223 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
2224
2225 return CC_SUCCESS;
2226 }
2227
2228 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
2229 {
2230 int i;
2231
2232 trace_usb_xhci_slot_disable(slotid);
2233 assert(slotid >= 1 && slotid <= xhci->numslots);
2234
2235 for (i = 1; i <= 31; i++) {
2236 if (xhci->slots[slotid-1].eps[i-1]) {
2237 xhci_disable_ep(xhci, slotid, i);
2238 }
2239 }
2240
2241 xhci->slots[slotid-1].enabled = 0;
2242 xhci->slots[slotid-1].addressed = 0;
2243 xhci->slots[slotid-1].uport = NULL;
2244 return CC_SUCCESS;
2245 }
2246
2247 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx)
2248 {
2249 USBPort *uport;
2250 char path[32];
2251 int i, pos, port;
2252
2253 port = (slot_ctx[1]>>16) & 0xFF;
2254 port = xhci->ports[port-1].uport->index+1;
2255 pos = snprintf(path, sizeof(path), "%d", port);
2256 for (i = 0; i < 5; i++) {
2257 port = (slot_ctx[0] >> 4*i) & 0x0f;
2258 if (!port) {
2259 break;
2260 }
2261 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port);
2262 }
2263
2264 QTAILQ_FOREACH(uport, &xhci->bus.used, next) {
2265 if (strcmp(uport->path, path) == 0) {
2266 return uport;
2267 }
2268 }
2269 return NULL;
2270 }
2271
2272 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
2273 uint64_t pictx, bool bsr)
2274 {
2275 XHCISlot *slot;
2276 USBPort *uport;
2277 USBDevice *dev;
2278 dma_addr_t ictx, octx, dcbaap;
2279 uint64_t poctx;
2280 uint32_t ictl_ctx[2];
2281 uint32_t slot_ctx[4];
2282 uint32_t ep0_ctx[5];
2283 int i;
2284 TRBCCode res;
2285
2286 assert(slotid >= 1 && slotid <= xhci->numslots);
2287
2288 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
2289 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid);
2290 ictx = xhci_mask64(pictx);
2291 octx = xhci_mask64(poctx);
2292
2293 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2294 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2295
2296 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2297
2298 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
2299 DPRINTF("xhci: invalid input context control %08x %08x\n",
2300 ictl_ctx[0], ictl_ctx[1]);
2301 return CC_TRB_ERROR;
2302 }
2303
2304 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx));
2305 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx));
2306
2307 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2308 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2309
2310 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2311 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2312
2313 uport = xhci_lookup_uport(xhci, slot_ctx);
2314 if (uport == NULL) {
2315 DPRINTF("xhci: port not found\n");
2316 return CC_TRB_ERROR;
2317 }
2318 trace_usb_xhci_slot_address(slotid, uport->path);
2319
2320 dev = uport->dev;
2321 if (!dev || !dev->attached) {
2322 DPRINTF("xhci: port %s not connected\n", uport->path);
2323 return CC_USB_TRANSACTION_ERROR;
2324 }
2325
2326 for (i = 0; i < xhci->numslots; i++) {
2327 if (i == slotid-1) {
2328 continue;
2329 }
2330 if (xhci->slots[i].uport == uport) {
2331 DPRINTF("xhci: port %s already assigned to slot %d\n",
2332 uport->path, i+1);
2333 return CC_TRB_ERROR;
2334 }
2335 }
2336
2337 slot = &xhci->slots[slotid-1];
2338 slot->uport = uport;
2339 slot->ctx = octx;
2340
2341 if (bsr) {
2342 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
2343 } else {
2344 USBPacket p;
2345 uint8_t buf[1];
2346
2347 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid;
2348 usb_device_reset(dev);
2349 memset(&p, 0, sizeof(p));
2350 usb_packet_addbuf(&p, buf, sizeof(buf));
2351 usb_packet_setup(&p, USB_TOKEN_OUT,
2352 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0,
2353 0, false, false);
2354 usb_device_handle_control(dev, &p,
2355 DeviceOutRequest | USB_REQ_SET_ADDRESS,
2356 slotid, 0, 0, NULL);
2357 assert(p.status != USB_RET_ASYNC);
2358 }
2359
2360 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
2361
2362 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2363 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2364 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2365 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2366
2367 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2368 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2369
2370 xhci->slots[slotid-1].addressed = 1;
2371 return res;
2372 }
2373
2374
2375 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
2376 uint64_t pictx, bool dc)
2377 {
2378 dma_addr_t ictx, octx;
2379 uint32_t ictl_ctx[2];
2380 uint32_t slot_ctx[4];
2381 uint32_t islot_ctx[4];
2382 uint32_t ep_ctx[5];
2383 int i;
2384 TRBCCode res;
2385
2386 trace_usb_xhci_slot_configure(slotid);
2387 assert(slotid >= 1 && slotid <= xhci->numslots);
2388
2389 ictx = xhci_mask64(pictx);
2390 octx = xhci->slots[slotid-1].ctx;
2391
2392 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2393 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2394
2395 if (dc) {
2396 for (i = 2; i <= 31; i++) {
2397 if (xhci->slots[slotid-1].eps[i-1]) {
2398 xhci_disable_ep(xhci, slotid, i);
2399 }
2400 }
2401
2402 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2403 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2404 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
2405 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2406 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2407 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2408
2409 return CC_SUCCESS;
2410 }
2411
2412 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2413
2414 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
2415 DPRINTF("xhci: invalid input context control %08x %08x\n",
2416 ictl_ctx[0], ictl_ctx[1]);
2417 return CC_TRB_ERROR;
2418 }
2419
2420 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2421 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2422
2423 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
2424 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]);
2425 return CC_CONTEXT_STATE_ERROR;
2426 }
2427
2428 xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]);
2429
2430 for (i = 2; i <= 31; i++) {
2431 if (ictl_ctx[0] & (1<<i)) {
2432 xhci_disable_ep(xhci, slotid, i);
2433 }
2434 if (ictl_ctx[1] & (1<<i)) {
2435 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx));
2436 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2437 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2438 ep_ctx[3], ep_ctx[4]);
2439 xhci_disable_ep(xhci, slotid, i);
2440 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
2441 if (res != CC_SUCCESS) {
2442 return res;
2443 }
2444 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2445 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2446 ep_ctx[3], ep_ctx[4]);
2447 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx));
2448 }
2449 }
2450
2451 res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]);
2452 if (res != CC_SUCCESS) {
2453 for (i = 2; i <= 31; i++) {
2454 if (ictl_ctx[1] & (1 << i)) {
2455 xhci_disable_ep(xhci, slotid, i);
2456 }
2457 }
2458 return res;
2459 }
2460
2461 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2462 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
2463 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
2464 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
2465 SLOT_CONTEXT_ENTRIES_SHIFT);
2466 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2467 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2468
2469 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2470
2471 return CC_SUCCESS;
2472 }
2473
2474
2475 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
2476 uint64_t pictx)
2477 {
2478 dma_addr_t ictx, octx;
2479 uint32_t ictl_ctx[2];
2480 uint32_t iep0_ctx[5];
2481 uint32_t ep0_ctx[5];
2482 uint32_t islot_ctx[4];
2483 uint32_t slot_ctx[4];
2484
2485 trace_usb_xhci_slot_evaluate(slotid);
2486 assert(slotid >= 1 && slotid <= xhci->numslots);
2487
2488 ictx = xhci_mask64(pictx);
2489 octx = xhci->slots[slotid-1].ctx;
2490
2491 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2492 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2493
2494 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2495
2496 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
2497 DPRINTF("xhci: invalid input context control %08x %08x\n",
2498 ictl_ctx[0], ictl_ctx[1]);
2499 return CC_TRB_ERROR;
2500 }
2501
2502 if (ictl_ctx[1] & 0x1) {
2503 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2504
2505 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2506 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
2507
2508 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2509
2510 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
2511 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
2512 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
2513 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
2514
2515 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2516 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2517
2518 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2519 }
2520
2521 if (ictl_ctx[1] & 0x2) {
2522 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx));
2523
2524 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2525 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
2526 iep0_ctx[3], iep0_ctx[4]);
2527
2528 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2529
2530 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2531 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2532
2533 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2534 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2535
2536 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2537 }
2538
2539 return CC_SUCCESS;
2540 }
2541
2542 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2543 {
2544 uint32_t slot_ctx[4];
2545 dma_addr_t octx;
2546 int i;
2547
2548 trace_usb_xhci_slot_reset(slotid);
2549 assert(slotid >= 1 && slotid <= xhci->numslots);
2550
2551 octx = xhci->slots[slotid-1].ctx;
2552
2553 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2554
2555 for (i = 2; i <= 31; i++) {
2556 if (xhci->slots[slotid-1].eps[i-1]) {
2557 xhci_disable_ep(xhci, slotid, i);
2558 }
2559 }
2560
2561 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2562 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2563 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
2564 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2565 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2566 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2567
2568 return CC_SUCCESS;
2569 }
2570
2571 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2572 {
2573 unsigned int slotid;
2574 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
2575 if (slotid < 1 || slotid > xhci->numslots) {
2576 DPRINTF("xhci: bad slot id %d\n", slotid);
2577 event->ccode = CC_TRB_ERROR;
2578 return 0;
2579 } else if (!xhci->slots[slotid-1].enabled) {
2580 DPRINTF("xhci: slot id %d not enabled\n", slotid);
2581 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2582 return 0;
2583 }
2584 return slotid;
2585 }
2586
2587 /* cleanup slot state on usb device detach */
2588 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport)
2589 {
2590 int slot, ep;
2591
2592 for (slot = 0; slot < xhci->numslots; slot++) {
2593 if (xhci->slots[slot].uport == uport) {
2594 break;
2595 }
2596 }
2597 if (slot == xhci->numslots) {
2598 return;
2599 }
2600
2601 for (ep = 0; ep < 31; ep++) {
2602 if (xhci->slots[slot].eps[ep]) {
2603 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0);
2604 }
2605 }
2606 xhci->slots[slot].uport = NULL;
2607 }
2608
2609 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2610 {
2611 dma_addr_t ctx;
2612 uint8_t bw_ctx[xhci->numports+1];
2613
2614 DPRINTF("xhci_get_port_bandwidth()\n");
2615
2616 ctx = xhci_mask64(pctx);
2617
2618 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
2619
2620 /* TODO: actually implement real values here */
2621 bw_ctx[0] = 0;
2622 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
2623 pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx));
2624
2625 return CC_SUCCESS;
2626 }
2627
2628 static uint32_t rotl(uint32_t v, unsigned count)
2629 {
2630 count &= 31;
2631 return (v << count) | (v >> (32 - count));
2632 }
2633
2634
2635 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2636 {
2637 uint32_t val;
2638 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2639 val += rotl(lo + 0x49434878, hi & 0x1F);
2640 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2641 return ~val;
2642 }
2643
2644 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
2645 {
2646 PCIDevice *pci_dev = PCI_DEVICE(xhci);
2647 uint32_t buf[8];
2648 uint32_t obuf[8];
2649 dma_addr_t paddr = xhci_mask64(addr);
2650
2651 pci_dma_read(pci_dev, paddr, &buf, 32);
2652
2653 memcpy(obuf, buf, sizeof(obuf));
2654
2655 if ((buf[0] & 0xff) == 2) {
2656 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3];
2657 obuf[0] |= (buf[2] * buf[3]) & 0xff;
2658 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3];
2659 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3];
2660 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3];
2661 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3];
2662 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3];
2663 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956;
2664 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
2665 }
2666
2667 pci_dma_write(pci_dev, paddr, &obuf, 32);
2668 }
2669
2670 static void xhci_process_commands(XHCIState *xhci)
2671 {
2672 XHCITRB trb;
2673 TRBType type;
2674 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
2675 dma_addr_t addr;
2676 unsigned int i, slotid = 0;
2677
2678 DPRINTF("xhci_process_commands()\n");
2679 if (!xhci_running(xhci)) {
2680 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2681 return;
2682 }
2683
2684 xhci->crcr_low |= CRCR_CRR;
2685
2686 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2687 event.ptr = addr;
2688 switch (type) {
2689 case CR_ENABLE_SLOT:
2690 for (i = 0; i < xhci->numslots; i++) {
2691 if (!xhci->slots[i].enabled) {
2692 break;
2693 }
2694 }
2695 if (i >= xhci->numslots) {
2696 DPRINTF("xhci: no device slots available\n");
2697 event.ccode = CC_NO_SLOTS_ERROR;
2698 } else {
2699 slotid = i+1;
2700 event.ccode = xhci_enable_slot(xhci, slotid);
2701 }
2702 break;
2703 case CR_DISABLE_SLOT:
2704 slotid = xhci_get_slot(xhci, &event, &trb);
2705 if (slotid) {
2706 event.ccode = xhci_disable_slot(xhci, slotid);
2707 }
2708 break;
2709 case CR_ADDRESS_DEVICE:
2710 slotid = xhci_get_slot(xhci, &event, &trb);
2711 if (slotid) {
2712 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2713 trb.control & TRB_CR_BSR);
2714 }
2715 break;
2716 case CR_CONFIGURE_ENDPOINT:
2717 slotid = xhci_get_slot(xhci, &event, &trb);
2718 if (slotid) {
2719 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2720 trb.control & TRB_CR_DC);
2721 }
2722 break;
2723 case CR_EVALUATE_CONTEXT:
2724 slotid = xhci_get_slot(xhci, &event, &trb);
2725 if (slotid) {
2726 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2727 }
2728 break;
2729 case CR_STOP_ENDPOINT:
2730 slotid = xhci_get_slot(xhci, &event, &trb);
2731 if (slotid) {
2732 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2733 & TRB_CR_EPID_MASK;
2734 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2735 }
2736 break;
2737 case CR_RESET_ENDPOINT:
2738 slotid = xhci_get_slot(xhci, &event, &trb);
2739 if (slotid) {
2740 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2741 & TRB_CR_EPID_MASK;
2742 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2743 }
2744 break;
2745 case CR_SET_TR_DEQUEUE:
2746 slotid = xhci_get_slot(xhci, &event, &trb);
2747 if (slotid) {
2748 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2749 & TRB_CR_EPID_MASK;
2750 unsigned int streamid = (trb.status >> 16) & 0xffff;
2751 event.ccode = xhci_set_ep_dequeue(xhci, slotid,
2752 epid, streamid,
2753 trb.parameter);
2754 }
2755 break;
2756 case CR_RESET_DEVICE:
2757 slotid = xhci_get_slot(xhci, &event, &trb);
2758 if (slotid) {
2759 event.ccode = xhci_reset_slot(xhci, slotid);
2760 }
2761 break;
2762 case CR_GET_PORT_BANDWIDTH:
2763 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2764 break;
2765 case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
2766 xhci_via_challenge(xhci, trb.parameter);
2767 break;
2768 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2769 event.type = 48; /* NEC reply */
2770 event.length = 0x3025;
2771 break;
2772 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2773 {
2774 uint32_t chi = trb.parameter >> 32;
2775 uint32_t clo = trb.parameter;
2776 uint32_t val = xhci_nec_challenge(chi, clo);
2777 event.length = val & 0xFFFF;
2778 event.epid = val >> 16;
2779 slotid = val >> 24;
2780 event.type = 48; /* NEC reply */
2781 }
2782 break;
2783 default:
2784 trace_usb_xhci_unimplemented("command", type);
2785 event.ccode = CC_TRB_ERROR;
2786 break;
2787 }
2788 event.slotid = slotid;
2789 xhci_event(xhci, &event, 0);
2790 }
2791 }
2792
2793 static bool xhci_port_have_device(XHCIPort *port)
2794 {
2795 if (!port->uport->dev || !port->uport->dev->attached) {
2796 return false; /* no device present */
2797 }
2798 if (!((1 << port->uport->dev->speed) & port->speedmask)) {
2799 return false; /* speed mismatch */
2800 }
2801 return true;
2802 }
2803
2804 static void xhci_port_notify(XHCIPort *port, uint32_t bits)
2805 {
2806 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
2807 port->portnr << 24 };
2808
2809 if ((port->portsc & bits) == bits) {
2810 return;
2811 }
2812 trace_usb_xhci_port_notify(port->portnr, bits);
2813 port->portsc |= bits;
2814 if (!xhci_running(port->xhci)) {
2815 return;
2816 }
2817 xhci_event(port->xhci, &ev, 0);
2818 }
2819
2820 static void xhci_port_update(XHCIPort *port, int is_detach)
2821 {
2822 uint32_t pls = PLS_RX_DETECT;
2823
2824 port->portsc = PORTSC_PP;
2825 if (!is_detach && xhci_port_have_device(port)) {
2826 port->portsc |= PORTSC_CCS;
2827 switch (port->uport->dev->speed) {
2828 case USB_SPEED_LOW:
2829 port->portsc |= PORTSC_SPEED_LOW;
2830 pls = PLS_POLLING;
2831 break;
2832 case USB_SPEED_FULL:
2833 port->portsc |= PORTSC_SPEED_FULL;
2834 pls = PLS_POLLING;
2835 break;
2836 case USB_SPEED_HIGH:
2837 port->portsc |= PORTSC_SPEED_HIGH;
2838 pls = PLS_POLLING;
2839 break;
2840 case USB_SPEED_SUPER:
2841 port->portsc |= PORTSC_SPEED_SUPER;
2842 port->portsc |= PORTSC_PED;
2843 pls = PLS_U0;
2844 break;
2845 }
2846 }
2847 set_field(&port->portsc, pls, PORTSC_PLS);
2848 trace_usb_xhci_port_link(port->portnr, pls);
2849 xhci_port_notify(port, PORTSC_CSC);
2850 }
2851
2852 static void xhci_port_reset(XHCIPort *port, bool warm_reset)
2853 {
2854 trace_usb_xhci_port_reset(port->portnr);
2855
2856 if (!xhci_port_have_device(port)) {
2857 return;
2858 }
2859
2860 usb_device_reset(port->uport->dev);
2861
2862 switch (port->uport->dev->speed) {
2863 case USB_SPEED_SUPER:
2864 if (warm_reset) {
2865 port->portsc |= PORTSC_WRC;
2866 }
2867 /* fall through */
2868 case USB_SPEED_LOW:
2869 case USB_SPEED_FULL:
2870 case USB_SPEED_HIGH:
2871 set_field(&port->portsc, PLS_U0, PORTSC_PLS);
2872 trace_usb_xhci_port_link(port->portnr, PLS_U0);
2873 port->portsc |= PORTSC_PED;
2874 break;
2875 }
2876
2877 port->portsc &= ~PORTSC_PR;
2878 xhci_port_notify(port, PORTSC_PRC);
2879 }
2880
2881 static void xhci_reset(DeviceState *dev)
2882 {
2883 XHCIState *xhci = XHCI(dev);
2884 int i;
2885
2886 trace_usb_xhci_reset();
2887 if (!(xhci->usbsts & USBSTS_HCH)) {
2888 DPRINTF("xhci: reset while running!\n");
2889 }
2890
2891 xhci->usbcmd = 0;
2892 xhci->usbsts = USBSTS_HCH;
2893 xhci->dnctrl = 0;
2894 xhci->crcr_low = 0;
2895 xhci->crcr_high = 0;
2896 xhci->dcbaap_low = 0;
2897 xhci->dcbaap_high = 0;
2898 xhci->config = 0;
2899
2900 for (i = 0; i < xhci->numslots; i++) {
2901 xhci_disable_slot(xhci, i+1);
2902 }
2903
2904 for (i = 0; i < xhci->numports; i++) {
2905 xhci_port_update(xhci->ports + i, 0);
2906 }
2907
2908 for (i = 0; i < xhci->numintrs; i++) {
2909 xhci->intr[i].iman = 0;
2910 xhci->intr[i].imod = 0;
2911 xhci->intr[i].erstsz = 0;
2912 xhci->intr[i].erstba_low = 0;
2913 xhci->intr[i].erstba_high = 0;
2914 xhci->intr[i].erdp_low = 0;
2915 xhci->intr[i].erdp_high = 0;
2916 xhci->intr[i].msix_used = 0;
2917
2918 xhci->intr[i].er_ep_idx = 0;
2919 xhci->intr[i].er_pcs = 1;
2920 xhci->intr[i].er_full = 0;
2921 xhci->intr[i].ev_buffer_put = 0;
2922 xhci->intr[i].ev_buffer_get = 0;
2923 }
2924
2925 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2926 xhci_mfwrap_update(xhci);
2927 }
2928
2929 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
2930 {
2931 XHCIState *xhci = ptr;
2932 uint32_t ret;
2933
2934 switch (reg) {
2935 case 0x00: /* HCIVERSION, CAPLENGTH */
2936 ret = 0x01000000 | LEN_CAP;
2937 break;
2938 case 0x04: /* HCSPARAMS 1 */
2939 ret = ((xhci->numports_2+xhci->numports_3)<<24)
2940 | (xhci->numintrs<<8) | xhci->numslots;
2941 break;
2942 case 0x08: /* HCSPARAMS 2 */
2943 ret = 0x0000000f;
2944 break;
2945 case 0x0c: /* HCSPARAMS 3 */
2946 ret = 0x00000000;
2947 break;
2948 case 0x10: /* HCCPARAMS */
2949 if (sizeof(dma_addr_t) == 4) {
2950 ret = 0x00087000;
2951 } else {
2952 ret = 0x00087001;
2953 }
2954 break;
2955 case 0x14: /* DBOFF */
2956 ret = OFF_DOORBELL;
2957 break;
2958 case 0x18: /* RTSOFF */
2959 ret = OFF_RUNTIME;
2960 break;
2961
2962 /* extended capabilities */
2963 case 0x20: /* Supported Protocol:00 */
2964 ret = 0x02000402; /* USB 2.0 */
2965 break;
2966 case 0x24: /* Supported Protocol:04 */
2967 ret = 0x20425355; /* "USB " */
2968 break;
2969 case 0x28: /* Supported Protocol:08 */
2970 ret = 0x00000001 | (xhci->numports_2<<8);
2971 break;
2972 case 0x2c: /* Supported Protocol:0c */
2973 ret = 0x00000000; /* reserved */
2974 break;
2975 case 0x30: /* Supported Protocol:00 */
2976 ret = 0x03000002; /* USB 3.0 */
2977 break;
2978 case 0x34: /* Supported Protocol:04 */
2979 ret = 0x20425355; /* "USB " */
2980 break;
2981 case 0x38: /* Supported Protocol:08 */
2982 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8);
2983 break;
2984 case 0x3c: /* Supported Protocol:0c */
2985 ret = 0x00000000; /* reserved */
2986 break;
2987 default:
2988 trace_usb_xhci_unimplemented("cap read", reg);
2989 ret = 0;
2990 }
2991
2992 trace_usb_xhci_cap_read(reg, ret);
2993 return ret;
2994 }
2995
2996 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
2997 {
2998 XHCIPort *port = ptr;
2999 uint32_t ret;
3000
3001 switch (reg) {
3002 case 0x00: /* PORTSC */
3003 ret = port->portsc;
3004 break;
3005 case 0x04: /* PORTPMSC */
3006 case 0x08: /* PORTLI */
3007 ret = 0;
3008 break;
3009 case 0x0c: /* reserved */
3010 default:
3011 trace_usb_xhci_unimplemented("port read", reg);
3012 ret = 0;
3013 }
3014
3015 trace_usb_xhci_port_read(port->portnr, reg, ret);
3016 return ret;
3017 }
3018
3019 static void xhci_port_write(void *ptr, hwaddr reg,
3020 uint64_t val, unsigned size)
3021 {
3022 XHCIPort *port = ptr;
3023 uint32_t portsc, notify;
3024
3025 trace_usb_xhci_port_write(port->portnr, reg, val);
3026
3027 switch (reg) {
3028 case 0x00: /* PORTSC */
3029 /* write-1-to-start bits */
3030 if (val & PORTSC_WPR) {
3031 xhci_port_reset(port, true);
3032 break;
3033 }
3034 if (val & PORTSC_PR) {
3035 xhci_port_reset(port, false);
3036 break;
3037 }
3038
3039 portsc = port->portsc;
3040 notify = 0;
3041 /* write-1-to-clear bits*/
3042 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
3043 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
3044 if (val & PORTSC_LWS) {
3045 /* overwrite PLS only when LWS=1 */
3046 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS);
3047 uint32_t new_pls = get_field(val, PORTSC_PLS);
3048 switch (new_pls) {
3049 case PLS_U0:
3050 if (old_pls != PLS_U0) {
3051 set_field(&portsc, new_pls, PORTSC_PLS);
3052 trace_usb_xhci_port_link(port->portnr, new_pls);
3053 notify = PORTSC_PLC;
3054 }
3055 break;
3056 case PLS_U3:
3057 if (old_pls < PLS_U3) {
3058 set_field(&portsc, new_pls, PORTSC_PLS);
3059 trace_usb_xhci_port_link(port->portnr, new_pls);
3060 }
3061 break;
3062 case PLS_RESUME:
3063 /* windows does this for some reason, don't spam stderr */
3064 break;
3065 default:
3066 DPRINTF("%s: ignore pls write (old %d, new %d)\n",
3067 __func__, old_pls, new_pls);
3068 break;
3069 }
3070 }
3071 /* read/write bits */
3072 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
3073 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
3074 port->portsc = portsc;
3075 if (notify) {
3076 xhci_port_notify(port, notify);
3077 }
3078 break;
3079 case 0x04: /* PORTPMSC */
3080 case 0x08: /* PORTLI */
3081 default:
3082 trace_usb_xhci_unimplemented("port write", reg);
3083 }
3084 }
3085
3086 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
3087 {
3088 XHCIState *xhci = ptr;
3089 uint32_t ret;
3090
3091 switch (reg) {
3092 case 0x00: /* USBCMD */
3093 ret = xhci->usbcmd;
3094 break;
3095 case 0x04: /* USBSTS */
3096 ret = xhci->usbsts;
3097 break;
3098 case 0x08: /* PAGESIZE */
3099 ret = 1; /* 4KiB */
3100 break;
3101 case 0x14: /* DNCTRL */
3102 ret = xhci->dnctrl;
3103 break;
3104 case 0x18: /* CRCR low */
3105 ret = xhci->crcr_low & ~0xe;
3106 break;
3107 case 0x1c: /* CRCR high */
3108 ret = xhci->crcr_high;
3109 break;
3110 case 0x30: /* DCBAAP low */
3111 ret = xhci->dcbaap_low;
3112 break;
3113 case 0x34: /* DCBAAP high */
3114 ret = xhci->dcbaap_high;
3115 break;
3116 case 0x38: /* CONFIG */
3117 ret = xhci->config;
3118 break;
3119 default:
3120 trace_usb_xhci_unimplemented("oper read", reg);
3121 ret = 0;
3122 }
3123
3124 trace_usb_xhci_oper_read(reg, ret);
3125 return ret;
3126 }
3127
3128 static void xhci_oper_write(void *ptr, hwaddr reg,
3129 uint64_t val, unsigned size)
3130 {
3131 XHCIState *xhci = ptr;
3132 DeviceState *d = DEVICE(ptr);
3133
3134 trace_usb_xhci_oper_write(reg, val);
3135
3136 switch (reg) {
3137 case 0x00: /* USBCMD */
3138 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
3139 xhci_run(xhci);
3140 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
3141 xhci_stop(xhci);
3142 }
3143 if (val & USBCMD_CSS) {
3144 /* save state */
3145 xhci->usbsts &= ~USBSTS_SRE;
3146 }
3147 if (val & USBCMD_CRS) {
3148 /* restore state */
3149 xhci->usbsts |= USBSTS_SRE;
3150 }
3151 xhci->usbcmd = val & 0xc0f;
3152 xhci_mfwrap_update(xhci);
3153 if (val & USBCMD_HCRST) {
3154 xhci_reset(d);
3155 }
3156 xhci_intx_update(xhci);
3157 break;
3158
3159 case 0x04: /* USBSTS */
3160 /* these bits are write-1-to-clear */
3161 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
3162 xhci_intx_update(xhci);
3163 break;
3164
3165 case 0x14: /* DNCTRL */
3166 xhci->dnctrl = val & 0xffff;
3167 break;
3168 case 0x18: /* CRCR low */
3169 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
3170 break;
3171 case 0x1c: /* CRCR high */
3172 xhci->crcr_high = val;
3173 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
3174 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
3175 xhci->crcr_low &= ~CRCR_CRR;
3176 xhci_event(xhci, &event, 0);
3177 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
3178 } else {
3179 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
3180 xhci_ring_init(xhci, &xhci->cmd_ring, base);
3181 }
3182 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
3183 break;
3184 case 0x30: /* DCBAAP low */
3185 xhci->dcbaap_low = val & 0xffffffc0;
3186 break;
3187 case 0x34: /* DCBAAP high */
3188 xhci->dcbaap_high = val;
3189 break;
3190 case 0x38: /* CONFIG */
3191 xhci->config = val & 0xff;
3192 break;
3193 default:
3194 trace_usb_xhci_unimplemented("oper write", reg);
3195 }
3196 }
3197
3198 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
3199 unsigned size)
3200 {
3201 XHCIState *xhci = ptr;
3202 uint32_t ret = 0;
3203
3204 if (reg < 0x20) {
3205 switch (reg) {
3206 case 0x00: /* MFINDEX */
3207 ret = xhci_mfindex_get(xhci) & 0x3fff;
3208 break;
3209 default:
3210 trace_usb_xhci_unimplemented("runtime read", reg);
3211 break;
3212 }
3213 } else {
3214 int v = (reg - 0x20) / 0x20;
3215 XHCIInterrupter *intr = &xhci->intr[v];
3216 switch (reg & 0x1f) {
3217 case 0x00: /* IMAN */
3218 ret = intr->iman;
3219 break;
3220 case 0x04: /* IMOD */
3221 ret = intr->imod;
3222 break;
3223 case 0x08: /* ERSTSZ */
3224 ret = intr->erstsz;
3225 break;
3226 case 0x10: /* ERSTBA low */
3227 ret = intr->erstba_low;
3228 break;
3229 case 0x14: /* ERSTBA high */
3230 ret = intr->erstba_high;
3231 break;
3232 case 0x18: /* ERDP low */
3233 ret = intr->erdp_low;
3234 break;
3235 case 0x1c: /* ERDP high */
3236 ret = intr->erdp_high;
3237 break;
3238 }
3239 }
3240
3241 trace_usb_xhci_runtime_read(reg, ret);
3242 return ret;
3243 }
3244
3245 static void xhci_runtime_write(void *ptr, hwaddr reg,
3246 uint64_t val, unsigned size)
3247 {
3248 XHCIState *xhci = ptr;
3249 int v = (reg - 0x20) / 0x20;
3250 XHCIInterrupter *intr = &xhci->intr[v];
3251 trace_usb_xhci_runtime_write(reg, val);
3252
3253 if (reg < 0x20) {
3254 trace_usb_xhci_unimplemented("runtime write", reg);
3255 return;
3256 }
3257
3258 switch (reg & 0x1f) {
3259 case 0x00: /* IMAN */
3260 if (val & IMAN_IP) {
3261 intr->iman &= ~IMAN_IP;
3262 }
3263 intr->iman &= ~IMAN_IE;
3264 intr->iman |= val & IMAN_IE;
3265 if (v == 0) {
3266 xhci_intx_update(xhci);
3267 }
3268 xhci_msix_update(xhci, v);
3269 break;
3270 case 0x04: /* IMOD */
3271 intr->imod = val;
3272 break;
3273 case 0x08: /* ERSTSZ */
3274 intr->erstsz = val & 0xffff;
3275 break;
3276 case 0x10: /* ERSTBA low */
3277 /* XXX NEC driver bug: it doesn't align this to 64 bytes
3278 intr->erstba_low = val & 0xffffffc0; */
3279 intr->erstba_low = val & 0xfffffff0;
3280 break;
3281 case 0x14: /* ERSTBA high */
3282 intr->erstba_high = val;
3283 xhci_er_reset(xhci, v);
3284 break;
3285 case 0x18: /* ERDP low */
3286 if (val & ERDP_EHB) {
3287 intr->erdp_low &= ~ERDP_EHB;
3288 }
3289 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB);
3290 break;
3291 case 0x1c: /* ERDP high */
3292 intr->erdp_high = val;
3293 xhci_events_update(xhci, v);
3294 break;
3295 default:
3296 trace_usb_xhci_unimplemented("oper write", reg);
3297 }
3298 }
3299
3300 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg,
3301 unsigned size)
3302 {
3303 /* doorbells always read as 0 */
3304 trace_usb_xhci_doorbell_read(reg, 0);
3305 return 0;
3306 }
3307
3308 static void xhci_doorbell_write(void *ptr, hwaddr reg,
3309 uint64_t val, unsigned size)
3310 {
3311 XHCIState *xhci = ptr;
3312 unsigned int epid, streamid;
3313
3314 trace_usb_xhci_doorbell_write(reg, val);
3315
3316 if (!xhci_running(xhci)) {
3317 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n");
3318 return;
3319 }
3320
3321 reg >>= 2;
3322
3323 if (reg == 0) {
3324 if (val == 0) {
3325 xhci_process_commands(xhci);
3326 } else {
3327 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n",
3328 (uint32_t)val);
3329 }
3330 } else {
3331 epid = val & 0xff;
3332 streamid = (val >> 16) & 0xffff;
3333 if (reg > xhci->numslots) {
3334 DPRINTF("xhci: bad doorbell %d\n", (int)reg);
3335 } else if (epid > 31) {
3336 DPRINTF("xhci: bad doorbell %d write: 0x%x\n",
3337 (int)reg, (uint32_t)val);
3338 } else {
3339 xhci_kick_ep(xhci, reg, epid, streamid);
3340 }
3341 }
3342 }
3343
3344 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val,
3345 unsigned width)
3346 {
3347 /* nothing */
3348 }
3349
3350 static const MemoryRegionOps xhci_cap_ops = {
3351 .read = xhci_cap_read,
3352 .write = xhci_cap_write,
3353 .valid.min_access_size = 1,
3354 .valid.max_access_size = 4,
3355 .impl.min_access_size = 4,
3356 .impl.max_access_size = 4,
3357 .endianness = DEVICE_LITTLE_ENDIAN,
3358 };
3359
3360 static const MemoryRegionOps xhci_oper_ops = {
3361 .read = xhci_oper_read,
3362 .write = xhci_oper_write,
3363 .valid.min_access_size = 4,
3364 .valid.max_access_size = 4,
3365 .endianness = DEVICE_LITTLE_ENDIAN,
3366 };
3367
3368 static const MemoryRegionOps xhci_port_ops = {
3369 .read = xhci_port_read,
3370 .write = xhci_port_write,
3371 .valid.min_access_size = 4,
3372 .valid.max_access_size = 4,
3373 .endianness = DEVICE_LITTLE_ENDIAN,
3374 };
3375
3376 static const MemoryRegionOps xhci_runtime_ops = {
3377 .read = xhci_runtime_read,
3378 .write = xhci_runtime_write,
3379 .valid.min_access_size = 4,
3380 .valid.max_access_size = 4,
3381 .endianness = DEVICE_LITTLE_ENDIAN,
3382 };
3383
3384 static const MemoryRegionOps xhci_doorbell_ops = {
3385 .read = xhci_doorbell_read,
3386 .write = xhci_doorbell_write,
3387 .valid.min_access_size = 4,
3388 .valid.max_access_size = 4,
3389 .endianness = DEVICE_LITTLE_ENDIAN,
3390 };
3391
3392 static void xhci_attach(USBPort *usbport)
3393 {
3394 XHCIState *xhci = usbport->opaque;
3395 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3396
3397 xhci_port_update(port, 0);
3398 }
3399
3400 static void xhci_detach(USBPort *usbport)
3401 {
3402 XHCIState *xhci = usbport->opaque;
3403 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3404
3405 xhci_detach_slot(xhci, usbport);
3406 xhci_port_update(port, 1);
3407 }
3408
3409 static void xhci_wakeup(USBPort *usbport)
3410 {
3411 XHCIState *xhci = usbport->opaque;
3412 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3413
3414 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) {
3415 return;
3416 }
3417 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS);
3418 xhci_port_notify(port, PORTSC_PLC);
3419 }
3420
3421 static void xhci_complete(USBPort *port, USBPacket *packet)
3422 {
3423 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
3424
3425 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
3426 xhci_ep_nuke_one_xfer(xfer, 0);
3427 return;
3428 }
3429 xhci_complete_packet(xfer);
3430 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid, xfer->streamid);
3431 }
3432
3433 static void xhci_child_detach(USBPort *uport, USBDevice *child)
3434 {
3435 USBBus *bus = usb_bus_from_device(child);
3436 XHCIState *xhci = container_of(bus, XHCIState, bus);
3437
3438 xhci_detach_slot(xhci, uport);
3439 }
3440
3441 static USBPortOps xhci_uport_ops = {
3442 .attach = xhci_attach,
3443 .detach = xhci_detach,
3444 .wakeup = xhci_wakeup,
3445 .complete = xhci_complete,
3446 .child_detach = xhci_child_detach,
3447 };
3448
3449 static int xhci_find_epid(USBEndpoint *ep)
3450 {
3451 if (ep->nr == 0) {
3452 return 1;
3453 }
3454 if (ep->pid == USB_TOKEN_IN) {
3455 return ep->nr * 2 + 1;
3456 } else {
3457 return ep->nr * 2;
3458 }
3459 }
3460
3461 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci,
3462 unsigned int slotid, unsigned int epid)
3463 {
3464 assert(slotid >= 1 && slotid <= xhci->numslots);
3465
3466 if (!xhci->slots[slotid - 1].uport) {
3467 return NULL;
3468 }
3469
3470 return usb_ep_get(xhci->slots[slotid - 1].uport->dev,
3471 (epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT, epid >> 1);
3472 }
3473
3474 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
3475 unsigned int stream)
3476 {
3477 XHCIState *xhci = container_of(bus, XHCIState, bus);
3478 int slotid;
3479
3480 DPRINTF("%s\n", __func__);
3481 slotid = ep->dev->addr;
3482 if (slotid == 0 || !xhci->slots[slotid-1].enabled) {
3483 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
3484 return;
3485 }
3486 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream);
3487 }
3488
3489 static USBBusOps xhci_bus_ops = {
3490 .wakeup_endpoint = xhci_wakeup_endpoint,
3491 };
3492
3493 static void usb_xhci_init(XHCIState *xhci)
3494 {
3495 DeviceState *dev = DEVICE(xhci);
3496 XHCIPort *port;
3497 int i, usbports, speedmask;
3498
3499 xhci->usbsts = USBSTS_HCH;
3500
3501 if (xhci->numports_2 > MAXPORTS_2) {
3502 xhci->numports_2 = MAXPORTS_2;
3503 }
3504 if (xhci->numports_3 > MAXPORTS_3) {
3505 xhci->numports_3 = MAXPORTS_3;
3506 }
3507 usbports = MAX(xhci->numports_2, xhci->numports_3);
3508 xhci->numports = xhci->numports_2 + xhci->numports_3;
3509
3510 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev);
3511
3512 for (i = 0; i < usbports; i++) {
3513 speedmask = 0;
3514 if (i < xhci->numports_2) {
3515 port = &xhci->ports[i];
3516 port->portnr = i + 1;
3517 port->uport = &xhci->uports[i];
3518 port->speedmask =
3519 USB_SPEED_MASK_LOW |
3520 USB_SPEED_MASK_FULL |
3521 USB_SPEED_MASK_HIGH;
3522 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1);
3523 speedmask |= port->speedmask;
3524 }
3525 if (i < xhci->numports_3) {
3526 port = &xhci->ports[i + xhci->numports_2];
3527 port->portnr = i + 1 + xhci->numports_2;
3528 port->uport = &xhci->uports[i];
3529 port->speedmask = USB_SPEED_MASK_SUPER;
3530 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1);
3531 speedmask |= port->speedmask;
3532 }
3533 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i,
3534 &xhci_uport_ops, speedmask);
3535 }
3536 }
3537
3538 static int usb_xhci_initfn(struct PCIDevice *dev)
3539 {
3540 int i, ret;
3541
3542 XHCIState *xhci = XHCI(dev);
3543
3544 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */
3545 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
3546 dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
3547 dev->config[0x60] = 0x30; /* release number */
3548
3549 usb_xhci_init(xhci);
3550
3551 if (xhci->numintrs > MAXINTRS) {
3552 xhci->numintrs = MAXINTRS;
3553 }
3554 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */
3555 xhci->numintrs++;
3556 }
3557 if (xhci->numintrs < 1) {
3558 xhci->numintrs = 1;
3559 }
3560 if (xhci->numslots > MAXSLOTS) {
3561 xhci->numslots = MAXSLOTS;
3562 }
3563 if (xhci->numslots < 1) {
3564 xhci->numslots = 1;
3565 }
3566
3567 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
3568
3569 memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS);
3570 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci,
3571 "capabilities", LEN_CAP);
3572 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci,
3573 "operational", 0x400);
3574 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci,
3575 "runtime", LEN_RUNTIME);
3576 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci,
3577 "doorbell", LEN_DOORBELL);
3578
3579 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
3580 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper);
3581 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime);
3582 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell);
3583
3584 for (i = 0; i < xhci->numports; i++) {
3585 XHCIPort *port = &xhci->ports[i];
3586 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i;
3587 port->xhci = xhci;
3588 memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port,
3589 port->name, 0x10);
3590 memory_region_add_subregion(&xhci->mem, offset, &port->mem);
3591 }
3592
3593 pci_register_bar(dev, 0,
3594 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
3595 &xhci->mem);
3596
3597 ret = pcie_endpoint_cap_init(dev, 0xa0);
3598 assert(ret >= 0);
3599
3600 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) {
3601 msi_init(dev, 0x70, xhci->numintrs, true, false);
3602 }
3603 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) {
3604 msix_init(dev, xhci->numintrs,
3605 &xhci->mem, 0, OFF_MSIX_TABLE,
3606 &xhci->mem, 0, OFF_MSIX_PBA,
3607 0x90);
3608 }
3609
3610 return 0;
3611 }
3612
3613 static int usb_xhci_post_load(void *opaque, int version_id)
3614 {
3615 XHCIState *xhci = opaque;
3616 PCIDevice *pci_dev = PCI_DEVICE(xhci);
3617 XHCISlot *slot;
3618 XHCIEPContext *epctx;
3619 dma_addr_t dcbaap, pctx;
3620 uint32_t slot_ctx[4];
3621 uint32_t ep_ctx[5];
3622 int slotid, epid, state, intr;
3623
3624 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
3625
3626 for (slotid = 1; slotid <= xhci->numslots; slotid++) {
3627 slot = &xhci->slots[slotid-1];
3628 if (!slot->addressed) {
3629 continue;
3630 }
3631 slot->ctx =
3632 xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid));
3633 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
3634 slot->uport = xhci_lookup_uport(xhci, slot_ctx);
3635 assert(slot->uport && slot->uport->dev);
3636
3637 for (epid = 1; epid <= 31; epid++) {
3638 pctx = slot->ctx + 32 * epid;
3639 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx));
3640 state = ep_ctx[0] & EP_STATE_MASK;
3641 if (state == EP_DISABLED) {
3642 continue;
3643 }
3644 epctx = xhci_alloc_epctx(xhci, slotid, epid);
3645 slot->eps[epid-1] = epctx;
3646 xhci_init_epctx(epctx, pctx, ep_ctx);
3647 epctx->state = state;
3648 if (state == EP_RUNNING) {
3649 /* kick endpoint after vmload is finished */
3650 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
3651 }
3652 }
3653 }
3654
3655 for (intr = 0; intr < xhci->numintrs; intr++) {
3656 if (xhci->intr[intr].msix_used) {
3657 msix_vector_use(pci_dev, intr);
3658 } else {
3659 msix_vector_unuse(pci_dev, intr);
3660 }
3661 }
3662
3663 return 0;
3664 }
3665
3666 static const VMStateDescription vmstate_xhci_ring = {
3667 .name = "xhci-ring",
3668 .version_id = 1,
3669 .fields = (VMStateField[]) {
3670 VMSTATE_UINT64(dequeue, XHCIRing),
3671 VMSTATE_BOOL(ccs, XHCIRing),
3672 VMSTATE_END_OF_LIST()
3673 }
3674 };
3675
3676 static const VMStateDescription vmstate_xhci_port = {
3677 .name = "xhci-port",
3678 .version_id = 1,
3679 .fields = (VMStateField[]) {
3680 VMSTATE_UINT32(portsc, XHCIPort),
3681 VMSTATE_END_OF_LIST()
3682 }
3683 };
3684
3685 static const VMStateDescription vmstate_xhci_slot = {
3686 .name = "xhci-slot",
3687 .version_id = 1,
3688 .fields = (VMStateField[]) {
3689 VMSTATE_BOOL(enabled, XHCISlot),
3690 VMSTATE_BOOL(addressed, XHCISlot),
3691 VMSTATE_END_OF_LIST()
3692 }
3693 };
3694
3695 static const VMStateDescription vmstate_xhci_event = {
3696 .name = "xhci-event",
3697 .version_id = 1,
3698 .fields = (VMStateField[]) {
3699 VMSTATE_UINT32(type, XHCIEvent),
3700 VMSTATE_UINT32(ccode, XHCIEvent),
3701 VMSTATE_UINT64(ptr, XHCIEvent),
3702 VMSTATE_UINT32(length, XHCIEvent),
3703 VMSTATE_UINT32(flags, XHCIEvent),
3704 VMSTATE_UINT8(slotid, XHCIEvent),
3705 VMSTATE_UINT8(epid, XHCIEvent),
3706 }
3707 };
3708
3709 static bool xhci_er_full(void *opaque, int version_id)
3710 {
3711 struct XHCIInterrupter *intr = opaque;
3712 return intr->er_full;
3713 }
3714
3715 static const VMStateDescription vmstate_xhci_intr = {
3716 .name = "xhci-intr",
3717 .version_id = 1,
3718 .fields = (VMStateField[]) {
3719 /* registers */
3720 VMSTATE_UINT32(iman, XHCIInterrupter),
3721 VMSTATE_UINT32(imod, XHCIInterrupter),
3722 VMSTATE_UINT32(erstsz, XHCIInterrupter),
3723 VMSTATE_UINT32(erstba_low, XHCIInterrupter),
3724 VMSTATE_UINT32(erstba_high, XHCIInterrupter),
3725 VMSTATE_UINT32(erdp_low, XHCIInterrupter),
3726 VMSTATE_UINT32(erdp_high, XHCIInterrupter),
3727
3728 /* state */
3729 VMSTATE_BOOL(msix_used, XHCIInterrupter),
3730 VMSTATE_BOOL(er_pcs, XHCIInterrupter),
3731 VMSTATE_UINT64(er_start, XHCIInterrupter),
3732 VMSTATE_UINT32(er_size, XHCIInterrupter),
3733 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter),
3734
3735 /* event queue (used if ring is full) */
3736 VMSTATE_BOOL(er_full, XHCIInterrupter),
3737 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full),
3738 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full),
3739 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE,
3740 xhci_er_full, 1,
3741 vmstate_xhci_event, XHCIEvent),
3742
3743 VMSTATE_END_OF_LIST()
3744 }
3745 };
3746
3747 static const VMStateDescription vmstate_xhci = {
3748 .name = "xhci",
3749 .version_id = 1,
3750 .post_load = usb_xhci_post_load,
3751 .fields = (VMStateField[]) {
3752 VMSTATE_PCIE_DEVICE(parent_obj, XHCIState),
3753 VMSTATE_MSIX(parent_obj, XHCIState),
3754
3755 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
3756 vmstate_xhci_port, XHCIPort),
3757 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1,
3758 vmstate_xhci_slot, XHCISlot),
3759 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1,
3760 vmstate_xhci_intr, XHCIInterrupter),
3761
3762 /* Operational Registers */
3763 VMSTATE_UINT32(usbcmd, XHCIState),
3764 VMSTATE_UINT32(usbsts, XHCIState),
3765 VMSTATE_UINT32(dnctrl, XHCIState),
3766 VMSTATE_UINT32(crcr_low, XHCIState),
3767 VMSTATE_UINT32(crcr_high, XHCIState),
3768 VMSTATE_UINT32(dcbaap_low, XHCIState),
3769 VMSTATE_UINT32(dcbaap_high, XHCIState),
3770 VMSTATE_UINT32(config, XHCIState),
3771
3772 /* Runtime Registers & state */
3773 VMSTATE_INT64(mfindex_start, XHCIState),
3774 VMSTATE_TIMER(mfwrap_timer, XHCIState),
3775 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing),
3776
3777 VMSTATE_END_OF_LIST()
3778 }
3779 };
3780
3781 static Property xhci_properties[] = {
3782 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true),
3783 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true),
3784 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS),
3785 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS),
3786 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),
3787 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4),
3788 DEFINE_PROP_END_OF_LIST(),
3789 };
3790
3791 static void xhci_class_init(ObjectClass *klass, void *data)
3792 {
3793 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3794 DeviceClass *dc = DEVICE_CLASS(klass);
3795
3796 dc->vmsd = &vmstate_xhci;
3797 dc->props = xhci_properties;
3798 dc->reset = xhci_reset;
3799 dc->hotpluggable = false;
3800 set_bit(DEVICE_CATEGORY_USB, dc->categories);
3801 k->init = usb_xhci_initfn;
3802 k->vendor_id = PCI_VENDOR_ID_NEC;
3803 k->device_id = PCI_DEVICE_ID_NEC_UPD720200;
3804 k->class_id = PCI_CLASS_SERIAL_USB;
3805 k->revision = 0x03;
3806 k->is_express = 1;
3807 }
3808
3809 static const TypeInfo xhci_info = {
3810 .name = TYPE_XHCI,
3811 .parent = TYPE_PCI_DEVICE,
3812 .instance_size = sizeof(XHCIState),
3813 .class_init = xhci_class_init,
3814 };
3815
3816 static void xhci_register_types(void)
3817 {
3818 type_register_static(&xhci_info);
3819 }
3820
3821 type_init(xhci_register_types)
Random patches