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sysemu.h: Document what MAX_CPUMASK_BITS really limits
[qemu/kevin.git] / hw / net / lan9118.c
blobe528290b41ded1b5f8f7df2a4203ffee63672220
1 /*
2 * SMSC LAN9118 Ethernet interface emulation
3 *
4 * Copyright (c) 2009 CodeSourcery, LLC.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the GNU GPL v2
8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
11 */
12
13 #include "hw/sysbus.h"
14 #include "net/net.h"
15 #include "hw/devices.h"
16 #include "sysemu/sysemu.h"
17 #include "hw/ptimer.h"
18 /* For crc32 */
19 #include <zlib.h>
20
21 //#define DEBUG_LAN9118
22
23 #ifdef DEBUG_LAN9118
24 #define DPRINTF(fmt, ...) \
25 do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
26 #define BADF(fmt, ...) \
27 do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
28 #else
29 #define DPRINTF(fmt, ...) do {} while(0)
30 #define BADF(fmt, ...) \
31 do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
32 #endif
33
34 #define CSR_ID_REV 0x50
35 #define CSR_IRQ_CFG 0x54
36 #define CSR_INT_STS 0x58
37 #define CSR_INT_EN 0x5c
38 #define CSR_BYTE_TEST 0x64
39 #define CSR_FIFO_INT 0x68
40 #define CSR_RX_CFG 0x6c
41 #define CSR_TX_CFG 0x70
42 #define CSR_HW_CFG 0x74
43 #define CSR_RX_DP_CTRL 0x78
44 #define CSR_RX_FIFO_INF 0x7c
45 #define CSR_TX_FIFO_INF 0x80
46 #define CSR_PMT_CTRL 0x84
47 #define CSR_GPIO_CFG 0x88
48 #define CSR_GPT_CFG 0x8c
49 #define CSR_GPT_CNT 0x90
50 #define CSR_WORD_SWAP 0x98
51 #define CSR_FREE_RUN 0x9c
52 #define CSR_RX_DROP 0xa0
53 #define CSR_MAC_CSR_CMD 0xa4
54 #define CSR_MAC_CSR_DATA 0xa8
55 #define CSR_AFC_CFG 0xac
56 #define CSR_E2P_CMD 0xb0
57 #define CSR_E2P_DATA 0xb4
58
59 /* IRQ_CFG */
60 #define IRQ_INT 0x00001000
61 #define IRQ_EN 0x00000100
62 #define IRQ_POL 0x00000010
63 #define IRQ_TYPE 0x00000001
64
65 /* INT_STS/INT_EN */
66 #define SW_INT 0x80000000
67 #define TXSTOP_INT 0x02000000
68 #define RXSTOP_INT 0x01000000
69 #define RXDFH_INT 0x00800000
70 #define TX_IOC_INT 0x00200000
71 #define RXD_INT 0x00100000
72 #define GPT_INT 0x00080000
73 #define PHY_INT 0x00040000
74 #define PME_INT 0x00020000
75 #define TXSO_INT 0x00010000
76 #define RWT_INT 0x00008000
77 #define RXE_INT 0x00004000
78 #define TXE_INT 0x00002000
79 #define TDFU_INT 0x00000800
80 #define TDFO_INT 0x00000400
81 #define TDFA_INT 0x00000200
82 #define TSFF_INT 0x00000100
83 #define TSFL_INT 0x00000080
84 #define RXDF_INT 0x00000040
85 #define RDFL_INT 0x00000020
86 #define RSFF_INT 0x00000010
87 #define RSFL_INT 0x00000008
88 #define GPIO2_INT 0x00000004
89 #define GPIO1_INT 0x00000002
90 #define GPIO0_INT 0x00000001
91 #define RESERVED_INT 0x7c001000
92
93 #define MAC_CR 1
94 #define MAC_ADDRH 2
95 #define MAC_ADDRL 3
96 #define MAC_HASHH 4
97 #define MAC_HASHL 5
98 #define MAC_MII_ACC 6
99 #define MAC_MII_DATA 7
100 #define MAC_FLOW 8
101 #define MAC_VLAN1 9 /* TODO */
102 #define MAC_VLAN2 10 /* TODO */
103 #define MAC_WUFF 11 /* TODO */
104 #define MAC_WUCSR 12 /* TODO */
105
106 #define MAC_CR_RXALL 0x80000000
107 #define MAC_CR_RCVOWN 0x00800000
108 #define MAC_CR_LOOPBK 0x00200000
109 #define MAC_CR_FDPX 0x00100000
110 #define MAC_CR_MCPAS 0x00080000
111 #define MAC_CR_PRMS 0x00040000
112 #define MAC_CR_INVFILT 0x00020000
113 #define MAC_CR_PASSBAD 0x00010000
114 #define MAC_CR_HO 0x00008000
115 #define MAC_CR_HPFILT 0x00002000
116 #define MAC_CR_LCOLL 0x00001000
117 #define MAC_CR_BCAST 0x00000800
118 #define MAC_CR_DISRTY 0x00000400
119 #define MAC_CR_PADSTR 0x00000100
120 #define MAC_CR_BOLMT 0x000000c0
121 #define MAC_CR_DFCHK 0x00000020
122 #define MAC_CR_TXEN 0x00000008
123 #define MAC_CR_RXEN 0x00000004
124 #define MAC_CR_RESERVED 0x7f404213
125
126 #define PHY_INT_ENERGYON 0x80
127 #define PHY_INT_AUTONEG_COMPLETE 0x40
128 #define PHY_INT_FAULT 0x20
129 #define PHY_INT_DOWN 0x10
130 #define PHY_INT_AUTONEG_LP 0x08
131 #define PHY_INT_PARFAULT 0x04
132 #define PHY_INT_AUTONEG_PAGE 0x02
133
134 #define GPT_TIMER_EN 0x20000000
135
136 enum tx_state {
137 TX_IDLE,
138 TX_B,
139 TX_DATA
140 };
141
142 typedef struct {
143 /* state is a tx_state but we can't put enums in VMStateDescriptions. */
144 uint32_t state;
145 uint32_t cmd_a;
146 uint32_t cmd_b;
147 int32_t buffer_size;
148 int32_t offset;
149 int32_t pad;
150 int32_t fifo_used;
151 int32_t len;
152 uint8_t data[2048];
153 } LAN9118Packet;
154
155 static const VMStateDescription vmstate_lan9118_packet = {
156 .name = "lan9118_packet",
157 .version_id = 1,
158 .minimum_version_id = 1,
159 .fields = (VMStateField[]) {
160 VMSTATE_UINT32(state, LAN9118Packet),
161 VMSTATE_UINT32(cmd_a, LAN9118Packet),
162 VMSTATE_UINT32(cmd_b, LAN9118Packet),
163 VMSTATE_INT32(buffer_size, LAN9118Packet),
164 VMSTATE_INT32(offset, LAN9118Packet),
165 VMSTATE_INT32(pad, LAN9118Packet),
166 VMSTATE_INT32(fifo_used, LAN9118Packet),
167 VMSTATE_INT32(len, LAN9118Packet),
168 VMSTATE_UINT8_ARRAY(data, LAN9118Packet, 2048),
169 VMSTATE_END_OF_LIST()
170 }
171 };
172
173 #define TYPE_LAN9118 "lan9118"
174 #define LAN9118(obj) OBJECT_CHECK(lan9118_state, (obj), TYPE_LAN9118)
175
176 typedef struct {
177 SysBusDevice parent_obj;
178
179 NICState *nic;
180 NICConf conf;
181 qemu_irq irq;
182 MemoryRegion mmio;
183 ptimer_state *timer;
184
185 uint32_t irq_cfg;
186 uint32_t int_sts;
187 uint32_t int_en;
188 uint32_t fifo_int;
189 uint32_t rx_cfg;
190 uint32_t tx_cfg;
191 uint32_t hw_cfg;
192 uint32_t pmt_ctrl;
193 uint32_t gpio_cfg;
194 uint32_t gpt_cfg;
195 uint32_t word_swap;
196 uint32_t free_timer_start;
197 uint32_t mac_cmd;
198 uint32_t mac_data;
199 uint32_t afc_cfg;
200 uint32_t e2p_cmd;
201 uint32_t e2p_data;
202
203 uint32_t mac_cr;
204 uint32_t mac_hashh;
205 uint32_t mac_hashl;
206 uint32_t mac_mii_acc;
207 uint32_t mac_mii_data;
208 uint32_t mac_flow;
209
210 uint32_t phy_status;
211 uint32_t phy_control;
212 uint32_t phy_advertise;
213 uint32_t phy_int;
214 uint32_t phy_int_mask;
215
216 int32_t eeprom_writable;
217 uint8_t eeprom[128];
218
219 int32_t tx_fifo_size;
220 LAN9118Packet *txp;
221 LAN9118Packet tx_packet;
222
223 int32_t tx_status_fifo_used;
224 int32_t tx_status_fifo_head;
225 uint32_t tx_status_fifo[512];
226
227 int32_t rx_status_fifo_size;
228 int32_t rx_status_fifo_used;
229 int32_t rx_status_fifo_head;
230 uint32_t rx_status_fifo[896];
231 int32_t rx_fifo_size;
232 int32_t rx_fifo_used;
233 int32_t rx_fifo_head;
234 uint32_t rx_fifo[3360];
235 int32_t rx_packet_size_head;
236 int32_t rx_packet_size_tail;
237 int32_t rx_packet_size[1024];
238
239 int32_t rxp_offset;
240 int32_t rxp_size;
241 int32_t rxp_pad;
242
243 uint32_t write_word_prev_offset;
244 uint32_t write_word_n;
245 uint16_t write_word_l;
246 uint16_t write_word_h;
247 uint32_t read_word_prev_offset;
248 uint32_t read_word_n;
249 uint32_t read_long;
250
251 uint32_t mode_16bit;
252 } lan9118_state;
253
254 static const VMStateDescription vmstate_lan9118 = {
255 .name = "lan9118",
256 .version_id = 2,
257 .minimum_version_id = 1,
258 .fields = (VMStateField[]) {
259 VMSTATE_PTIMER(timer, lan9118_state),
260 VMSTATE_UINT32(irq_cfg, lan9118_state),
261 VMSTATE_UINT32(int_sts, lan9118_state),
262 VMSTATE_UINT32(int_en, lan9118_state),
263 VMSTATE_UINT32(fifo_int, lan9118_state),
264 VMSTATE_UINT32(rx_cfg, lan9118_state),
265 VMSTATE_UINT32(tx_cfg, lan9118_state),
266 VMSTATE_UINT32(hw_cfg, lan9118_state),
267 VMSTATE_UINT32(pmt_ctrl, lan9118_state),
268 VMSTATE_UINT32(gpio_cfg, lan9118_state),
269 VMSTATE_UINT32(gpt_cfg, lan9118_state),
270 VMSTATE_UINT32(word_swap, lan9118_state),
271 VMSTATE_UINT32(free_timer_start, lan9118_state),
272 VMSTATE_UINT32(mac_cmd, lan9118_state),
273 VMSTATE_UINT32(mac_data, lan9118_state),
274 VMSTATE_UINT32(afc_cfg, lan9118_state),
275 VMSTATE_UINT32(e2p_cmd, lan9118_state),
276 VMSTATE_UINT32(e2p_data, lan9118_state),
277 VMSTATE_UINT32(mac_cr, lan9118_state),
278 VMSTATE_UINT32(mac_hashh, lan9118_state),
279 VMSTATE_UINT32(mac_hashl, lan9118_state),
280 VMSTATE_UINT32(mac_mii_acc, lan9118_state),
281 VMSTATE_UINT32(mac_mii_data, lan9118_state),
282 VMSTATE_UINT32(mac_flow, lan9118_state),
283 VMSTATE_UINT32(phy_status, lan9118_state),
284 VMSTATE_UINT32(phy_control, lan9118_state),
285 VMSTATE_UINT32(phy_advertise, lan9118_state),
286 VMSTATE_UINT32(phy_int, lan9118_state),
287 VMSTATE_UINT32(phy_int_mask, lan9118_state),
288 VMSTATE_INT32(eeprom_writable, lan9118_state),
289 VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
290 VMSTATE_INT32(tx_fifo_size, lan9118_state),
291 /* txp always points at tx_packet so need not be saved */
292 VMSTATE_STRUCT(tx_packet, lan9118_state, 0,
293 vmstate_lan9118_packet, LAN9118Packet),
294 VMSTATE_INT32(tx_status_fifo_used, lan9118_state),
295 VMSTATE_INT32(tx_status_fifo_head, lan9118_state),
296 VMSTATE_UINT32_ARRAY(tx_status_fifo, lan9118_state, 512),
297 VMSTATE_INT32(rx_status_fifo_size, lan9118_state),
298 VMSTATE_INT32(rx_status_fifo_used, lan9118_state),
299 VMSTATE_INT32(rx_status_fifo_head, lan9118_state),
300 VMSTATE_UINT32_ARRAY(rx_status_fifo, lan9118_state, 896),
301 VMSTATE_INT32(rx_fifo_size, lan9118_state),
302 VMSTATE_INT32(rx_fifo_used, lan9118_state),
303 VMSTATE_INT32(rx_fifo_head, lan9118_state),
304 VMSTATE_UINT32_ARRAY(rx_fifo, lan9118_state, 3360),
305 VMSTATE_INT32(rx_packet_size_head, lan9118_state),
306 VMSTATE_INT32(rx_packet_size_tail, lan9118_state),
307 VMSTATE_INT32_ARRAY(rx_packet_size, lan9118_state, 1024),
308 VMSTATE_INT32(rxp_offset, lan9118_state),
309 VMSTATE_INT32(rxp_size, lan9118_state),
310 VMSTATE_INT32(rxp_pad, lan9118_state),
311 VMSTATE_UINT32_V(write_word_prev_offset, lan9118_state, 2),
312 VMSTATE_UINT32_V(write_word_n, lan9118_state, 2),
313 VMSTATE_UINT16_V(write_word_l, lan9118_state, 2),
314 VMSTATE_UINT16_V(write_word_h, lan9118_state, 2),
315 VMSTATE_UINT32_V(read_word_prev_offset, lan9118_state, 2),
316 VMSTATE_UINT32_V(read_word_n, lan9118_state, 2),
317 VMSTATE_UINT32_V(read_long, lan9118_state, 2),
318 VMSTATE_UINT32_V(mode_16bit, lan9118_state, 2),
319 VMSTATE_END_OF_LIST()
320 }
321 };
322
323 static void lan9118_update(lan9118_state *s)
324 {
325 int level;
326
327 /* TODO: Implement FIFO level IRQs. */
328 level = (s->int_sts & s->int_en) != 0;
329 if (level) {
330 s->irq_cfg |= IRQ_INT;
331 } else {
332 s->irq_cfg &= ~IRQ_INT;
333 }
334 if ((s->irq_cfg & IRQ_EN) == 0) {
335 level = 0;
336 }
337 if ((s->irq_cfg & (IRQ_TYPE | IRQ_POL)) != (IRQ_TYPE | IRQ_POL)) {
338 /* Interrupt is active low unless we're configured as
339 * active-high polarity, push-pull type.
340 */
341 level = !level;
342 }
343 qemu_set_irq(s->irq, level);
344 }
345
346 static void lan9118_mac_changed(lan9118_state *s)
347 {
348 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
349 }
350
351 static void lan9118_reload_eeprom(lan9118_state *s)
352 {
353 int i;
354 if (s->eeprom[0] != 0xa5) {
355 s->e2p_cmd &= ~0x10;
356 DPRINTF("MACADDR load failed\n");
357 return;
358 }
359 for (i = 0; i < 6; i++) {
360 s->conf.macaddr.a[i] = s->eeprom[i + 1];
361 }
362 s->e2p_cmd |= 0x10;
363 DPRINTF("MACADDR loaded from eeprom\n");
364 lan9118_mac_changed(s);
365 }
366
367 static void phy_update_irq(lan9118_state *s)
368 {
369 if (s->phy_int & s->phy_int_mask) {
370 s->int_sts |= PHY_INT;
371 } else {
372 s->int_sts &= ~PHY_INT;
373 }
374 lan9118_update(s);
375 }
376
377 static void phy_update_link(lan9118_state *s)
378 {
379 /* Autonegotiation status mirrors link status. */
380 if (qemu_get_queue(s->nic)->link_down) {
381 s->phy_status &= ~0x0024;
382 s->phy_int |= PHY_INT_DOWN;
383 } else {
384 s->phy_status |= 0x0024;
385 s->phy_int |= PHY_INT_ENERGYON;
386 s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
387 }
388 phy_update_irq(s);
389 }
390
391 static void lan9118_set_link(NetClientState *nc)
392 {
393 phy_update_link(qemu_get_nic_opaque(nc));
394 }
395
396 static void phy_reset(lan9118_state *s)
397 {
398 s->phy_status = 0x7809;
399 s->phy_control = 0x3000;
400 s->phy_advertise = 0x01e1;
401 s->phy_int_mask = 0;
402 s->phy_int = 0;
403 phy_update_link(s);
404 }
405
406 static void lan9118_reset(DeviceState *d)
407 {
408 lan9118_state *s = LAN9118(d);
409
410 s->irq_cfg &= (IRQ_TYPE | IRQ_POL);
411 s->int_sts = 0;
412 s->int_en = 0;
413 s->fifo_int = 0x48000000;
414 s->rx_cfg = 0;
415 s->tx_cfg = 0;
416 s->hw_cfg = s->mode_16bit ? 0x00050000 : 0x00050004;
417 s->pmt_ctrl &= 0x45;
418 s->gpio_cfg = 0;
419 s->txp->fifo_used = 0;
420 s->txp->state = TX_IDLE;
421 s->txp->cmd_a = 0xffffffffu;
422 s->txp->cmd_b = 0xffffffffu;
423 s->txp->len = 0;
424 s->txp->fifo_used = 0;
425 s->tx_fifo_size = 4608;
426 s->tx_status_fifo_used = 0;
427 s->rx_status_fifo_size = 704;
428 s->rx_fifo_size = 2640;
429 s->rx_fifo_used = 0;
430 s->rx_status_fifo_size = 176;
431 s->rx_status_fifo_used = 0;
432 s->rxp_offset = 0;
433 s->rxp_size = 0;
434 s->rxp_pad = 0;
435 s->rx_packet_size_tail = s->rx_packet_size_head;
436 s->rx_packet_size[s->rx_packet_size_head] = 0;
437 s->mac_cmd = 0;
438 s->mac_data = 0;
439 s->afc_cfg = 0;
440 s->e2p_cmd = 0;
441 s->e2p_data = 0;
442 s->free_timer_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 40;
443
444 ptimer_stop(s->timer);
445 ptimer_set_count(s->timer, 0xffff);
446 s->gpt_cfg = 0xffff;
447
448 s->mac_cr = MAC_CR_PRMS;
449 s->mac_hashh = 0;
450 s->mac_hashl = 0;
451 s->mac_mii_acc = 0;
452 s->mac_mii_data = 0;
453 s->mac_flow = 0;
454
455 s->read_word_n = 0;
456 s->write_word_n = 0;
457
458 phy_reset(s);
459
460 s->eeprom_writable = 0;
461 lan9118_reload_eeprom(s);
462 }
463
464 static int lan9118_can_receive(NetClientState *nc)
465 {
466 return 1;
467 }
468
469 static void rx_fifo_push(lan9118_state *s, uint32_t val)
470 {
471 int fifo_pos;
472 fifo_pos = s->rx_fifo_head + s->rx_fifo_used;
473 if (fifo_pos >= s->rx_fifo_size)
474 fifo_pos -= s->rx_fifo_size;
475 s->rx_fifo[fifo_pos] = val;
476 s->rx_fifo_used++;
477 }
478
479 /* Return nonzero if the packet is accepted by the filter. */
480 static int lan9118_filter(lan9118_state *s, const uint8_t *addr)
481 {
482 int multicast;
483 uint32_t hash;
484
485 if (s->mac_cr & MAC_CR_PRMS) {
486 return 1;
487 }
488 if (addr[0] == 0xff && addr[1] == 0xff && addr[2] == 0xff &&
489 addr[3] == 0xff && addr[4] == 0xff && addr[5] == 0xff) {
490 return (s->mac_cr & MAC_CR_BCAST) == 0;
491 }
492
493 multicast = addr[0] & 1;
494 if (multicast &&s->mac_cr & MAC_CR_MCPAS) {
495 return 1;
496 }
497 if (multicast ? (s->mac_cr & MAC_CR_HPFILT) == 0
498 : (s->mac_cr & MAC_CR_HO) == 0) {
499 /* Exact matching. */
500 hash = memcmp(addr, s->conf.macaddr.a, 6);
501 if (s->mac_cr & MAC_CR_INVFILT) {
502 return hash != 0;
503 } else {
504 return hash == 0;
505 }
506 } else {
507 /* Hash matching */
508 hash = compute_mcast_idx(addr);
509 if (hash & 0x20) {
510 return (s->mac_hashh >> (hash & 0x1f)) & 1;
511 } else {
512 return (s->mac_hashl >> (hash & 0x1f)) & 1;
513 }
514 }
515 }
516
517 static ssize_t lan9118_receive(NetClientState *nc, const uint8_t *buf,
518 size_t size)
519 {
520 lan9118_state *s = qemu_get_nic_opaque(nc);
521 int fifo_len;
522 int offset;
523 int src_pos;
524 int n;
525 int filter;
526 uint32_t val;
527 uint32_t crc;
528 uint32_t status;
529
530 if ((s->mac_cr & MAC_CR_RXEN) == 0) {
531 return -1;
532 }
533
534 if (size >= 2048 || size < 14) {
535 return -1;
536 }
537
538 /* TODO: Implement FIFO overflow notification. */
539 if (s->rx_status_fifo_used == s->rx_status_fifo_size) {
540 return -1;
541 }
542
543 filter = lan9118_filter(s, buf);
544 if (!filter && (s->mac_cr & MAC_CR_RXALL) == 0) {
545 return size;
546 }
547
548 offset = (s->rx_cfg >> 8) & 0x1f;
549 n = offset & 3;
550 fifo_len = (size + n + 3) >> 2;
551 /* Add a word for the CRC. */
552 fifo_len++;
553 if (s->rx_fifo_size - s->rx_fifo_used < fifo_len) {
554 return -1;
555 }
556
557 DPRINTF("Got packet len:%d fifo:%d filter:%s\n",
558 (int)size, fifo_len, filter ? "pass" : "fail");
559 val = 0;
560 crc = bswap32(crc32(~0, buf, size));
561 for (src_pos = 0; src_pos < size; src_pos++) {
562 val = (val >> 8) | ((uint32_t)buf[src_pos] << 24);
563 n++;
564 if (n == 4) {
565 n = 0;
566 rx_fifo_push(s, val);
567 val = 0;
568 }
569 }
570 if (n) {
571 val >>= ((4 - n) * 8);
572 val |= crc << (n * 8);
573 rx_fifo_push(s, val);
574 val = crc >> ((4 - n) * 8);
575 rx_fifo_push(s, val);
576 } else {
577 rx_fifo_push(s, crc);
578 }
579 n = s->rx_status_fifo_head + s->rx_status_fifo_used;
580 if (n >= s->rx_status_fifo_size) {
581 n -= s->rx_status_fifo_size;
582 }
583 s->rx_packet_size[s->rx_packet_size_tail] = fifo_len;
584 s->rx_packet_size_tail = (s->rx_packet_size_tail + 1023) & 1023;
585 s->rx_status_fifo_used++;
586
587 status = (size + 4) << 16;
588 if (buf[0] == 0xff && buf[1] == 0xff && buf[2] == 0xff &&
589 buf[3] == 0xff && buf[4] == 0xff && buf[5] == 0xff) {
590 status |= 0x00002000;
591 } else if (buf[0] & 1) {
592 status |= 0x00000400;
593 }
594 if (!filter) {
595 status |= 0x40000000;
596 }
597 s->rx_status_fifo[n] = status;
598
599 if (s->rx_status_fifo_used > (s->fifo_int & 0xff)) {
600 s->int_sts |= RSFL_INT;
601 }
602 lan9118_update(s);
603
604 return size;
605 }
606
607 static uint32_t rx_fifo_pop(lan9118_state *s)
608 {
609 int n;
610 uint32_t val;
611
612 if (s->rxp_size == 0 && s->rxp_pad == 0) {
613 s->rxp_size = s->rx_packet_size[s->rx_packet_size_head];
614 s->rx_packet_size[s->rx_packet_size_head] = 0;
615 if (s->rxp_size != 0) {
616 s->rx_packet_size_head = (s->rx_packet_size_head + 1023) & 1023;
617 s->rxp_offset = (s->rx_cfg >> 10) & 7;
618 n = s->rxp_offset + s->rxp_size;
619 switch (s->rx_cfg >> 30) {
620 case 1:
621 n = (-n) & 3;
622 break;
623 case 2:
624 n = (-n) & 7;
625 break;
626 default:
627 n = 0;
628 break;
629 }
630 s->rxp_pad = n;
631 DPRINTF("Pop packet size:%d offset:%d pad: %d\n",
632 s->rxp_size, s->rxp_offset, s->rxp_pad);
633 }
634 }
635 if (s->rxp_offset > 0) {
636 s->rxp_offset--;
637 val = 0;
638 } else if (s->rxp_size > 0) {
639 s->rxp_size--;
640 val = s->rx_fifo[s->rx_fifo_head++];
641 if (s->rx_fifo_head >= s->rx_fifo_size) {
642 s->rx_fifo_head -= s->rx_fifo_size;
643 }
644 s->rx_fifo_used--;
645 } else if (s->rxp_pad > 0) {
646 s->rxp_pad--;
647 val = 0;
648 } else {
649 DPRINTF("RX underflow\n");
650 s->int_sts |= RXE_INT;
651 val = 0;
652 }
653 lan9118_update(s);
654 return val;
655 }
656
657 static void do_tx_packet(lan9118_state *s)
658 {
659 int n;
660 uint32_t status;
661
662 /* FIXME: Honor TX disable, and allow queueing of packets. */
663 if (s->phy_control & 0x4000) {
664 /* This assumes the receive routine doesn't touch the VLANClient. */
665 lan9118_receive(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
666 } else {
667 qemu_send_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
668 }
669 s->txp->fifo_used = 0;
670
671 if (s->tx_status_fifo_used == 512) {
672 /* Status FIFO full */
673 return;
674 }
675 /* Add entry to status FIFO. */
676 status = s->txp->cmd_b & 0xffff0000u;
677 DPRINTF("Sent packet tag:%04x len %d\n", status >> 16, s->txp->len);
678 n = (s->tx_status_fifo_head + s->tx_status_fifo_used) & 511;
679 s->tx_status_fifo[n] = status;
680 s->tx_status_fifo_used++;
681 if (s->tx_status_fifo_used == 512) {
682 s->int_sts |= TSFF_INT;
683 /* TODO: Stop transmission. */
684 }
685 }
686
687 static uint32_t rx_status_fifo_pop(lan9118_state *s)
688 {
689 uint32_t val;
690
691 val = s->rx_status_fifo[s->rx_status_fifo_head];
692 if (s->rx_status_fifo_used != 0) {
693 s->rx_status_fifo_used--;
694 s->rx_status_fifo_head++;
695 if (s->rx_status_fifo_head >= s->rx_status_fifo_size) {
696 s->rx_status_fifo_head -= s->rx_status_fifo_size;
697 }
698 /* ??? What value should be returned when the FIFO is empty? */
699 DPRINTF("RX status pop 0x%08x\n", val);
700 }
701 return val;
702 }
703
704 static uint32_t tx_status_fifo_pop(lan9118_state *s)
705 {
706 uint32_t val;
707
708 val = s->tx_status_fifo[s->tx_status_fifo_head];
709 if (s->tx_status_fifo_used != 0) {
710 s->tx_status_fifo_used--;
711 s->tx_status_fifo_head = (s->tx_status_fifo_head + 1) & 511;
712 /* ??? What value should be returned when the FIFO is empty? */
713 }
714 return val;
715 }
716
717 static void tx_fifo_push(lan9118_state *s, uint32_t val)
718 {
719 int n;
720
721 if (s->txp->fifo_used == s->tx_fifo_size) {
722 s->int_sts |= TDFO_INT;
723 return;
724 }
725 switch (s->txp->state) {
726 case TX_IDLE:
727 s->txp->cmd_a = val & 0x831f37ff;
728 s->txp->fifo_used++;
729 s->txp->state = TX_B;
730 s->txp->buffer_size = extract32(s->txp->cmd_a, 0, 11);
731 s->txp->offset = extract32(s->txp->cmd_a, 16, 5);
732 break;
733 case TX_B:
734 if (s->txp->cmd_a & 0x2000) {
735 /* First segment */
736 s->txp->cmd_b = val;
737 s->txp->fifo_used++;
738 /* End alignment does not include command words. */
739 n = (s->txp->buffer_size + s->txp->offset + 3) >> 2;
740 switch ((n >> 24) & 3) {
741 case 1:
742 n = (-n) & 3;
743 break;
744 case 2:
745 n = (-n) & 7;
746 break;
747 default:
748 n = 0;
749 }
750 s->txp->pad = n;
751 s->txp->len = 0;
752 }
753 DPRINTF("Block len:%d offset:%d pad:%d cmd %08x\n",
754 s->txp->buffer_size, s->txp->offset, s->txp->pad,
755 s->txp->cmd_a);
756 s->txp->state = TX_DATA;
757 break;
758 case TX_DATA:
759 if (s->txp->offset >= 4) {
760 s->txp->offset -= 4;
761 break;
762 }
763 if (s->txp->buffer_size <= 0 && s->txp->pad != 0) {
764 s->txp->pad--;
765 } else {
766 n = MIN(4, s->txp->buffer_size + s->txp->offset);
767 while (s->txp->offset) {
768 val >>= 8;
769 n--;
770 s->txp->offset--;
771 }
772 /* Documentation is somewhat unclear on the ordering of bytes
773 in FIFO words. Empirical results show it to be little-endian.
774 */
775 /* TODO: FIFO overflow checking. */
776 while (n--) {
777 s->txp->data[s->txp->len] = val & 0xff;
778 s->txp->len++;
779 val >>= 8;
780 s->txp->buffer_size--;
781 }
782 s->txp->fifo_used++;
783 }
784 if (s->txp->buffer_size <= 0 && s->txp->pad == 0) {
785 if (s->txp->cmd_a & 0x1000) {
786 do_tx_packet(s);
787 }
788 if (s->txp->cmd_a & 0x80000000) {
789 s->int_sts |= TX_IOC_INT;
790 }
791 s->txp->state = TX_IDLE;
792 }
793 break;
794 }
795 }
796
797 static uint32_t do_phy_read(lan9118_state *s, int reg)
798 {
799 uint32_t val;
800
801 switch (reg) {
802 case 0: /* Basic Control */
803 return s->phy_control;
804 case 1: /* Basic Status */
805 return s->phy_status;
806 case 2: /* ID1 */
807 return 0x0007;
808 case 3: /* ID2 */
809 return 0xc0d1;
810 case 4: /* Auto-neg advertisement */
811 return s->phy_advertise;
812 case 5: /* Auto-neg Link Partner Ability */
813 return 0x0f71;
814 case 6: /* Auto-neg Expansion */
815 return 1;
816 /* TODO 17, 18, 27, 29, 30, 31 */
817 case 29: /* Interrupt source. */
818 val = s->phy_int;
819 s->phy_int = 0;
820 phy_update_irq(s);
821 return val;
822 case 30: /* Interrupt mask */
823 return s->phy_int_mask;
824 default:
825 BADF("PHY read reg %d\n", reg);
826 return 0;
827 }
828 }
829
830 static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
831 {
832 switch (reg) {
833 case 0: /* Basic Control */
834 if (val & 0x8000) {
835 phy_reset(s);
836 break;
837 }
838 s->phy_control = val & 0x7980;
839 /* Complete autonegotiation immediately. */
840 if (val & 0x1000) {
841 s->phy_status |= 0x0020;
842 }
843 break;
844 case 4: /* Auto-neg advertisement */
845 s->phy_advertise = (val & 0x2d7f) | 0x80;
846 break;
847 /* TODO 17, 18, 27, 31 */
848 case 30: /* Interrupt mask */
849 s->phy_int_mask = val & 0xff;
850 phy_update_irq(s);
851 break;
852 default:
853 BADF("PHY write reg %d = 0x%04x\n", reg, val);
854 }
855 }
856
857 static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
858 {
859 switch (reg) {
860 case MAC_CR:
861 if ((s->mac_cr & MAC_CR_RXEN) != 0 && (val & MAC_CR_RXEN) == 0) {
862 s->int_sts |= RXSTOP_INT;
863 }
864 s->mac_cr = val & ~MAC_CR_RESERVED;
865 DPRINTF("MAC_CR: %08x\n", val);
866 break;
867 case MAC_ADDRH:
868 s->conf.macaddr.a[4] = val & 0xff;
869 s->conf.macaddr.a[5] = (val >> 8) & 0xff;
870 lan9118_mac_changed(s);
871 break;
872 case MAC_ADDRL:
873 s->conf.macaddr.a[0] = val & 0xff;
874 s->conf.macaddr.a[1] = (val >> 8) & 0xff;
875 s->conf.macaddr.a[2] = (val >> 16) & 0xff;
876 s->conf.macaddr.a[3] = (val >> 24) & 0xff;
877 lan9118_mac_changed(s);
878 break;
879 case MAC_HASHH:
880 s->mac_hashh = val;
881 break;
882 case MAC_HASHL:
883 s->mac_hashl = val;
884 break;
885 case MAC_MII_ACC:
886 s->mac_mii_acc = val & 0xffc2;
887 if (val & 2) {
888 DPRINTF("PHY write %d = 0x%04x\n",
889 (val >> 6) & 0x1f, s->mac_mii_data);
890 do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
891 } else {
892 s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
893 DPRINTF("PHY read %d = 0x%04x\n",
894 (val >> 6) & 0x1f, s->mac_mii_data);
895 }
896 break;
897 case MAC_MII_DATA:
898 s->mac_mii_data = val & 0xffff;
899 break;
900 case MAC_FLOW:
901 s->mac_flow = val & 0xffff0000;
902 break;
903 case MAC_VLAN1:
904 /* Writing to this register changes a condition for
905 * FrameTooLong bit in rx_status. Since we do not set
906 * FrameTooLong anyway, just ignore write to this.
907 */
908 break;
909 default:
910 hw_error("lan9118: Unimplemented MAC register write: %d = 0x%x\n",
911 s->mac_cmd & 0xf, val);
912 }
913 }
914
915 static uint32_t do_mac_read(lan9118_state *s, int reg)
916 {
917 switch (reg) {
918 case MAC_CR:
919 return s->mac_cr;
920 case MAC_ADDRH:
921 return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8);
922 case MAC_ADDRL:
923 return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8)
924 | (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24);
925 case MAC_HASHH:
926 return s->mac_hashh;
927 break;
928 case MAC_HASHL:
929 return s->mac_hashl;
930 break;
931 case MAC_MII_ACC:
932 return s->mac_mii_acc;
933 case MAC_MII_DATA:
934 return s->mac_mii_data;
935 case MAC_FLOW:
936 return s->mac_flow;
937 default:
938 hw_error("lan9118: Unimplemented MAC register read: %d\n",
939 s->mac_cmd & 0xf);
940 }
941 }
942
943 static void lan9118_eeprom_cmd(lan9118_state *s, int cmd, int addr)
944 {
945 s->e2p_cmd = (s->e2p_cmd & 0x10) | (cmd << 28) | addr;
946 switch (cmd) {
947 case 0:
948 s->e2p_data = s->eeprom[addr];
949 DPRINTF("EEPROM Read %d = 0x%02x\n", addr, s->e2p_data);
950 break;
951 case 1:
952 s->eeprom_writable = 0;
953 DPRINTF("EEPROM Write Disable\n");
954 break;
955 case 2: /* EWEN */
956 s->eeprom_writable = 1;
957 DPRINTF("EEPROM Write Enable\n");
958 break;
959 case 3: /* WRITE */
960 if (s->eeprom_writable) {
961 s->eeprom[addr] &= s->e2p_data;
962 DPRINTF("EEPROM Write %d = 0x%02x\n", addr, s->e2p_data);
963 } else {
964 DPRINTF("EEPROM Write %d (ignored)\n", addr);
965 }
966 break;
967 case 4: /* WRAL */
968 if (s->eeprom_writable) {
969 for (addr = 0; addr < 128; addr++) {
970 s->eeprom[addr] &= s->e2p_data;
971 }
972 DPRINTF("EEPROM Write All 0x%02x\n", s->e2p_data);
973 } else {
974 DPRINTF("EEPROM Write All (ignored)\n");
975 }
976 break;
977 case 5: /* ERASE */
978 if (s->eeprom_writable) {
979 s->eeprom[addr] = 0xff;
980 DPRINTF("EEPROM Erase %d\n", addr);
981 } else {
982 DPRINTF("EEPROM Erase %d (ignored)\n", addr);
983 }
984 break;
985 case 6: /* ERAL */
986 if (s->eeprom_writable) {
987 memset(s->eeprom, 0xff, 128);
988 DPRINTF("EEPROM Erase All\n");
989 } else {
990 DPRINTF("EEPROM Erase All (ignored)\n");
991 }
992 break;
993 case 7: /* RELOAD */
994 lan9118_reload_eeprom(s);
995 break;
996 }
997 }
998
999 static void lan9118_tick(void *opaque)
1000 {
1001 lan9118_state *s = (lan9118_state *)opaque;
1002 if (s->int_en & GPT_INT) {
1003 s->int_sts |= GPT_INT;
1004 }
1005 lan9118_update(s);
1006 }
1007
1008 static void lan9118_writel(void *opaque, hwaddr offset,
1009 uint64_t val, unsigned size)
1010 {
1011 lan9118_state *s = (lan9118_state *)opaque;
1012 offset &= 0xff;
1013
1014 //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
1015 if (offset >= 0x20 && offset < 0x40) {
1016 /* TX FIFO */
1017 tx_fifo_push(s, val);
1018 return;
1019 }
1020 switch (offset) {
1021 case CSR_IRQ_CFG:
1022 /* TODO: Implement interrupt deassertion intervals. */
1023 val &= (IRQ_EN | IRQ_POL | IRQ_TYPE);
1024 s->irq_cfg = (s->irq_cfg & IRQ_INT) | val;
1025 break;
1026 case CSR_INT_STS:
1027 s->int_sts &= ~val;
1028 break;
1029 case CSR_INT_EN:
1030 s->int_en = val & ~RESERVED_INT;
1031 s->int_sts |= val & SW_INT;
1032 break;
1033 case CSR_FIFO_INT:
1034 DPRINTF("FIFO INT levels %08x\n", val);
1035 s->fifo_int = val;
1036 break;
1037 case CSR_RX_CFG:
1038 if (val & 0x8000) {
1039 /* RX_DUMP */
1040 s->rx_fifo_used = 0;
1041 s->rx_status_fifo_used = 0;
1042 s->rx_packet_size_tail = s->rx_packet_size_head;
1043 s->rx_packet_size[s->rx_packet_size_head] = 0;
1044 }
1045 s->rx_cfg = val & 0xcfff1ff0;
1046 break;
1047 case CSR_TX_CFG:
1048 if (val & 0x8000) {
1049 s->tx_status_fifo_used = 0;
1050 }
1051 if (val & 0x4000) {
1052 s->txp->state = TX_IDLE;
1053 s->txp->fifo_used = 0;
1054 s->txp->cmd_a = 0xffffffff;
1055 }
1056 s->tx_cfg = val & 6;
1057 break;
1058 case CSR_HW_CFG:
1059 if (val & 1) {
1060 /* SRST */
1061 lan9118_reset(DEVICE(s));
1062 } else {
1063 s->hw_cfg = (val & 0x003f300) | (s->hw_cfg & 0x4);
1064 }
1065 break;
1066 case CSR_RX_DP_CTRL:
1067 if (val & 0x80000000) {
1068 /* Skip forward to next packet. */
1069 s->rxp_pad = 0;
1070 s->rxp_offset = 0;
1071 if (s->rxp_size == 0) {
1072 /* Pop a word to start the next packet. */
1073 rx_fifo_pop(s);
1074 s->rxp_pad = 0;
1075 s->rxp_offset = 0;
1076 }
1077 s->rx_fifo_head += s->rxp_size;
1078 if (s->rx_fifo_head >= s->rx_fifo_size) {
1079 s->rx_fifo_head -= s->rx_fifo_size;
1080 }
1081 }
1082 break;
1083 case CSR_PMT_CTRL:
1084 if (val & 0x400) {
1085 phy_reset(s);
1086 }
1087 s->pmt_ctrl &= ~0x34e;
1088 s->pmt_ctrl |= (val & 0x34e);
1089 break;
1090 case CSR_GPIO_CFG:
1091 /* Probably just enabling LEDs. */
1092 s->gpio_cfg = val & 0x7777071f;
1093 break;
1094 case CSR_GPT_CFG:
1095 if ((s->gpt_cfg ^ val) & GPT_TIMER_EN) {
1096 if (val & GPT_TIMER_EN) {
1097 ptimer_set_count(s->timer, val & 0xffff);
1098 ptimer_run(s->timer, 0);
1099 } else {
1100 ptimer_stop(s->timer);
1101 ptimer_set_count(s->timer, 0xffff);
1102 }
1103 }
1104 s->gpt_cfg = val & (GPT_TIMER_EN | 0xffff);
1105 break;
1106 case CSR_WORD_SWAP:
1107 /* Ignored because we're in 32-bit mode. */
1108 s->word_swap = val;
1109 break;
1110 case CSR_MAC_CSR_CMD:
1111 s->mac_cmd = val & 0x4000000f;
1112 if (val & 0x80000000) {
1113 if (val & 0x40000000) {
1114 s->mac_data = do_mac_read(s, val & 0xf);
1115 DPRINTF("MAC read %d = 0x%08x\n", val & 0xf, s->mac_data);
1116 } else {
1117 DPRINTF("MAC write %d = 0x%08x\n", val & 0xf, s->mac_data);
1118 do_mac_write(s, val & 0xf, s->mac_data);
1119 }
1120 }
1121 break;
1122 case CSR_MAC_CSR_DATA:
1123 s->mac_data = val;
1124 break;
1125 case CSR_AFC_CFG:
1126 s->afc_cfg = val & 0x00ffffff;
1127 break;
1128 case CSR_E2P_CMD:
1129 lan9118_eeprom_cmd(s, (val >> 28) & 7, val & 0x7f);
1130 break;
1131 case CSR_E2P_DATA:
1132 s->e2p_data = val & 0xff;
1133 break;
1134
1135 default:
1136 hw_error("lan9118_write: Bad reg 0x%x = %x\n", (int)offset, (int)val);
1137 break;
1138 }
1139 lan9118_update(s);
1140 }
1141
1142 static void lan9118_writew(void *opaque, hwaddr offset,
1143 uint32_t val)
1144 {
1145 lan9118_state *s = (lan9118_state *)opaque;
1146 offset &= 0xff;
1147
1148 if (s->write_word_prev_offset != (offset & ~0x3)) {
1149 /* New offset, reset word counter */
1150 s->write_word_n = 0;
1151 s->write_word_prev_offset = offset & ~0x3;
1152 }
1153
1154 if (offset & 0x2) {
1155 s->write_word_h = val;
1156 } else {
1157 s->write_word_l = val;
1158 }
1159
1160 //DPRINTF("Writew reg 0x%02x = 0x%08x\n", (int)offset, val);
1161 s->write_word_n++;
1162 if (s->write_word_n == 2) {
1163 s->write_word_n = 0;
1164 lan9118_writel(s, offset & ~3, s->write_word_l +
1165 (s->write_word_h << 16), 4);
1166 }
1167 }
1168
1169 static void lan9118_16bit_mode_write(void *opaque, hwaddr offset,
1170 uint64_t val, unsigned size)
1171 {
1172 switch (size) {
1173 case 2:
1174 lan9118_writew(opaque, offset, (uint32_t)val);
1175 return;
1176 case 4:
1177 lan9118_writel(opaque, offset, val, size);
1178 return;
1179 }
1180
1181 hw_error("lan9118_write: Bad size 0x%x\n", size);
1182 }
1183
1184 static uint64_t lan9118_readl(void *opaque, hwaddr offset,
1185 unsigned size)
1186 {
1187 lan9118_state *s = (lan9118_state *)opaque;
1188
1189 //DPRINTF("Read reg 0x%02x\n", (int)offset);
1190 if (offset < 0x20) {
1191 /* RX FIFO */
1192 return rx_fifo_pop(s);
1193 }
1194 switch (offset) {
1195 case 0x40:
1196 return rx_status_fifo_pop(s);
1197 case 0x44:
1198 return s->rx_status_fifo[s->tx_status_fifo_head];
1199 case 0x48:
1200 return tx_status_fifo_pop(s);
1201 case 0x4c:
1202 return s->tx_status_fifo[s->tx_status_fifo_head];
1203 case CSR_ID_REV:
1204 return 0x01180001;
1205 case CSR_IRQ_CFG:
1206 return s->irq_cfg;
1207 case CSR_INT_STS:
1208 return s->int_sts;
1209 case CSR_INT_EN:
1210 return s->int_en;
1211 case CSR_BYTE_TEST:
1212 return 0x87654321;
1213 case CSR_FIFO_INT:
1214 return s->fifo_int;
1215 case CSR_RX_CFG:
1216 return s->rx_cfg;
1217 case CSR_TX_CFG:
1218 return s->tx_cfg;
1219 case CSR_HW_CFG:
1220 return s->hw_cfg;
1221 case CSR_RX_DP_CTRL:
1222 return 0;
1223 case CSR_RX_FIFO_INF:
1224 return (s->rx_status_fifo_used << 16) | (s->rx_fifo_used << 2);
1225 case CSR_TX_FIFO_INF:
1226 return (s->tx_status_fifo_used << 16)
1227 | (s->tx_fifo_size - s->txp->fifo_used);
1228 case CSR_PMT_CTRL:
1229 return s->pmt_ctrl;
1230 case CSR_GPIO_CFG:
1231 return s->gpio_cfg;
1232 case CSR_GPT_CFG:
1233 return s->gpt_cfg;
1234 case CSR_GPT_CNT:
1235 return ptimer_get_count(s->timer);
1236 case CSR_WORD_SWAP:
1237 return s->word_swap;
1238 case CSR_FREE_RUN:
1239 return (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 40) - s->free_timer_start;
1240 case CSR_RX_DROP:
1241 /* TODO: Implement dropped frames counter. */
1242 return 0;
1243 case CSR_MAC_CSR_CMD:
1244 return s->mac_cmd;
1245 case CSR_MAC_CSR_DATA:
1246 return s->mac_data;
1247 case CSR_AFC_CFG:
1248 return s->afc_cfg;
1249 case CSR_E2P_CMD:
1250 return s->e2p_cmd;
1251 case CSR_E2P_DATA:
1252 return s->e2p_data;
1253 }
1254 hw_error("lan9118_read: Bad reg 0x%x\n", (int)offset);
1255 return 0;
1256 }
1257
1258 static uint32_t lan9118_readw(void *opaque, hwaddr offset)
1259 {
1260 lan9118_state *s = (lan9118_state *)opaque;
1261 uint32_t val;
1262
1263 if (s->read_word_prev_offset != (offset & ~0x3)) {
1264 /* New offset, reset word counter */
1265 s->read_word_n = 0;
1266 s->read_word_prev_offset = offset & ~0x3;
1267 }
1268
1269 s->read_word_n++;
1270 if (s->read_word_n == 1) {
1271 s->read_long = lan9118_readl(s, offset & ~3, 4);
1272 } else {
1273 s->read_word_n = 0;
1274 }
1275
1276 if (offset & 2) {
1277 val = s->read_long >> 16;
1278 } else {
1279 val = s->read_long & 0xFFFF;
1280 }
1281
1282 //DPRINTF("Readw reg 0x%02x, val 0x%x\n", (int)offset, val);
1283 return val;
1284 }
1285
1286 static uint64_t lan9118_16bit_mode_read(void *opaque, hwaddr offset,
1287 unsigned size)
1288 {
1289 switch (size) {
1290 case 2:
1291 return lan9118_readw(opaque, offset);
1292 case 4:
1293 return lan9118_readl(opaque, offset, size);
1294 }
1295
1296 hw_error("lan9118_read: Bad size 0x%x\n", size);
1297 return 0;
1298 }
1299
1300 static const MemoryRegionOps lan9118_mem_ops = {
1301 .read = lan9118_readl,
1302 .write = lan9118_writel,
1303 .endianness = DEVICE_NATIVE_ENDIAN,
1304 };
1305
1306 static const MemoryRegionOps lan9118_16bit_mem_ops = {
1307 .read = lan9118_16bit_mode_read,
1308 .write = lan9118_16bit_mode_write,
1309 .endianness = DEVICE_NATIVE_ENDIAN,
1310 };
1311
1312 static void lan9118_cleanup(NetClientState *nc)
1313 {
1314 lan9118_state *s = qemu_get_nic_opaque(nc);
1315
1316 s->nic = NULL;
1317 }
1318
1319 static NetClientInfo net_lan9118_info = {
1320 .type = NET_CLIENT_OPTIONS_KIND_NIC,
1321 .size = sizeof(NICState),
1322 .can_receive = lan9118_can_receive,
1323 .receive = lan9118_receive,
1324 .cleanup = lan9118_cleanup,
1325 .link_status_changed = lan9118_set_link,
1326 };
1327
1328 static int lan9118_init1(SysBusDevice *sbd)
1329 {
1330 DeviceState *dev = DEVICE(sbd);
1331 lan9118_state *s = LAN9118(dev);
1332 QEMUBH *bh;
1333 int i;
1334 const MemoryRegionOps *mem_ops =
1335 s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops;
1336
1337 memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s,
1338 "lan9118-mmio", 0x100);
1339 sysbus_init_mmio(sbd, &s->mmio);
1340 sysbus_init_irq(sbd, &s->irq);
1341 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1342
1343 s->nic = qemu_new_nic(&net_lan9118_info, &s->conf,
1344 object_get_typename(OBJECT(dev)), dev->id, s);
1345 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1346 s->eeprom[0] = 0xa5;
1347 for (i = 0; i < 6; i++) {
1348 s->eeprom[i + 1] = s->conf.macaddr.a[i];
1349 }
1350 s->pmt_ctrl = 1;
1351 s->txp = &s->tx_packet;
1352
1353 bh = qemu_bh_new(lan9118_tick, s);
1354 s->timer = ptimer_init(bh);
1355 ptimer_set_freq(s->timer, 10000);
1356 ptimer_set_limit(s->timer, 0xffff, 1);
1357
1358 return 0;
1359 }
1360
1361 static Property lan9118_properties[] = {
1362 DEFINE_NIC_PROPERTIES(lan9118_state, conf),
1363 DEFINE_PROP_UINT32("mode_16bit", lan9118_state, mode_16bit, 0),
1364 DEFINE_PROP_END_OF_LIST(),
1365 };
1366
1367 static void lan9118_class_init(ObjectClass *klass, void *data)
1368 {
1369 DeviceClass *dc = DEVICE_CLASS(klass);
1370 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1371
1372 k->init = lan9118_init1;
1373 dc->reset = lan9118_reset;
1374 dc->props = lan9118_properties;
1375 dc->vmsd = &vmstate_lan9118;
1376 }
1377
1378 static const TypeInfo lan9118_info = {
1379 .name = TYPE_LAN9118,
1380 .parent = TYPE_SYS_BUS_DEVICE,
1381 .instance_size = sizeof(lan9118_state),
1382 .class_init = lan9118_class_init,
1383 };
1384
1385 static void lan9118_register_types(void)
1386 {
1387 type_register_static(&lan9118_info);
1388 }
1389
1390 /* Legacy helper function. Should go away when machine config files are
1391 implemented. */
1392 void lan9118_init(NICInfo *nd, uint32_t base, qemu_irq irq)
1393 {
1394 DeviceState *dev;
1395 SysBusDevice *s;
1396
1397 qemu_check_nic_model(nd, "lan9118");
1398 dev = qdev_create(NULL, TYPE_LAN9118);
1399 qdev_set_nic_properties(dev, nd);
1400 qdev_init_nofail(dev);
1401 s = SYS_BUS_DEVICE(dev);
1402 sysbus_mmio_map(s, 0, base);
1403 sysbus_connect_irq(s, 0, irq);
1404 }
1405
1406 type_init(lan9118_register_types)
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