| blob | 1c4391b4156ff304b76fa7995a8bc66dcab0d122 |
1 /*
2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
18 #ifndef HEXAGON_GEN_TCG_H
19 #define HEXAGON_GEN_TCG_H
21 /*
22 * Here is a primer to understand the tag names for load/store instructions
23 *
24 * Data types
25 * b signed byte r0 = memb(r2+#0)
26 * ub unsigned byte r0 = memub(r2+#0)
27 * h signed half word (16 bits) r0 = memh(r2+#0)
28 * uh unsigned half word r0 = memuh(r2+#0)
29 * i integer (32 bits) r0 = memw(r2+#0)
30 * d double word (64 bits) r1:0 = memd(r2+#0)
31 *
32 * Addressing modes
33 * _io indirect with offset r0 = memw(r1+#4)
34 * _ur absolute with register offset r0 = memw(r1<<#4+##variable)
35 * _rr indirect with register offset r0 = memw(r1+r4<<#2)
36 * gp global pointer relative r0 = memw(gp+#200)
37 * _sp stack pointer relative r0 = memw(r29+#12)
38 * _ap absolute set r0 = memw(r1=##variable)
39 * _pr post increment register r0 = memw(r1++m1)
40 * _pbr post increment bit reverse r0 = memw(r1++m1:brev)
41 * _pi post increment immediate r0 = memb(r1++#1)
42 * _pci post increment circular immediate r0 = memw(r1++#4:circ(m0))
43 * _pcr post increment circular register r0 = memw(r1++I:circ(m0))
44 */
46 /* Macros for complex addressing modes */
47 #define GET_EA_ap \
48 do { \
49 fEA_IMM(UiV); \
50 tcg_gen_movi_tl(ReV, UiV); \
51 } while (0)
52 #define GET_EA_pr \
53 do { \
54 fEA_REG(RxV); \
55 fPM_M(RxV, MuV); \
56 } while (0)
57 #define GET_EA_pbr \
58 do { \
59 gen_helper_fbrev(EA, RxV); \
60 tcg_gen_add_tl(RxV, RxV, MuV); \
61 } while (0)
62 #define GET_EA_pi \
63 do { \
64 fEA_REG(RxV); \
65 fPM_I(RxV, siV); \
66 } while (0)
67 #define GET_EA_pci \
68 do { \
69 TCGv tcgv_siV = tcg_constant_tl(siV); \
70 tcg_gen_mov_tl(EA, RxV); \
71 gen_helper_fcircadd(RxV, RxV, tcgv_siV, MuV, CS); \
72 } while (0)
73 #define GET_EA_pcr(SHIFT) \
74 do { \
75 TCGv ireg = tcg_temp_new(); \
76 tcg_gen_mov_tl(EA, RxV); \
77 gen_read_ireg(ireg, MuV, (SHIFT)); \
78 gen_helper_fcircadd(RxV, RxV, ireg, MuV, CS); \
79 } while (0)
81 /* Instructions with multiple definitions */
82 #define fGEN_TCG_LOAD_AP(RES, SIZE, SIGN) \
83 do { \
84 fMUST_IMMEXT(UiV); \
85 fEA_IMM(UiV); \
86 fLOAD(1, SIZE, SIGN, EA, RES); \
87 tcg_gen_movi_tl(ReV, UiV); \
88 } while (0)
90 #define fGEN_TCG_L4_loadrub_ap(SHORTCODE) \
91 fGEN_TCG_LOAD_AP(RdV, 1, u)
92 #define fGEN_TCG_L4_loadrb_ap(SHORTCODE) \
93 fGEN_TCG_LOAD_AP(RdV, 1, s)
94 #define fGEN_TCG_L4_loadruh_ap(SHORTCODE) \
95 fGEN_TCG_LOAD_AP(RdV, 2, u)
96 #define fGEN_TCG_L4_loadrh_ap(SHORTCODE) \
97 fGEN_TCG_LOAD_AP(RdV, 2, s)
98 #define fGEN_TCG_L4_loadri_ap(SHORTCODE) \
99 fGEN_TCG_LOAD_AP(RdV, 4, u)
100 #define fGEN_TCG_L4_loadrd_ap(SHORTCODE) \
101 fGEN_TCG_LOAD_AP(RddV, 8, u)
103 #define fGEN_TCG_L2_loadrub_pci(SHORTCODE) SHORTCODE
104 #define fGEN_TCG_L2_loadrb_pci(SHORTCODE) SHORTCODE
105 #define fGEN_TCG_L2_loadruh_pci(SHORTCODE) SHORTCODE
106 #define fGEN_TCG_L2_loadrh_pci(SHORTCODE) SHORTCODE
107 #define fGEN_TCG_L2_loadri_pci(SHORTCODE) SHORTCODE
108 #define fGEN_TCG_L2_loadrd_pci(SHORTCODE) SHORTCODE
110 #define fGEN_TCG_LOAD_pcr(SHIFT, LOAD) \
111 do { \
112 TCGv ireg = tcg_temp_new(); \
113 tcg_gen_mov_tl(EA, RxV); \
114 gen_read_ireg(ireg, MuV, SHIFT); \
115 gen_helper_fcircadd(RxV, RxV, ireg, MuV, CS); \
116 LOAD; \
117 } while (0)
119 #define fGEN_TCG_L2_loadrub_pcr(SHORTCODE) \
120 fGEN_TCG_LOAD_pcr(0, fLOAD(1, 1, u, EA, RdV))
121 #define fGEN_TCG_L2_loadrb_pcr(SHORTCODE) \
122 fGEN_TCG_LOAD_pcr(0, fLOAD(1, 1, s, EA, RdV))
123 #define fGEN_TCG_L2_loadruh_pcr(SHORTCODE) \
124 fGEN_TCG_LOAD_pcr(1, fLOAD(1, 2, u, EA, RdV))
125 #define fGEN_TCG_L2_loadrh_pcr(SHORTCODE) \
126 fGEN_TCG_LOAD_pcr(1, fLOAD(1, 2, s, EA, RdV))
127 #define fGEN_TCG_L2_loadri_pcr(SHORTCODE) \
128 fGEN_TCG_LOAD_pcr(2, fLOAD(1, 4, u, EA, RdV))
129 #define fGEN_TCG_L2_loadrd_pcr(SHORTCODE) \
130 fGEN_TCG_LOAD_pcr(3, fLOAD(1, 8, u, EA, RddV))
132 #define fGEN_TCG_L2_loadrub_pr(SHORTCODE) SHORTCODE
133 #define fGEN_TCG_L2_loadrub_pbr(SHORTCODE) SHORTCODE
134 #define fGEN_TCG_L2_loadrub_pi(SHORTCODE) SHORTCODE
135 #define fGEN_TCG_L2_loadrb_pr(SHORTCODE) SHORTCODE
136 #define fGEN_TCG_L2_loadrb_pbr(SHORTCODE) SHORTCODE
137 #define fGEN_TCG_L2_loadrb_pi(SHORTCODE) SHORTCODE
138 #define fGEN_TCG_L2_loadruh_pr(SHORTCODE) SHORTCODE
139 #define fGEN_TCG_L2_loadruh_pbr(SHORTCODE) SHORTCODE
140 #define fGEN_TCG_L2_loadruh_pi(SHORTCODE) SHORTCODE
141 #define fGEN_TCG_L2_loadrh_pr(SHORTCODE) SHORTCODE
142 #define fGEN_TCG_L2_loadrh_pbr(SHORTCODE) SHORTCODE
143 #define fGEN_TCG_L2_loadrh_pi(SHORTCODE) SHORTCODE
144 #define fGEN_TCG_L2_loadri_pr(SHORTCODE) SHORTCODE
145 #define fGEN_TCG_L2_loadri_pbr(SHORTCODE) SHORTCODE
146 #define fGEN_TCG_L2_loadri_pi(SHORTCODE) SHORTCODE
147 #define fGEN_TCG_L2_loadrd_pr(SHORTCODE) SHORTCODE
148 #define fGEN_TCG_L2_loadrd_pbr(SHORTCODE) SHORTCODE
149 #define fGEN_TCG_L2_loadrd_pi(SHORTCODE) SHORTCODE
151 /*
152 * These instructions load 2 bytes and places them in
153 * two halves of the destination register.
154 * The GET_EA macro determines the addressing mode.
155 * The SIGN argument determines whether to zero-extend or
156 * sign-extend.
157 */
158 #define fGEN_TCG_loadbXw2(GET_EA, SIGN) \
159 do { \
160 TCGv tmp = tcg_temp_new(); \
161 TCGv byte = tcg_temp_new(); \
162 GET_EA; \
163 fLOAD(1, 2, u, EA, tmp); \
164 tcg_gen_movi_tl(RdV, 0); \
165 for (int i = 0; i < 2; i++) { \
166 gen_set_half(i, RdV, gen_get_byte(byte, i, tmp, (SIGN))); \
167 } \
168 } while (0)
170 #define fGEN_TCG_L2_loadbzw2_io(SHORTCODE) \
171 fGEN_TCG_loadbXw2(fEA_RI(RsV, siV), false)
172 #define fGEN_TCG_L4_loadbzw2_ur(SHORTCODE) \
173 fGEN_TCG_loadbXw2(fEA_IRs(UiV, RtV, uiV), false)
174 #define fGEN_TCG_L2_loadbsw2_io(SHORTCODE) \
175 fGEN_TCG_loadbXw2(fEA_RI(RsV, siV), true)
176 #define fGEN_TCG_L4_loadbsw2_ur(SHORTCODE) \
177 fGEN_TCG_loadbXw2(fEA_IRs(UiV, RtV, uiV), true)
178 #define fGEN_TCG_L4_loadbzw2_ap(SHORTCODE) \
179 fGEN_TCG_loadbXw2(GET_EA_ap, false)
180 #define fGEN_TCG_L2_loadbzw2_pr(SHORTCODE) \
181 fGEN_TCG_loadbXw2(GET_EA_pr, false)
182 #define fGEN_TCG_L2_loadbzw2_pbr(SHORTCODE) \
183 fGEN_TCG_loadbXw2(GET_EA_pbr, false)
184 #define fGEN_TCG_L2_loadbzw2_pi(SHORTCODE) \
185 fGEN_TCG_loadbXw2(GET_EA_pi, false)
186 #define fGEN_TCG_L4_loadbsw2_ap(SHORTCODE) \
187 fGEN_TCG_loadbXw2(GET_EA_ap, true)
188 #define fGEN_TCG_L2_loadbsw2_pr(SHORTCODE) \
189 fGEN_TCG_loadbXw2(GET_EA_pr, true)
190 #define fGEN_TCG_L2_loadbsw2_pbr(SHORTCODE) \
191 fGEN_TCG_loadbXw2(GET_EA_pbr, true)
192 #define fGEN_TCG_L2_loadbsw2_pi(SHORTCODE) \
193 fGEN_TCG_loadbXw2(GET_EA_pi, true)
194 #define fGEN_TCG_L2_loadbzw2_pci(SHORTCODE) \
195 fGEN_TCG_loadbXw2(GET_EA_pci, false)
196 #define fGEN_TCG_L2_loadbsw2_pci(SHORTCODE) \
197 fGEN_TCG_loadbXw2(GET_EA_pci, true)
198 #define fGEN_TCG_L2_loadbzw2_pcr(SHORTCODE) \
199 fGEN_TCG_loadbXw2(GET_EA_pcr(1), false)
200 #define fGEN_TCG_L2_loadbsw2_pcr(SHORTCODE) \
201 fGEN_TCG_loadbXw2(GET_EA_pcr(1), true)
203 /*
204 * These instructions load 4 bytes and places them in
205 * four halves of the destination register pair.
206 * The GET_EA macro determines the addressing mode.
207 * The SIGN argument determines whether to zero-extend or
208 * sign-extend.
209 */
210 #define fGEN_TCG_loadbXw4(GET_EA, SIGN) \
211 do { \
212 TCGv tmp = tcg_temp_new(); \
213 TCGv byte = tcg_temp_new(); \
214 GET_EA; \
215 fLOAD(1, 4, u, EA, tmp); \
216 tcg_gen_movi_i64(RddV, 0); \
217 for (int i = 0; i < 4; i++) { \
218 gen_set_half_i64(i, RddV, gen_get_byte(byte, i, tmp, (SIGN))); \
219 } \
220 } while (0)
222 #define fGEN_TCG_L2_loadbzw4_io(SHORTCODE) \
223 fGEN_TCG_loadbXw4(fEA_RI(RsV, siV), false)
224 #define fGEN_TCG_L4_loadbzw4_ur(SHORTCODE) \
225 fGEN_TCG_loadbXw4(fEA_IRs(UiV, RtV, uiV), false)
226 #define fGEN_TCG_L2_loadbsw4_io(SHORTCODE) \
227 fGEN_TCG_loadbXw4(fEA_RI(RsV, siV), true)
228 #define fGEN_TCG_L4_loadbsw4_ur(SHORTCODE) \
229 fGEN_TCG_loadbXw4(fEA_IRs(UiV, RtV, uiV), true)
230 #define fGEN_TCG_L2_loadbzw4_pci(SHORTCODE) \
231 fGEN_TCG_loadbXw4(GET_EA_pci, false)
232 #define fGEN_TCG_L2_loadbsw4_pci(SHORTCODE) \
233 fGEN_TCG_loadbXw4(GET_EA_pci, true)
234 #define fGEN_TCG_L2_loadbzw4_pcr(SHORTCODE) \
235 fGEN_TCG_loadbXw4(GET_EA_pcr(2), false)
236 #define fGEN_TCG_L2_loadbsw4_pcr(SHORTCODE) \
237 fGEN_TCG_loadbXw4(GET_EA_pcr(2), true)
238 #define fGEN_TCG_L4_loadbzw4_ap(SHORTCODE) \
239 fGEN_TCG_loadbXw4(GET_EA_ap, false)
240 #define fGEN_TCG_L2_loadbzw4_pr(SHORTCODE) \
241 fGEN_TCG_loadbXw4(GET_EA_pr, false)
242 #define fGEN_TCG_L2_loadbzw4_pbr(SHORTCODE) \
243 fGEN_TCG_loadbXw4(GET_EA_pbr, false)
244 #define fGEN_TCG_L2_loadbzw4_pi(SHORTCODE) \
245 fGEN_TCG_loadbXw4(GET_EA_pi, false)
246 #define fGEN_TCG_L4_loadbsw4_ap(SHORTCODE) \
247 fGEN_TCG_loadbXw4(GET_EA_ap, true)
248 #define fGEN_TCG_L2_loadbsw4_pr(SHORTCODE) \
249 fGEN_TCG_loadbXw4(GET_EA_pr, true)
250 #define fGEN_TCG_L2_loadbsw4_pbr(SHORTCODE) \
251 fGEN_TCG_loadbXw4(GET_EA_pbr, true)
252 #define fGEN_TCG_L2_loadbsw4_pi(SHORTCODE) \
253 fGEN_TCG_loadbXw4(GET_EA_pi, true)
255 /*
256 * These instructions load a half word, shift the destination right by 16 bits
257 * and place the loaded value in the high half word of the destination pair.
258 * The GET_EA macro determines the addressing mode.
259 */
260 #define fGEN_TCG_loadalignh(GET_EA) \
261 do { \
262 TCGv tmp = tcg_temp_new(); \
263 TCGv_i64 tmp_i64 = tcg_temp_new_i64(); \
264 GET_EA; \
265 fLOAD(1, 2, u, EA, tmp); \
266 tcg_gen_extu_i32_i64(tmp_i64, tmp); \
267 tcg_gen_shri_i64(RyyV, RyyV, 16); \
268 tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 48, 16); \
269 } while (0)
271 #define fGEN_TCG_L4_loadalignh_ur(SHORTCODE) \
272 fGEN_TCG_loadalignh(fEA_IRs(UiV, RtV, uiV))
273 #define fGEN_TCG_L2_loadalignh_io(SHORTCODE) \
274 fGEN_TCG_loadalignh(fEA_RI(RsV, siV))
275 #define fGEN_TCG_L2_loadalignh_pci(SHORTCODE) \
276 fGEN_TCG_loadalignh(GET_EA_pci)
277 #define fGEN_TCG_L2_loadalignh_pcr(SHORTCODE) \
278 fGEN_TCG_loadalignh(GET_EA_pcr(1))
279 #define fGEN_TCG_L4_loadalignh_ap(SHORTCODE) \
280 fGEN_TCG_loadalignh(GET_EA_ap)
281 #define fGEN_TCG_L2_loadalignh_pr(SHORTCODE) \
282 fGEN_TCG_loadalignh(GET_EA_pr)
283 #define fGEN_TCG_L2_loadalignh_pbr(SHORTCODE) \
284 fGEN_TCG_loadalignh(GET_EA_pbr)
285 #define fGEN_TCG_L2_loadalignh_pi(SHORTCODE) \
286 fGEN_TCG_loadalignh(GET_EA_pi)
288 /* Same as above, but loads a byte instead of half word */
289 #define fGEN_TCG_loadalignb(GET_EA) \
290 do { \
291 TCGv tmp = tcg_temp_new(); \
292 TCGv_i64 tmp_i64 = tcg_temp_new_i64(); \
293 GET_EA; \
294 fLOAD(1, 1, u, EA, tmp); \
295 tcg_gen_extu_i32_i64(tmp_i64, tmp); \
296 tcg_gen_shri_i64(RyyV, RyyV, 8); \
297 tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 56, 8); \
298 } while (0)
300 #define fGEN_TCG_L2_loadalignb_io(SHORTCODE) \
301 fGEN_TCG_loadalignb(fEA_RI(RsV, siV))
302 #define fGEN_TCG_L4_loadalignb_ur(SHORTCODE) \
303 fGEN_TCG_loadalignb(fEA_IRs(UiV, RtV, uiV))
304 #define fGEN_TCG_L2_loadalignb_pci(SHORTCODE) \
305 fGEN_TCG_loadalignb(GET_EA_pci)
306 #define fGEN_TCG_L2_loadalignb_pcr(SHORTCODE) \
307 fGEN_TCG_loadalignb(GET_EA_pcr(0))
308 #define fGEN_TCG_L4_loadalignb_ap(SHORTCODE) \
309 fGEN_TCG_loadalignb(GET_EA_ap)
310 #define fGEN_TCG_L2_loadalignb_pr(SHORTCODE) \
311 fGEN_TCG_loadalignb(GET_EA_pr)
312 #define fGEN_TCG_L2_loadalignb_pbr(SHORTCODE) \
313 fGEN_TCG_loadalignb(GET_EA_pbr)
314 #define fGEN_TCG_L2_loadalignb_pi(SHORTCODE) \
315 fGEN_TCG_loadalignb(GET_EA_pi)
317 /*
318 * Predicated loads
319 * Here is a primer to understand the tag names
320 *
321 * Predicate used
322 * t true "old" value if (p0) r0 = memb(r2+#0)
323 * f false "old" value if (!p0) r0 = memb(r2+#0)
324 * tnew true "new" value if (p0.new) r0 = memb(r2+#0)
325 * fnew false "new" value if (!p0.new) r0 = memb(r2+#0)
326 */
327 #define fGEN_TCG_PRED_LOAD(GET_EA, PRED, SIZE, SIGN) \
328 do { \
329 TCGv LSB = tcg_temp_new(); \
330 TCGLabel *label = gen_new_label(); \
331 tcg_gen_movi_tl(EA, 0); \
332 PRED; \
333 CHECK_NOSHUF_PRED(GET_EA, SIZE, LSB); \
334 tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \
335 fLOAD(1, SIZE, SIGN, EA, RdV); \
336 gen_set_label(label); \
337 } while (0)
339 #define fGEN_TCG_L2_ploadrubt_pi(SHORTCODE) \
340 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 1, u)
341 #define fGEN_TCG_L2_ploadrubf_pi(SHORTCODE) \
342 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 1, u)
343 #define fGEN_TCG_L2_ploadrubtnew_pi(SHORTCODE) \
344 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 1, u)
345 #define fGEN_TCG_L2_ploadrubfnew_pi(SHORTCODE) \
346 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 1, u)
347 #define fGEN_TCG_L2_ploadrbt_pi(SHORTCODE) \
348 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 1, s)
349 #define fGEN_TCG_L2_ploadrbf_pi(SHORTCODE) \
350 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 1, s)
351 #define fGEN_TCG_L2_ploadrbtnew_pi(SHORTCODE) \
352 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 1, s)
353 #define fGEN_TCG_L2_ploadrbfnew_pi(SHORTCODE) \
354 fGEN_TCG_PRED_LOAD({ fEA_REG(RxV); fPM_I(RxV, siV); }, \
355 fLSBNEWNOT(PtN), 1, s)
357 #define fGEN_TCG_L2_ploadruht_pi(SHORTCODE) \
358 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 2, u)
359 #define fGEN_TCG_L2_ploadruhf_pi(SHORTCODE) \
360 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 2, u)
361 #define fGEN_TCG_L2_ploadruhtnew_pi(SHORTCODE) \
362 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 2, u)
363 #define fGEN_TCG_L2_ploadruhfnew_pi(SHORTCODE) \
364 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 2, u)
365 #define fGEN_TCG_L2_ploadrht_pi(SHORTCODE) \
366 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 2, s)
367 #define fGEN_TCG_L2_ploadrhf_pi(SHORTCODE) \
368 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 2, s)
369 #define fGEN_TCG_L2_ploadrhtnew_pi(SHORTCODE) \
370 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 2, s)
371 #define fGEN_TCG_L2_ploadrhfnew_pi(SHORTCODE) \
372 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 2, s)
374 #define fGEN_TCG_L2_ploadrit_pi(SHORTCODE) \
375 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 4, u)
376 #define fGEN_TCG_L2_ploadrif_pi(SHORTCODE) \
377 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 4, u)
378 #define fGEN_TCG_L2_ploadritnew_pi(SHORTCODE) \
379 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 4, u)
380 #define fGEN_TCG_L2_ploadrifnew_pi(SHORTCODE) \
381 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 4, u)
383 /* Predicated loads into a register pair */
384 #define fGEN_TCG_PRED_LOAD_PAIR(GET_EA, PRED) \
385 do { \
386 TCGv LSB = tcg_temp_new(); \
387 TCGLabel *label = gen_new_label(); \
388 tcg_gen_movi_tl(EA, 0); \
389 PRED; \
390 CHECK_NOSHUF_PRED(GET_EA, 8, LSB); \
391 tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \
392 fLOAD(1, 8, u, EA, RddV); \
393 gen_set_label(label); \
394 } while (0)
396 #define fGEN_TCG_L2_ploadrdt_pi(SHORTCODE) \
397 fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBOLD(PtV))
398 #define fGEN_TCG_L2_ploadrdf_pi(SHORTCODE) \
399 fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBOLDNOT(PtV))
400 #define fGEN_TCG_L2_ploadrdtnew_pi(SHORTCODE) \
401 fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBNEW(PtN))
402 #define fGEN_TCG_L2_ploadrdfnew_pi(SHORTCODE) \
403 fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBNEWNOT(PtN))
405 /* load-locked and store-locked */
406 #define fGEN_TCG_L2_loadw_locked(SHORTCODE) \
407 SHORTCODE
408 #define fGEN_TCG_L4_loadd_locked(SHORTCODE) \
409 SHORTCODE
410 #define fGEN_TCG_S2_storew_locked(SHORTCODE) \
411 SHORTCODE
412 #define fGEN_TCG_S4_stored_locked(SHORTCODE) \
413 SHORTCODE
415 #define fGEN_TCG_STORE(SHORTCODE) \
416 do { \
417 TCGv HALF G_GNUC_UNUSED = tcg_temp_new(); \
418 TCGv BYTE G_GNUC_UNUSED = tcg_temp_new(); \
419 SHORTCODE; \
420 } while (0)
422 #define fGEN_TCG_STORE_pcr(SHIFT, STORE) \
423 do { \
424 TCGv ireg = tcg_temp_new(); \
425 TCGv HALF G_GNUC_UNUSED = tcg_temp_new(); \
426 TCGv BYTE G_GNUC_UNUSED = tcg_temp_new(); \
427 tcg_gen_mov_tl(EA, RxV); \
428 gen_read_ireg(ireg, MuV, SHIFT); \
429 gen_helper_fcircadd(RxV, RxV, ireg, MuV, CS); \
430 STORE; \
431 } while (0)
433 #define fGEN_TCG_S2_storerb_pbr(SHORTCODE) \
434 fGEN_TCG_STORE(SHORTCODE)
435 #define fGEN_TCG_S2_storerb_pci(SHORTCODE) \
436 fGEN_TCG_STORE(SHORTCODE)
437 #define fGEN_TCG_S2_storerb_pcr(SHORTCODE) \
438 fGEN_TCG_STORE_pcr(0, fSTORE(1, 1, EA, fGETBYTE(0, RtV)))
440 #define fGEN_TCG_S2_storerh_pbr(SHORTCODE) \
441 fGEN_TCG_STORE(SHORTCODE)
442 #define fGEN_TCG_S2_storerh_pci(SHORTCODE) \
443 fGEN_TCG_STORE(SHORTCODE)
444 #define fGEN_TCG_S2_storerh_pcr(SHORTCODE) \
445 fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(0, RtV)))
447 #define fGEN_TCG_S2_storerf_pbr(SHORTCODE) \
448 fGEN_TCG_STORE(SHORTCODE)
449 #define fGEN_TCG_S2_storerf_pci(SHORTCODE) \
450 fGEN_TCG_STORE(SHORTCODE)
451 #define fGEN_TCG_S2_storerf_pcr(SHORTCODE) \
452 fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(1, RtV)))
454 #define fGEN_TCG_S2_storeri_pbr(SHORTCODE) \
455 fGEN_TCG_STORE(SHORTCODE)
456 #define fGEN_TCG_S2_storeri_pci(SHORTCODE) \
457 fGEN_TCG_STORE(SHORTCODE)
458 #define fGEN_TCG_S2_storeri_pcr(SHORTCODE) \
459 fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, RtV))
461 #define fGEN_TCG_S2_storerd_pbr(SHORTCODE) \
462 fGEN_TCG_STORE(SHORTCODE)
463 #define fGEN_TCG_S2_storerd_pci(SHORTCODE) \
464 fGEN_TCG_STORE(SHORTCODE)
465 #define fGEN_TCG_S2_storerd_pcr(SHORTCODE) \
466 fGEN_TCG_STORE_pcr(3, fSTORE(1, 8, EA, RttV))
468 #define fGEN_TCG_S2_storerbnew_pbr(SHORTCODE) \
469 fGEN_TCG_STORE(SHORTCODE)
470 #define fGEN_TCG_S2_storerbnew_pci(SHORTCODE) \
471 fGEN_TCG_STORE(SHORTCODE)
472 #define fGEN_TCG_S2_storerbnew_pcr(SHORTCODE) \
473 fGEN_TCG_STORE_pcr(0, fSTORE(1, 1, EA, fGETBYTE(0, NtN)))
475 #define fGEN_TCG_S2_storerhnew_pbr(SHORTCODE) \
476 fGEN_TCG_STORE(SHORTCODE)
477 #define fGEN_TCG_S2_storerhnew_pci(SHORTCODE) \
478 fGEN_TCG_STORE(SHORTCODE)
479 #define fGEN_TCG_S2_storerhnew_pcr(SHORTCODE) \
480 fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(0, NtN)))
482 #define fGEN_TCG_S2_storerinew_pbr(SHORTCODE) \
483 fGEN_TCG_STORE(SHORTCODE)
484 #define fGEN_TCG_S2_storerinew_pci(SHORTCODE) \
485 fGEN_TCG_STORE(SHORTCODE)
486 #define fGEN_TCG_S2_storerinew_pcr(SHORTCODE) \
487 fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, NtN))
489 /* dczeroa clears the 32 byte cache line at the address given */
490 #define fGEN_TCG_Y2_dczeroa(SHORTCODE) SHORTCODE
492 /* In linux-user mode, these are not modelled, suppress compiler warning */
493 #define fGEN_TCG_Y2_dcinva(SHORTCODE) \
494 do { RsV = RsV; } while (0)
495 #define fGEN_TCG_Y2_dccleaninva(SHORTCODE) \
496 do { RsV = RsV; } while (0)
497 #define fGEN_TCG_Y2_dccleana(SHORTCODE) \
498 do { RsV = RsV; } while (0)
499 #define fGEN_TCG_Y2_icinva(SHORTCODE) \
500 do { RsV = RsV; } while (0)
502 /*
503 * allocframe(#uiV)
504 * RxV == r29
505 */
506 #define fGEN_TCG_S2_allocframe(SHORTCODE) \
507 gen_allocframe(ctx, RxV, uiV)
509 /* sub-instruction version (no RxV, so handle it manually) */
510 #define fGEN_TCG_SS2_allocframe(SHORTCODE) \
511 do { \
512 TCGv r29 = tcg_temp_new(); \
513 tcg_gen_mov_tl(r29, hex_gpr[HEX_REG_SP]); \
514 gen_allocframe(ctx, r29, uiV); \
515 gen_log_reg_write(ctx, HEX_REG_SP, r29); \
516 } while (0)
518 /*
519 * Rdd32 = deallocframe(Rs32):raw
520 * RddV == r31:30
521 * RsV == r30
522 */
523 #define fGEN_TCG_L2_deallocframe(SHORTCODE) \
524 gen_deallocframe(ctx, RddV, RsV)
526 /* sub-instruction version (no RddV/RsV, so handle it manually) */
527 #define fGEN_TCG_SL2_deallocframe(SHORTCODE) \
528 do { \
529 TCGv_i64 r31_30 = tcg_temp_new_i64(); \
530 gen_deallocframe(ctx, r31_30, hex_gpr[HEX_REG_FP]); \
531 gen_log_reg_write_pair(ctx, HEX_REG_FP, r31_30); \
532 } while (0)
534 /*
535 * dealloc_return
536 * Assembler mapped to
537 * r31:30 = dealloc_return(r30):raw
538 */
539 #define fGEN_TCG_L4_return(SHORTCODE) \
540 gen_return(ctx, RddV, RsV)
542 /*
543 * sub-instruction version (no RddV, so handle it manually)
544 */
545 #define fGEN_TCG_SL2_return(SHORTCODE) \
546 do { \
547 TCGv_i64 RddV = get_result_gpr_pair(ctx, HEX_REG_FP); \
548 gen_return(ctx, RddV, hex_gpr[HEX_REG_FP]); \
549 gen_log_reg_write_pair(ctx, HEX_REG_FP, RddV); \
550 } while (0)
552 /*
553 * Conditional returns follow this naming convention
554 * _t predicate true
555 * _f predicate false
556 * _tnew_pt predicate.new true predict taken
557 * _fnew_pt predicate.new false predict taken
558 * _tnew_pnt predicate.new true predict not taken
559 * _fnew_pnt predicate.new false predict not taken
560 * Predictions are not modelled in QEMU
561 *
562 * Example:
563 * if (p1) r31:30 = dealloc_return(r30):raw
564 */
565 #define fGEN_TCG_L4_return_t(SHORTCODE) \
566 gen_cond_return(ctx, RddV, RsV, PvV, TCG_COND_EQ);
567 #define fGEN_TCG_L4_return_f(SHORTCODE) \
568 gen_cond_return(ctx, RddV, RsV, PvV, TCG_COND_NE)
569 #define fGEN_TCG_L4_return_tnew_pt(SHORTCODE) \
570 gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_EQ)
571 #define fGEN_TCG_L4_return_fnew_pt(SHORTCODE) \
572 gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_NE)
573 #define fGEN_TCG_L4_return_tnew_pnt(SHORTCODE) \
574 gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_EQ)
575 #define fGEN_TCG_L4_return_fnew_pnt(SHORTCODE) \
576 gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_NE)
578 #define fGEN_TCG_SL2_return_t(SHORTCODE) \
579 gen_cond_return_subinsn(ctx, TCG_COND_EQ, hex_pred[0])
580 #define fGEN_TCG_SL2_return_f(SHORTCODE) \
581 gen_cond_return_subinsn(ctx, TCG_COND_NE, hex_pred[0])
582 #define fGEN_TCG_SL2_return_tnew(SHORTCODE) \
583 gen_cond_return_subinsn(ctx, TCG_COND_EQ, ctx->new_pred_value[0])
584 #define fGEN_TCG_SL2_return_fnew(SHORTCODE) \
585 gen_cond_return_subinsn(ctx, TCG_COND_NE, ctx->new_pred_value[0])
587 /*
588 * Mathematical operations with more than one definition require
589 * special handling
590 */
591 #define fGEN_TCG_A5_ACS(SHORTCODE) \
592 do { \
593 gen_helper_vacsh_pred(PeV, tcg_env, RxxV, RssV, RttV); \
594 gen_helper_vacsh_val(RxxV, tcg_env, RxxV, RssV, RttV, \
595 tcg_constant_tl(ctx->need_commit)); \
596 } while (0)
598 #define fGEN_TCG_S2_cabacdecbin(SHORTCODE) \
599 do { \
600 TCGv p0 = tcg_temp_new(); \
601 gen_helper_cabacdecbin_pred(p0, RssV, RttV); \
602 gen_helper_cabacdecbin_val(RddV, RssV, RttV); \
603 gen_log_pred_write(ctx, 0, p0); \
604 } while (0)
606 /*
607 * Approximate reciprocal
608 * r3,p1 = sfrecipa(r0, r1)
609 *
610 * The helper packs the 2 32-bit results into a 64-bit value,
611 * so unpack them into the proper results.
612 */
613 #define fGEN_TCG_F2_sfrecipa(SHORTCODE) \
614 do { \
615 TCGv_i64 tmp = tcg_temp_new_i64(); \
616 gen_helper_sfrecipa(tmp, tcg_env, RsV, RtV); \
617 tcg_gen_extrh_i64_i32(RdV, tmp); \
618 tcg_gen_extrl_i64_i32(PeV, tmp); \
619 } while (0)
621 /*
622 * Approximation of the reciprocal square root
623 * r1,p0 = sfinvsqrta(r0)
624 *
625 * The helper packs the 2 32-bit results into a 64-bit value,
626 * so unpack them into the proper results.
627 */
628 #define fGEN_TCG_F2_sfinvsqrta(SHORTCODE) \
629 do { \
630 TCGv_i64 tmp = tcg_temp_new_i64(); \
631 gen_helper_sfinvsqrta(tmp, tcg_env, RsV); \
632 tcg_gen_extrh_i64_i32(RdV, tmp); \
633 tcg_gen_extrl_i64_i32(PeV, tmp); \
634 } while (0)
636 /*
637 * Add or subtract with carry.
638 * Predicate register is used as an extra input and output.
639 * r5:4 = add(r1:0, r3:2, p1):carry
640 */
641 #define fGEN_TCG_A4_addp_c(SHORTCODE) \
642 do { \
643 TCGv_i64 carry = tcg_temp_new_i64(); \
644 TCGv_i64 zero = tcg_constant_i64(0); \
645 tcg_gen_extu_i32_i64(carry, PxV); \
646 tcg_gen_andi_i64(carry, carry, 1); \
647 tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \
648 tcg_gen_add2_i64(RddV, carry, RddV, carry, RttV, zero); \
649 tcg_gen_extrl_i64_i32(PxV, carry); \
650 gen_8bitsof(PxV, PxV); \
651 } while (0)
653 /* r5:4 = sub(r1:0, r3:2, p1):carry */
654 #define fGEN_TCG_A4_subp_c(SHORTCODE) \
655 do { \
656 TCGv_i64 carry = tcg_temp_new_i64(); \
657 TCGv_i64 zero = tcg_constant_i64(0); \
658 TCGv_i64 not_RttV = tcg_temp_new_i64(); \
659 tcg_gen_extu_i32_i64(carry, PxV); \
660 tcg_gen_andi_i64(carry, carry, 1); \
661 tcg_gen_not_i64(not_RttV, RttV); \
662 tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \
663 tcg_gen_add2_i64(RddV, carry, RddV, carry, not_RttV, zero); \
664 tcg_gen_extrl_i64_i32(PxV, carry); \
665 gen_8bitsof(PxV, PxV); \
666 } while (0)
668 /*
669 * Compare each of the 8 unsigned bytes
670 * The minimum is placed in each byte of the destination.
671 * Each bit of the predicate is set true if the bit from the first operand
672 * is greater than the bit from the second operand.
673 * r5:4,p1 = vminub(r1:0, r3:2)
674 */
675 #define fGEN_TCG_A6_vminub_RdP(SHORTCODE) \
676 do { \
677 TCGv left = tcg_temp_new(); \
678 TCGv right = tcg_temp_new(); \
679 TCGv tmp = tcg_temp_new(); \
680 tcg_gen_movi_tl(PeV, 0); \
681 tcg_gen_movi_i64(RddV, 0); \
682 for (int i = 0; i < 8; i++) { \
683 gen_get_byte_i64(left, i, RttV, false); \
684 gen_get_byte_i64(right, i, RssV, false); \
685 tcg_gen_setcond_tl(TCG_COND_GT, tmp, left, right); \
686 tcg_gen_deposit_tl(PeV, PeV, tmp, i, 1); \
687 tcg_gen_umin_tl(tmp, left, right); \
688 gen_set_byte_i64(i, RddV, tmp); \
689 } \
690 } while (0)
692 #define fGEN_TCG_J2_call(SHORTCODE) \
693 gen_call(ctx, riV)
694 #define fGEN_TCG_J2_callr(SHORTCODE) \
695 gen_callr(ctx, RsV)
696 #define fGEN_TCG_J2_callrh(SHORTCODE) \
697 gen_callr(ctx, RsV)
699 #define fGEN_TCG_J2_callt(SHORTCODE) \
700 gen_cond_call(ctx, PuV, TCG_COND_EQ, riV)
701 #define fGEN_TCG_J2_callf(SHORTCODE) \
702 gen_cond_call(ctx, PuV, TCG_COND_NE, riV)
703 #define fGEN_TCG_J2_callrt(SHORTCODE) \
704 gen_cond_callr(ctx, TCG_COND_EQ, PuV, RsV)
705 #define fGEN_TCG_J2_callrf(SHORTCODE) \
706 gen_cond_callr(ctx, TCG_COND_NE, PuV, RsV)
708 #define fGEN_TCG_J2_loop0r(SHORTCODE) \
709 gen_loop0r(ctx, RsV, riV)
710 #define fGEN_TCG_J2_loop1r(SHORTCODE) \
711 gen_loop1r(ctx, RsV, riV)
712 #define fGEN_TCG_J2_loop0i(SHORTCODE) \
713 gen_loop0i(ctx, UiV, riV)
714 #define fGEN_TCG_J2_loop1i(SHORTCODE) \
715 gen_loop1i(ctx, UiV, riV)
716 #define fGEN_TCG_J2_ploop1sr(SHORTCODE) \
717 gen_ploopNsr(ctx, 1, RsV, riV)
718 #define fGEN_TCG_J2_ploop1si(SHORTCODE) \
719 gen_ploopNsi(ctx, 1, UiV, riV)
720 #define fGEN_TCG_J2_ploop2sr(SHORTCODE) \
721 gen_ploopNsr(ctx, 2, RsV, riV)
722 #define fGEN_TCG_J2_ploop2si(SHORTCODE) \
723 gen_ploopNsi(ctx, 2, UiV, riV)
724 #define fGEN_TCG_J2_ploop3sr(SHORTCODE) \
725 gen_ploopNsr(ctx, 3, RsV, riV)
726 #define fGEN_TCG_J2_ploop3si(SHORTCODE) \
727 gen_ploopNsi(ctx, 3, UiV, riV)
729 #define fGEN_TCG_J2_endloop0(SHORTCODE) \
730 gen_endloop0(ctx)
731 #define fGEN_TCG_J2_endloop1(SHORTCODE) \
732 gen_endloop1(ctx)
733 #define fGEN_TCG_J2_endloop01(SHORTCODE) \
734 gen_endloop01(ctx)
736 /*
737 * Compound compare and jump instructions
738 * Here is a primer to understand the tag names
739 *
740 * Comparison
741 * cmpeqi compare equal to an immediate
742 * cmpgti compare greater than an immediate
743 * cmpgtiu compare greater than an unsigned immediate
744 * cmpeqn1 compare equal to negative 1
745 * cmpgtn1 compare greater than negative 1
746 * cmpeq compare equal (two registers)
747 * cmpgtu compare greater than unsigned (two registers)
748 * tstbit0 test bit zero
749 *
750 * Condition
751 * tp0 p0 is true p0 = cmp.eq(r0,#5); if (p0.new) jump:nt address
752 * fp0 p0 is false p0 = cmp.eq(r0,#5); if (!p0.new) jump:nt address
753 * tp1 p1 is true p1 = cmp.eq(r0,#5); if (p1.new) jump:nt address
754 * fp1 p1 is false p1 = cmp.eq(r0,#5); if (!p1.new) jump:nt address
755 *
756 * Prediction (not modelled in qemu)
757 * _nt not taken
758 * _t taken
759 */
760 #define fGEN_TCG_J4_cmpeq_tp0_jump_t(SHORTCODE) \
761 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_EQ, RsV, RtV, riV)
762 #define fGEN_TCG_J4_cmpeq_tp0_jump_nt(SHORTCODE) \
763 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_EQ, RsV, RtV, riV)
764 #define fGEN_TCG_J4_cmpeq_fp0_jump_t(SHORTCODE) \
765 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_EQ, RsV, RtV, riV)
766 #define fGEN_TCG_J4_cmpeq_fp0_jump_nt(SHORTCODE) \
767 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_EQ, RsV, RtV, riV)
768 #define fGEN_TCG_J4_cmpeq_tp1_jump_t(SHORTCODE) \
769 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_EQ, RsV, RtV, riV)
770 #define fGEN_TCG_J4_cmpeq_tp1_jump_nt(SHORTCODE) \
771 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_EQ, RsV, RtV, riV)
772 #define fGEN_TCG_J4_cmpeq_fp1_jump_t(SHORTCODE) \
773 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_EQ, RsV, RtV, riV)
774 #define fGEN_TCG_J4_cmpeq_fp1_jump_nt(SHORTCODE) \
775 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_EQ, RsV, RtV, riV)
777 #define fGEN_TCG_J4_cmpgt_tp0_jump_t(SHORTCODE) \
778 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GT, RsV, RtV, riV)
779 #define fGEN_TCG_J4_cmpgt_tp0_jump_nt(SHORTCODE) \
780 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GT, RsV, RtV, riV)
781 #define fGEN_TCG_J4_cmpgt_fp0_jump_t(SHORTCODE) \
782 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GT, RsV, RtV, riV)
783 #define fGEN_TCG_J4_cmpgt_fp0_jump_nt(SHORTCODE) \
784 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GT, RsV, RtV, riV)
785 #define fGEN_TCG_J4_cmpgt_tp1_jump_t(SHORTCODE) \
786 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GT, RsV, RtV, riV)
787 #define fGEN_TCG_J4_cmpgt_tp1_jump_nt(SHORTCODE) \
788 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GT, RsV, RtV, riV)
789 #define fGEN_TCG_J4_cmpgt_fp1_jump_t(SHORTCODE) \
790 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GT, RsV, RtV, riV)
791 #define fGEN_TCG_J4_cmpgt_fp1_jump_nt(SHORTCODE) \
792 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GT, RsV, RtV, riV)
794 #define fGEN_TCG_J4_cmpgtu_tp0_jump_t(SHORTCODE) \
795 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GTU, RsV, RtV, riV)
796 #define fGEN_TCG_J4_cmpgtu_tp0_jump_nt(SHORTCODE) \
797 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GTU, RsV, RtV, riV)
798 #define fGEN_TCG_J4_cmpgtu_fp0_jump_t(SHORTCODE) \
799 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GTU, RsV, RtV, riV)
800 #define fGEN_TCG_J4_cmpgtu_fp0_jump_nt(SHORTCODE) \
801 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GTU, RsV, RtV, riV)
802 #define fGEN_TCG_J4_cmpgtu_tp1_jump_t(SHORTCODE) \
803 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GTU, RsV, RtV, riV)
804 #define fGEN_TCG_J4_cmpgtu_tp1_jump_nt(SHORTCODE) \
805 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GTU, RsV, RtV, riV)
806 #define fGEN_TCG_J4_cmpgtu_fp1_jump_t(SHORTCODE) \
807 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GTU, RsV, RtV, riV)
808 #define fGEN_TCG_J4_cmpgtu_fp1_jump_nt(SHORTCODE) \
809 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GTU, RsV, RtV, riV)
811 #define fGEN_TCG_J4_cmpeqi_tp0_jump_t(SHORTCODE) \
812 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_EQ, RsV, UiV, riV)
813 #define fGEN_TCG_J4_cmpeqi_tp0_jump_nt(SHORTCODE) \
814 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_EQ, RsV, UiV, riV)
815 #define fGEN_TCG_J4_cmpeqi_fp0_jump_t(SHORTCODE) \
816 gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_EQ, RsV, UiV, riV)
817 #define fGEN_TCG_J4_cmpeqi_fp0_jump_nt(SHORTCODE) \
818 gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_EQ, RsV, UiV, riV)
819 #define fGEN_TCG_J4_cmpeqi_tp1_jump_t(SHORTCODE) \
820 gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_EQ, RsV, UiV, riV)
821 #define fGEN_TCG_J4_cmpeqi_tp1_jump_nt(SHORTCODE) \
822 gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_EQ, RsV, UiV, riV)
823 #define fGEN_TCG_J4_cmpeqi_fp1_jump_t(SHORTCODE) \
824 gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_EQ, RsV, UiV, riV)
825 #define fGEN_TCG_J4_cmpeqi_fp1_jump_nt(SHORTCODE) \
826 gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_EQ, RsV, UiV, riV)
828 #define fGEN_TCG_J4_cmpgti_tp0_jump_t(SHORTCODE) \
829 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_GT, RsV, UiV, riV)
830 #define fGEN_TCG_J4_cmpgti_tp0_jump_nt(SHORTCODE) \
831 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_GT, RsV, UiV, riV)
832 #define fGEN_TCG_J4_cmpgti_fp0_jump_t(SHORTCODE) \
833 gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_GT, RsV, UiV, riV)
834 #define fGEN_TCG_J4_cmpgti_fp0_jump_nt(SHORTCODE) \
835 gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_GT, RsV, UiV, riV)
836 #define fGEN_TCG_J4_cmpgti_tp1_jump_t(SHORTCODE) \
837 gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_GT, RsV, UiV, riV)
838 #define fGEN_TCG_J4_cmpgti_tp1_jump_nt(SHORTCODE) \
839 gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_GT, RsV, UiV, riV)
840 #define fGEN_TCG_J4_cmpgti_fp1_jump_t(SHORTCODE) \
841 gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_GT, RsV, UiV, riV)
842 #define fGEN_TCG_J4_cmpgti_fp1_jump_nt(SHORTCODE) \
843 gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_GT, RsV, UiV, riV)
845 #define fGEN_TCG_J4_cmpgtui_tp0_jump_t(SHORTCODE) \
846 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_GTU, RsV, UiV, riV)
847 #define fGEN_TCG_J4_cmpgtui_tp0_jump_nt(SHORTCODE) \
848 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_GTU, RsV, UiV, riV)
849 #define fGEN_TCG_J4_cmpgtui_fp0_jump_t(SHORTCODE) \
850 gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_GTU, RsV, UiV, riV)
851 #define fGEN_TCG_J4_cmpgtui_fp0_jump_nt(SHORTCODE) \
852 gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_GTU, RsV, UiV, riV)
853 #define fGEN_TCG_J4_cmpgtui_tp1_jump_t(SHORTCODE) \
854 gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_GTU, RsV, UiV, riV)
855 #define fGEN_TCG_J4_cmpgtui_tp1_jump_nt(SHORTCODE) \
856 gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_GTU, RsV, UiV, riV)
857 #define fGEN_TCG_J4_cmpgtui_fp1_jump_t(SHORTCODE) \
858 gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_GTU, RsV, UiV, riV)
859 #define fGEN_TCG_J4_cmpgtui_fp1_jump_nt(SHORTCODE) \
860 gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_GTU, RsV, UiV, riV)
862 #define fGEN_TCG_J4_cmpeqn1_tp0_jump_t(SHORTCODE) \
863 gen_cmpnd_cmp_n1_jmp_t(ctx, 0, TCG_COND_EQ, RsV, riV)
864 #define fGEN_TCG_J4_cmpeqn1_tp0_jump_nt(SHORTCODE) \
865 gen_cmpnd_cmp_n1_jmp_t(ctx, 0, TCG_COND_EQ, RsV, riV)
866 #define fGEN_TCG_J4_cmpeqn1_fp0_jump_t(SHORTCODE) \
867 gen_cmpnd_cmp_n1_jmp_f(ctx, 0, TCG_COND_EQ, RsV, riV)
868 #define fGEN_TCG_J4_cmpeqn1_fp0_jump_nt(SHORTCODE) \
869 gen_cmpnd_cmp_n1_jmp_f(ctx, 0, TCG_COND_EQ, RsV, riV)
870 #define fGEN_TCG_J4_cmpeqn1_tp1_jump_t(SHORTCODE) \
871 gen_cmpnd_cmp_n1_jmp_t(ctx, 1, TCG_COND_EQ, RsV, riV)
872 #define fGEN_TCG_J4_cmpeqn1_tp1_jump_nt(SHORTCODE) \
873 gen_cmpnd_cmp_n1_jmp_t(ctx, 1, TCG_COND_EQ, RsV, riV)
874 #define fGEN_TCG_J4_cmpeqn1_fp1_jump_t(SHORTCODE) \
875 gen_cmpnd_cmp_n1_jmp_f(ctx, 1, TCG_COND_EQ, RsV, riV)
876 #define fGEN_TCG_J4_cmpeqn1_fp1_jump_nt(SHORTCODE) \
877 gen_cmpnd_cmp_n1_jmp_f(ctx, 1, TCG_COND_EQ, RsV, riV)
879 #define fGEN_TCG_J4_cmpgtn1_tp0_jump_t(SHORTCODE) \
880 gen_cmpnd_cmp_n1_jmp_t(ctx, 0, TCG_COND_GT, RsV, riV)
881 #define fGEN_TCG_J4_cmpgtn1_tp0_jump_nt(SHORTCODE) \
882 gen_cmpnd_cmp_n1_jmp_t(ctx, 0, TCG_COND_GT, RsV, riV)
883 #define fGEN_TCG_J4_cmpgtn1_fp0_jump_t(SHORTCODE) \
884 gen_cmpnd_cmp_n1_jmp_f(ctx, 0, TCG_COND_GT, RsV, riV)
885 #define fGEN_TCG_J4_cmpgtn1_fp0_jump_nt(SHORTCODE) \
886 gen_cmpnd_cmp_n1_jmp_f(ctx, 0, TCG_COND_GT, RsV, riV)
887 #define fGEN_TCG_J4_cmpgtn1_tp1_jump_t(SHORTCODE) \
888 gen_cmpnd_cmp_n1_jmp_t(ctx, 1, TCG_COND_GT, RsV, riV)
889 #define fGEN_TCG_J4_cmpgtn1_tp1_jump_nt(SHORTCODE) \
890 gen_cmpnd_cmp_n1_jmp_t(ctx, 1, TCG_COND_GT, RsV, riV)
891 #define fGEN_TCG_J4_cmpgtn1_fp1_jump_t(SHORTCODE) \
892 gen_cmpnd_cmp_n1_jmp_f(ctx, 1, TCG_COND_GT, RsV, riV)
893 #define fGEN_TCG_J4_cmpgtn1_fp1_jump_nt(SHORTCODE) \
894 gen_cmpnd_cmp_n1_jmp_f(ctx, 1, TCG_COND_GT, RsV, riV)
896 #define fGEN_TCG_J4_tstbit0_tp0_jump_nt(SHORTCODE) \
897 gen_cmpnd_tstbit0_jmp(ctx, 0, RsV, TCG_COND_EQ, riV)
898 #define fGEN_TCG_J4_tstbit0_tp0_jump_t(SHORTCODE) \
899 gen_cmpnd_tstbit0_jmp(ctx, 0, RsV, TCG_COND_EQ, riV)
900 #define fGEN_TCG_J4_tstbit0_fp0_jump_nt(SHORTCODE) \
901 gen_cmpnd_tstbit0_jmp(ctx, 0, RsV, TCG_COND_NE, riV)
902 #define fGEN_TCG_J4_tstbit0_fp0_jump_t(SHORTCODE) \
903 gen_cmpnd_tstbit0_jmp(ctx, 0, RsV, TCG_COND_NE, riV)
904 #define fGEN_TCG_J4_tstbit0_tp1_jump_nt(SHORTCODE) \
905 gen_cmpnd_tstbit0_jmp(ctx, 1, RsV, TCG_COND_EQ, riV)
906 #define fGEN_TCG_J4_tstbit0_tp1_jump_t(SHORTCODE) \
907 gen_cmpnd_tstbit0_jmp(ctx, 1, RsV, TCG_COND_EQ, riV)
908 #define fGEN_TCG_J4_tstbit0_fp1_jump_nt(SHORTCODE) \
909 gen_cmpnd_tstbit0_jmp(ctx, 1, RsV, TCG_COND_NE, riV)
910 #define fGEN_TCG_J4_tstbit0_fp1_jump_t(SHORTCODE) \
911 gen_cmpnd_tstbit0_jmp(ctx, 1, RsV, TCG_COND_NE, riV)
913 /* p0 = cmp.eq(r0, #7) */
914 #define fGEN_TCG_SA1_cmpeqi(SHORTCODE) \
915 do { \
916 TCGv p0 = tcg_temp_new(); \
917 gen_comparei(TCG_COND_EQ, p0, RsV, uiV); \
918 gen_log_pred_write(ctx, 0, p0); \
919 } while (0)
921 #define fGEN_TCG_J2_jump(SHORTCODE) \
922 gen_jump(ctx, riV)
923 #define fGEN_TCG_J2_jumpr(SHORTCODE) \
924 gen_jumpr(ctx, RsV)
925 #define fGEN_TCG_J2_jumprh(SHORTCODE) \
926 gen_jumpr(ctx, RsV)
927 #define fGEN_TCG_J4_jumpseti(SHORTCODE) \
928 do { \
929 tcg_gen_movi_tl(RdV, UiV); \
930 gen_jump(ctx, riV); \
931 } while (0)
933 #define fGEN_TCG_cond_jumpt(COND) \
934 do { \
935 TCGv LSB = tcg_temp_new(); \
936 COND; \
937 gen_cond_jump(ctx, TCG_COND_EQ, LSB, riV); \
938 } while (0)
939 #define fGEN_TCG_cond_jumpf(COND) \
940 do { \
941 TCGv LSB = tcg_temp_new(); \
942 COND; \
943 gen_cond_jump(ctx, TCG_COND_NE, LSB, riV); \
944 } while (0)
946 #define fGEN_TCG_J2_jumpt(SHORTCODE) \
947 fGEN_TCG_cond_jumpt(fLSBOLD(PuV))
948 #define fGEN_TCG_J2_jumptpt(SHORTCODE) \
949 fGEN_TCG_cond_jumpt(fLSBOLD(PuV))
950 #define fGEN_TCG_J2_jumpf(SHORTCODE) \
951 fGEN_TCG_cond_jumpf(fLSBOLD(PuV))
952 #define fGEN_TCG_J2_jumpfpt(SHORTCODE) \
953 fGEN_TCG_cond_jumpf(fLSBOLD(PuV))
954 #define fGEN_TCG_J2_jumptnew(SHORTCODE) \
955 gen_cond_jump(ctx, TCG_COND_EQ, PuN, riV)
956 #define fGEN_TCG_J2_jumptnewpt(SHORTCODE) \
957 gen_cond_jump(ctx, TCG_COND_EQ, PuN, riV)
958 #define fGEN_TCG_J2_jumpfnewpt(SHORTCODE) \
959 fGEN_TCG_cond_jumpf(fLSBNEW(PuN))
960 #define fGEN_TCG_J2_jumpfnew(SHORTCODE) \
961 fGEN_TCG_cond_jumpf(fLSBNEW(PuN))
962 #define fGEN_TCG_J2_jumprz(SHORTCODE) \
963 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_NE, LSB, RsV, 0))
964 #define fGEN_TCG_J2_jumprzpt(SHORTCODE) \
965 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_NE, LSB, RsV, 0))
966 #define fGEN_TCG_J2_jumprnz(SHORTCODE) \
967 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_EQ, LSB, RsV, 0))
968 #define fGEN_TCG_J2_jumprnzpt(SHORTCODE) \
969 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_EQ, LSB, RsV, 0))
970 #define fGEN_TCG_J2_jumprgtez(SHORTCODE) \
971 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_GE, LSB, RsV, 0))
972 #define fGEN_TCG_J2_jumprgtezpt(SHORTCODE) \
973 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_GE, LSB, RsV, 0))
974 #define fGEN_TCG_J2_jumprltez(SHORTCODE) \
975 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_LE, LSB, RsV, 0))
976 #define fGEN_TCG_J2_jumprltezpt(SHORTCODE) \
977 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_LE, LSB, RsV, 0))
979 #define fGEN_TCG_cond_jumprt(COND) \
980 do { \
981 TCGv LSB = tcg_temp_new(); \
982 COND; \
983 gen_cond_jumpr(ctx, RsV, TCG_COND_EQ, LSB); \
984 } while (0)
985 #define fGEN_TCG_cond_jumprf(COND) \
986 do { \
987 TCGv LSB = tcg_temp_new(); \
988 COND; \
989 gen_cond_jumpr(ctx, RsV, TCG_COND_NE, LSB); \
990 } while (0)
992 #define fGEN_TCG_J2_jumprt(SHORTCODE) \
993 fGEN_TCG_cond_jumprt(fLSBOLD(PuV))
994 #define fGEN_TCG_J2_jumprtpt(SHORTCODE) \
995 fGEN_TCG_cond_jumprt(fLSBOLD(PuV))
996 #define fGEN_TCG_J2_jumprf(SHORTCODE) \
997 fGEN_TCG_cond_jumprf(fLSBOLD(PuV))
998 #define fGEN_TCG_J2_jumprfpt(SHORTCODE) \
999 fGEN_TCG_cond_jumprf(fLSBOLD(PuV))
1000 #define fGEN_TCG_J2_jumprtnew(SHORTCODE) \
1001 fGEN_TCG_cond_jumprt(fLSBNEW(PuN))
1002 #define fGEN_TCG_J2_jumprtnewpt(SHORTCODE) \
1003 fGEN_TCG_cond_jumprt(fLSBNEW(PuN))
1004 #define fGEN_TCG_J2_jumprfnew(SHORTCODE) \
1005 fGEN_TCG_cond_jumprf(fLSBNEW(PuN))
1006 #define fGEN_TCG_J2_jumprfnewpt(SHORTCODE) \
1007 fGEN_TCG_cond_jumprf(fLSBNEW(PuN))
1009 /*
1010 * New value compare & jump instructions
1011 * if ([!]COND(r0.new, r1) jump:t address
1012 * if ([!]COND(r0.new, #7) jump:t address
1013 */
1014 #define fGEN_TCG_J4_cmpgt_t_jumpnv_t(SHORTCODE) \
1015 gen_cmp_jumpnv(ctx, TCG_COND_GT, NsN, RtV, riV)
1016 #define fGEN_TCG_J4_cmpgt_t_jumpnv_nt(SHORTCODE) \
1017 gen_cmp_jumpnv(ctx, TCG_COND_GT, NsN, RtV, riV)
1018 #define fGEN_TCG_J4_cmpgt_f_jumpnv_t(SHORTCODE) \
1019 gen_cmp_jumpnv(ctx, TCG_COND_LE, NsN, RtV, riV)
1020 #define fGEN_TCG_J4_cmpgt_f_jumpnv_nt(SHORTCODE) \
1021 gen_cmp_jumpnv(ctx, TCG_COND_LE, NsN, RtV, riV)
1023 #define fGEN_TCG_J4_cmpeq_t_jumpnv_t(SHORTCODE) \
1024 gen_cmp_jumpnv(ctx, TCG_COND_EQ, NsN, RtV, riV)
1025 #define fGEN_TCG_J4_cmpeq_t_jumpnv_nt(SHORTCODE) \
1026 gen_cmp_jumpnv(ctx, TCG_COND_EQ, NsN, RtV, riV)
1027 #define fGEN_TCG_J4_cmpeq_f_jumpnv_t(SHORTCODE) \
1028 gen_cmp_jumpnv(ctx, TCG_COND_NE, NsN, RtV, riV)
1029 #define fGEN_TCG_J4_cmpeq_f_jumpnv_nt(SHORTCODE) \
1030 gen_cmp_jumpnv(ctx, TCG_COND_NE, NsN, RtV, riV)
1032 #define fGEN_TCG_J4_cmplt_t_jumpnv_t(SHORTCODE) \
1033 gen_cmp_jumpnv(ctx, TCG_COND_LT, NsN, RtV, riV)
1034 #define fGEN_TCG_J4_cmplt_t_jumpnv_nt(SHORTCODE) \
1035 gen_cmp_jumpnv(ctx, TCG_COND_LT, NsN, RtV, riV)
1036 #define fGEN_TCG_J4_cmplt_f_jumpnv_t(SHORTCODE) \
1037 gen_cmp_jumpnv(ctx, TCG_COND_GE, NsN, RtV, riV)
1038 #define fGEN_TCG_J4_cmplt_f_jumpnv_nt(SHORTCODE) \
1039 gen_cmp_jumpnv(ctx, TCG_COND_GE, NsN, RtV, riV)
1041 #define fGEN_TCG_J4_cmpeqi_t_jumpnv_t(SHORTCODE) \
1042 gen_cmpi_jumpnv(ctx, TCG_COND_EQ, NsN, UiV, riV)
1043 #define fGEN_TCG_J4_cmpeqi_t_jumpnv_nt(SHORTCODE) \
1044 gen_cmpi_jumpnv(ctx, TCG_COND_EQ, NsN, UiV, riV)
1045 #define fGEN_TCG_J4_cmpeqi_f_jumpnv_t(SHORTCODE) \
1046 gen_cmpi_jumpnv(ctx, TCG_COND_NE, NsN, UiV, riV)
1047 #define fGEN_TCG_J4_cmpeqi_f_jumpnv_nt(SHORTCODE) \
1048 gen_cmpi_jumpnv(ctx, TCG_COND_NE, NsN, UiV, riV)
1050 #define fGEN_TCG_J4_cmpgti_t_jumpnv_t(SHORTCODE) \
1051 gen_cmpi_jumpnv(ctx, TCG_COND_GT, NsN, UiV, riV)
1052 #define fGEN_TCG_J4_cmpgti_t_jumpnv_nt(SHORTCODE) \
1053 gen_cmpi_jumpnv(ctx, TCG_COND_GT, NsN, UiV, riV)
1054 #define fGEN_TCG_J4_cmpgti_f_jumpnv_t(SHORTCODE) \
1055 gen_cmpi_jumpnv(ctx, TCG_COND_LE, NsN, UiV, riV)
1056 #define fGEN_TCG_J4_cmpgti_f_jumpnv_nt(SHORTCODE) \
1057 gen_cmpi_jumpnv(ctx, TCG_COND_LE, NsN, UiV, riV)
1059 #define fGEN_TCG_J4_cmpltu_t_jumpnv_t(SHORTCODE) \
1060 gen_cmp_jumpnv(ctx, TCG_COND_LTU, NsN, RtV, riV)
1061 #define fGEN_TCG_J4_cmpltu_t_jumpnv_nt(SHORTCODE) \
1062 gen_cmp_jumpnv(ctx, TCG_COND_LTU, NsN, RtV, riV)
1063 #define fGEN_TCG_J4_cmpltu_f_jumpnv_t(SHORTCODE) \
1064 gen_cmp_jumpnv(ctx, TCG_COND_GEU, NsN, RtV, riV)
1065 #define fGEN_TCG_J4_cmpltu_f_jumpnv_nt(SHORTCODE) \
1066 gen_cmp_jumpnv(ctx, TCG_COND_GEU, NsN, RtV, riV)
1068 #define fGEN_TCG_J4_cmpgtui_t_jumpnv_t(SHORTCODE) \
1069 gen_cmpi_jumpnv(ctx, TCG_COND_GTU, NsN, UiV, riV)
1070 #define fGEN_TCG_J4_cmpgtui_t_jumpnv_nt(SHORTCODE) \
1071 gen_cmpi_jumpnv(ctx, TCG_COND_GTU, NsN, UiV, riV)
1072 #define fGEN_TCG_J4_cmpgtui_f_jumpnv_t(SHORTCODE) \
1073 gen_cmpi_jumpnv(ctx, TCG_COND_LEU, NsN, UiV, riV)
1074 #define fGEN_TCG_J4_cmpgtui_f_jumpnv_nt(SHORTCODE) \
1075 gen_cmpi_jumpnv(ctx, TCG_COND_LEU, NsN, UiV, riV)
1077 #define fGEN_TCG_J4_cmpgtu_t_jumpnv_t(SHORTCODE) \
1078 gen_cmp_jumpnv(ctx, TCG_COND_GTU, NsN, RtV, riV)
1079 #define fGEN_TCG_J4_cmpgtu_t_jumpnv_nt(SHORTCODE) \
1080 gen_cmp_jumpnv(ctx, TCG_COND_GTU, NsN, RtV, riV)
1081 #define fGEN_TCG_J4_cmpgtu_f_jumpnv_t(SHORTCODE) \
1082 gen_cmp_jumpnv(ctx, TCG_COND_LEU, NsN, RtV, riV)
1083 #define fGEN_TCG_J4_cmpgtu_f_jumpnv_nt(SHORTCODE) \
1084 gen_cmp_jumpnv(ctx, TCG_COND_LEU, NsN, RtV, riV)
1086 #define fGEN_TCG_J4_cmpeqn1_t_jumpnv_t(SHORTCODE) \
1087 gen_cmpi_jumpnv(ctx, TCG_COND_EQ, NsN, -1, riV)
1088 #define fGEN_TCG_J4_cmpeqn1_t_jumpnv_nt(SHORTCODE) \
1089 gen_cmpi_jumpnv(ctx, TCG_COND_EQ, NsN, -1, riV)
1090 #define fGEN_TCG_J4_cmpeqn1_f_jumpnv_t(SHORTCODE) \
1091 gen_cmpi_jumpnv(ctx, TCG_COND_NE, NsN, -1, riV)
1092 #define fGEN_TCG_J4_cmpeqn1_f_jumpnv_nt(SHORTCODE) \
1093 gen_cmpi_jumpnv(ctx, TCG_COND_NE, NsN, -1, riV)
1095 #define fGEN_TCG_J4_cmpgtn1_t_jumpnv_t(SHORTCODE) \
1096 gen_cmpi_jumpnv(ctx, TCG_COND_GT, NsN, -1, riV)
1097 #define fGEN_TCG_J4_cmpgtn1_t_jumpnv_nt(SHORTCODE) \
1098 gen_cmpi_jumpnv(ctx, TCG_COND_GT, NsN, -1, riV)
1099 #define fGEN_TCG_J4_cmpgtn1_f_jumpnv_t(SHORTCODE) \
1100 gen_cmpi_jumpnv(ctx, TCG_COND_LE, NsN, -1, riV)
1101 #define fGEN_TCG_J4_cmpgtn1_f_jumpnv_nt(SHORTCODE) \
1102 gen_cmpi_jumpnv(ctx, TCG_COND_LE, NsN, -1, riV)
1104 #define fGEN_TCG_J4_tstbit0_t_jumpnv_t(SHORTCODE) \
1105 gen_testbit0_jumpnv(ctx, NsN, TCG_COND_EQ, riV)
1106 #define fGEN_TCG_J4_tstbit0_t_jumpnv_nt(SHORTCODE) \
1107 gen_testbit0_jumpnv(ctx, NsN, TCG_COND_EQ, riV)
1108 #define fGEN_TCG_J4_tstbit0_f_jumpnv_t(SHORTCODE) \
1109 gen_testbit0_jumpnv(ctx, NsN, TCG_COND_NE, riV)
1110 #define fGEN_TCG_J4_tstbit0_f_jumpnv_nt(SHORTCODE) \
1111 gen_testbit0_jumpnv(ctx, NsN, TCG_COND_NE, riV)
1113 /* r0 = r1 ; jump address */
1114 #define fGEN_TCG_J4_jumpsetr(SHORTCODE) \
1115 do { \
1116 tcg_gen_mov_tl(RdV, RsV); \
1117 gen_jump(ctx, riV); \
1118 } while (0)
1120 /* if (p0.new) r0 = #0 */
1121 #define fGEN_TCG_SA1_clrtnew(SHORTCODE) \
1122 do { \
1123 tcg_gen_movcond_tl(TCG_COND_EQ, RdV, \
1124 ctx->new_pred_value[0], tcg_constant_tl(0), \
1125 RdV, tcg_constant_tl(0)); \
1126 } while (0)
1128 /* if (!p0.new) r0 = #0 */
1129 #define fGEN_TCG_SA1_clrfnew(SHORTCODE) \
1130 do { \
1131 tcg_gen_movcond_tl(TCG_COND_NE, RdV, \
1132 ctx->new_pred_value[0], tcg_constant_tl(0), \
1133 RdV, tcg_constant_tl(0)); \
1134 } while (0)
1136 #define fGEN_TCG_J2_pause(SHORTCODE) \
1137 do { \
1138 uiV = uiV; \
1139 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->next_PC); \
1140 } while (0)
1142 /* r0 = asr(r1, r2):sat */
1143 #define fGEN_TCG_S2_asr_r_r_sat(SHORTCODE) \
1144 gen_asr_r_r_sat(ctx, RdV, RsV, RtV)
1146 /* r0 = asl(r1, r2):sat */
1147 #define fGEN_TCG_S2_asl_r_r_sat(SHORTCODE) \
1148 gen_asl_r_r_sat(ctx, RdV, RsV, RtV)
1150 #define fGEN_TCG_SL2_jumpr31(SHORTCODE) \
1151 gen_jumpr(ctx, hex_gpr[HEX_REG_LR])
1153 #define fGEN_TCG_SL2_jumpr31_t(SHORTCODE) \
1154 gen_cond_jumpr31(ctx, TCG_COND_EQ, hex_pred[0])
1155 #define fGEN_TCG_SL2_jumpr31_f(SHORTCODE) \
1156 gen_cond_jumpr31(ctx, TCG_COND_NE, hex_pred[0])
1158 #define fGEN_TCG_SL2_jumpr31_tnew(SHORTCODE) \
1159 gen_cond_jumpr31(ctx, TCG_COND_EQ, ctx->new_pred_value[0])
1160 #define fGEN_TCG_SL2_jumpr31_fnew(SHORTCODE) \
1161 gen_cond_jumpr31(ctx, TCG_COND_NE, ctx->new_pred_value[0])
1163 /* Count trailing zeros/ones */
1164 #define fGEN_TCG_S2_ct0(SHORTCODE) \
1165 do { \
1166 tcg_gen_ctzi_tl(RdV, RsV, 32); \
1167 } while (0)
1168 #define fGEN_TCG_S2_ct1(SHORTCODE) \
1169 do { \
1170 tcg_gen_not_tl(RdV, RsV); \
1171 tcg_gen_ctzi_tl(RdV, RdV, 32); \
1172 } while (0)
1173 #define fGEN_TCG_S2_ct0p(SHORTCODE) \
1174 do { \
1175 TCGv_i64 tmp = tcg_temp_new_i64(); \
1176 tcg_gen_ctzi_i64(tmp, RssV, 64); \
1177 tcg_gen_extrl_i64_i32(RdV, tmp); \
1178 } while (0)
1179 #define fGEN_TCG_S2_ct1p(SHORTCODE) \
1180 do { \
1181 TCGv_i64 tmp = tcg_temp_new_i64(); \
1182 tcg_gen_not_i64(tmp, RssV); \
1183 tcg_gen_ctzi_i64(tmp, tmp, 64); \
1184 tcg_gen_extrl_i64_i32(RdV, tmp); \
1185 } while (0)
1187 #define fGEN_TCG_S2_insert(SHORTCODE) \
1188 do { \
1189 int width = uiV; \
1190 int offset = UiV; \
1191 if (width != 0) { \
1192 if (offset + width > 32) { \
1193 width = 32 - offset; \
1194 } \
1195 tcg_gen_deposit_tl(RxV, RxV, RsV, offset, width); \
1196 } \
1197 } while (0)
1198 #define fGEN_TCG_S2_insert_rp(SHORTCODE) \
1199 gen_insert_rp(ctx, RxV, RsV, RttV)
1200 #define fGEN_TCG_S2_asr_r_svw_trun(SHORTCODE) \
1201 gen_asr_r_svw_trun(ctx, RdV, RssV, RtV)
1202 #define fGEN_TCG_A2_swiz(SHORTCODE) \
1203 tcg_gen_bswap_tl(RdV, RsV)
1205 /* Floating point */
1206 #define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
1207 gen_helper_conv_sf2df(RddV, tcg_env, RsV)
1208 #define fGEN_TCG_F2_conv_df2sf(SHORTCODE) \
1209 gen_helper_conv_df2sf(RdV, tcg_env, RssV)
1210 #define fGEN_TCG_F2_conv_uw2sf(SHORTCODE) \
1211 gen_helper_conv_uw2sf(RdV, tcg_env, RsV)
1212 #define fGEN_TCG_F2_conv_uw2df(SHORTCODE) \
1213 gen_helper_conv_uw2df(RddV, tcg_env, RsV)
1214 #define fGEN_TCG_F2_conv_w2sf(SHORTCODE) \
1215 gen_helper_conv_w2sf(RdV, tcg_env, RsV)
1216 #define fGEN_TCG_F2_conv_w2df(SHORTCODE) \
1217 gen_helper_conv_w2df(RddV, tcg_env, RsV)
1218 #define fGEN_TCG_F2_conv_ud2sf(SHORTCODE) \
1219 gen_helper_conv_ud2sf(RdV, tcg_env, RssV)
1220 #define fGEN_TCG_F2_conv_ud2df(SHORTCODE) \
1221 gen_helper_conv_ud2df(RddV, tcg_env, RssV)
1222 #define fGEN_TCG_F2_conv_d2sf(SHORTCODE) \
1223 gen_helper_conv_d2sf(RdV, tcg_env, RssV)
1224 #define fGEN_TCG_F2_conv_d2df(SHORTCODE) \
1225 gen_helper_conv_d2df(RddV, tcg_env, RssV)
1226 #define fGEN_TCG_F2_conv_sf2uw(SHORTCODE) \
1227 gen_helper_conv_sf2uw(RdV, tcg_env, RsV)
1228 #define fGEN_TCG_F2_conv_sf2w(SHORTCODE) \
1229 gen_helper_conv_sf2w(RdV, tcg_env, RsV)
1230 #define fGEN_TCG_F2_conv_sf2ud(SHORTCODE) \
1231 gen_helper_conv_sf2ud(RddV, tcg_env, RsV)
1232 #define fGEN_TCG_F2_conv_sf2d(SHORTCODE) \
1233 gen_helper_conv_sf2d(RddV, tcg_env, RsV)
1234 #define fGEN_TCG_F2_conv_df2uw(SHORTCODE) \
1235 gen_helper_conv_df2uw(RdV, tcg_env, RssV)
1236 #define fGEN_TCG_F2_conv_df2w(SHORTCODE) \
1237 gen_helper_conv_df2w(RdV, tcg_env, RssV)
1238 #define fGEN_TCG_F2_conv_df2ud(SHORTCODE) \
1239 gen_helper_conv_df2ud(RddV, tcg_env, RssV)
1240 #define fGEN_TCG_F2_conv_df2d(SHORTCODE) \
1241 gen_helper_conv_df2d(RddV, tcg_env, RssV)
1242 #define fGEN_TCG_F2_conv_sf2uw_chop(SHORTCODE) \
1243 gen_helper_conv_sf2uw_chop(RdV, tcg_env, RsV)
1244 #define fGEN_TCG_F2_conv_sf2w_chop(SHORTCODE) \
1245 gen_helper_conv_sf2w_chop(RdV, tcg_env, RsV)
1246 #define fGEN_TCG_F2_conv_sf2ud_chop(SHORTCODE) \
1247 gen_helper_conv_sf2ud_chop(RddV, tcg_env, RsV)
1248 #define fGEN_TCG_F2_conv_sf2d_chop(SHORTCODE) \
1249 gen_helper_conv_sf2d_chop(RddV, tcg_env, RsV)
1250 #define fGEN_TCG_F2_conv_df2uw_chop(SHORTCODE) \
1251 gen_helper_conv_df2uw_chop(RdV, tcg_env, RssV)
1252 #define fGEN_TCG_F2_conv_df2w_chop(SHORTCODE) \
1253 gen_helper_conv_df2w_chop(RdV, tcg_env, RssV)
1254 #define fGEN_TCG_F2_conv_df2ud_chop(SHORTCODE) \
1255 gen_helper_conv_df2ud_chop(RddV, tcg_env, RssV)
1256 #define fGEN_TCG_F2_conv_df2d_chop(SHORTCODE) \
1257 gen_helper_conv_df2d_chop(RddV, tcg_env, RssV)
1258 #define fGEN_TCG_F2_sfadd(SHORTCODE) \
1259 gen_helper_sfadd(RdV, tcg_env, RsV, RtV)
1260 #define fGEN_TCG_F2_sfsub(SHORTCODE) \
1261 gen_helper_sfsub(RdV, tcg_env, RsV, RtV)
1262 #define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \
1263 gen_helper_sfcmpeq(PdV, tcg_env, RsV, RtV)
1264 #define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \
1265 gen_helper_sfcmpgt(PdV, tcg_env, RsV, RtV)
1266 #define fGEN_TCG_F2_sfcmpge(SHORTCODE) \
1267 gen_helper_sfcmpge(PdV, tcg_env, RsV, RtV)
1268 #define fGEN_TCG_F2_sfcmpuo(SHORTCODE) \
1269 gen_helper_sfcmpuo(PdV, tcg_env, RsV, RtV)
1270 #define fGEN_TCG_F2_sfmax(SHORTCODE) \
1271 gen_helper_sfmax(RdV, tcg_env, RsV, RtV)
1272 #define fGEN_TCG_F2_sfmin(SHORTCODE) \
1273 gen_helper_sfmin(RdV, tcg_env, RsV, RtV)
1274 #define fGEN_TCG_F2_sfclass(SHORTCODE) \
1275 do { \
1276 TCGv imm = tcg_constant_tl(uiV); \
1277 gen_helper_sfclass(PdV, tcg_env, RsV, imm); \
1278 } while (0)
1279 #define fGEN_TCG_F2_sffixupn(SHORTCODE) \
1280 gen_helper_sffixupn(RdV, tcg_env, RsV, RtV)
1281 #define fGEN_TCG_F2_sffixupd(SHORTCODE) \
1282 gen_helper_sffixupd(RdV, tcg_env, RsV, RtV)
1283 #define fGEN_TCG_F2_sffixupr(SHORTCODE) \
1284 gen_helper_sffixupr(RdV, tcg_env, RsV)
1285 #define fGEN_TCG_F2_dfadd(SHORTCODE) \
1286 gen_helper_dfadd(RddV, tcg_env, RssV, RttV)
1287 #define fGEN_TCG_F2_dfsub(SHORTCODE) \
1288 gen_helper_dfsub(RddV, tcg_env, RssV, RttV)
1289 #define fGEN_TCG_F2_dfmax(SHORTCODE) \
1290 gen_helper_dfmax(RddV, tcg_env, RssV, RttV)
1291 #define fGEN_TCG_F2_dfmin(SHORTCODE) \
1292 gen_helper_dfmin(RddV, tcg_env, RssV, RttV)
1293 #define fGEN_TCG_F2_dfcmpeq(SHORTCODE) \
1294 gen_helper_dfcmpeq(PdV, tcg_env, RssV, RttV)
1295 #define fGEN_TCG_F2_dfcmpgt(SHORTCODE) \
1296 gen_helper_dfcmpgt(PdV, tcg_env, RssV, RttV)
1297 #define fGEN_TCG_F2_dfcmpge(SHORTCODE) \
1298 gen_helper_dfcmpge(PdV, tcg_env, RssV, RttV)
1299 #define fGEN_TCG_F2_dfcmpuo(SHORTCODE) \
1300 gen_helper_dfcmpuo(PdV, tcg_env, RssV, RttV)
1301 #define fGEN_TCG_F2_dfclass(SHORTCODE) \
1302 do { \
1303 TCGv imm = tcg_constant_tl(uiV); \
1304 gen_helper_dfclass(PdV, tcg_env, RssV, imm); \
1305 } while (0)
1306 #define fGEN_TCG_F2_sfmpy(SHORTCODE) \
1307 gen_helper_sfmpy(RdV, tcg_env, RsV, RtV)
1308 #define fGEN_TCG_F2_sffma(SHORTCODE) \
1309 gen_helper_sffma(RxV, tcg_env, RxV, RsV, RtV)
1310 #define fGEN_TCG_F2_sffma_sc(SHORTCODE) \
1311 gen_helper_sffma_sc(RxV, tcg_env, RxV, RsV, RtV, PuV)
1312 #define fGEN_TCG_F2_sffms(SHORTCODE) \
1313 gen_helper_sffms(RxV, tcg_env, RxV, RsV, RtV)
1314 #define fGEN_TCG_F2_sffma_lib(SHORTCODE) \
1315 gen_helper_sffma_lib(RxV, tcg_env, RxV, RsV, RtV)
1316 #define fGEN_TCG_F2_sffms_lib(SHORTCODE) \
1317 gen_helper_sffms_lib(RxV, tcg_env, RxV, RsV, RtV)
1319 #define fGEN_TCG_F2_dfmpyfix(SHORTCODE) \
1320 gen_helper_dfmpyfix(RddV, tcg_env, RssV, RttV)
1321 #define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \
1322 gen_helper_dfmpyhh(RxxV, tcg_env, RxxV, RssV, RttV)
1324 /* Nothing to do for these in qemu, need to suppress compiler warnings */
1325 #define fGEN_TCG_Y4_l2fetch(SHORTCODE) \
1326 do { \
1327 RsV = RsV; \
1328 RtV = RtV; \
1329 } while (0)
1330 #define fGEN_TCG_Y5_l2fetch(SHORTCODE) \
1331 do { \
1332 RsV = RsV; \
1333 } while (0)
1334 #define fGEN_TCG_Y2_isync(SHORTCODE) \
1335 do { } while (0)
1336 #define fGEN_TCG_Y2_barrier(SHORTCODE) \
1337 do { } while (0)
1338 #define fGEN_TCG_Y2_syncht(SHORTCODE) \
1339 do { } while (0)
1340 #define fGEN_TCG_Y2_dcfetchbo(SHORTCODE) \
1341 do { \
1342 RsV = RsV; \
1343 uiV = uiV; \
1344 } while (0)
1346 #define fGEN_TCG_L2_loadw_aq(SHORTCODE) SHORTCODE
1347 #define fGEN_TCG_L4_loadd_aq(SHORTCODE) SHORTCODE
1349 /* Nothing to do for these in qemu, need to suppress compiler warnings */
1350 #define fGEN_TCG_R6_release_at_vi(SHORTCODE) \
1351 do { \
1352 RsV = RsV; \
1353 } while (0)
1354 #define fGEN_TCG_R6_release_st_vi(SHORTCODE) \
1355 do { \
1356 RsV = RsV; \
1357 } while (0)
1359 #define fGEN_TCG_S2_storew_rl_at_vi(SHORTCODE) SHORTCODE
1360 #define fGEN_TCG_S4_stored_rl_at_vi(SHORTCODE) SHORTCODE
1361 #define fGEN_TCG_S2_storew_rl_st_vi(SHORTCODE) SHORTCODE
1362 #define fGEN_TCG_S4_stored_rl_st_vi(SHORTCODE) SHORTCODE
1364 #define fGEN_TCG_J2_trap0(SHORTCODE) \
1365 do { \
1366 uiV = uiV; \
1367 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt->pc); \
1368 TCGv excp = tcg_constant_tl(HEX_EXCP_TRAP0); \
1369 gen_helper_raise_exception(tcg_env, excp); \
1370 } while (0)
1371 #endif