tcg/tcg.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef TCG_H
  26 #define TCG_H
  27
  28 #include "qemu-common.h"
  29 #include "cpu.h"
  30 #include "exec/tb-context.h"
  31 #include "qemu/bitops.h"
  32 #include "tcg-mo.h"
  33 #include "tcg-target.h"
  34
  35 /* XXX: make safe guess about sizes */
  36 #define MAX_OP_PER_INSTR 266
  37
  38 #if HOST_LONG_BITS == 32
  39 #define MAX_OPC_PARAM_PER_ARG 2
  40 #else
  41 #define MAX_OPC_PARAM_PER_ARG 1
  42 #endif
  43 #define MAX_OPC_PARAM_IARGS 5
  44 #define MAX_OPC_PARAM_OARGS 1
  45 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  46
  47 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  48  * and up to 4 + N parameters on 64-bit archs
  49  * (N = number of input arguments + output arguments).  */
  50 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  51 #define OPC_BUF_SIZE 640
  52 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  53
  54 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  55
  56 #define CPU_TEMP_BUF_NLONGS 128
  57
  58 /* Default target word size to pointer size.  */
  59 #ifndef TCG_TARGET_REG_BITS
  60 # if UINTPTR_MAX == UINT32_MAX
  61 #  define TCG_TARGET_REG_BITS 32
  62 # elif UINTPTR_MAX == UINT64_MAX
  63 #  define TCG_TARGET_REG_BITS 64
  64 # else
  65 #  error Unknown pointer size for tcg target
  66 # endif
  67 #endif
  68
  69 #if TCG_TARGET_REG_BITS == 32
  70 typedef int32_t tcg_target_long;
  71 typedef uint32_t tcg_target_ulong;
  72 #define TCG_PRIlx PRIx32
  73 #define TCG_PRIld PRId32
  74 #elif TCG_TARGET_REG_BITS == 64
  75 typedef int64_t tcg_target_long;
  76 typedef uint64_t tcg_target_ulong;
  77 #define TCG_PRIlx PRIx64
  78 #define TCG_PRIld PRId64
  79 #else
  80 #error unsupported
  81 #endif
  82
  83 /* Oversized TCG guests make things like MTTCG hard
  84  * as we can't use atomics for cputlb updates.
  85  */
  86 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
  87 #define TCG_OVERSIZED_GUEST 1
  88 #else
  89 #define TCG_OVERSIZED_GUEST 0
  90 #endif
  91
  92 #if TCG_TARGET_NB_REGS <= 32
  93 typedef uint32_t TCGRegSet;
  94 #elif TCG_TARGET_NB_REGS <= 64
  95 typedef uint64_t TCGRegSet;
  96 #else
  97 #error unsupported
  98 #endif
  99
 100 #if TCG_TARGET_REG_BITS == 32
 101 /* Turn some undef macros into false macros.  */
 102 #define TCG_TARGET_HAS_extrl_i64_i32    0
 103 #define TCG_TARGET_HAS_extrh_i64_i32    0
 104 #define TCG_TARGET_HAS_div_i64          0
 105 #define TCG_TARGET_HAS_rem_i64          0
 106 #define TCG_TARGET_HAS_div2_i64         0
 107 #define TCG_TARGET_HAS_rot_i64          0
 108 #define TCG_TARGET_HAS_ext8s_i64        0
 109 #define TCG_TARGET_HAS_ext16s_i64       0
 110 #define TCG_TARGET_HAS_ext32s_i64       0
 111 #define TCG_TARGET_HAS_ext8u_i64        0
 112 #define TCG_TARGET_HAS_ext16u_i64       0
 113 #define TCG_TARGET_HAS_ext32u_i64       0
 114 #define TCG_TARGET_HAS_bswap16_i64      0
 115 #define TCG_TARGET_HAS_bswap32_i64      0
 116 #define TCG_TARGET_HAS_bswap64_i64      0
 117 #define TCG_TARGET_HAS_neg_i64          0
 118 #define TCG_TARGET_HAS_not_i64          0
 119 #define TCG_TARGET_HAS_andc_i64         0
 120 #define TCG_TARGET_HAS_orc_i64          0
 121 #define TCG_TARGET_HAS_eqv_i64          0
 122 #define TCG_TARGET_HAS_nand_i64         0
 123 #define TCG_TARGET_HAS_nor_i64          0
 124 #define TCG_TARGET_HAS_clz_i64          0
 125 #define TCG_TARGET_HAS_ctz_i64          0
 126 #define TCG_TARGET_HAS_ctpop_i64        0
 127 #define TCG_TARGET_HAS_deposit_i64      0
 128 #define TCG_TARGET_HAS_extract_i64      0
 129 #define TCG_TARGET_HAS_sextract_i64     0
 130 #define TCG_TARGET_HAS_movcond_i64      0
 131 #define TCG_TARGET_HAS_add2_i64         0
 132 #define TCG_TARGET_HAS_sub2_i64         0
 133 #define TCG_TARGET_HAS_mulu2_i64        0
 134 #define TCG_TARGET_HAS_muls2_i64        0
 135 #define TCG_TARGET_HAS_muluh_i64        0
 136 #define TCG_TARGET_HAS_mulsh_i64        0
 137 /* Turn some undef macros into true macros.  */
 138 #define TCG_TARGET_HAS_add2_i32         1
 139 #define TCG_TARGET_HAS_sub2_i32         1
 140 #endif
 141
 142 #ifndef TCG_TARGET_deposit_i32_valid
 143 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
 144 #endif
 145 #ifndef TCG_TARGET_deposit_i64_valid
 146 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
 147 #endif
 148 #ifndef TCG_TARGET_extract_i32_valid
 149 #define TCG_TARGET_extract_i32_valid(ofs, len) 1
 150 #endif
 151 #ifndef TCG_TARGET_extract_i64_valid
 152 #define TCG_TARGET_extract_i64_valid(ofs, len) 1
 153 #endif
 154
 155 /* Only one of DIV or DIV2 should be defined.  */
 156 #if defined(TCG_TARGET_HAS_div_i32)
 157 #define TCG_TARGET_HAS_div2_i32         0
 158 #elif defined(TCG_TARGET_HAS_div2_i32)
 159 #define TCG_TARGET_HAS_div_i32          0
 160 #define TCG_TARGET_HAS_rem_i32          0
 161 #endif
 162 #if defined(TCG_TARGET_HAS_div_i64)
 163 #define TCG_TARGET_HAS_div2_i64         0
 164 #elif defined(TCG_TARGET_HAS_div2_i64)
 165 #define TCG_TARGET_HAS_div_i64          0
 166 #define TCG_TARGET_HAS_rem_i64          0
 167 #endif
 168
 169 /* For 32-bit targets, some sort of unsigned widening multiply is required.  */
 170 #if TCG_TARGET_REG_BITS == 32 \
 171     && !(defined(TCG_TARGET_HAS_mulu2_i32) \
 172          || defined(TCG_TARGET_HAS_muluh_i32))
 173 # error "Missing unsigned widening multiply"
 174 #endif
 175
 176 #ifndef TARGET_INSN_START_EXTRA_WORDS
 177 # define TARGET_INSN_START_WORDS 1
 178 #else
 179 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
 180 #endif
 181
 182 typedef enum TCGOpcode {
 183 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
 184 #include "tcg-opc.h"
 185 #undef DEF
 186     NB_OPS,
 187 } TCGOpcode;
 188
 189 #define tcg_regset_set(d, s) (d) = (s)
 190 #define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg)
 191 #define tcg_regset_set_reg(d, r) (d) |= 1L << (r)
 192 #define tcg_regset_reset_reg(d, r) (d) &= ~(1L << (r))
 193 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)
 194 #define tcg_regset_or(d, a, b) (d) = (a) | (b)
 195 #define tcg_regset_and(d, a, b) (d) = (a) & (b)
 196 #define tcg_regset_andnot(d, a, b) (d) = (a) & ~(b)
 197 #define tcg_regset_not(d, a) (d) = ~(a)
 198
 199 #ifndef TCG_TARGET_INSN_UNIT_SIZE
 200 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
 201 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
 202 typedef uint8_t tcg_insn_unit;
 203 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
 204 typedef uint16_t tcg_insn_unit;
 205 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
 206 typedef uint32_t tcg_insn_unit;
 207 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
 208 typedef uint64_t tcg_insn_unit;
 209 #else
 210 /* The port better have done this.  */
 211 #endif
 212
 213
 214 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS
 215 # define tcg_debug_assert(X) do { assert(X); } while (0)
 216 #elif QEMU_GNUC_PREREQ(4, 5)
 217 # define tcg_debug_assert(X) \
 218     do { if (!(X)) { __builtin_unreachable(); } } while (0)
 219 #else
 220 # define tcg_debug_assert(X) do { (void)(X); } while (0)
 221 #endif
 222
 223 typedef struct TCGRelocation {
 224     struct TCGRelocation *next;
 225     int type;
 226     tcg_insn_unit *ptr;
 227     intptr_t addend;
 228 } TCGRelocation;
 229
 230 typedef struct TCGLabel {
 231     unsigned has_value : 1;
 232     unsigned id : 31;
 233     union {
 234         uintptr_t value;
 235         tcg_insn_unit *value_ptr;
 236         TCGRelocation *first_reloc;
 237     } u;
 238 } TCGLabel;
 239
 240 typedef struct TCGPool {
 241     struct TCGPool *next;
 242     int size;
 243     uint8_t data[0] __attribute__ ((aligned));
 244 } TCGPool;
 245
 246 #define TCG_POOL_CHUNK_SIZE 32768
 247
 248 #define TCG_MAX_TEMPS 512
 249 #define TCG_MAX_INSNS 512
 250
 251 /* when the size of the arguments of a called function is smaller than
 252    this value, they are statically allocated in the TB stack frame */
 253 #define TCG_STATIC_CALL_ARGS_SIZE 128
 254
 255 typedef enum TCGType {
 256     TCG_TYPE_I32,
 257     TCG_TYPE_I64,
 258     TCG_TYPE_COUNT, /* number of different types */
 259
 260     /* An alias for the size of the host register.  */
 261 #if TCG_TARGET_REG_BITS == 32
 262     TCG_TYPE_REG = TCG_TYPE_I32,
 263 #else
 264     TCG_TYPE_REG = TCG_TYPE_I64,
 265 #endif
 266
 267     /* An alias for the size of the native pointer.  */
 268 #if UINTPTR_MAX == UINT32_MAX
 269     TCG_TYPE_PTR = TCG_TYPE_I32,
 270 #else
 271     TCG_TYPE_PTR = TCG_TYPE_I64,
 272 #endif
 273
 274     /* An alias for the size of the target "long", aka register.  */
 275 #if TARGET_LONG_BITS == 64
 276     TCG_TYPE_TL = TCG_TYPE_I64,
 277 #else
 278     TCG_TYPE_TL = TCG_TYPE_I32,
 279 #endif
 280 } TCGType;
 281
 282 /* Constants for qemu_ld and qemu_st for the Memory Operation field.  */
 283 typedef enum TCGMemOp {
 284     MO_8     = 0,
 285     MO_16    = 1,
 286     MO_32    = 2,
 287     MO_64    = 3,
 288     MO_SIZE  = 3,   /* Mask for the above.  */
 289
 290     MO_SIGN  = 4,   /* Sign-extended, otherwise zero-extended.  */
 291
 292     MO_BSWAP = 8,   /* Host reverse endian.  */
 293 #ifdef HOST_WORDS_BIGENDIAN
 294     MO_LE    = MO_BSWAP,
 295     MO_BE    = 0,
 296 #else
 297     MO_LE    = 0,
 298     MO_BE    = MO_BSWAP,
 299 #endif
 300 #ifdef TARGET_WORDS_BIGENDIAN
 301     MO_TE    = MO_BE,
 302 #else
 303     MO_TE    = MO_LE,
 304 #endif
 305
 306     /* MO_UNALN accesses are never checked for alignment.
 307      * MO_ALIGN accesses will result in a call to the CPU's
 308      * do_unaligned_access hook if the guest address is not aligned.
 309      * The default depends on whether the target CPU defines ALIGNED_ONLY.
 310      *
 311      * Some architectures (e.g. ARMv8) need the address which is aligned
 312      * to a size more than the size of the memory access.
 313      * Some architectures (e.g. SPARCv9) need an address which is aligned,
 314      * but less strictly than the natural alignment.
 315      *
 316      * MO_ALIGN supposes the alignment size is the size of a memory access.
 317      *
 318      * There are three options:
 319      * - unaligned access permitted (MO_UNALN).
 320      * - an alignment to the size of an access (MO_ALIGN);
 321      * - an alignment to a specified size, which may be more or less than
 322      *   the access size (MO_ALIGN_x where 'x' is a size in bytes);
 323      */
 324     MO_ASHIFT = 4,
 325     MO_AMASK = 7 << MO_ASHIFT,
 326 #ifdef ALIGNED_ONLY
 327     MO_ALIGN = 0,
 328     MO_UNALN = MO_AMASK,
 329 #else
 330     MO_ALIGN = MO_AMASK,
 331     MO_UNALN = 0,
 332 #endif
 333     MO_ALIGN_2  = 1 << MO_ASHIFT,
 334     MO_ALIGN_4  = 2 << MO_ASHIFT,
 335     MO_ALIGN_8  = 3 << MO_ASHIFT,
 336     MO_ALIGN_16 = 4 << MO_ASHIFT,
 337     MO_ALIGN_32 = 5 << MO_ASHIFT,
 338     MO_ALIGN_64 = 6 << MO_ASHIFT,
 339
 340     /* Combinations of the above, for ease of use.  */
 341     MO_UB    = MO_8,
 342     MO_UW    = MO_16,
 343     MO_UL    = MO_32,
 344     MO_SB    = MO_SIGN | MO_8,
 345     MO_SW    = MO_SIGN | MO_16,
 346     MO_SL    = MO_SIGN | MO_32,
 347     MO_Q     = MO_64,
 348
 349     MO_LEUW  = MO_LE | MO_UW,
 350     MO_LEUL  = MO_LE | MO_UL,
 351     MO_LESW  = MO_LE | MO_SW,
 352     MO_LESL  = MO_LE | MO_SL,
 353     MO_LEQ   = MO_LE | MO_Q,
 354
 355     MO_BEUW  = MO_BE | MO_UW,
 356     MO_BEUL  = MO_BE | MO_UL,
 357     MO_BESW  = MO_BE | MO_SW,
 358     MO_BESL  = MO_BE | MO_SL,
 359     MO_BEQ   = MO_BE | MO_Q,
 360
 361     MO_TEUW  = MO_TE | MO_UW,
 362     MO_TEUL  = MO_TE | MO_UL,
 363     MO_TESW  = MO_TE | MO_SW,
 364     MO_TESL  = MO_TE | MO_SL,
 365     MO_TEQ   = MO_TE | MO_Q,
 366
 367     MO_SSIZE = MO_SIZE | MO_SIGN,
 368 } TCGMemOp;
 369
 370 /**
 371  * get_alignment_bits
 372  * @memop: TCGMemOp value
 373  *
 374  * Extract the alignment size from the memop.
 375  */
 376 static inline unsigned get_alignment_bits(TCGMemOp memop)
 377 {
 378     unsigned a = memop & MO_AMASK;
 379
 380     if (a == MO_UNALN) {
 381         /* No alignment required.  */
 382         a = 0;
 383     } else if (a == MO_ALIGN) {
 384         /* A natural alignment requirement.  */
 385         a = memop & MO_SIZE;
 386     } else {
 387         /* A specific alignment requirement.  */
 388         a = a >> MO_ASHIFT;
 389     }
 390 #if defined(CONFIG_SOFTMMU)
 391     /* The requested alignment cannot overlap the TLB flags.  */
 392     tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0);
 393 #endif
 394     return a;
 395 }
 396
 397 typedef tcg_target_ulong TCGArg;
 398
 399 /* Define type and accessor macros for TCG variables.
 400
 401    TCG variables are the inputs and outputs of TCG ops, as described
 402    in tcg/README. Target CPU front-end code uses these types to deal
 403    with TCG variables as it emits TCG code via the tcg_gen_* functions.
 404    They come in several flavours:
 405     * TCGv_i32 : 32 bit integer type
 406     * TCGv_i64 : 64 bit integer type
 407     * TCGv_ptr : a host pointer type
 408     * TCGv : an integer type the same size as target_ulong
 409              (an alias for either TCGv_i32 or TCGv_i64)
 410    The compiler's type checking will complain if you mix them
 411    up and pass the wrong sized TCGv to a function.
 412
 413    Users of tcg_gen_* don't need to know about any of the internal
 414    details of these, and should treat them as opaque types.
 415    You won't be able to look inside them in a debugger either.
 416
 417    Internal implementation details follow:
 418
 419    Note that there is no definition of the structs TCGv_i32_d etc anywhere.
 420    This is deliberate, because the values we store in variables of type
 421    TCGv_i32 are not really pointers-to-structures. They're just small
 422    integers, but keeping them in pointer types like this means that the
 423    compiler will complain if you accidentally pass a TCGv_i32 to a
 424    function which takes a TCGv_i64, and so on. Only the internals of
 425    TCG need to care about the actual contents of the types, and they always
 426    box and unbox via the MAKE_TCGV_* and GET_TCGV_* functions.
 427    Converting to and from intptr_t rather than int reduces the number
 428    of sign-extension instructions that get implied on 64-bit hosts.  */
 429
 430 typedef struct TCGv_i32_d *TCGv_i32;
 431 typedef struct TCGv_i64_d *TCGv_i64;
 432 typedef struct TCGv_ptr_d *TCGv_ptr;
 433 typedef TCGv_ptr TCGv_env;
 434 #if TARGET_LONG_BITS == 32
 435 #define TCGv TCGv_i32
 436 #elif TARGET_LONG_BITS == 64
 437 #define TCGv TCGv_i64
 438 #else
 439 #error Unhandled TARGET_LONG_BITS value
 440 #endif
 441
 442 static inline TCGv_i32 QEMU_ARTIFICIAL MAKE_TCGV_I32(intptr_t i)
 443 {
 444     return (TCGv_i32)i;
 445 }
 446
 447 static inline TCGv_i64 QEMU_ARTIFICIAL MAKE_TCGV_I64(intptr_t i)
 448 {
 449     return (TCGv_i64)i;
 450 }
 451
 452 static inline TCGv_ptr QEMU_ARTIFICIAL MAKE_TCGV_PTR(intptr_t i)
 453 {
 454     return (TCGv_ptr)i;
 455 }
 456
 457 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I32(TCGv_i32 t)
 458 {
 459     return (intptr_t)t;
 460 }
 461
 462 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I64(TCGv_i64 t)
 463 {
 464     return (intptr_t)t;
 465 }
 466
 467 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCGv_ptr t)
 468 {
 469     return (intptr_t)t;
 470 }
 471
 472 #if TCG_TARGET_REG_BITS == 32
 473 #define TCGV_LOW(t) MAKE_TCGV_I32(GET_TCGV_I64(t))
 474 #define TCGV_HIGH(t) MAKE_TCGV_I32(GET_TCGV_I64(t) + 1)
 475 #endif
 476
 477 #define TCGV_EQUAL_I32(a, b) (GET_TCGV_I32(a) == GET_TCGV_I32(b))
 478 #define TCGV_EQUAL_I64(a, b) (GET_TCGV_I64(a) == GET_TCGV_I64(b))
 479 #define TCGV_EQUAL_PTR(a, b) (GET_TCGV_PTR(a) == GET_TCGV_PTR(b))
 480
 481 /* Dummy definition to avoid compiler warnings.  */
 482 #define TCGV_UNUSED_I32(x) x = MAKE_TCGV_I32(-1)
 483 #define TCGV_UNUSED_I64(x) x = MAKE_TCGV_I64(-1)
 484 #define TCGV_UNUSED_PTR(x) x = MAKE_TCGV_PTR(-1)
 485
 486 #define TCGV_IS_UNUSED_I32(x) (GET_TCGV_I32(x) == -1)
 487 #define TCGV_IS_UNUSED_I64(x) (GET_TCGV_I64(x) == -1)
 488 #define TCGV_IS_UNUSED_PTR(x) (GET_TCGV_PTR(x) == -1)
 489
 490 /* call flags */
 491 /* Helper does not read globals (either directly or through an exception). It
 492    implies TCG_CALL_NO_WRITE_GLOBALS. */
 493 #define TCG_CALL_NO_READ_GLOBALS    0x0010
 494 /* Helper does not write globals */
 495 #define TCG_CALL_NO_WRITE_GLOBALS   0x0020
 496 /* Helper can be safely suppressed if the return value is not used. */
 497 #define TCG_CALL_NO_SIDE_EFFECTS    0x0040
 498
 499 /* convenience version of most used call flags */
 500 #define TCG_CALL_NO_RWG         TCG_CALL_NO_READ_GLOBALS
 501 #define TCG_CALL_NO_WG          TCG_CALL_NO_WRITE_GLOBALS
 502 #define TCG_CALL_NO_SE          TCG_CALL_NO_SIDE_EFFECTS
 503 #define TCG_CALL_NO_RWG_SE      (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
 504 #define TCG_CALL_NO_WG_SE       (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
 505
 506 /* used to align parameters */
 507 #define TCG_CALL_DUMMY_TCGV     MAKE_TCGV_I32(-1)
 508 #define TCG_CALL_DUMMY_ARG      ((TCGArg)(-1))
 509
 510 /* Conditions.  Note that these are laid out for easy manipulation by
 511    the functions below:
 512      bit 0 is used for inverting;
 513      bit 1 is signed,
 514      bit 2 is unsigned,
 515      bit 3 is used with bit 0 for swapping signed/unsigned.  */
 516 typedef enum {
 517     /* non-signed */
 518     TCG_COND_NEVER  = 0 | 0 | 0 | 0,
 519     TCG_COND_ALWAYS = 0 | 0 | 0 | 1,
 520     TCG_COND_EQ     = 8 | 0 | 0 | 0,
 521     TCG_COND_NE     = 8 | 0 | 0 | 1,
 522     /* signed */
 523     TCG_COND_LT     = 0 | 0 | 2 | 0,
 524     TCG_COND_GE     = 0 | 0 | 2 | 1,
 525     TCG_COND_LE     = 8 | 0 | 2 | 0,
 526     TCG_COND_GT     = 8 | 0 | 2 | 1,
 527     /* unsigned */
 528     TCG_COND_LTU    = 0 | 4 | 0 | 0,
 529     TCG_COND_GEU    = 0 | 4 | 0 | 1,
 530     TCG_COND_LEU    = 8 | 4 | 0 | 0,
 531     TCG_COND_GTU    = 8 | 4 | 0 | 1,
 532 } TCGCond;
 533
 534 /* Invert the sense of the comparison.  */
 535 static inline TCGCond tcg_invert_cond(TCGCond c)
 536 {
 537     return (TCGCond)(c ^ 1);
 538 }
 539
 540 /* Swap the operands in a comparison.  */
 541 static inline TCGCond tcg_swap_cond(TCGCond c)
 542 {
 543     return c & 6 ? (TCGCond)(c ^ 9) : c;
 544 }
 545
 546 /* Create an "unsigned" version of a "signed" comparison.  */
 547 static inline TCGCond tcg_unsigned_cond(TCGCond c)
 548 {
 549     return c & 2 ? (TCGCond)(c ^ 6) : c;
 550 }
 551
 552 /* Must a comparison be considered unsigned?  */
 553 static inline bool is_unsigned_cond(TCGCond c)
 554 {
 555     return (c & 4) != 0;
 556 }
 557
 558 /* Create a "high" version of a double-word comparison.
 559    This removes equality from a LTE or GTE comparison.  */
 560 static inline TCGCond tcg_high_cond(TCGCond c)
 561 {
 562     switch (c) {
 563     case TCG_COND_GE:
 564     case TCG_COND_LE:
 565     case TCG_COND_GEU:
 566     case TCG_COND_LEU:
 567         return (TCGCond)(c ^ 8);
 568     default:
 569         return c;
 570     }
 571 }
 572
 573 typedef enum TCGTempVal {
 574     TEMP_VAL_DEAD,
 575     TEMP_VAL_REG,
 576     TEMP_VAL_MEM,
 577     TEMP_VAL_CONST,
 578 } TCGTempVal;
 579
 580 typedef struct TCGTemp {
 581     TCGReg reg:8;
 582     TCGTempVal val_type:8;
 583     TCGType base_type:8;
 584     TCGType type:8;
 585     unsigned int fixed_reg:1;
 586     unsigned int indirect_reg:1;
 587     unsigned int indirect_base:1;
 588     unsigned int mem_coherent:1;
 589     unsigned int mem_allocated:1;
 590     unsigned int temp_local:1; /* If true, the temp is saved across
 591                                   basic blocks. Otherwise, it is not
 592                                   preserved across basic blocks. */
 593     unsigned int temp_allocated:1; /* never used for code gen */
 594
 595     tcg_target_long val;
 596     struct TCGTemp *mem_base;
 597     intptr_t mem_offset;
 598     const char *name;
 599 } TCGTemp;
 600
 601 typedef struct TCGContext TCGContext;
 602
 603 typedef struct TCGTempSet {
 604     unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)];
 605 } TCGTempSet;
 606
 607 /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding,
 608    this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands.
 609    There are never more than 2 outputs, which means that we can store all
 610    dead + sync data within 16 bits.  */
 611 #define DEAD_ARG  4
 612 #define SYNC_ARG  1
 613 typedef uint16_t TCGLifeData;
 614
 615 /* The layout here is designed to avoid crossing of a 32-bit boundary.
 616    If we do so, gcc adds padding, expanding the size to 12.  */
 617 typedef struct TCGOp {
 618     TCGOpcode opc   : 8;        /*  8 */
 619
 620     /* Index of the prev/next op, or 0 for the end of the list.  */
 621     unsigned prev   : 10;       /* 18 */
 622     unsigned next   : 10;       /* 28 */
 623
 624     /* The number of out and in parameter for a call.  */
 625     unsigned calli  : 4;        /* 32 */
 626     unsigned callo  : 2;        /* 34 */
 627
 628     /* Index of the arguments for this op, or 0 for zero-operand ops.  */
 629     unsigned args   : 14;       /* 48 */
 630
 631     /* Lifetime data of the operands.  */
 632     unsigned life   : 16;       /* 64 */
 633 } TCGOp;
 634
 635 /* Make sure operands fit in the bitfields above.  */
 636 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
 637 QEMU_BUILD_BUG_ON(OPC_BUF_SIZE > (1 << 10));
 638 QEMU_BUILD_BUG_ON(OPPARAM_BUF_SIZE > (1 << 14));
 639
 640 /* Make sure that we don't overflow 64 bits without noticing.  */
 641 QEMU_BUILD_BUG_ON(sizeof(TCGOp) > 8);
 642
 643 struct TCGContext {
 644     uint8_t *pool_cur, *pool_end;
 645     TCGPool *pool_first, *pool_current, *pool_first_large;
 646     int nb_labels;
 647     int nb_globals;
 648     int nb_temps;
 649     int nb_indirects;
 650
 651     /* goto_tb support */
 652     tcg_insn_unit *code_buf;
 653     uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */
 654     uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */
 655     uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */
 656
 657     TCGRegSet reserved_regs;
 658     intptr_t current_frame_offset;
 659     intptr_t frame_start;
 660     intptr_t frame_end;
 661     TCGTemp *frame_temp;
 662
 663     tcg_insn_unit *code_ptr;
 664
 665     GHashTable *helpers;
 666
 667 #ifdef CONFIG_PROFILER
 668     /* profiling info */
 669     int64_t tb_count1;
 670     int64_t tb_count;
 671     int64_t op_count; /* total insn count */
 672     int op_count_max; /* max insn per TB */
 673     int64_t temp_count;
 674     int temp_count_max;
 675     int64_t del_op_count;
 676     int64_t code_in_len;
 677     int64_t code_out_len;
 678     int64_t search_out_len;
 679     int64_t interm_time;
 680     int64_t code_time;
 681     int64_t la_time;
 682     int64_t opt_time;
 683     int64_t restore_count;
 684     int64_t restore_time;
 685 #endif
 686
 687 #ifdef CONFIG_DEBUG_TCG
 688     int temps_in_use;
 689     int goto_tb_issue_mask;
 690 #endif
 691
 692     int gen_next_op_idx;
 693     int gen_next_parm_idx;
 694
 695     /* Code generation.  Note that we specifically do not use tcg_insn_unit
 696        here, because there's too much arithmetic throughout that relies
 697        on addition and subtraction working on bytes.  Rely on the GCC
 698        extension that allows arithmetic on void*.  */
 699     void *code_gen_prologue;
 700     void *code_gen_epilogue;
 701     void *code_gen_buffer;
 702     size_t code_gen_buffer_size;
 703     void *code_gen_ptr;
 704     void *data_gen_ptr;
 705
 706     /* Threshold to flush the translated code buffer.  */
 707     void *code_gen_highwater;
 708
 709     TBContext tb_ctx;
 710
 711     /* Track which vCPU triggers events */
 712     CPUState *cpu;                      /* *_trans */
 713     TCGv_env tcg_env;                   /* *_exec  */
 714
 715     /* These structures are private to tcg-target.inc.c.  */
 716 #ifdef TCG_TARGET_NEED_LDST_LABELS
 717     struct TCGLabelQemuLdst *ldst_labels;
 718 #endif
 719 #ifdef TCG_TARGET_NEED_POOL_LABELS
 720     struct TCGLabelPoolData *pool_labels;
 721 #endif
 722
 723     TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
 724     TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
 725
 726     /* Tells which temporary holds a given register.
 727        It does not take into account fixed registers */
 728     TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
 729
 730     TCGOp gen_op_buf[OPC_BUF_SIZE];
 731     TCGArg gen_opparam_buf[OPPARAM_BUF_SIZE];
 732
 733     uint16_t gen_insn_end_off[TCG_MAX_INSNS];
 734     target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
 735 };
 736
 737 extern TCGContext tcg_ctx;
 738 extern bool parallel_cpus;
 739
 740 static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
 741 {
 742     int op_argi = tcg_ctx.gen_op_buf[op_idx].args;
 743     tcg_ctx.gen_opparam_buf[op_argi + arg] = v;
 744 }
 745
 746 /* The number of opcodes emitted so far.  */
 747 static inline int tcg_op_buf_count(void)
 748 {
 749     return tcg_ctx.gen_next_op_idx;
 750 }
 751
 752 /* Test for whether to terminate the TB for using too many opcodes.  */
 753 static inline bool tcg_op_buf_full(void)
 754 {
 755     return tcg_op_buf_count() >= OPC_MAX_SIZE;
 756 }
 757
 758 /* pool based memory allocation */
 759
 760 /* tb_lock must be held for tcg_malloc_internal. */
 761 void *tcg_malloc_internal(TCGContext *s, int size);
 762 void tcg_pool_reset(TCGContext *s);
 763 TranslationBlock *tcg_tb_alloc(TCGContext *s);
 764
 765 /* Called with tb_lock held.  */
 766 static inline void *tcg_malloc(int size)
 767 {
 768     TCGContext *s = &tcg_ctx;
 769     uint8_t *ptr, *ptr_end;
 770
 771     /* ??? This is a weak placeholder for minimum malloc alignment.  */
 772     size = QEMU_ALIGN_UP(size, 8);
 773
 774     ptr = s->pool_cur;
 775     ptr_end = ptr + size;
 776     if (unlikely(ptr_end > s->pool_end)) {
 777         return tcg_malloc_internal(&tcg_ctx, size);
 778     } else {
 779         s->pool_cur = ptr_end;
 780         return ptr;
 781     }
 782 }
 783
 784 void tcg_context_init(TCGContext *s);
 785 void tcg_prologue_init(TCGContext *s);
 786 void tcg_func_start(TCGContext *s);
 787
 788 int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
 789
 790 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
 791
 792 int tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *);
 793
 794 TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name);
 795 TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name);
 796
 797 TCGv_i32 tcg_temp_new_internal_i32(int temp_local);
 798 TCGv_i64 tcg_temp_new_internal_i64(int temp_local);
 799
 800 void tcg_temp_free_i32(TCGv_i32 arg);
 801 void tcg_temp_free_i64(TCGv_i64 arg);
 802
 803 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
 804                                               const char *name)
 805 {
 806     int idx = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
 807     return MAKE_TCGV_I32(idx);
 808 }
 809
 810 static inline TCGv_i32 tcg_temp_new_i32(void)
 811 {
 812     return tcg_temp_new_internal_i32(0);
 813 }
 814
 815 static inline TCGv_i32 tcg_temp_local_new_i32(void)
 816 {
 817     return tcg_temp_new_internal_i32(1);
 818 }
 819
 820 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
 821                                               const char *name)
 822 {
 823     int idx = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
 824     return MAKE_TCGV_I64(idx);
 825 }
 826
 827 static inline TCGv_i64 tcg_temp_new_i64(void)
 828 {
 829     return tcg_temp_new_internal_i64(0);
 830 }
 831
 832 static inline TCGv_i64 tcg_temp_local_new_i64(void)
 833 {
 834     return tcg_temp_new_internal_i64(1);
 835 }
 836
 837 #if defined(CONFIG_DEBUG_TCG)
 838 /* If you call tcg_clear_temp_count() at the start of a section of
 839  * code which is not supposed to leak any TCG temporaries, then
 840  * calling tcg_check_temp_count() at the end of the section will
 841  * return 1 if the section did in fact leak a temporary.
 842  */
 843 void tcg_clear_temp_count(void);
 844 int tcg_check_temp_count(void);
 845 #else
 846 #define tcg_clear_temp_count() do { } while (0)
 847 #define tcg_check_temp_count() 0
 848 #endif
 849
 850 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf);
 851 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf);
 852
 853 #define TCG_CT_ALIAS  0x80
 854 #define TCG_CT_IALIAS 0x40
 855 #define TCG_CT_NEWREG 0x20 /* output requires a new register */
 856 #define TCG_CT_REG    0x01
 857 #define TCG_CT_CONST  0x02 /* any constant of register size */
 858
 859 typedef struct TCGArgConstraint {
 860     uint16_t ct;
 861     uint8_t alias_index;
 862     union {
 863         TCGRegSet regs;
 864     } u;
 865 } TCGArgConstraint;
 866
 867 #define TCG_MAX_OP_ARGS 16
 868
 869 /* Bits for TCGOpDef->flags, 8 bits available.  */
 870 enum {
 871     /* Instruction defines the end of a basic block.  */
 872     TCG_OPF_BB_END       = 0x01,
 873     /* Instruction clobbers call registers and potentially update globals.  */
 874     TCG_OPF_CALL_CLOBBER = 0x02,
 875     /* Instruction has side effects: it cannot be removed if its outputs
 876        are not used, and might trigger exceptions.  */
 877     TCG_OPF_SIDE_EFFECTS = 0x04,
 878     /* Instruction operands are 64-bits (otherwise 32-bits).  */
 879     TCG_OPF_64BIT        = 0x08,
 880     /* Instruction is optional and not implemented by the host, or insn
 881        is generic and should not be implemened by the host.  */
 882     TCG_OPF_NOT_PRESENT  = 0x10,
 883 };
 884
 885 typedef struct TCGOpDef {
 886     const char *name;
 887     uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
 888     uint8_t flags;
 889     TCGArgConstraint *args_ct;
 890     int *sorted_args;
 891 #if defined(CONFIG_DEBUG_TCG)
 892     int used;
 893 #endif
 894 } TCGOpDef;
 895
 896 extern TCGOpDef tcg_op_defs[];
 897 extern const size_t tcg_op_defs_max;
 898
 899 typedef struct TCGTargetOpDef {
 900     TCGOpcode op;
 901     const char *args_ct_str[TCG_MAX_OP_ARGS];
 902 } TCGTargetOpDef;
 903
 904 #define tcg_abort() \
 905 do {\
 906     fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
 907     abort();\
 908 } while (0)
 909
 910 #if UINTPTR_MAX == UINT32_MAX
 911 #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I32(n))
 912 #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I32(GET_TCGV_PTR(n))
 913
 914 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V)))
 915 #define tcg_global_reg_new_ptr(R, N) \
 916     TCGV_NAT_TO_PTR(tcg_global_reg_new_i32((R), (N)))
 917 #define tcg_global_mem_new_ptr(R, O, N) \
 918     TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N)))
 919 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32())
 920 #define tcg_temp_free_ptr(T) tcg_temp_free_i32(TCGV_PTR_TO_NAT(T))
 921 #else
 922 #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I64(n))
 923 #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I64(GET_TCGV_PTR(n))
 924
 925 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V)))
 926 #define tcg_global_reg_new_ptr(R, N) \
 927     TCGV_NAT_TO_PTR(tcg_global_reg_new_i64((R), (N)))
 928 #define tcg_global_mem_new_ptr(R, O, N) \
 929     TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N)))
 930 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64())
 931 #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T))
 932 #endif
 933
 934 bool tcg_op_supported(TCGOpcode op);
 935
 936 void tcg_gen_callN(TCGContext *s, void *func,
 937                    TCGArg ret, int nargs, TCGArg *args);
 938
 939 void tcg_op_remove(TCGContext *s, TCGOp *op);
 940 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg);
 941 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg);
 942
 943 void tcg_optimize(TCGContext *s);
 944
 945 /* only used for debugging purposes */
 946 void tcg_dump_ops(TCGContext *s);
 947
 948 TCGv_i32 tcg_const_i32(int32_t val);
 949 TCGv_i64 tcg_const_i64(int64_t val);
 950 TCGv_i32 tcg_const_local_i32(int32_t val);
 951 TCGv_i64 tcg_const_local_i64(int64_t val);
 952
 953 TCGLabel *gen_new_label(void);
 954
 955 /**
 956  * label_arg
 957  * @l: label
 958  *
 959  * Encode a label for storage in the TCG opcode stream.
 960  */
 961
 962 static inline TCGArg label_arg(TCGLabel *l)
 963 {
 964     return (uintptr_t)l;
 965 }
 966
 967 /**
 968  * arg_label
 969  * @i: value
 970  *
 971  * The opposite of label_arg.  Retrieve a label from the
 972  * encoding of the TCG opcode stream.
 973  */
 974
 975 static inline TCGLabel *arg_label(TCGArg i)
 976 {
 977     return (TCGLabel *)(uintptr_t)i;
 978 }
 979
 980 /**
 981  * tcg_ptr_byte_diff
 982  * @a, @b: addresses to be differenced
 983  *
 984  * There are many places within the TCG backends where we need a byte
 985  * difference between two pointers.  While this can be accomplished
 986  * with local casting, it's easy to get wrong -- especially if one is
 987  * concerned with the signedness of the result.
 988  *
 989  * This version relies on GCC's void pointer arithmetic to get the
 990  * correct result.
 991  */
 992
 993 static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b)
 994 {
 995     return a - b;
 996 }
 997
 998 /**
 999  * tcg_pcrel_diff
1000  * @s: the tcg context
1001  * @target: address of the target
1002  *
1003  * Produce a pc-relative difference, from the current code_ptr
1004  * to the destination address.
1005  */
1006
1007 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target)
1008 {
1009     return tcg_ptr_byte_diff(target, s->code_ptr);
1010 }
1011
1012 /**
1013  * tcg_current_code_size
1014  * @s: the tcg context
1015  *
1016  * Compute the current code size within the translation block.
1017  * This is used to fill in qemu's data structures for goto_tb.
1018  */
1019
1020 static inline size_t tcg_current_code_size(TCGContext *s)
1021 {
1022     return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
1023 }
1024
1025 /* Combine the TCGMemOp and mmu_idx parameters into a single value.  */
1026 typedef uint32_t TCGMemOpIdx;
1027
1028 /**
1029  * make_memop_idx
1030  * @op: memory operation
1031  * @idx: mmu index
1032  *
1033  * Encode these values into a single parameter.
1034  */
1035 static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
1036 {
1037     tcg_debug_assert(idx <= 15);
1038     return (op << 4) | idx;
1039 }
1040
1041 /**
1042  * get_memop
1043  * @oi: combined op/idx parameter
1044  *
1045  * Extract the memory operation from the combined value.
1046  */
1047 static inline TCGMemOp get_memop(TCGMemOpIdx oi)
1048 {
1049     return oi >> 4;
1050 }
1051
1052 /**
1053  * get_mmuidx
1054  * @oi: combined op/idx parameter
1055  *
1056  * Extract the mmu index from the combined value.
1057  */
1058 static inline unsigned get_mmuidx(TCGMemOpIdx oi)
1059 {
1060     return oi & 15;
1061 }
1062
1063 /**
1064  * tcg_qemu_tb_exec:
1065  * @env: pointer to CPUArchState for the CPU
1066  * @tb_ptr: address of generated code for the TB to execute
1067  *
1068  * Start executing code from a given translation block.
1069  * Where translation blocks have been linked, execution
1070  * may proceed from the given TB into successive ones.
1071  * Control eventually returns only when some action is needed
1072  * from the top-level loop: either control must pass to a TB
1073  * which has not yet been directly linked, or an asynchronous
1074  * event such as an interrupt needs handling.
1075  *
1076  * Return: The return value is the value passed to the corresponding
1077  * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
1078  * The value is either zero or a 4-byte aligned pointer to that TB combined
1079  * with additional information in its two least significant bits. The
1080  * additional information is encoded as follows:
1081  *  0, 1: the link between this TB and the next is via the specified
1082  *        TB index (0 or 1). That is, we left the TB via (the equivalent
1083  *        of) "goto_tb <index>". The main loop uses this to determine
1084  *        how to link the TB just executed to the next.
1085  *  2:    we are using instruction counting code generation, and we
1086  *        did not start executing this TB because the instruction counter
1087  *        would hit zero midway through it. In this case the pointer
1088  *        returned is the TB we were about to execute, and the caller must
1089  *        arrange to execute the remaining count of instructions.
1090  *  3:    we stopped because the CPU's exit_request flag was set
1091  *        (usually meaning that there is an interrupt that needs to be
1092  *        handled). The pointer returned is the TB we were about to execute
1093  *        when we noticed the pending exit request.
1094  *
1095  * If the bottom two bits indicate an exit-via-index then the CPU
1096  * state is correctly synchronised and ready for execution of the next
1097  * TB (and in particular the guest PC is the address to execute next).
1098  * Otherwise, we gave up on execution of this TB before it started, and
1099  * the caller must fix up the CPU state by calling the CPU's
1100  * synchronize_from_tb() method with the TB pointer we return (falling
1101  * back to calling the CPU's set_pc method with tb->pb if no
1102  * synchronize_from_tb() method exists).
1103  *
1104  * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
1105  * to this default (which just calls the prologue.code emitted by
1106  * tcg_target_qemu_prologue()).
1107  */
1108 #define TB_EXIT_MASK 3
1109 #define TB_EXIT_IDX0 0
1110 #define TB_EXIT_IDX1 1
1111 #define TB_EXIT_REQUESTED 3
1112
1113 #ifdef HAVE_TCG_QEMU_TB_EXEC
1114 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
1115 #else
1116 # define tcg_qemu_tb_exec(env, tb_ptr) \
1117     ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr)
1118 #endif
1119
1120 void tcg_register_jit(void *buf, size_t buf_size);
1121
1122 /*
1123  * Memory helpers that will be used by TCG generated code.
1124  */
1125 #ifdef CONFIG_SOFTMMU
1126 /* Value zero-extended to tcg register size.  */
1127 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
1128                                      TCGMemOpIdx oi, uintptr_t retaddr);
1129 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
1130                                     TCGMemOpIdx oi, uintptr_t retaddr);
1131 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
1132                                     TCGMemOpIdx oi, uintptr_t retaddr);
1133 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
1134                            TCGMemOpIdx oi, uintptr_t retaddr);
1135 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
1136                                     TCGMemOpIdx oi, uintptr_t retaddr);
1137 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
1138                                     TCGMemOpIdx oi, uintptr_t retaddr);
1139 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
1140                            TCGMemOpIdx oi, uintptr_t retaddr);
1141
1142 /* Value sign-extended to tcg register size.  */
1143 tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
1144                                      TCGMemOpIdx oi, uintptr_t retaddr);
1145 tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
1146                                     TCGMemOpIdx oi, uintptr_t retaddr);
1147 tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
1148                                     TCGMemOpIdx oi, uintptr_t retaddr);
1149 tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
1150                                     TCGMemOpIdx oi, uintptr_t retaddr);
1151 tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
1152                                     TCGMemOpIdx oi, uintptr_t retaddr);
1153
1154 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
1155                         TCGMemOpIdx oi, uintptr_t retaddr);
1156 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1157                        TCGMemOpIdx oi, uintptr_t retaddr);
1158 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1159                        TCGMemOpIdx oi, uintptr_t retaddr);
1160 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1161                        TCGMemOpIdx oi, uintptr_t retaddr);
1162 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1163                        TCGMemOpIdx oi, uintptr_t retaddr);
1164 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1165                        TCGMemOpIdx oi, uintptr_t retaddr);
1166 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1167                        TCGMemOpIdx oi, uintptr_t retaddr);
1168
1169 uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
1170                             TCGMemOpIdx oi, uintptr_t retaddr);
1171 uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
1172                             TCGMemOpIdx oi, uintptr_t retaddr);
1173 uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
1174                             TCGMemOpIdx oi, uintptr_t retaddr);
1175 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
1176                             TCGMemOpIdx oi, uintptr_t retaddr);
1177 uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
1178                             TCGMemOpIdx oi, uintptr_t retaddr);
1179 uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
1180                             TCGMemOpIdx oi, uintptr_t retaddr);
1181 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
1182                             TCGMemOpIdx oi, uintptr_t retaddr);
1183
1184 /* Temporary aliases until backends are converted.  */
1185 #ifdef TARGET_WORDS_BIGENDIAN
1186 # define helper_ret_ldsw_mmu  helper_be_ldsw_mmu
1187 # define helper_ret_lduw_mmu  helper_be_lduw_mmu
1188 # define helper_ret_ldsl_mmu  helper_be_ldsl_mmu
1189 # define helper_ret_ldul_mmu  helper_be_ldul_mmu
1190 # define helper_ret_ldl_mmu   helper_be_ldul_mmu
1191 # define helper_ret_ldq_mmu   helper_be_ldq_mmu
1192 # define helper_ret_stw_mmu   helper_be_stw_mmu
1193 # define helper_ret_stl_mmu   helper_be_stl_mmu
1194 # define helper_ret_stq_mmu   helper_be_stq_mmu
1195 # define helper_ret_ldw_cmmu  helper_be_ldw_cmmu
1196 # define helper_ret_ldl_cmmu  helper_be_ldl_cmmu
1197 # define helper_ret_ldq_cmmu  helper_be_ldq_cmmu
1198 #else
1199 # define helper_ret_ldsw_mmu  helper_le_ldsw_mmu
1200 # define helper_ret_lduw_mmu  helper_le_lduw_mmu
1201 # define helper_ret_ldsl_mmu  helper_le_ldsl_mmu
1202 # define helper_ret_ldul_mmu  helper_le_ldul_mmu
1203 # define helper_ret_ldl_mmu   helper_le_ldul_mmu
1204 # define helper_ret_ldq_mmu   helper_le_ldq_mmu
1205 # define helper_ret_stw_mmu   helper_le_stw_mmu
1206 # define helper_ret_stl_mmu   helper_le_stl_mmu
1207 # define helper_ret_stq_mmu   helper_le_stq_mmu
1208 # define helper_ret_ldw_cmmu  helper_le_ldw_cmmu
1209 # define helper_ret_ldl_cmmu  helper_le_ldl_cmmu
1210 # define helper_ret_ldq_cmmu  helper_le_ldq_cmmu
1211 #endif
1212
1213 uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
1214                                     uint32_t cmpv, uint32_t newv,
1215                                     TCGMemOpIdx oi, uintptr_t retaddr);
1216 uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
1217                                        uint32_t cmpv, uint32_t newv,
1218                                        TCGMemOpIdx oi, uintptr_t retaddr);
1219 uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
1220                                        uint32_t cmpv, uint32_t newv,
1221                                        TCGMemOpIdx oi, uintptr_t retaddr);
1222 uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
1223                                        uint64_t cmpv, uint64_t newv,
1224                                        TCGMemOpIdx oi, uintptr_t retaddr);
1225 uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
1226                                        uint32_t cmpv, uint32_t newv,
1227                                        TCGMemOpIdx oi, uintptr_t retaddr);
1228 uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
1229                                        uint32_t cmpv, uint32_t newv,
1230                                        TCGMemOpIdx oi, uintptr_t retaddr);
1231 uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
1232                                        uint64_t cmpv, uint64_t newv,
1233                                        TCGMemOpIdx oi, uintptr_t retaddr);
1234
1235 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX)         \
1236 TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu         \
1237     (CPUArchState *env, target_ulong addr, TYPE val,  \
1238      TCGMemOpIdx oi, uintptr_t retaddr);
1239
1240 #ifdef CONFIG_ATOMIC64
1241 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1242     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1243     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1244     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1245     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1246     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)  \
1247     GEN_ATOMIC_HELPER(NAME, uint64_t, q_le)  \
1248     GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
1249 #else
1250 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1251     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1252     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1253     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1254     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1255     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
1256 #endif
1257
1258 GEN_ATOMIC_HELPER_ALL(fetch_add)
1259 GEN_ATOMIC_HELPER_ALL(fetch_sub)
1260 GEN_ATOMIC_HELPER_ALL(fetch_and)
1261 GEN_ATOMIC_HELPER_ALL(fetch_or)
1262 GEN_ATOMIC_HELPER_ALL(fetch_xor)
1263
1264 GEN_ATOMIC_HELPER_ALL(add_fetch)
1265 GEN_ATOMIC_HELPER_ALL(sub_fetch)
1266 GEN_ATOMIC_HELPER_ALL(and_fetch)
1267 GEN_ATOMIC_HELPER_ALL(or_fetch)
1268 GEN_ATOMIC_HELPER_ALL(xor_fetch)
1269
1270 GEN_ATOMIC_HELPER_ALL(xchg)
1271
1272 #undef GEN_ATOMIC_HELPER_ALL
1273 #undef GEN_ATOMIC_HELPER
1274 #endif /* CONFIG_SOFTMMU */
1275
1276 #ifdef CONFIG_ATOMIC128
1277 #include "qemu/int128.h"
1278
1279 /* These aren't really a "proper" helpers because TCG cannot manage Int128.
1280    However, use the same format as the others, for use by the backends. */
1281 Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
1282                                      Int128 cmpv, Int128 newv,
1283                                      TCGMemOpIdx oi, uintptr_t retaddr);
1284 Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
1285                                      Int128 cmpv, Int128 newv,
1286                                      TCGMemOpIdx oi, uintptr_t retaddr);
1287
1288 Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
1289                                 TCGMemOpIdx oi, uintptr_t retaddr);
1290 Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
1291                                 TCGMemOpIdx oi, uintptr_t retaddr);
1292 void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1293                               TCGMemOpIdx oi, uintptr_t retaddr);
1294 void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1295                               TCGMemOpIdx oi, uintptr_t retaddr);
1296
1297 #endif /* CONFIG_ATOMIC128 */
1298
1299 #endif /* TCG_H */