zap qemu_egl_has_ext in include/ui/egl-helpers.h
[qemu/kevin.git] / hw / lm32 / lm32_boards.c
blobefa6f91fd2a9c2b94154a8c179bf6c20542407ea
1 /*
2 * QEMU models for LatticeMico32 uclinux and evr32 boards.
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "hw/sysbus.h"
22 #include "hw/hw.h"
23 #include "hw/block/flash.h"
24 #include "hw/devices.h"
25 #include "hw/boards.h"
26 #include "hw/loader.h"
27 #include "sysemu/block-backend.h"
28 #include "elf.h"
29 #include "lm32_hwsetup.h"
30 #include "lm32.h"
31 #include "exec/address-spaces.h"
33 typedef struct {
34 LM32CPU *cpu;
35 hwaddr bootstrap_pc;
36 hwaddr flash_base;
37 hwaddr hwsetup_base;
38 hwaddr initrd_base;
39 size_t initrd_size;
40 hwaddr cmdline_base;
41 } ResetInfo;
43 static void cpu_irq_handler(void *opaque, int irq, int level)
45 LM32CPU *cpu = opaque;
46 CPUState *cs = CPU(cpu);
48 if (level) {
49 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
50 } else {
51 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
55 static void main_cpu_reset(void *opaque)
57 ResetInfo *reset_info = opaque;
58 CPULM32State *env = &reset_info->cpu->env;
60 cpu_reset(CPU(reset_info->cpu));
62 /* init defaults */
63 env->pc = (uint32_t)reset_info->bootstrap_pc;
64 env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
65 env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
66 env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
67 env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
68 reset_info->initrd_size);
69 env->eba = reset_info->flash_base;
70 env->deba = reset_info->flash_base;
73 static void lm32_evr_init(MachineState *machine)
75 const char *cpu_model = machine->cpu_model;
76 const char *kernel_filename = machine->kernel_filename;
77 LM32CPU *cpu;
78 CPULM32State *env;
79 DriveInfo *dinfo;
80 MemoryRegion *address_space_mem = get_system_memory();
81 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
82 qemu_irq irq[32];
83 ResetInfo *reset_info;
84 int i;
86 /* memory map */
87 hwaddr flash_base = 0x04000000;
88 size_t flash_sector_size = 256 * 1024;
89 size_t flash_size = 32 * 1024 * 1024;
90 hwaddr ram_base = 0x08000000;
91 size_t ram_size = 64 * 1024 * 1024;
92 hwaddr timer0_base = 0x80002000;
93 hwaddr uart0_base = 0x80006000;
94 hwaddr timer1_base = 0x8000a000;
95 int uart0_irq = 0;
96 int timer0_irq = 1;
97 int timer1_irq = 3;
99 reset_info = g_malloc0(sizeof(ResetInfo));
101 if (cpu_model == NULL) {
102 cpu_model = "lm32-full";
104 cpu = cpu_lm32_init(cpu_model);
105 if (cpu == NULL) {
106 fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
107 exit(1);
110 env = &cpu->env;
111 reset_info->cpu = cpu;
113 reset_info->flash_base = flash_base;
115 memory_region_allocate_system_memory(phys_ram, NULL, "lm32_evr.sdram",
116 ram_size);
117 memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
119 dinfo = drive_get(IF_PFLASH, 0, 0);
120 /* Spansion S29NS128P */
121 pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
122 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
123 flash_sector_size, flash_size / flash_sector_size,
124 1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
126 /* create irq lines */
127 env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
128 for (i = 0; i < 32; i++) {
129 irq[i] = qdev_get_gpio_in(env->pic_state, i);
132 sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
133 sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
134 sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
136 /* make sure juart isn't the first chardev */
137 env->juart_state = lm32_juart_init();
139 reset_info->bootstrap_pc = flash_base;
141 if (kernel_filename) {
142 uint64_t entry;
143 int kernel_size;
145 kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
146 1, EM_LATTICEMICO32, 0);
147 reset_info->bootstrap_pc = entry;
149 if (kernel_size < 0) {
150 kernel_size = load_image_targphys(kernel_filename, ram_base,
151 ram_size);
152 reset_info->bootstrap_pc = ram_base;
155 if (kernel_size < 0) {
156 fprintf(stderr, "qemu: could not load kernel '%s'\n",
157 kernel_filename);
158 exit(1);
162 qemu_register_reset(main_cpu_reset, reset_info);
165 static void lm32_uclinux_init(MachineState *machine)
167 const char *cpu_model = machine->cpu_model;
168 const char *kernel_filename = machine->kernel_filename;
169 const char *kernel_cmdline = machine->kernel_cmdline;
170 const char *initrd_filename = machine->initrd_filename;
171 LM32CPU *cpu;
172 CPULM32State *env;
173 DriveInfo *dinfo;
174 MemoryRegion *address_space_mem = get_system_memory();
175 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
176 qemu_irq irq[32];
177 HWSetup *hw;
178 ResetInfo *reset_info;
179 int i;
181 /* memory map */
182 hwaddr flash_base = 0x04000000;
183 size_t flash_sector_size = 256 * 1024;
184 size_t flash_size = 32 * 1024 * 1024;
185 hwaddr ram_base = 0x08000000;
186 size_t ram_size = 64 * 1024 * 1024;
187 hwaddr uart0_base = 0x80000000;
188 hwaddr timer0_base = 0x80002000;
189 hwaddr timer1_base = 0x80010000;
190 hwaddr timer2_base = 0x80012000;
191 int uart0_irq = 0;
192 int timer0_irq = 1;
193 int timer1_irq = 20;
194 int timer2_irq = 21;
195 hwaddr hwsetup_base = 0x0bffe000;
196 hwaddr cmdline_base = 0x0bfff000;
197 hwaddr initrd_base = 0x08400000;
198 size_t initrd_max = 0x01000000;
200 reset_info = g_malloc0(sizeof(ResetInfo));
202 if (cpu_model == NULL) {
203 cpu_model = "lm32-full";
205 cpu = cpu_lm32_init(cpu_model);
206 if (cpu == NULL) {
207 fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
208 exit(1);
211 env = &cpu->env;
212 reset_info->cpu = cpu;
214 reset_info->flash_base = flash_base;
216 memory_region_allocate_system_memory(phys_ram, NULL,
217 "lm32_uclinux.sdram", ram_size);
218 memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
220 dinfo = drive_get(IF_PFLASH, 0, 0);
221 /* Spansion S29NS128P */
222 pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
223 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
224 flash_sector_size, flash_size / flash_sector_size,
225 1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
227 /* create irq lines */
228 env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));
229 for (i = 0; i < 32; i++) {
230 irq[i] = qdev_get_gpio_in(env->pic_state, i);
233 sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
234 sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
235 sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
236 sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
238 /* make sure juart isn't the first chardev */
239 env->juart_state = lm32_juart_init();
241 reset_info->bootstrap_pc = flash_base;
243 if (kernel_filename) {
244 uint64_t entry;
245 int kernel_size;
247 kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
248 1, EM_LATTICEMICO32, 0);
249 reset_info->bootstrap_pc = entry;
251 if (kernel_size < 0) {
252 kernel_size = load_image_targphys(kernel_filename, ram_base,
253 ram_size);
254 reset_info->bootstrap_pc = ram_base;
257 if (kernel_size < 0) {
258 fprintf(stderr, "qemu: could not load kernel '%s'\n",
259 kernel_filename);
260 exit(1);
264 /* generate a rom with the hardware description */
265 hw = hwsetup_init();
266 hwsetup_add_cpu(hw, "LM32", 75000000);
267 hwsetup_add_flash(hw, "flash", flash_base, flash_size);
268 hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
269 hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
270 hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
271 hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
272 hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
273 hwsetup_add_trailer(hw);
274 hwsetup_create_rom(hw, hwsetup_base);
275 hwsetup_free(hw);
277 reset_info->hwsetup_base = hwsetup_base;
279 if (kernel_cmdline && strlen(kernel_cmdline)) {
280 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
281 kernel_cmdline);
282 reset_info->cmdline_base = cmdline_base;
285 if (initrd_filename) {
286 size_t initrd_size;
287 initrd_size = load_image_targphys(initrd_filename, initrd_base,
288 initrd_max);
289 reset_info->initrd_base = initrd_base;
290 reset_info->initrd_size = initrd_size;
293 qemu_register_reset(main_cpu_reset, reset_info);
296 static void lm32_evr_class_init(ObjectClass *oc, void *data)
298 MachineClass *mc = MACHINE_CLASS(oc);
300 mc->desc = "LatticeMico32 EVR32 eval system";
301 mc->init = lm32_evr_init;
302 mc->is_default = 1;
305 static const TypeInfo lm32_evr_type = {
306 .name = MACHINE_TYPE_NAME("lm32-evr"),
307 .parent = TYPE_MACHINE,
308 .class_init = lm32_evr_class_init,
311 static void lm32_uclinux_class_init(ObjectClass *oc, void *data)
313 MachineClass *mc = MACHINE_CLASS(oc);
315 mc->desc = "lm32 platform for uClinux and u-boot by Theobroma Systems";
316 mc->init = lm32_uclinux_init;
317 mc->is_default = 0;
320 static const TypeInfo lm32_uclinux_type = {
321 .name = MACHINE_TYPE_NAME("lm32-uclinux"),
322 .parent = TYPE_MACHINE,
323 .class_init = lm32_uclinux_class_init,
326 static void lm32_machine_init(void)
328 type_register_static(&lm32_evr_type);
329 type_register_static(&lm32_uclinux_type);
332 machine_init(lm32_machine_init)