target/openrisc/cpu.c

   1 /*
   2  * QEMU OpenRISC CPU
   3  *
   4  * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "qemu-common.h"
  24
  25 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
  26 {
  27     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  28
  29     cpu->env.pc = value;
  30 }
  31
  32 static bool openrisc_cpu_has_work(CPUState *cs)
  33 {
  34     return cs->interrupt_request & (CPU_INTERRUPT_HARD |
  35                                     CPU_INTERRUPT_TIMER);
  36 }
  37
  38 /* CPUClass::reset() */
  39 static void openrisc_cpu_reset(CPUState *s)
  40 {
  41     OpenRISCCPU *cpu = OPENRISC_CPU(s);
  42     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
  43
  44     occ->parent_reset(s);
  45
  46     memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
  47
  48     cpu->env.pc = 0x100;
  49     cpu->env.sr = SR_FO | SR_SM;
  50     cpu->env.lock_addr = -1;
  51     s->exception_index = -1;
  52
  53     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP |
  54                    UPR_PMP;
  55     cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
  56     cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
  57
  58 #ifndef CONFIG_USER_ONLY
  59     cpu->env.picmr = 0x00000000;
  60     cpu->env.picsr = 0x00000000;
  61
  62     cpu->env.ttmr = 0x00000000;
  63 #endif
  64 }
  65
  66 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
  67 {
  68     CPUState *cs = CPU(dev);
  69     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
  70     Error *local_err = NULL;
  71
  72     cpu_exec_realizefn(cs, &local_err);
  73     if (local_err != NULL) {
  74         error_propagate(errp, local_err);
  75         return;
  76     }
  77
  78     qemu_init_vcpu(cs);
  79     cpu_reset(cs);
  80
  81     occ->parent_realize(dev, errp);
  82 }
  83
  84 static void openrisc_cpu_initfn(Object *obj)
  85 {
  86     CPUState *cs = CPU(obj);
  87     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
  88
  89     cs->env_ptr = &cpu->env;
  90
  91 #ifndef CONFIG_USER_ONLY
  92     cpu_openrisc_mmu_init(cpu);
  93 #endif
  94 }
  95
  96 /* CPU models */
  97
  98 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
  99 {
 100     ObjectClass *oc;
 101     char *typename;
 102
 103     typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model);
 104     oc = object_class_by_name(typename);
 105     g_free(typename);
 106     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
 107                        object_class_is_abstract(oc))) {
 108         return NULL;
 109     }
 110     return oc;
 111 }
 112
 113 static void or1200_initfn(Object *obj)
 114 {
 115     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 116
 117     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
 118                        CPUCFGR_EVBARP;
 119 }
 120
 121 static void openrisc_any_initfn(Object *obj)
 122 {
 123     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 124
 125     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP;
 126 }
 127
 128 static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
 129 {
 130     OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
 131     CPUClass *cc = CPU_CLASS(occ);
 132     DeviceClass *dc = DEVICE_CLASS(oc);
 133
 134     device_class_set_parent_realize(dc, openrisc_cpu_realizefn,
 135                                     &occ->parent_realize);
 136     occ->parent_reset = cc->reset;
 137     cc->reset = openrisc_cpu_reset;
 138
 139     cc->class_by_name = openrisc_cpu_class_by_name;
 140     cc->has_work = openrisc_cpu_has_work;
 141     cc->do_interrupt = openrisc_cpu_do_interrupt;
 142     cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
 143     cc->dump_state = openrisc_cpu_dump_state;
 144     cc->set_pc = openrisc_cpu_set_pc;
 145     cc->gdb_read_register = openrisc_cpu_gdb_read_register;
 146     cc->gdb_write_register = openrisc_cpu_gdb_write_register;
 147 #ifdef CONFIG_USER_ONLY
 148     cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault;
 149 #else
 150     cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
 151     dc->vmsd = &vmstate_openrisc_cpu;
 152 #endif
 153     cc->gdb_num_core_regs = 32 + 3;
 154     cc->tcg_initialize = openrisc_translate_init;
 155 }
 156
 157 /* Sort alphabetically by type name, except for "any". */
 158 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
 159 {
 160     ObjectClass *class_a = (ObjectClass *)a;
 161     ObjectClass *class_b = (ObjectClass *)b;
 162     const char *name_a, *name_b;
 163
 164     name_a = object_class_get_name(class_a);
 165     name_b = object_class_get_name(class_b);
 166     if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
 167         return 1;
 168     } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
 169         return -1;
 170     } else {
 171         return strcmp(name_a, name_b);
 172     }
 173 }
 174
 175 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
 176 {
 177     ObjectClass *oc = data;
 178     CPUListState *s = user_data;
 179     const char *typename;
 180     char *name;
 181
 182     typename = object_class_get_name(oc);
 183     name = g_strndup(typename,
 184                      strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
 185     (*s->cpu_fprintf)(s->file, "  %s\n",
 186                       name);
 187     g_free(name);
 188 }
 189
 190 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
 191 {
 192     CPUListState s = {
 193         .file = f,
 194         .cpu_fprintf = cpu_fprintf,
 195     };
 196     GSList *list;
 197
 198     list = object_class_get_list(TYPE_OPENRISC_CPU, false);
 199     list = g_slist_sort(list, openrisc_cpu_list_compare);
 200     (*cpu_fprintf)(f, "Available CPUs:\n");
 201     g_slist_foreach(list, openrisc_cpu_list_entry, &s);
 202     g_slist_free(list);
 203 }
 204
 205 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \
 206     {                                               \
 207         .parent = TYPE_OPENRISC_CPU,                \
 208         .instance_init = initfn,                    \
 209         .name = OPENRISC_CPU_TYPE_NAME(cpu_model),  \
 210     }
 211
 212 static const TypeInfo openrisc_cpus_type_infos[] = {
 213     { /* base class should be registered first */
 214         .name = TYPE_OPENRISC_CPU,
 215         .parent = TYPE_CPU,
 216         .instance_size = sizeof(OpenRISCCPU),
 217         .instance_init = openrisc_cpu_initfn,
 218         .abstract = true,
 219         .class_size = sizeof(OpenRISCCPUClass),
 220         .class_init = openrisc_cpu_class_init,
 221     },
 222     DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn),
 223     DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn),
 224 };
 225
 226 DEFINE_TYPES(openrisc_cpus_type_infos)