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ppc: Speed up dcbz
[qemu/kevin.git] / target-ppc / translate.c
blobac2c79bf28697dea848f347c4f6de602fee6aad2
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91 tcg_ctx.tcg_env = cpu_env;
92
93 p = cpu_reg_names;
94 cpu_reg_names_size = sizeof(cpu_reg_names);
95
96 for (i = 0; i < 8; i++) {
97 snprintf(p, cpu_reg_names_size, "crf%d", i);
98 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
99 offsetof(CPUPPCState, crf[i]), p);
100 p += 5;
101 cpu_reg_names_size -= 5;
102 }
103
104 for (i = 0; i < 32; i++) {
105 snprintf(p, cpu_reg_names_size, "r%d", i);
106 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gpr[i]), p);
108 p += (i < 10) ? 3 : 4;
109 cpu_reg_names_size -= (i < 10) ? 3 : 4;
110 snprintf(p, cpu_reg_names_size, "r%dH", i);
111 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUPPCState, gprh[i]), p);
113 p += (i < 10) ? 4 : 5;
114 cpu_reg_names_size -= (i < 10) ? 4 : 5;
115
116 snprintf(p, cpu_reg_names_size, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
118 offsetof(CPUPPCState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120 cpu_reg_names_size -= (i < 10) ? 4 : 5;
121
122 snprintf(p, cpu_reg_names_size, "avr%dH", i);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
125 offsetof(CPUPPCState, avr[i].u64[0]), p);
126 #else
127 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
128 offsetof(CPUPPCState, avr[i].u64[1]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 cpu_reg_names_size -= (i < 10) ? 6 : 7;
132
133 snprintf(p, cpu_reg_names_size, "avr%dL", i);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
136 offsetof(CPUPPCState, avr[i].u64[1]), p);
137 #else
138 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
139 offsetof(CPUPPCState, avr[i].u64[0]), p);
140 #endif
141 p += (i < 10) ? 6 : 7;
142 cpu_reg_names_size -= (i < 10) ? 6 : 7;
143 snprintf(p, cpu_reg_names_size, "vsr%d", i);
144 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
145 offsetof(CPUPPCState, vsr[i]), p);
146 p += (i < 10) ? 5 : 6;
147 cpu_reg_names_size -= (i < 10) ? 5 : 6;
148 }
149
150 cpu_nip = tcg_global_mem_new(cpu_env,
151 offsetof(CPUPPCState, nip), "nip");
152
153 cpu_msr = tcg_global_mem_new(cpu_env,
154 offsetof(CPUPPCState, msr), "msr");
155
156 cpu_ctr = tcg_global_mem_new(cpu_env,
157 offsetof(CPUPPCState, ctr), "ctr");
158
159 cpu_lr = tcg_global_mem_new(cpu_env,
160 offsetof(CPUPPCState, lr), "lr");
161
162 #if defined(TARGET_PPC64)
163 cpu_cfar = tcg_global_mem_new(cpu_env,
164 offsetof(CPUPPCState, cfar), "cfar");
165 #endif
166
167 cpu_xer = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, xer), "xer");
169 cpu_so = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, so), "SO");
171 cpu_ov = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ov), "OV");
173 cpu_ca = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ca), "CA");
175
176 cpu_reserve = tcg_global_mem_new(cpu_env,
177 offsetof(CPUPPCState, reserve_addr),
178 "reserve_addr");
179
180 cpu_fpscr = tcg_global_mem_new(cpu_env,
181 offsetof(CPUPPCState, fpscr), "fpscr");
182
183 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
184 offsetof(CPUPPCState, access_type), "access_type");
185
186 done_init = 1;
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 struct TranslationBlock *tb;
192 target_ulong nip;
193 uint32_t opcode;
194 uint32_t exception;
195 /* Routine used to access memory */
196 bool pr, hv, dr, le_mode;
197 bool lazy_tlb_flush;
198 int mem_idx;
199 int access_type;
200 /* Translation flags */
201 TCGMemOp default_tcg_memop_mask;
202 #if defined(TARGET_PPC64)
203 bool sf_mode;
204 bool has_cfar;
205 #endif
206 bool fpu_enabled;
207 bool altivec_enabled;
208 bool vsx_enabled;
209 bool spe_enabled;
210 bool tm_enabled;
211 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
212 int singlestep_enabled;
213 uint64_t insns_flags;
214 uint64_t insns_flags2;
215 };
216
217 /* Return true iff byteswap is needed in a scalar memop */
218 static inline bool need_byteswap(const DisasContext *ctx)
219 {
220 #if defined(TARGET_WORDS_BIGENDIAN)
221 return ctx->le_mode;
222 #else
223 return !ctx->le_mode;
224 #endif
225 }
226
227 /* True when active word size < size of target_long. */
228 #ifdef TARGET_PPC64
229 # define NARROW_MODE(C) (!(C)->sf_mode)
230 #else
231 # define NARROW_MODE(C) 0
232 #endif
233
234 struct opc_handler_t {
235 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
236 uint32_t inval1;
237 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
238 uint32_t inval2;
239 /* instruction type */
240 uint64_t type;
241 /* extended instruction type */
242 uint64_t type2;
243 /* handler */
244 void (*handler)(DisasContext *ctx);
245 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
246 const char *oname;
247 #endif
248 #if defined(DO_PPC_STATISTICS)
249 uint64_t count;
250 #endif
251 };
252
253 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
254 {
255 if (ctx->access_type != access_type) {
256 tcg_gen_movi_i32(cpu_access_type, access_type);
257 ctx->access_type = access_type;
258 }
259 }
260
261 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
262 {
263 if (NARROW_MODE(ctx)) {
264 nip = (uint32_t)nip;
265 }
266 tcg_gen_movi_tl(cpu_nip, nip);
267 }
268
269 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
270 {
271 TCGv_i32 t0, t1;
272
273 /* These are all synchronous exceptions, we set the PC back to
274 * the faulting instruction
275 */
276 if (ctx->exception == POWERPC_EXCP_NONE) {
277 gen_update_nip(ctx, ctx->nip - 4);
278 }
279 t0 = tcg_const_i32(excp);
280 t1 = tcg_const_i32(error);
281 gen_helper_raise_exception_err(cpu_env, t0, t1);
282 tcg_temp_free_i32(t0);
283 tcg_temp_free_i32(t1);
284 ctx->exception = (excp);
285 }
286
287 static void gen_exception(DisasContext *ctx, uint32_t excp)
288 {
289 TCGv_i32 t0;
290
291 /* These are all synchronous exceptions, we set the PC back to
292 * the faulting instruction
293 */
294 if (ctx->exception == POWERPC_EXCP_NONE) {
295 gen_update_nip(ctx, ctx->nip - 4);
296 }
297 t0 = tcg_const_i32(excp);
298 gen_helper_raise_exception(cpu_env, t0);
299 tcg_temp_free_i32(t0);
300 ctx->exception = (excp);
301 }
302
303 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
304 target_ulong nip)
305 {
306 TCGv_i32 t0;
307
308 gen_update_nip(ctx, nip);
309 t0 = tcg_const_i32(excp);
310 gen_helper_raise_exception(cpu_env, t0);
311 tcg_temp_free_i32(t0);
312 ctx->exception = (excp);
313 }
314
315 static void gen_debug_exception(DisasContext *ctx)
316 {
317 TCGv_i32 t0;
318
319 /* These are all synchronous exceptions, we set the PC back to
320 * the faulting instruction
321 */
322 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
323 (ctx->exception != POWERPC_EXCP_SYNC)) {
324 gen_update_nip(ctx, ctx->nip - 4);
325 }
326 t0 = tcg_const_i32(EXCP_DEBUG);
327 gen_helper_raise_exception(cpu_env, t0);
328 tcg_temp_free_i32(t0);
329 }
330
331 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
332 {
333 /* Will be converted to program check if needed */
334 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
335 }
336
337 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
338 {
339 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
340 }
341
342 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
343 {
344 /* Will be converted to program check if needed */
345 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
346 }
347
348 /* Stop translation */
349 static inline void gen_stop_exception(DisasContext *ctx)
350 {
351 gen_update_nip(ctx, ctx->nip);
352 ctx->exception = POWERPC_EXCP_STOP;
353 }
354
355 #ifndef CONFIG_USER_ONLY
356 /* No need to update nip here, as execution flow will change */
357 static inline void gen_sync_exception(DisasContext *ctx)
358 {
359 ctx->exception = POWERPC_EXCP_SYNC;
360 }
361 #endif
362
363 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
364 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
365
366 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
367 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
368
369 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
370 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
371
372 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
373 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
374
375 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
376 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
377
378 typedef struct opcode_t {
379 unsigned char opc1, opc2, opc3, opc4;
380 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
381 unsigned char pad[4];
382 #endif
383 opc_handler_t handler;
384 const char *oname;
385 } opcode_t;
386
387 /* Helpers for priv. check */
388 #define GEN_PRIV \
389 do { \
390 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
391 } while (0)
392
393 #if defined(CONFIG_USER_ONLY)
394 #define CHK_HV GEN_PRIV
395 #define CHK_SV GEN_PRIV
396 #define CHK_HVRM GEN_PRIV
397 #else
398 #define CHK_HV \
399 do { \
400 if (unlikely(ctx->pr || !ctx->hv)) { \
401 GEN_PRIV; \
402 } \
403 } while (0)
404 #define CHK_SV \
405 do { \
406 if (unlikely(ctx->pr)) { \
407 GEN_PRIV; \
408 } \
409 } while (0)
410 #define CHK_HVRM \
411 do { \
412 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
413 GEN_PRIV; \
414 } \
415 } while (0)
416 #endif
417
418 #define CHK_NONE
419
420
421 /*****************************************************************************/
422 /*** Instruction decoding ***/
423 #define EXTRACT_HELPER(name, shift, nb) \
424 static inline uint32_t name(uint32_t opcode) \
425 { \
426 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
427 }
428
429 #define EXTRACT_SHELPER(name, shift, nb) \
430 static inline int32_t name(uint32_t opcode) \
431 { \
432 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
433 }
434
435 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
436 static inline uint32_t name(uint32_t opcode) \
437 { \
438 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
439 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
440 }
441
442 #define EXTRACT_HELPER_DXFORM(name, \
443 d0_bits, shift_op_d0, shift_d0, \
444 d1_bits, shift_op_d1, shift_d1, \
445 d2_bits, shift_op_d2, shift_d2) \
446 static inline int16_t name(uint32_t opcode) \
447 { \
448 return \
449 (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
450 (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
451 (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
452 }
453
454
455 /* Opcode part 1 */
456 EXTRACT_HELPER(opc1, 26, 6);
457 /* Opcode part 2 */
458 EXTRACT_HELPER(opc2, 1, 5);
459 /* Opcode part 3 */
460 EXTRACT_HELPER(opc3, 6, 5);
461 /* Opcode part 4 */
462 EXTRACT_HELPER(opc4, 16, 5);
463 /* Update Cr0 flags */
464 EXTRACT_HELPER(Rc, 0, 1);
465 /* Update Cr6 flags (Altivec) */
466 EXTRACT_HELPER(Rc21, 10, 1);
467 /* Destination */
468 EXTRACT_HELPER(rD, 21, 5);
469 /* Source */
470 EXTRACT_HELPER(rS, 21, 5);
471 /* First operand */
472 EXTRACT_HELPER(rA, 16, 5);
473 /* Second operand */
474 EXTRACT_HELPER(rB, 11, 5);
475 /* Third operand */
476 EXTRACT_HELPER(rC, 6, 5);
477 /*** Get CRn ***/
478 EXTRACT_HELPER(crfD, 23, 3);
479 EXTRACT_HELPER(crfS, 18, 3);
480 EXTRACT_HELPER(crbD, 21, 5);
481 EXTRACT_HELPER(crbA, 16, 5);
482 EXTRACT_HELPER(crbB, 11, 5);
483 /* SPR / TBL */
484 EXTRACT_HELPER(_SPR, 11, 10);
485 static inline uint32_t SPR(uint32_t opcode)
486 {
487 uint32_t sprn = _SPR(opcode);
488
489 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
490 }
491 /*** Get constants ***/
492 /* 16 bits signed immediate value */
493 EXTRACT_SHELPER(SIMM, 0, 16);
494 /* 16 bits unsigned immediate value */
495 EXTRACT_HELPER(UIMM, 0, 16);
496 /* 5 bits signed immediate value */
497 EXTRACT_HELPER(SIMM5, 16, 5);
498 /* 5 bits signed immediate value */
499 EXTRACT_HELPER(UIMM5, 16, 5);
500 /* Bit count */
501 EXTRACT_HELPER(NB, 11, 5);
502 /* Shift count */
503 EXTRACT_HELPER(SH, 11, 5);
504 /* Vector shift count */
505 EXTRACT_HELPER(VSH, 6, 4);
506 /* Mask start */
507 EXTRACT_HELPER(MB, 6, 5);
508 /* Mask end */
509 EXTRACT_HELPER(ME, 1, 5);
510 /* Trap operand */
511 EXTRACT_HELPER(TO, 21, 5);
512
513 EXTRACT_HELPER(CRM, 12, 8);
514
515 #ifndef CONFIG_USER_ONLY
516 EXTRACT_HELPER(SR, 16, 4);
517 #endif
518
519 /* mtfsf/mtfsfi */
520 EXTRACT_HELPER(FPBF, 23, 3);
521 EXTRACT_HELPER(FPIMM, 12, 4);
522 EXTRACT_HELPER(FPL, 25, 1);
523 EXTRACT_HELPER(FPFLM, 17, 8);
524 EXTRACT_HELPER(FPW, 16, 1);
525
526 /* addpcis */
527 EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
528
529 /*** Jump target decoding ***/
530 /* Immediate address */
531 static inline target_ulong LI(uint32_t opcode)
532 {
533 return (opcode >> 0) & 0x03FFFFFC;
534 }
535
536 static inline uint32_t BD(uint32_t opcode)
537 {
538 return (opcode >> 0) & 0xFFFC;
539 }
540
541 EXTRACT_HELPER(BO, 21, 5);
542 EXTRACT_HELPER(BI, 16, 5);
543 /* Absolute/relative address */
544 EXTRACT_HELPER(AA, 1, 1);
545 /* Link */
546 EXTRACT_HELPER(LK, 0, 1);
547
548 /* DFP Z22-form */
549 EXTRACT_HELPER(DCM, 10, 6)
550
551 /* DFP Z23-form */
552 EXTRACT_HELPER(RMC, 9, 2)
553
554 /* Create a mask between <start> and <end> bits */
555 static inline target_ulong MASK(uint32_t start, uint32_t end)
556 {
557 target_ulong ret;
558
559 #if defined(TARGET_PPC64)
560 if (likely(start == 0)) {
561 ret = UINT64_MAX << (63 - end);
562 } else if (likely(end == 63)) {
563 ret = UINT64_MAX >> start;
564 }
565 #else
566 if (likely(start == 0)) {
567 ret = UINT32_MAX << (31 - end);
568 } else if (likely(end == 31)) {
569 ret = UINT32_MAX >> start;
570 }
571 #endif
572 else {
573 ret = (((target_ulong)(-1ULL)) >> (start)) ^
574 (((target_ulong)(-1ULL) >> (end)) >> 1);
575 if (unlikely(start > end))
576 return ~ret;
577 }
578
579 return ret;
580 }
581
582 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
583 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
584 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
585 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
586 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
587 EXTRACT_HELPER(DM, 8, 2);
588 EXTRACT_HELPER(UIM, 16, 2);
589 EXTRACT_HELPER(SHW, 8, 2);
590 EXTRACT_HELPER(SP, 19, 2);
591 /*****************************************************************************/
592 /* PowerPC instructions table */
593
594 #if defined(DO_PPC_STATISTICS)
595 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
596 { \
597 .opc1 = op1, \
598 .opc2 = op2, \
599 .opc3 = op3, \
600 .opc4 = 0xff, \
601 .handler = { \
602 .inval1 = invl, \
603 .type = _typ, \
604 .type2 = _typ2, \
605 .handler = &gen_##name, \
606 .oname = stringify(name), \
607 }, \
608 .oname = stringify(name), \
609 }
610 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
611 { \
612 .opc1 = op1, \
613 .opc2 = op2, \
614 .opc3 = op3, \
615 .opc4 = 0xff, \
616 .handler = { \
617 .inval1 = invl1, \
618 .inval2 = invl2, \
619 .type = _typ, \
620 .type2 = _typ2, \
621 .handler = &gen_##name, \
622 .oname = stringify(name), \
623 }, \
624 .oname = stringify(name), \
625 }
626 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
627 { \
628 .opc1 = op1, \
629 .opc2 = op2, \
630 .opc3 = op3, \
631 .opc4 = 0xff, \
632 .handler = { \
633 .inval1 = invl, \
634 .type = _typ, \
635 .type2 = _typ2, \
636 .handler = &gen_##name, \
637 .oname = onam, \
638 }, \
639 .oname = onam, \
640 }
641 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
642 { \
643 .opc1 = op1, \
644 .opc2 = op2, \
645 .opc3 = op3, \
646 .opc4 = op4, \
647 .handler = { \
648 .inval1 = invl, \
649 .type = _typ, \
650 .type2 = _typ2, \
651 .handler = &gen_##name, \
652 .oname = stringify(name), \
653 }, \
654 .oname = stringify(name), \
655 }
656 #else
657 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
658 { \
659 .opc1 = op1, \
660 .opc2 = op2, \
661 .opc3 = op3, \
662 .opc4 = 0xff, \
663 .handler = { \
664 .inval1 = invl, \
665 .type = _typ, \
666 .type2 = _typ2, \
667 .handler = &gen_##name, \
668 }, \
669 .oname = stringify(name), \
670 }
671 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
672 { \
673 .opc1 = op1, \
674 .opc2 = op2, \
675 .opc3 = op3, \
676 .opc4 = 0xff, \
677 .handler = { \
678 .inval1 = invl1, \
679 .inval2 = invl2, \
680 .type = _typ, \
681 .type2 = _typ2, \
682 .handler = &gen_##name, \
683 }, \
684 .oname = stringify(name), \
685 }
686 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
687 { \
688 .opc1 = op1, \
689 .opc2 = op2, \
690 .opc3 = op3, \
691 .opc4 = 0xff, \
692 .handler = { \
693 .inval1 = invl, \
694 .type = _typ, \
695 .type2 = _typ2, \
696 .handler = &gen_##name, \
697 }, \
698 .oname = onam, \
699 }
700 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
701 { \
702 .opc1 = op1, \
703 .opc2 = op2, \
704 .opc3 = op3, \
705 .opc4 = op4, \
706 .handler = { \
707 .inval1 = invl, \
708 .type = _typ, \
709 .type2 = _typ2, \
710 .handler = &gen_##name, \
711 }, \
712 .oname = stringify(name), \
713 }
714 #endif
715
716 /* SPR load/store helpers */
717 static inline void gen_load_spr(TCGv t, int reg)
718 {
719 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
720 }
721
722 static inline void gen_store_spr(int reg, TCGv t)
723 {
724 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
725 }
726
727 /* Invalid instruction */
728 static void gen_invalid(DisasContext *ctx)
729 {
730 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
731 }
732
733 static opc_handler_t invalid_handler = {
734 .inval1 = 0xFFFFFFFF,
735 .inval2 = 0xFFFFFFFF,
736 .type = PPC_NONE,
737 .type2 = PPC_NONE,
738 .handler = gen_invalid,
739 };
740
741 /*** Integer comparison ***/
742
743 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
744 {
745 TCGv t0 = tcg_temp_new();
746 TCGv_i32 t1 = tcg_temp_new_i32();
747
748 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
749
750 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
751 tcg_gen_trunc_tl_i32(t1, t0);
752 tcg_gen_shli_i32(t1, t1, CRF_LT);
753 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
754
755 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
756 tcg_gen_trunc_tl_i32(t1, t0);
757 tcg_gen_shli_i32(t1, t1, CRF_GT);
758 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
759
760 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
761 tcg_gen_trunc_tl_i32(t1, t0);
762 tcg_gen_shli_i32(t1, t1, CRF_EQ);
763 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
764
765 tcg_temp_free(t0);
766 tcg_temp_free_i32(t1);
767 }
768
769 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
770 {
771 TCGv t0 = tcg_const_tl(arg1);
772 gen_op_cmp(arg0, t0, s, crf);
773 tcg_temp_free(t0);
774 }
775
776 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
777 {
778 TCGv t0, t1;
779 t0 = tcg_temp_new();
780 t1 = tcg_temp_new();
781 if (s) {
782 tcg_gen_ext32s_tl(t0, arg0);
783 tcg_gen_ext32s_tl(t1, arg1);
784 } else {
785 tcg_gen_ext32u_tl(t0, arg0);
786 tcg_gen_ext32u_tl(t1, arg1);
787 }
788 gen_op_cmp(t0, t1, s, crf);
789 tcg_temp_free(t1);
790 tcg_temp_free(t0);
791 }
792
793 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
794 {
795 TCGv t0 = tcg_const_tl(arg1);
796 gen_op_cmp32(arg0, t0, s, crf);
797 tcg_temp_free(t0);
798 }
799
800 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
801 {
802 if (NARROW_MODE(ctx)) {
803 gen_op_cmpi32(reg, 0, 1, 0);
804 } else {
805 gen_op_cmpi(reg, 0, 1, 0);
806 }
807 }
808
809 /* cmp */
810 static void gen_cmp(DisasContext *ctx)
811 {
812 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
813 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
814 1, crfD(ctx->opcode));
815 } else {
816 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
817 1, crfD(ctx->opcode));
818 }
819 }
820
821 /* cmpi */
822 static void gen_cmpi(DisasContext *ctx)
823 {
824 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
825 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
826 1, crfD(ctx->opcode));
827 } else {
828 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
829 1, crfD(ctx->opcode));
830 }
831 }
832
833 /* cmpl */
834 static void gen_cmpl(DisasContext *ctx)
835 {
836 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
837 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
838 0, crfD(ctx->opcode));
839 } else {
840 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
841 0, crfD(ctx->opcode));
842 }
843 }
844
845 /* cmpli */
846 static void gen_cmpli(DisasContext *ctx)
847 {
848 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
849 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
850 0, crfD(ctx->opcode));
851 } else {
852 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
853 0, crfD(ctx->opcode));
854 }
855 }
856
857 /* cmprb - range comparison: isupper, isaplha, islower*/
858 static void gen_cmprb(DisasContext *ctx)
859 {
860 TCGv_i32 src1 = tcg_temp_new_i32();
861 TCGv_i32 src2 = tcg_temp_new_i32();
862 TCGv_i32 src2lo = tcg_temp_new_i32();
863 TCGv_i32 src2hi = tcg_temp_new_i32();
864 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
865
866 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
867 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
868
869 tcg_gen_andi_i32(src1, src1, 0xFF);
870 tcg_gen_ext8u_i32(src2lo, src2);
871 tcg_gen_shri_i32(src2, src2, 8);
872 tcg_gen_ext8u_i32(src2hi, src2);
873
874 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
875 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
876 tcg_gen_and_i32(crf, src2lo, src2hi);
877
878 if (ctx->opcode & 0x00200000) {
879 tcg_gen_shri_i32(src2, src2, 8);
880 tcg_gen_ext8u_i32(src2lo, src2);
881 tcg_gen_shri_i32(src2, src2, 8);
882 tcg_gen_ext8u_i32(src2hi, src2);
883 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
884 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
885 tcg_gen_and_i32(src2lo, src2lo, src2hi);
886 tcg_gen_or_i32(crf, crf, src2lo);
887 }
888 tcg_gen_shli_i32(crf, crf, CRF_GT);
889 tcg_temp_free_i32(src1);
890 tcg_temp_free_i32(src2);
891 tcg_temp_free_i32(src2lo);
892 tcg_temp_free_i32(src2hi);
893 }
894
895 #if defined(TARGET_PPC64)
896 /* cmpeqb */
897 static void gen_cmpeqb(DisasContext *ctx)
898 {
899 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
900 cpu_gpr[rB(ctx->opcode)]);
901 }
902 #endif
903
904 /* isel (PowerPC 2.03 specification) */
905 static void gen_isel(DisasContext *ctx)
906 {
907 uint32_t bi = rC(ctx->opcode);
908 uint32_t mask = 0x08 >> (bi & 0x03);
909 TCGv t0 = tcg_temp_new();
910 TCGv zr;
911
912 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
913 tcg_gen_andi_tl(t0, t0, mask);
914
915 zr = tcg_const_tl(0);
916 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
917 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
918 cpu_gpr[rB(ctx->opcode)]);
919 tcg_temp_free(zr);
920 tcg_temp_free(t0);
921 }
922
923 /* cmpb: PowerPC 2.05 specification */
924 static void gen_cmpb(DisasContext *ctx)
925 {
926 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
927 cpu_gpr[rB(ctx->opcode)]);
928 }
929
930 /*** Integer arithmetic ***/
931
932 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
933 TCGv arg1, TCGv arg2, int sub)
934 {
935 TCGv t0 = tcg_temp_new();
936
937 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
938 tcg_gen_xor_tl(t0, arg1, arg2);
939 if (sub) {
940 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
941 } else {
942 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
943 }
944 tcg_temp_free(t0);
945 if (NARROW_MODE(ctx)) {
946 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
947 }
948 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
949 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
950 }
951
952 /* Common add function */
953 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
954 TCGv arg2, bool add_ca, bool compute_ca,
955 bool compute_ov, bool compute_rc0)
956 {
957 TCGv t0 = ret;
958
959 if (compute_ca || compute_ov) {
960 t0 = tcg_temp_new();
961 }
962
963 if (compute_ca) {
964 if (NARROW_MODE(ctx)) {
965 /* Caution: a non-obvious corner case of the spec is that we
966 must produce the *entire* 64-bit addition, but produce the
967 carry into bit 32. */
968 TCGv t1 = tcg_temp_new();
969 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
970 tcg_gen_add_tl(t0, arg1, arg2);
971 if (add_ca) {
972 tcg_gen_add_tl(t0, t0, cpu_ca);
973 }
974 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
975 tcg_temp_free(t1);
976 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
977 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
978 } else {
979 TCGv zero = tcg_const_tl(0);
980 if (add_ca) {
981 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
982 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
983 } else {
984 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
985 }
986 tcg_temp_free(zero);
987 }
988 } else {
989 tcg_gen_add_tl(t0, arg1, arg2);
990 if (add_ca) {
991 tcg_gen_add_tl(t0, t0, cpu_ca);
992 }
993 }
994
995 if (compute_ov) {
996 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
997 }
998 if (unlikely(compute_rc0)) {
999 gen_set_Rc0(ctx, t0);
1000 }
1001
1002 if (!TCGV_EQUAL(t0, ret)) {
1003 tcg_gen_mov_tl(ret, t0);
1004 tcg_temp_free(t0);
1005 }
1006 }
1007 /* Add functions with two operands */
1008 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
1009 static void glue(gen_, name)(DisasContext *ctx) \
1010 { \
1011 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1012 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1013 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1014 }
1015 /* Add functions with one operand and one immediate */
1016 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
1017 add_ca, compute_ca, compute_ov) \
1018 static void glue(gen_, name)(DisasContext *ctx) \
1019 { \
1020 TCGv t0 = tcg_const_tl(const_val); \
1021 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1022 cpu_gpr[rA(ctx->opcode)], t0, \
1023 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1024 tcg_temp_free(t0); \
1025 }
1026
1027 /* add add. addo addo. */
1028 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1029 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1030 /* addc addc. addco addco. */
1031 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1032 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1033 /* adde adde. addeo addeo. */
1034 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1035 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1036 /* addme addme. addmeo addmeo. */
1037 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1038 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1039 /* addze addze. addzeo addzeo.*/
1040 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1041 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1042 /* addi */
1043 static void gen_addi(DisasContext *ctx)
1044 {
1045 target_long simm = SIMM(ctx->opcode);
1046
1047 if (rA(ctx->opcode) == 0) {
1048 /* li case */
1049 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1050 } else {
1051 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1052 cpu_gpr[rA(ctx->opcode)], simm);
1053 }
1054 }
1055 /* addic addic.*/
1056 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1057 {
1058 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1059 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1060 c, 0, 1, 0, compute_rc0);
1061 tcg_temp_free(c);
1062 }
1063
1064 static void gen_addic(DisasContext *ctx)
1065 {
1066 gen_op_addic(ctx, 0);
1067 }
1068
1069 static void gen_addic_(DisasContext *ctx)
1070 {
1071 gen_op_addic(ctx, 1);
1072 }
1073
1074 /* addis */
1075 static void gen_addis(DisasContext *ctx)
1076 {
1077 target_long simm = SIMM(ctx->opcode);
1078
1079 if (rA(ctx->opcode) == 0) {
1080 /* lis case */
1081 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1082 } else {
1083 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1084 cpu_gpr[rA(ctx->opcode)], simm << 16);
1085 }
1086 }
1087
1088 /* addpcis */
1089 static void gen_addpcis(DisasContext *ctx)
1090 {
1091 target_long d = DX(ctx->opcode);
1092
1093 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
1094 }
1095
1096 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1097 TCGv arg2, int sign, int compute_ov)
1098 {
1099 TCGLabel *l1 = gen_new_label();
1100 TCGLabel *l2 = gen_new_label();
1101 TCGv_i32 t0 = tcg_temp_local_new_i32();
1102 TCGv_i32 t1 = tcg_temp_local_new_i32();
1103
1104 tcg_gen_trunc_tl_i32(t0, arg1);
1105 tcg_gen_trunc_tl_i32(t1, arg2);
1106 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1107 if (sign) {
1108 TCGLabel *l3 = gen_new_label();
1109 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1110 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1111 gen_set_label(l3);
1112 tcg_gen_div_i32(t0, t0, t1);
1113 } else {
1114 tcg_gen_divu_i32(t0, t0, t1);
1115 }
1116 if (compute_ov) {
1117 tcg_gen_movi_tl(cpu_ov, 0);
1118 }
1119 tcg_gen_br(l2);
1120 gen_set_label(l1);
1121 if (sign) {
1122 tcg_gen_sari_i32(t0, t0, 31);
1123 } else {
1124 tcg_gen_movi_i32(t0, 0);
1125 }
1126 if (compute_ov) {
1127 tcg_gen_movi_tl(cpu_ov, 1);
1128 tcg_gen_movi_tl(cpu_so, 1);
1129 }
1130 gen_set_label(l2);
1131 tcg_gen_extu_i32_tl(ret, t0);
1132 tcg_temp_free_i32(t0);
1133 tcg_temp_free_i32(t1);
1134 if (unlikely(Rc(ctx->opcode) != 0))
1135 gen_set_Rc0(ctx, ret);
1136 }
1137 /* Div functions */
1138 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1139 static void glue(gen_, name)(DisasContext *ctx) \
1140 { \
1141 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1142 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1143 sign, compute_ov); \
1144 }
1145 /* divwu divwu. divwuo divwuo. */
1146 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1147 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1148 /* divw divw. divwo divwo. */
1149 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1150 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1151
1152 /* div[wd]eu[o][.] */
1153 #define GEN_DIVE(name, hlpr, compute_ov) \
1154 static void gen_##name(DisasContext *ctx) \
1155 { \
1156 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1157 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1158 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1159 tcg_temp_free_i32(t0); \
1160 if (unlikely(Rc(ctx->opcode) != 0)) { \
1161 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1162 } \
1163 }
1164
1165 GEN_DIVE(divweu, divweu, 0);
1166 GEN_DIVE(divweuo, divweu, 1);
1167 GEN_DIVE(divwe, divwe, 0);
1168 GEN_DIVE(divweo, divwe, 1);
1169
1170 #if defined(TARGET_PPC64)
1171 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1172 TCGv arg2, int sign, int compute_ov)
1173 {
1174 TCGLabel *l1 = gen_new_label();
1175 TCGLabel *l2 = gen_new_label();
1176
1177 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1178 if (sign) {
1179 TCGLabel *l3 = gen_new_label();
1180 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1181 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1182 gen_set_label(l3);
1183 tcg_gen_div_i64(ret, arg1, arg2);
1184 } else {
1185 tcg_gen_divu_i64(ret, arg1, arg2);
1186 }
1187 if (compute_ov) {
1188 tcg_gen_movi_tl(cpu_ov, 0);
1189 }
1190 tcg_gen_br(l2);
1191 gen_set_label(l1);
1192 if (sign) {
1193 tcg_gen_sari_i64(ret, arg1, 63);
1194 } else {
1195 tcg_gen_movi_i64(ret, 0);
1196 }
1197 if (compute_ov) {
1198 tcg_gen_movi_tl(cpu_ov, 1);
1199 tcg_gen_movi_tl(cpu_so, 1);
1200 }
1201 gen_set_label(l2);
1202 if (unlikely(Rc(ctx->opcode) != 0))
1203 gen_set_Rc0(ctx, ret);
1204 }
1205 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1206 static void glue(gen_, name)(DisasContext *ctx) \
1207 { \
1208 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1209 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1210 sign, compute_ov); \
1211 }
1212 /* divwu divwu. divwuo divwuo. */
1213 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1214 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1215 /* divw divw. divwo divwo. */
1216 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1217 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1218
1219 GEN_DIVE(divdeu, divdeu, 0);
1220 GEN_DIVE(divdeuo, divdeu, 1);
1221 GEN_DIVE(divde, divde, 0);
1222 GEN_DIVE(divdeo, divde, 1);
1223 #endif
1224
1225 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1226 TCGv arg2, int sign)
1227 {
1228 TCGv_i32 t0 = tcg_temp_new_i32();
1229 TCGv_i32 t1 = tcg_temp_new_i32();
1230
1231 tcg_gen_trunc_tl_i32(t0, arg1);
1232 tcg_gen_trunc_tl_i32(t1, arg2);
1233 if (sign) {
1234 TCGv_i32 t2 = tcg_temp_new_i32();
1235 TCGv_i32 t3 = tcg_temp_new_i32();
1236 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1237 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1238 tcg_gen_and_i32(t2, t2, t3);
1239 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1240 tcg_gen_or_i32(t2, t2, t3);
1241 tcg_gen_movi_i32(t3, 0);
1242 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1243 tcg_gen_rem_i32(t3, t0, t1);
1244 tcg_gen_ext_i32_tl(ret, t3);
1245 tcg_temp_free_i32(t2);
1246 tcg_temp_free_i32(t3);
1247 } else {
1248 TCGv_i32 t2 = tcg_const_i32(1);
1249 TCGv_i32 t3 = tcg_const_i32(0);
1250 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1251 tcg_gen_remu_i32(t3, t0, t1);
1252 tcg_gen_extu_i32_tl(ret, t3);
1253 tcg_temp_free_i32(t2);
1254 tcg_temp_free_i32(t3);
1255 }
1256 tcg_temp_free_i32(t0);
1257 tcg_temp_free_i32(t1);
1258 }
1259
1260 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1261 static void glue(gen_, name)(DisasContext *ctx) \
1262 { \
1263 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1264 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1265 sign); \
1266 }
1267
1268 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1269 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1270
1271 #if defined(TARGET_PPC64)
1272 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1273 TCGv arg2, int sign)
1274 {
1275 TCGv_i64 t0 = tcg_temp_new_i64();
1276 TCGv_i64 t1 = tcg_temp_new_i64();
1277
1278 tcg_gen_mov_i64(t0, arg1);
1279 tcg_gen_mov_i64(t1, arg2);
1280 if (sign) {
1281 TCGv_i64 t2 = tcg_temp_new_i64();
1282 TCGv_i64 t3 = tcg_temp_new_i64();
1283 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1284 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1285 tcg_gen_and_i64(t2, t2, t3);
1286 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1287 tcg_gen_or_i64(t2, t2, t3);
1288 tcg_gen_movi_i64(t3, 0);
1289 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1290 tcg_gen_rem_i64(ret, t0, t1);
1291 tcg_temp_free_i64(t2);
1292 tcg_temp_free_i64(t3);
1293 } else {
1294 TCGv_i64 t2 = tcg_const_i64(1);
1295 TCGv_i64 t3 = tcg_const_i64(0);
1296 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1297 tcg_gen_remu_i64(ret, t0, t1);
1298 tcg_temp_free_i64(t2);
1299 tcg_temp_free_i64(t3);
1300 }
1301 tcg_temp_free_i64(t0);
1302 tcg_temp_free_i64(t1);
1303 }
1304
1305 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1306 static void glue(gen_, name)(DisasContext *ctx) \
1307 { \
1308 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1309 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1310 sign); \
1311 }
1312
1313 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1314 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1315 #endif
1316
1317 /* mulhw mulhw. */
1318 static void gen_mulhw(DisasContext *ctx)
1319 {
1320 TCGv_i32 t0 = tcg_temp_new_i32();
1321 TCGv_i32 t1 = tcg_temp_new_i32();
1322
1323 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1324 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1325 tcg_gen_muls2_i32(t0, t1, t0, t1);
1326 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1327 tcg_temp_free_i32(t0);
1328 tcg_temp_free_i32(t1);
1329 if (unlikely(Rc(ctx->opcode) != 0))
1330 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1331 }
1332
1333 /* mulhwu mulhwu. */
1334 static void gen_mulhwu(DisasContext *ctx)
1335 {
1336 TCGv_i32 t0 = tcg_temp_new_i32();
1337 TCGv_i32 t1 = tcg_temp_new_i32();
1338
1339 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1340 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1341 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1342 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1343 tcg_temp_free_i32(t0);
1344 tcg_temp_free_i32(t1);
1345 if (unlikely(Rc(ctx->opcode) != 0))
1346 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1347 }
1348
1349 /* mullw mullw. */
1350 static void gen_mullw(DisasContext *ctx)
1351 {
1352 #if defined(TARGET_PPC64)
1353 TCGv_i64 t0, t1;
1354 t0 = tcg_temp_new_i64();
1355 t1 = tcg_temp_new_i64();
1356 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1357 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1358 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1359 tcg_temp_free(t0);
1360 tcg_temp_free(t1);
1361 #else
1362 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1363 cpu_gpr[rB(ctx->opcode)]);
1364 #endif
1365 if (unlikely(Rc(ctx->opcode) != 0))
1366 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1367 }
1368
1369 /* mullwo mullwo. */
1370 static void gen_mullwo(DisasContext *ctx)
1371 {
1372 TCGv_i32 t0 = tcg_temp_new_i32();
1373 TCGv_i32 t1 = tcg_temp_new_i32();
1374
1375 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1376 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1377 tcg_gen_muls2_i32(t0, t1, t0, t1);
1378 #if defined(TARGET_PPC64)
1379 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1380 #else
1381 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1382 #endif
1383
1384 tcg_gen_sari_i32(t0, t0, 31);
1385 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1386 tcg_gen_extu_i32_tl(cpu_ov, t0);
1387 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1388
1389 tcg_temp_free_i32(t0);
1390 tcg_temp_free_i32(t1);
1391 if (unlikely(Rc(ctx->opcode) != 0))
1392 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1393 }
1394
1395 /* mulli */
1396 static void gen_mulli(DisasContext *ctx)
1397 {
1398 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1399 SIMM(ctx->opcode));
1400 }
1401
1402 #if defined(TARGET_PPC64)
1403 /* mulhd mulhd. */
1404 static void gen_mulhd(DisasContext *ctx)
1405 {
1406 TCGv lo = tcg_temp_new();
1407 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1408 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1409 tcg_temp_free(lo);
1410 if (unlikely(Rc(ctx->opcode) != 0)) {
1411 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1412 }
1413 }
1414
1415 /* mulhdu mulhdu. */
1416 static void gen_mulhdu(DisasContext *ctx)
1417 {
1418 TCGv lo = tcg_temp_new();
1419 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1420 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1421 tcg_temp_free(lo);
1422 if (unlikely(Rc(ctx->opcode) != 0)) {
1423 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1424 }
1425 }
1426
1427 /* mulld mulld. */
1428 static void gen_mulld(DisasContext *ctx)
1429 {
1430 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1431 cpu_gpr[rB(ctx->opcode)]);
1432 if (unlikely(Rc(ctx->opcode) != 0))
1433 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1434 }
1435
1436 /* mulldo mulldo. */
1437 static void gen_mulldo(DisasContext *ctx)
1438 {
1439 TCGv_i64 t0 = tcg_temp_new_i64();
1440 TCGv_i64 t1 = tcg_temp_new_i64();
1441
1442 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1443 cpu_gpr[rB(ctx->opcode)]);
1444 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1445
1446 tcg_gen_sari_i64(t0, t0, 63);
1447 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1448 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1449
1450 tcg_temp_free_i64(t0);
1451 tcg_temp_free_i64(t1);
1452
1453 if (unlikely(Rc(ctx->opcode) != 0)) {
1454 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1455 }
1456 }
1457 #endif
1458
1459 /* Common subf function */
1460 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1461 TCGv arg2, bool add_ca, bool compute_ca,
1462 bool compute_ov, bool compute_rc0)
1463 {
1464 TCGv t0 = ret;
1465
1466 if (compute_ca || compute_ov) {
1467 t0 = tcg_temp_new();
1468 }
1469
1470 if (compute_ca) {
1471 /* dest = ~arg1 + arg2 [+ ca]. */
1472 if (NARROW_MODE(ctx)) {
1473 /* Caution: a non-obvious corner case of the spec is that we
1474 must produce the *entire* 64-bit addition, but produce the
1475 carry into bit 32. */
1476 TCGv inv1 = tcg_temp_new();
1477 TCGv t1 = tcg_temp_new();
1478 tcg_gen_not_tl(inv1, arg1);
1479 if (add_ca) {
1480 tcg_gen_add_tl(t0, arg2, cpu_ca);
1481 } else {
1482 tcg_gen_addi_tl(t0, arg2, 1);
1483 }
1484 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1485 tcg_gen_add_tl(t0, t0, inv1);
1486 tcg_temp_free(inv1);
1487 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1488 tcg_temp_free(t1);
1489 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1490 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1491 } else if (add_ca) {
1492 TCGv zero, inv1 = tcg_temp_new();
1493 tcg_gen_not_tl(inv1, arg1);
1494 zero = tcg_const_tl(0);
1495 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1496 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1497 tcg_temp_free(zero);
1498 tcg_temp_free(inv1);
1499 } else {
1500 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1501 tcg_gen_sub_tl(t0, arg2, arg1);
1502 }
1503 } else if (add_ca) {
1504 /* Since we're ignoring carry-out, we can simplify the
1505 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1506 tcg_gen_sub_tl(t0, arg2, arg1);
1507 tcg_gen_add_tl(t0, t0, cpu_ca);
1508 tcg_gen_subi_tl(t0, t0, 1);
1509 } else {
1510 tcg_gen_sub_tl(t0, arg2, arg1);
1511 }
1512
1513 if (compute_ov) {
1514 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1515 }
1516 if (unlikely(compute_rc0)) {
1517 gen_set_Rc0(ctx, t0);
1518 }
1519
1520 if (!TCGV_EQUAL(t0, ret)) {
1521 tcg_gen_mov_tl(ret, t0);
1522 tcg_temp_free(t0);
1523 }
1524 }
1525 /* Sub functions with Two operands functions */
1526 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1527 static void glue(gen_, name)(DisasContext *ctx) \
1528 { \
1529 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1530 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1531 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1532 }
1533 /* Sub functions with one operand and one immediate */
1534 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1535 add_ca, compute_ca, compute_ov) \
1536 static void glue(gen_, name)(DisasContext *ctx) \
1537 { \
1538 TCGv t0 = tcg_const_tl(const_val); \
1539 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1540 cpu_gpr[rA(ctx->opcode)], t0, \
1541 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1542 tcg_temp_free(t0); \
1543 }
1544 /* subf subf. subfo subfo. */
1545 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1546 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1547 /* subfc subfc. subfco subfco. */
1548 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1549 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1550 /* subfe subfe. subfeo subfo. */
1551 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1552 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1553 /* subfme subfme. subfmeo subfmeo. */
1554 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1555 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1556 /* subfze subfze. subfzeo subfzeo.*/
1557 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1558 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1559
1560 /* subfic */
1561 static void gen_subfic(DisasContext *ctx)
1562 {
1563 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1564 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1565 c, 0, 1, 0, 0);
1566 tcg_temp_free(c);
1567 }
1568
1569 /* neg neg. nego nego. */
1570 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1571 {
1572 TCGv zero = tcg_const_tl(0);
1573 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1574 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1575 tcg_temp_free(zero);
1576 }
1577
1578 static void gen_neg(DisasContext *ctx)
1579 {
1580 gen_op_arith_neg(ctx, 0);
1581 }
1582
1583 static void gen_nego(DisasContext *ctx)
1584 {
1585 gen_op_arith_neg(ctx, 1);
1586 }
1587
1588 /*** Integer logical ***/
1589 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1590 static void glue(gen_, name)(DisasContext *ctx) \
1591 { \
1592 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1593 cpu_gpr[rB(ctx->opcode)]); \
1594 if (unlikely(Rc(ctx->opcode) != 0)) \
1595 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1596 }
1597
1598 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1599 static void glue(gen_, name)(DisasContext *ctx) \
1600 { \
1601 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1602 if (unlikely(Rc(ctx->opcode) != 0)) \
1603 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1604 }
1605
1606 /* and & and. */
1607 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1608 /* andc & andc. */
1609 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1610
1611 /* andi. */
1612 static void gen_andi_(DisasContext *ctx)
1613 {
1614 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1615 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1616 }
1617
1618 /* andis. */
1619 static void gen_andis_(DisasContext *ctx)
1620 {
1621 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1622 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1623 }
1624
1625 /* cntlzw */
1626 static void gen_cntlzw(DisasContext *ctx)
1627 {
1628 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1629 if (unlikely(Rc(ctx->opcode) != 0))
1630 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1631 }
1632
1633 /* cnttzw */
1634 static void gen_cnttzw(DisasContext *ctx)
1635 {
1636 gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1637 if (unlikely(Rc(ctx->opcode) != 0)) {
1638 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1639 }
1640 }
1641
1642 /* eqv & eqv. */
1643 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1644 /* extsb & extsb. */
1645 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1646 /* extsh & extsh. */
1647 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1648 /* nand & nand. */
1649 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1650 /* nor & nor. */
1651 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1652
1653 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1654 static void gen_pause(DisasContext *ctx)
1655 {
1656 TCGv_i32 t0 = tcg_const_i32(0);
1657 tcg_gen_st_i32(t0, cpu_env,
1658 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1659 tcg_temp_free_i32(t0);
1660
1661 /* Stop translation, this gives other CPUs a chance to run */
1662 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
1663 }
1664 #endif /* defined(TARGET_PPC64) */
1665
1666 /* or & or. */
1667 static void gen_or(DisasContext *ctx)
1668 {
1669 int rs, ra, rb;
1670
1671 rs = rS(ctx->opcode);
1672 ra = rA(ctx->opcode);
1673 rb = rB(ctx->opcode);
1674 /* Optimisation for mr. ri case */
1675 if (rs != ra || rs != rb) {
1676 if (rs != rb)
1677 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1678 else
1679 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1680 if (unlikely(Rc(ctx->opcode) != 0))
1681 gen_set_Rc0(ctx, cpu_gpr[ra]);
1682 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1683 gen_set_Rc0(ctx, cpu_gpr[rs]);
1684 #if defined(TARGET_PPC64)
1685 } else if (rs != 0) { /* 0 is nop */
1686 int prio = 0;
1687
1688 switch (rs) {
1689 case 1:
1690 /* Set process priority to low */
1691 prio = 2;
1692 break;
1693 case 6:
1694 /* Set process priority to medium-low */
1695 prio = 3;
1696 break;
1697 case 2:
1698 /* Set process priority to normal */
1699 prio = 4;
1700 break;
1701 #if !defined(CONFIG_USER_ONLY)
1702 case 31:
1703 if (!ctx->pr) {
1704 /* Set process priority to very low */
1705 prio = 1;
1706 }
1707 break;
1708 case 5:
1709 if (!ctx->pr) {
1710 /* Set process priority to medium-hight */
1711 prio = 5;
1712 }
1713 break;
1714 case 3:
1715 if (!ctx->pr) {
1716 /* Set process priority to high */
1717 prio = 6;
1718 }
1719 break;
1720 case 7:
1721 if (ctx->hv && !ctx->pr) {
1722 /* Set process priority to very high */
1723 prio = 7;
1724 }
1725 break;
1726 #endif
1727 default:
1728 break;
1729 }
1730 if (prio) {
1731 TCGv t0 = tcg_temp_new();
1732 gen_load_spr(t0, SPR_PPR);
1733 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1734 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1735 gen_store_spr(SPR_PPR, t0);
1736 tcg_temp_free(t0);
1737 }
1738 #if !defined(CONFIG_USER_ONLY)
1739 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1740 * CPU and the kernel hangs. This applies to all encodings other
1741 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1742 * and all currently undefined.
1743 */
1744 gen_pause(ctx);
1745 #endif
1746 #endif
1747 }
1748 }
1749 /* orc & orc. */
1750 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1751
1752 /* xor & xor. */
1753 static void gen_xor(DisasContext *ctx)
1754 {
1755 /* Optimisation for "set to zero" case */
1756 if (rS(ctx->opcode) != rB(ctx->opcode))
1757 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1758 else
1759 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1760 if (unlikely(Rc(ctx->opcode) != 0))
1761 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1762 }
1763
1764 /* ori */
1765 static void gen_ori(DisasContext *ctx)
1766 {
1767 target_ulong uimm = UIMM(ctx->opcode);
1768
1769 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1770 return;
1771 }
1772 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1773 }
1774
1775 /* oris */
1776 static void gen_oris(DisasContext *ctx)
1777 {
1778 target_ulong uimm = UIMM(ctx->opcode);
1779
1780 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1781 /* NOP */
1782 return;
1783 }
1784 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1785 }
1786
1787 /* xori */
1788 static void gen_xori(DisasContext *ctx)
1789 {
1790 target_ulong uimm = UIMM(ctx->opcode);
1791
1792 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1793 /* NOP */
1794 return;
1795 }
1796 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1797 }
1798
1799 /* xoris */
1800 static void gen_xoris(DisasContext *ctx)
1801 {
1802 target_ulong uimm = UIMM(ctx->opcode);
1803
1804 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1805 /* NOP */
1806 return;
1807 }
1808 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1809 }
1810
1811 /* popcntb : PowerPC 2.03 specification */
1812 static void gen_popcntb(DisasContext *ctx)
1813 {
1814 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1815 }
1816
1817 static void gen_popcntw(DisasContext *ctx)
1818 {
1819 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1820 }
1821
1822 #if defined(TARGET_PPC64)
1823 /* popcntd: PowerPC 2.06 specification */
1824 static void gen_popcntd(DisasContext *ctx)
1825 {
1826 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1827 }
1828 #endif
1829
1830 /* prtyw: PowerPC 2.05 specification */
1831 static void gen_prtyw(DisasContext *ctx)
1832 {
1833 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1834 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1835 TCGv t0 = tcg_temp_new();
1836 tcg_gen_shri_tl(t0, rs, 16);
1837 tcg_gen_xor_tl(ra, rs, t0);
1838 tcg_gen_shri_tl(t0, ra, 8);
1839 tcg_gen_xor_tl(ra, ra, t0);
1840 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1841 tcg_temp_free(t0);
1842 }
1843
1844 #if defined(TARGET_PPC64)
1845 /* prtyd: PowerPC 2.05 specification */
1846 static void gen_prtyd(DisasContext *ctx)
1847 {
1848 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1849 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1850 TCGv t0 = tcg_temp_new();
1851 tcg_gen_shri_tl(t0, rs, 32);
1852 tcg_gen_xor_tl(ra, rs, t0);
1853 tcg_gen_shri_tl(t0, ra, 16);
1854 tcg_gen_xor_tl(ra, ra, t0);
1855 tcg_gen_shri_tl(t0, ra, 8);
1856 tcg_gen_xor_tl(ra, ra, t0);
1857 tcg_gen_andi_tl(ra, ra, 1);
1858 tcg_temp_free(t0);
1859 }
1860 #endif
1861
1862 #if defined(TARGET_PPC64)
1863 /* bpermd */
1864 static void gen_bpermd(DisasContext *ctx)
1865 {
1866 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1867 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1868 }
1869 #endif
1870
1871 #if defined(TARGET_PPC64)
1872 /* extsw & extsw. */
1873 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1874
1875 /* cntlzd */
1876 static void gen_cntlzd(DisasContext *ctx)
1877 {
1878 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1879 if (unlikely(Rc(ctx->opcode) != 0))
1880 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1881 }
1882
1883 /* cnttzd */
1884 static void gen_cnttzd(DisasContext *ctx)
1885 {
1886 gen_helper_cnttzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1887 if (unlikely(Rc(ctx->opcode) != 0)) {
1888 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1889 }
1890 }
1891 #endif
1892
1893 /*** Integer rotate ***/
1894
1895 /* rlwimi & rlwimi. */
1896 static void gen_rlwimi(DisasContext *ctx)
1897 {
1898 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1899 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1900 uint32_t sh = SH(ctx->opcode);
1901 uint32_t mb = MB(ctx->opcode);
1902 uint32_t me = ME(ctx->opcode);
1903
1904 if (sh == (31-me) && mb <= me) {
1905 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1906 } else {
1907 target_ulong mask;
1908 TCGv t1;
1909
1910 #if defined(TARGET_PPC64)
1911 mb += 32;
1912 me += 32;
1913 #endif
1914 mask = MASK(mb, me);
1915
1916 t1 = tcg_temp_new();
1917 if (mask <= 0xffffffffu) {
1918 TCGv_i32 t0 = tcg_temp_new_i32();
1919 tcg_gen_trunc_tl_i32(t0, t_rs);
1920 tcg_gen_rotli_i32(t0, t0, sh);
1921 tcg_gen_extu_i32_tl(t1, t0);
1922 tcg_temp_free_i32(t0);
1923 } else {
1924 #if defined(TARGET_PPC64)
1925 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1926 tcg_gen_rotli_i64(t1, t1, sh);
1927 #else
1928 g_assert_not_reached();
1929 #endif
1930 }
1931
1932 tcg_gen_andi_tl(t1, t1, mask);
1933 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1934 tcg_gen_or_tl(t_ra, t_ra, t1);
1935 tcg_temp_free(t1);
1936 }
1937 if (unlikely(Rc(ctx->opcode) != 0)) {
1938 gen_set_Rc0(ctx, t_ra);
1939 }
1940 }
1941
1942 /* rlwinm & rlwinm. */
1943 static void gen_rlwinm(DisasContext *ctx)
1944 {
1945 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1946 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1947 uint32_t sh = SH(ctx->opcode);
1948 uint32_t mb = MB(ctx->opcode);
1949 uint32_t me = ME(ctx->opcode);
1950
1951 if (mb == 0 && me == (31 - sh)) {
1952 tcg_gen_shli_tl(t_ra, t_rs, sh);
1953 tcg_gen_ext32u_tl(t_ra, t_ra);
1954 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1955 tcg_gen_ext32u_tl(t_ra, t_rs);
1956 tcg_gen_shri_tl(t_ra, t_ra, mb);
1957 } else {
1958 target_ulong mask;
1959 #if defined(TARGET_PPC64)
1960 mb += 32;
1961 me += 32;
1962 #endif
1963 mask = MASK(mb, me);
1964
1965 if (mask <= 0xffffffffu) {
1966 TCGv_i32 t0 = tcg_temp_new_i32();
1967 tcg_gen_trunc_tl_i32(t0, t_rs);
1968 tcg_gen_rotli_i32(t0, t0, sh);
1969 tcg_gen_andi_i32(t0, t0, mask);
1970 tcg_gen_extu_i32_tl(t_ra, t0);
1971 tcg_temp_free_i32(t0);
1972 } else {
1973 #if defined(TARGET_PPC64)
1974 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1975 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1976 tcg_gen_andi_i64(t_ra, t_ra, mask);
1977 #else
1978 g_assert_not_reached();
1979 #endif
1980 }
1981 }
1982 if (unlikely(Rc(ctx->opcode) != 0)) {
1983 gen_set_Rc0(ctx, t_ra);
1984 }
1985 }
1986
1987 /* rlwnm & rlwnm. */
1988 static void gen_rlwnm(DisasContext *ctx)
1989 {
1990 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1991 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1992 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1993 uint32_t mb = MB(ctx->opcode);
1994 uint32_t me = ME(ctx->opcode);
1995 target_ulong mask;
1996
1997 #if defined(TARGET_PPC64)
1998 mb += 32;
1999 me += 32;
2000 #endif
2001 mask = MASK(mb, me);
2002
2003 if (mask <= 0xffffffffu) {
2004 TCGv_i32 t0 = tcg_temp_new_i32();
2005 TCGv_i32 t1 = tcg_temp_new_i32();
2006 tcg_gen_trunc_tl_i32(t0, t_rb);
2007 tcg_gen_trunc_tl_i32(t1, t_rs);
2008 tcg_gen_andi_i32(t0, t0, 0x1f);
2009 tcg_gen_rotl_i32(t1, t1, t0);
2010 tcg_gen_extu_i32_tl(t_ra, t1);
2011 tcg_temp_free_i32(t0);
2012 tcg_temp_free_i32(t1);
2013 } else {
2014 #if defined(TARGET_PPC64)
2015 TCGv_i64 t0 = tcg_temp_new_i64();
2016 tcg_gen_andi_i64(t0, t_rb, 0x1f);
2017 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2018 tcg_gen_rotl_i64(t_ra, t_ra, t0);
2019 tcg_temp_free_i64(t0);
2020 #else
2021 g_assert_not_reached();
2022 #endif
2023 }
2024
2025 tcg_gen_andi_tl(t_ra, t_ra, mask);
2026
2027 if (unlikely(Rc(ctx->opcode) != 0)) {
2028 gen_set_Rc0(ctx, t_ra);
2029 }
2030 }
2031
2032 #if defined(TARGET_PPC64)
2033 #define GEN_PPC64_R2(name, opc1, opc2) \
2034 static void glue(gen_, name##0)(DisasContext *ctx) \
2035 { \
2036 gen_##name(ctx, 0); \
2037 } \
2038 \
2039 static void glue(gen_, name##1)(DisasContext *ctx) \
2040 { \
2041 gen_##name(ctx, 1); \
2042 }
2043 #define GEN_PPC64_R4(name, opc1, opc2) \
2044 static void glue(gen_, name##0)(DisasContext *ctx) \
2045 { \
2046 gen_##name(ctx, 0, 0); \
2047 } \
2048 \
2049 static void glue(gen_, name##1)(DisasContext *ctx) \
2050 { \
2051 gen_##name(ctx, 0, 1); \
2052 } \
2053 \
2054 static void glue(gen_, name##2)(DisasContext *ctx) \
2055 { \
2056 gen_##name(ctx, 1, 0); \
2057 } \
2058 \
2059 static void glue(gen_, name##3)(DisasContext *ctx) \
2060 { \
2061 gen_##name(ctx, 1, 1); \
2062 }
2063
2064 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2065 {
2066 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2067 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2068
2069 if (sh != 0 && mb == 0 && me == (63 - sh)) {
2070 tcg_gen_shli_tl(t_ra, t_rs, sh);
2071 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
2072 tcg_gen_shri_tl(t_ra, t_rs, mb);
2073 } else {
2074 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2075 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2076 }
2077 if (unlikely(Rc(ctx->opcode) != 0)) {
2078 gen_set_Rc0(ctx, t_ra);
2079 }
2080 }
2081
2082 /* rldicl - rldicl. */
2083 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2084 {
2085 uint32_t sh, mb;
2086
2087 sh = SH(ctx->opcode) | (shn << 5);
2088 mb = MB(ctx->opcode) | (mbn << 5);
2089 gen_rldinm(ctx, mb, 63, sh);
2090 }
2091 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2092
2093 /* rldicr - rldicr. */
2094 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2095 {
2096 uint32_t sh, me;
2097
2098 sh = SH(ctx->opcode) | (shn << 5);
2099 me = MB(ctx->opcode) | (men << 5);
2100 gen_rldinm(ctx, 0, me, sh);
2101 }
2102 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2103
2104 /* rldic - rldic. */
2105 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2106 {
2107 uint32_t sh, mb;
2108
2109 sh = SH(ctx->opcode) | (shn << 5);
2110 mb = MB(ctx->opcode) | (mbn << 5);
2111 gen_rldinm(ctx, mb, 63 - sh, sh);
2112 }
2113 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2114
2115 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2116 {
2117 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2118 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2119 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2120 TCGv t0;
2121
2122 t0 = tcg_temp_new();
2123 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2124 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2125 tcg_temp_free(t0);
2126
2127 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2128 if (unlikely(Rc(ctx->opcode) != 0)) {
2129 gen_set_Rc0(ctx, t_ra);
2130 }
2131 }
2132
2133 /* rldcl - rldcl. */
2134 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2135 {
2136 uint32_t mb;
2137
2138 mb = MB(ctx->opcode) | (mbn << 5);
2139 gen_rldnm(ctx, mb, 63);
2140 }
2141 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2142
2143 /* rldcr - rldcr. */
2144 static inline void gen_rldcr(DisasContext *ctx, int men)
2145 {
2146 uint32_t me;
2147
2148 me = MB(ctx->opcode) | (men << 5);
2149 gen_rldnm(ctx, 0, me);
2150 }
2151 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2152
2153 /* rldimi - rldimi. */
2154 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2155 {
2156 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2157 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2158 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2159 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2160 uint32_t me = 63 - sh;
2161
2162 if (mb <= me) {
2163 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2164 } else {
2165 target_ulong mask = MASK(mb, me);
2166 TCGv t1 = tcg_temp_new();
2167
2168 tcg_gen_rotli_tl(t1, t_rs, sh);
2169 tcg_gen_andi_tl(t1, t1, mask);
2170 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2171 tcg_gen_or_tl(t_ra, t_ra, t1);
2172 tcg_temp_free(t1);
2173 }
2174 if (unlikely(Rc(ctx->opcode) != 0)) {
2175 gen_set_Rc0(ctx, t_ra);
2176 }
2177 }
2178 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2179 #endif
2180
2181 /*** Integer shift ***/
2182
2183 /* slw & slw. */
2184 static void gen_slw(DisasContext *ctx)
2185 {
2186 TCGv t0, t1;
2187
2188 t0 = tcg_temp_new();
2189 /* AND rS with a mask that is 0 when rB >= 0x20 */
2190 #if defined(TARGET_PPC64)
2191 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2192 tcg_gen_sari_tl(t0, t0, 0x3f);
2193 #else
2194 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2195 tcg_gen_sari_tl(t0, t0, 0x1f);
2196 #endif
2197 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2198 t1 = tcg_temp_new();
2199 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2200 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2201 tcg_temp_free(t1);
2202 tcg_temp_free(t0);
2203 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2204 if (unlikely(Rc(ctx->opcode) != 0))
2205 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2206 }
2207
2208 /* sraw & sraw. */
2209 static void gen_sraw(DisasContext *ctx)
2210 {
2211 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2212 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2213 if (unlikely(Rc(ctx->opcode) != 0))
2214 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2215 }
2216
2217 /* srawi & srawi. */
2218 static void gen_srawi(DisasContext *ctx)
2219 {
2220 int sh = SH(ctx->opcode);
2221 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2222 TCGv src = cpu_gpr[rS(ctx->opcode)];
2223 if (sh == 0) {
2224 tcg_gen_ext32s_tl(dst, src);
2225 tcg_gen_movi_tl(cpu_ca, 0);
2226 } else {
2227 TCGv t0;
2228 tcg_gen_ext32s_tl(dst, src);
2229 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2230 t0 = tcg_temp_new();
2231 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2232 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2233 tcg_temp_free(t0);
2234 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2235 tcg_gen_sari_tl(dst, dst, sh);
2236 }
2237 if (unlikely(Rc(ctx->opcode) != 0)) {
2238 gen_set_Rc0(ctx, dst);
2239 }
2240 }
2241
2242 /* srw & srw. */
2243 static void gen_srw(DisasContext *ctx)
2244 {
2245 TCGv t0, t1;
2246
2247 t0 = tcg_temp_new();
2248 /* AND rS with a mask that is 0 when rB >= 0x20 */
2249 #if defined(TARGET_PPC64)
2250 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2251 tcg_gen_sari_tl(t0, t0, 0x3f);
2252 #else
2253 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2254 tcg_gen_sari_tl(t0, t0, 0x1f);
2255 #endif
2256 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2257 tcg_gen_ext32u_tl(t0, t0);
2258 t1 = tcg_temp_new();
2259 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2260 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2261 tcg_temp_free(t1);
2262 tcg_temp_free(t0);
2263 if (unlikely(Rc(ctx->opcode) != 0))
2264 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2265 }
2266
2267 #if defined(TARGET_PPC64)
2268 /* sld & sld. */
2269 static void gen_sld(DisasContext *ctx)
2270 {
2271 TCGv t0, t1;
2272
2273 t0 = tcg_temp_new();
2274 /* AND rS with a mask that is 0 when rB >= 0x40 */
2275 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2276 tcg_gen_sari_tl(t0, t0, 0x3f);
2277 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2278 t1 = tcg_temp_new();
2279 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2280 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2281 tcg_temp_free(t1);
2282 tcg_temp_free(t0);
2283 if (unlikely(Rc(ctx->opcode) != 0))
2284 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2285 }
2286
2287 /* srad & srad. */
2288 static void gen_srad(DisasContext *ctx)
2289 {
2290 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2291 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2292 if (unlikely(Rc(ctx->opcode) != 0))
2293 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2294 }
2295 /* sradi & sradi. */
2296 static inline void gen_sradi(DisasContext *ctx, int n)
2297 {
2298 int sh = SH(ctx->opcode) + (n << 5);
2299 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2300 TCGv src = cpu_gpr[rS(ctx->opcode)];
2301 if (sh == 0) {
2302 tcg_gen_mov_tl(dst, src);
2303 tcg_gen_movi_tl(cpu_ca, 0);
2304 } else {
2305 TCGv t0;
2306 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2307 t0 = tcg_temp_new();
2308 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2309 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2310 tcg_temp_free(t0);
2311 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2312 tcg_gen_sari_tl(dst, src, sh);
2313 }
2314 if (unlikely(Rc(ctx->opcode) != 0)) {
2315 gen_set_Rc0(ctx, dst);
2316 }
2317 }
2318
2319 static void gen_sradi0(DisasContext *ctx)
2320 {
2321 gen_sradi(ctx, 0);
2322 }
2323
2324 static void gen_sradi1(DisasContext *ctx)
2325 {
2326 gen_sradi(ctx, 1);
2327 }
2328
2329 /* srd & srd. */
2330 static void gen_srd(DisasContext *ctx)
2331 {
2332 TCGv t0, t1;
2333
2334 t0 = tcg_temp_new();
2335 /* AND rS with a mask that is 0 when rB >= 0x40 */
2336 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2337 tcg_gen_sari_tl(t0, t0, 0x3f);
2338 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2339 t1 = tcg_temp_new();
2340 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2341 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2342 tcg_temp_free(t1);
2343 tcg_temp_free(t0);
2344 if (unlikely(Rc(ctx->opcode) != 0))
2345 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2346 }
2347 #endif
2348
2349 /*** Addressing modes ***/
2350 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2351 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2352 target_long maskl)
2353 {
2354 target_long simm = SIMM(ctx->opcode);
2355
2356 simm &= ~maskl;
2357 if (rA(ctx->opcode) == 0) {
2358 if (NARROW_MODE(ctx)) {
2359 simm = (uint32_t)simm;
2360 }
2361 tcg_gen_movi_tl(EA, simm);
2362 } else if (likely(simm != 0)) {
2363 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2364 if (NARROW_MODE(ctx)) {
2365 tcg_gen_ext32u_tl(EA, EA);
2366 }
2367 } else {
2368 if (NARROW_MODE(ctx)) {
2369 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2370 } else {
2371 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2372 }
2373 }
2374 }
2375
2376 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2377 {
2378 if (rA(ctx->opcode) == 0) {
2379 if (NARROW_MODE(ctx)) {
2380 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2381 } else {
2382 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2383 }
2384 } else {
2385 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2386 if (NARROW_MODE(ctx)) {
2387 tcg_gen_ext32u_tl(EA, EA);
2388 }
2389 }
2390 }
2391
2392 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2393 {
2394 if (rA(ctx->opcode) == 0) {
2395 tcg_gen_movi_tl(EA, 0);
2396 } else if (NARROW_MODE(ctx)) {
2397 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2398 } else {
2399 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2400 }
2401 }
2402
2403 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2404 target_long val)
2405 {
2406 tcg_gen_addi_tl(ret, arg1, val);
2407 if (NARROW_MODE(ctx)) {
2408 tcg_gen_ext32u_tl(ret, ret);
2409 }
2410 }
2411
2412 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2413 {
2414 TCGLabel *l1 = gen_new_label();
2415 TCGv t0 = tcg_temp_new();
2416 TCGv_i32 t1, t2;
2417 tcg_gen_andi_tl(t0, EA, mask);
2418 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2419 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2420 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
2421 gen_update_nip(ctx, ctx->nip - 4);
2422 gen_helper_raise_exception_err(cpu_env, t1, t2);
2423 tcg_temp_free_i32(t1);
2424 tcg_temp_free_i32(t2);
2425 gen_set_label(l1);
2426 tcg_temp_free(t0);
2427 }
2428
2429 /*** Integer load ***/
2430 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2431 {
2432 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2433 }
2434
2435 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2436 {
2437 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2438 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2439 }
2440
2441 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2442 {
2443 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2444 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2445 }
2446
2447 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2448 {
2449 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2450 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2451 }
2452
2453 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2454 {
2455 TCGv tmp = tcg_temp_new();
2456 gen_qemu_ld32u(ctx, tmp, addr);
2457 tcg_gen_extu_tl_i64(val, tmp);
2458 tcg_temp_free(tmp);
2459 }
2460
2461 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2462 {
2463 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2464 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2465 }
2466
2467 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2468 {
2469 TCGv tmp = tcg_temp_new();
2470 gen_qemu_ld32s(ctx, tmp, addr);
2471 tcg_gen_ext_tl_i64(val, tmp);
2472 tcg_temp_free(tmp);
2473 }
2474
2475 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2476 {
2477 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2478 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2479 }
2480
2481 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2482 {
2483 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2484 }
2485
2486 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2487 {
2488 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2489 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2490 }
2491
2492 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2493 {
2494 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2495 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2496 }
2497
2498 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2499 {
2500 TCGv tmp = tcg_temp_new();
2501 tcg_gen_trunc_i64_tl(tmp, val);
2502 gen_qemu_st32(ctx, tmp, addr);
2503 tcg_temp_free(tmp);
2504 }
2505
2506 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2507 {
2508 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2509 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2510 }
2511
2512 #define GEN_LD(name, ldop, opc, type) \
2513 static void glue(gen_, name)(DisasContext *ctx) \
2514 { \
2515 TCGv EA; \
2516 gen_set_access_type(ctx, ACCESS_INT); \
2517 EA = tcg_temp_new(); \
2518 gen_addr_imm_index(ctx, EA, 0); \
2519 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2520 tcg_temp_free(EA); \
2521 }
2522
2523 #define GEN_LDU(name, ldop, opc, type) \
2524 static void glue(gen_, name##u)(DisasContext *ctx) \
2525 { \
2526 TCGv EA; \
2527 if (unlikely(rA(ctx->opcode) == 0 || \
2528 rA(ctx->opcode) == rD(ctx->opcode))) { \
2529 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2530 return; \
2531 } \
2532 gen_set_access_type(ctx, ACCESS_INT); \
2533 EA = tcg_temp_new(); \
2534 if (type == PPC_64B) \
2535 gen_addr_imm_index(ctx, EA, 0x03); \
2536 else \
2537 gen_addr_imm_index(ctx, EA, 0); \
2538 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2539 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2540 tcg_temp_free(EA); \
2541 }
2542
2543 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2544 static void glue(gen_, name##ux)(DisasContext *ctx) \
2545 { \
2546 TCGv EA; \
2547 if (unlikely(rA(ctx->opcode) == 0 || \
2548 rA(ctx->opcode) == rD(ctx->opcode))) { \
2549 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2550 return; \
2551 } \
2552 gen_set_access_type(ctx, ACCESS_INT); \
2553 EA = tcg_temp_new(); \
2554 gen_addr_reg_index(ctx, EA); \
2555 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2556 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2557 tcg_temp_free(EA); \
2558 }
2559
2560 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2561 static void glue(gen_, name##x)(DisasContext *ctx) \
2562 { \
2563 TCGv EA; \
2564 chk; \
2565 gen_set_access_type(ctx, ACCESS_INT); \
2566 EA = tcg_temp_new(); \
2567 gen_addr_reg_index(ctx, EA); \
2568 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2569 tcg_temp_free(EA); \
2570 }
2571
2572 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2573 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2574
2575 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2576 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2577
2578 #define GEN_LDS(name, ldop, op, type) \
2579 GEN_LD(name, ldop, op | 0x20, type); \
2580 GEN_LDU(name, ldop, op | 0x21, type); \
2581 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2582 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2583
2584 /* lbz lbzu lbzux lbzx */
2585 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2586 /* lha lhau lhaux lhax */
2587 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2588 /* lhz lhzu lhzux lhzx */
2589 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2590 /* lwz lwzu lwzux lwzx */
2591 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2592 #if defined(TARGET_PPC64)
2593 /* lwaux */
2594 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2595 /* lwax */
2596 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2597 /* ldux */
2598 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2599 /* ldx */
2600 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2601
2602 /* CI load/store variants */
2603 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
2604 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2605 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2606 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2607
2608 static void gen_ld(DisasContext *ctx)
2609 {
2610 TCGv EA;
2611 if (Rc(ctx->opcode)) {
2612 if (unlikely(rA(ctx->opcode) == 0 ||
2613 rA(ctx->opcode) == rD(ctx->opcode))) {
2614 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2615 return;
2616 }
2617 }
2618 gen_set_access_type(ctx, ACCESS_INT);
2619 EA = tcg_temp_new();
2620 gen_addr_imm_index(ctx, EA, 0x03);
2621 if (ctx->opcode & 0x02) {
2622 /* lwa (lwau is undefined) */
2623 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2624 } else {
2625 /* ld - ldu */
2626 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2627 }
2628 if (Rc(ctx->opcode))
2629 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2630 tcg_temp_free(EA);
2631 }
2632
2633 /* lq */
2634 static void gen_lq(DisasContext *ctx)
2635 {
2636 int ra, rd;
2637 TCGv EA;
2638
2639 /* lq is a legal user mode instruction starting in ISA 2.07 */
2640 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2641 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2642
2643 if (!legal_in_user_mode && ctx->pr) {
2644 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2645 return;
2646 }
2647
2648 if (!le_is_supported && ctx->le_mode) {
2649 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2650 return;
2651 }
2652
2653 ra = rA(ctx->opcode);
2654 rd = rD(ctx->opcode);
2655 if (unlikely((rd & 1) || rd == ra)) {
2656 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2657 return;
2658 }
2659
2660 gen_set_access_type(ctx, ACCESS_INT);
2661 EA = tcg_temp_new();
2662 gen_addr_imm_index(ctx, EA, 0x0F);
2663
2664 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2665 64-bit byteswap already. */
2666 if (unlikely(ctx->le_mode)) {
2667 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2668 gen_addr_add(ctx, EA, EA, 8);
2669 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2670 } else {
2671 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2672 gen_addr_add(ctx, EA, EA, 8);
2673 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2674 }
2675 tcg_temp_free(EA);
2676 }
2677 #endif
2678
2679 /*** Integer store ***/
2680 #define GEN_ST(name, stop, opc, type) \
2681 static void glue(gen_, name)(DisasContext *ctx) \
2682 { \
2683 TCGv EA; \
2684 gen_set_access_type(ctx, ACCESS_INT); \
2685 EA = tcg_temp_new(); \
2686 gen_addr_imm_index(ctx, EA, 0); \
2687 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2688 tcg_temp_free(EA); \
2689 }
2690
2691 #define GEN_STU(name, stop, opc, type) \
2692 static void glue(gen_, stop##u)(DisasContext *ctx) \
2693 { \
2694 TCGv EA; \
2695 if (unlikely(rA(ctx->opcode) == 0)) { \
2696 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2697 return; \
2698 } \
2699 gen_set_access_type(ctx, ACCESS_INT); \
2700 EA = tcg_temp_new(); \
2701 if (type == PPC_64B) \
2702 gen_addr_imm_index(ctx, EA, 0x03); \
2703 else \
2704 gen_addr_imm_index(ctx, EA, 0); \
2705 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2706 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2707 tcg_temp_free(EA); \
2708 }
2709
2710 #define GEN_STUX(name, stop, opc2, opc3, type) \
2711 static void glue(gen_, name##ux)(DisasContext *ctx) \
2712 { \
2713 TCGv EA; \
2714 if (unlikely(rA(ctx->opcode) == 0)) { \
2715 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2716 return; \
2717 } \
2718 gen_set_access_type(ctx, ACCESS_INT); \
2719 EA = tcg_temp_new(); \
2720 gen_addr_reg_index(ctx, EA); \
2721 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2722 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2723 tcg_temp_free(EA); \
2724 }
2725
2726 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2727 static void glue(gen_, name##x)(DisasContext *ctx) \
2728 { \
2729 TCGv EA; \
2730 chk; \
2731 gen_set_access_type(ctx, ACCESS_INT); \
2732 EA = tcg_temp_new(); \
2733 gen_addr_reg_index(ctx, EA); \
2734 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2735 tcg_temp_free(EA); \
2736 }
2737 #define GEN_STX(name, stop, opc2, opc3, type) \
2738 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2739
2740 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2741 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2742
2743 #define GEN_STS(name, stop, op, type) \
2744 GEN_ST(name, stop, op | 0x20, type); \
2745 GEN_STU(name, stop, op | 0x21, type); \
2746 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2747 GEN_STX(name, stop, 0x17, op | 0x00, type)
2748
2749 /* stb stbu stbux stbx */
2750 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2751 /* sth sthu sthux sthx */
2752 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2753 /* stw stwu stwux stwx */
2754 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2755 #if defined(TARGET_PPC64)
2756 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2757 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2758 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
2759 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2760 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2761 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2762
2763 static void gen_std(DisasContext *ctx)
2764 {
2765 int rs;
2766 TCGv EA;
2767
2768 rs = rS(ctx->opcode);
2769 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2770 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2771 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2772
2773 if (!(ctx->insns_flags & PPC_64BX)) {
2774 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2775 }
2776
2777 if (!legal_in_user_mode && ctx->pr) {
2778 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2779 return;
2780 }
2781
2782 if (!le_is_supported && ctx->le_mode) {
2783 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2784 return;
2785 }
2786
2787 if (unlikely(rs & 1)) {
2788 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2789 return;
2790 }
2791 gen_set_access_type(ctx, ACCESS_INT);
2792 EA = tcg_temp_new();
2793 gen_addr_imm_index(ctx, EA, 0x03);
2794
2795 /* We only need to swap high and low halves. gen_qemu_st64 does
2796 necessary 64-bit byteswap already. */
2797 if (unlikely(ctx->le_mode)) {
2798 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2799 gen_addr_add(ctx, EA, EA, 8);
2800 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2801 } else {
2802 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2803 gen_addr_add(ctx, EA, EA, 8);
2804 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2805 }
2806 tcg_temp_free(EA);
2807 } else {
2808 /* std / stdu*/
2809 if (Rc(ctx->opcode)) {
2810 if (unlikely(rA(ctx->opcode) == 0)) {
2811 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2812 return;
2813 }
2814 }
2815 gen_set_access_type(ctx, ACCESS_INT);
2816 EA = tcg_temp_new();
2817 gen_addr_imm_index(ctx, EA, 0x03);
2818 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2819 if (Rc(ctx->opcode))
2820 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2821 tcg_temp_free(EA);
2822 }
2823 }
2824 #endif
2825 /*** Integer load and store with byte reverse ***/
2826
2827 /* lhbrx */
2828 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2829 {
2830 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2831 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2832 }
2833 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2834
2835 /* lwbrx */
2836 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2837 {
2838 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2839 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2840 }
2841 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2842
2843 #if defined(TARGET_PPC64)
2844 /* ldbrx */
2845 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2846 {
2847 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2848 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2849 }
2850 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2851 #endif /* TARGET_PPC64 */
2852
2853 /* sthbrx */
2854 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2855 {
2856 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2857 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2858 }
2859 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2860
2861 /* stwbrx */
2862 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2863 {
2864 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2865 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2866 }
2867 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2868
2869 #if defined(TARGET_PPC64)
2870 /* stdbrx */
2871 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2872 {
2873 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2874 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2875 }
2876 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2877 #endif /* TARGET_PPC64 */
2878
2879 /*** Integer load and store multiple ***/
2880
2881 /* lmw */
2882 static void gen_lmw(DisasContext *ctx)
2883 {
2884 TCGv t0;
2885 TCGv_i32 t1;
2886 gen_set_access_type(ctx, ACCESS_INT);
2887 t0 = tcg_temp_new();
2888 t1 = tcg_const_i32(rD(ctx->opcode));
2889 gen_addr_imm_index(ctx, t0, 0);
2890 gen_helper_lmw(cpu_env, t0, t1);
2891 tcg_temp_free(t0);
2892 tcg_temp_free_i32(t1);
2893 }
2894
2895 /* stmw */
2896 static void gen_stmw(DisasContext *ctx)
2897 {
2898 TCGv t0;
2899 TCGv_i32 t1;
2900 gen_set_access_type(ctx, ACCESS_INT);
2901 t0 = tcg_temp_new();
2902 t1 = tcg_const_i32(rS(ctx->opcode));
2903 gen_addr_imm_index(ctx, t0, 0);
2904 gen_helper_stmw(cpu_env, t0, t1);
2905 tcg_temp_free(t0);
2906 tcg_temp_free_i32(t1);
2907 }
2908
2909 /*** Integer load and store strings ***/
2910
2911 /* lswi */
2912 /* PowerPC32 specification says we must generate an exception if
2913 * rA is in the range of registers to be loaded.
2914 * In an other hand, IBM says this is valid, but rA won't be loaded.
2915 * For now, I'll follow the spec...
2916 */
2917 static void gen_lswi(DisasContext *ctx)
2918 {
2919 TCGv t0;
2920 TCGv_i32 t1, t2;
2921 int nb = NB(ctx->opcode);
2922 int start = rD(ctx->opcode);
2923 int ra = rA(ctx->opcode);
2924 int nr;
2925
2926 if (nb == 0)
2927 nb = 32;
2928 nr = (nb + 3) / 4;
2929 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2930 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2931 return;
2932 }
2933 gen_set_access_type(ctx, ACCESS_INT);
2934 t0 = tcg_temp_new();
2935 gen_addr_register(ctx, t0);
2936 t1 = tcg_const_i32(nb);
2937 t2 = tcg_const_i32(start);
2938 gen_helper_lsw(cpu_env, t0, t1, t2);
2939 tcg_temp_free(t0);
2940 tcg_temp_free_i32(t1);
2941 tcg_temp_free_i32(t2);
2942 }
2943
2944 /* lswx */
2945 static void gen_lswx(DisasContext *ctx)
2946 {
2947 TCGv t0;
2948 TCGv_i32 t1, t2, t3;
2949 gen_set_access_type(ctx, ACCESS_INT);
2950 t0 = tcg_temp_new();
2951 gen_addr_reg_index(ctx, t0);
2952 t1 = tcg_const_i32(rD(ctx->opcode));
2953 t2 = tcg_const_i32(rA(ctx->opcode));
2954 t3 = tcg_const_i32(rB(ctx->opcode));
2955 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2956 tcg_temp_free(t0);
2957 tcg_temp_free_i32(t1);
2958 tcg_temp_free_i32(t2);
2959 tcg_temp_free_i32(t3);
2960 }
2961
2962 /* stswi */
2963 static void gen_stswi(DisasContext *ctx)
2964 {
2965 TCGv t0;
2966 TCGv_i32 t1, t2;
2967 int nb = NB(ctx->opcode);
2968 gen_set_access_type(ctx, ACCESS_INT);
2969 t0 = tcg_temp_new();
2970 gen_addr_register(ctx, t0);
2971 if (nb == 0)
2972 nb = 32;
2973 t1 = tcg_const_i32(nb);
2974 t2 = tcg_const_i32(rS(ctx->opcode));
2975 gen_helper_stsw(cpu_env, t0, t1, t2);
2976 tcg_temp_free(t0);
2977 tcg_temp_free_i32(t1);
2978 tcg_temp_free_i32(t2);
2979 }
2980
2981 /* stswx */
2982 static void gen_stswx(DisasContext *ctx)
2983 {
2984 TCGv t0;
2985 TCGv_i32 t1, t2;
2986 gen_set_access_type(ctx, ACCESS_INT);
2987 t0 = tcg_temp_new();
2988 gen_addr_reg_index(ctx, t0);
2989 t1 = tcg_temp_new_i32();
2990 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2991 tcg_gen_andi_i32(t1, t1, 0x7F);
2992 t2 = tcg_const_i32(rS(ctx->opcode));
2993 gen_helper_stsw(cpu_env, t0, t1, t2);
2994 tcg_temp_free(t0);
2995 tcg_temp_free_i32(t1);
2996 tcg_temp_free_i32(t2);
2997 }
2998
2999 /*** Memory synchronisation ***/
3000 /* eieio */
3001 static void gen_eieio(DisasContext *ctx)
3002 {
3003 }
3004
3005 #if !defined(CONFIG_USER_ONLY)
3006 static inline void gen_check_tlb_flush(DisasContext *ctx)
3007 {
3008 TCGv_i32 t;
3009 TCGLabel *l;
3010
3011 if (!ctx->lazy_tlb_flush) {
3012 return;
3013 }
3014 l = gen_new_label();
3015 t = tcg_temp_new_i32();
3016 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3017 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3018 gen_helper_check_tlb_flush(cpu_env);
3019 gen_set_label(l);
3020 tcg_temp_free_i32(t);
3021 }
3022 #else
3023 static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3024 #endif
3025
3026 /* isync */
3027 static void gen_isync(DisasContext *ctx)
3028 {
3029 /*
3030 * We need to check for a pending TLB flush. This can only happen in
3031 * kernel mode however so check MSR_PR
3032 */
3033 if (!ctx->pr) {
3034 gen_check_tlb_flush(ctx);
3035 }
3036 gen_stop_exception(ctx);
3037 }
3038
3039 #define LARX(name, len, loadop) \
3040 static void gen_##name(DisasContext *ctx) \
3041 { \
3042 TCGv t0; \
3043 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3044 gen_set_access_type(ctx, ACCESS_RES); \
3045 t0 = tcg_temp_local_new(); \
3046 gen_addr_reg_index(ctx, t0); \
3047 if ((len) > 1) { \
3048 gen_check_align(ctx, t0, (len)-1); \
3049 } \
3050 gen_qemu_##loadop(ctx, gpr, t0); \
3051 tcg_gen_mov_tl(cpu_reserve, t0); \
3052 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3053 tcg_temp_free(t0); \
3054 }
3055
3056 /* lwarx */
3057 LARX(lbarx, 1, ld8u);
3058 LARX(lharx, 2, ld16u);
3059 LARX(lwarx, 4, ld32u);
3060
3061
3062 #if defined(CONFIG_USER_ONLY)
3063 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3064 int reg, int size)
3065 {
3066 TCGv t0 = tcg_temp_new();
3067
3068 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3069 tcg_gen_movi_tl(t0, (size << 5) | reg);
3070 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3071 tcg_temp_free(t0);
3072 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
3073 }
3074 #else
3075 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3076 int reg, int size)
3077 {
3078 TCGLabel *l1;
3079
3080 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3081 l1 = gen_new_label();
3082 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3083 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3084 #if defined(TARGET_PPC64)
3085 if (size == 8) {
3086 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3087 } else
3088 #endif
3089 if (size == 4) {
3090 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3091 } else if (size == 2) {
3092 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3093 #if defined(TARGET_PPC64)
3094 } else if (size == 16) {
3095 TCGv gpr1, gpr2 , EA8;
3096 if (unlikely(ctx->le_mode)) {
3097 gpr1 = cpu_gpr[reg+1];
3098 gpr2 = cpu_gpr[reg];
3099 } else {
3100 gpr1 = cpu_gpr[reg];
3101 gpr2 = cpu_gpr[reg+1];
3102 }
3103 gen_qemu_st64(ctx, gpr1, EA);
3104 EA8 = tcg_temp_local_new();
3105 gen_addr_add(ctx, EA8, EA, 8);
3106 gen_qemu_st64(ctx, gpr2, EA8);
3107 tcg_temp_free(EA8);
3108 #endif
3109 } else {
3110 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3111 }
3112 gen_set_label(l1);
3113 tcg_gen_movi_tl(cpu_reserve, -1);
3114 }
3115 #endif
3116
3117 #define STCX(name, len) \
3118 static void gen_##name(DisasContext *ctx) \
3119 { \
3120 TCGv t0; \
3121 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3122 gen_inval_exception(ctx, \
3123 POWERPC_EXCP_INVAL_INVAL); \
3124 return; \
3125 } \
3126 gen_set_access_type(ctx, ACCESS_RES); \
3127 t0 = tcg_temp_local_new(); \
3128 gen_addr_reg_index(ctx, t0); \
3129 if (len > 1) { \
3130 gen_check_align(ctx, t0, (len)-1); \
3131 } \
3132 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3133 tcg_temp_free(t0); \
3134 }
3135
3136 STCX(stbcx_, 1);
3137 STCX(sthcx_, 2);
3138 STCX(stwcx_, 4);
3139
3140 #if defined(TARGET_PPC64)
3141 /* ldarx */
3142 LARX(ldarx, 8, ld64);
3143
3144 /* lqarx */
3145 static void gen_lqarx(DisasContext *ctx)
3146 {
3147 TCGv EA;
3148 int rd = rD(ctx->opcode);
3149 TCGv gpr1, gpr2;
3150
3151 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3152 (rd == rB(ctx->opcode)))) {
3153 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3154 return;
3155 }
3156
3157 gen_set_access_type(ctx, ACCESS_RES);
3158 EA = tcg_temp_local_new();
3159 gen_addr_reg_index(ctx, EA);
3160 gen_check_align(ctx, EA, 15);
3161 if (unlikely(ctx->le_mode)) {
3162 gpr1 = cpu_gpr[rd+1];
3163 gpr2 = cpu_gpr[rd];
3164 } else {
3165 gpr1 = cpu_gpr[rd];
3166 gpr2 = cpu_gpr[rd+1];
3167 }
3168 gen_qemu_ld64(ctx, gpr1, EA);
3169 tcg_gen_mov_tl(cpu_reserve, EA);
3170
3171 gen_addr_add(ctx, EA, EA, 8);
3172 gen_qemu_ld64(ctx, gpr2, EA);
3173
3174 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3175 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3176
3177 tcg_temp_free(EA);
3178 }
3179
3180 /* stdcx. */
3181 STCX(stdcx_, 8);
3182 STCX(stqcx_, 16);
3183 #endif /* defined(TARGET_PPC64) */
3184
3185 /* sync */
3186 static void gen_sync(DisasContext *ctx)
3187 {
3188 uint32_t l = (ctx->opcode >> 21) & 3;
3189
3190 /*
3191 * We may need to check for a pending TLB flush.
3192 *
3193 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3194 *
3195 * Additionally, this can only happen in kernel mode however so
3196 * check MSR_PR as well.
3197 */
3198 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3199 gen_check_tlb_flush(ctx);
3200 }
3201 }
3202
3203 /* wait */
3204 static void gen_wait(DisasContext *ctx)
3205 {
3206 TCGv_i32 t0 = tcg_const_i32(1);
3207 tcg_gen_st_i32(t0, cpu_env,
3208 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3209 tcg_temp_free_i32(t0);
3210 /* Stop translation, as the CPU is supposed to sleep from now */
3211 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
3212 }
3213
3214 #if defined(TARGET_PPC64)
3215 static void gen_doze(DisasContext *ctx)
3216 {
3217 #if defined(CONFIG_USER_ONLY)
3218 GEN_PRIV;
3219 #else
3220 TCGv_i32 t;
3221
3222 CHK_HV;
3223 t = tcg_const_i32(PPC_PM_DOZE);
3224 gen_helper_pminsn(cpu_env, t);
3225 tcg_temp_free_i32(t);
3226 gen_stop_exception(ctx);
3227 #endif /* defined(CONFIG_USER_ONLY) */
3228 }
3229
3230 static void gen_nap(DisasContext *ctx)
3231 {
3232 #if defined(CONFIG_USER_ONLY)
3233 GEN_PRIV;
3234 #else
3235 TCGv_i32 t;
3236
3237 CHK_HV;
3238 t = tcg_const_i32(PPC_PM_NAP);
3239 gen_helper_pminsn(cpu_env, t);
3240 tcg_temp_free_i32(t);
3241 gen_stop_exception(ctx);
3242 #endif /* defined(CONFIG_USER_ONLY) */
3243 }
3244
3245 static void gen_sleep(DisasContext *ctx)
3246 {
3247 #if defined(CONFIG_USER_ONLY)
3248 GEN_PRIV;
3249 #else
3250 TCGv_i32 t;
3251
3252 CHK_HV;
3253 t = tcg_const_i32(PPC_PM_SLEEP);
3254 gen_helper_pminsn(cpu_env, t);
3255 tcg_temp_free_i32(t);
3256 gen_stop_exception(ctx);
3257 #endif /* defined(CONFIG_USER_ONLY) */
3258 }
3259
3260 static void gen_rvwinkle(DisasContext *ctx)
3261 {
3262 #if defined(CONFIG_USER_ONLY)
3263 GEN_PRIV;
3264 #else
3265 TCGv_i32 t;
3266
3267 CHK_HV;
3268 t = tcg_const_i32(PPC_PM_RVWINKLE);
3269 gen_helper_pminsn(cpu_env, t);
3270 tcg_temp_free_i32(t);
3271 gen_stop_exception(ctx);
3272 #endif /* defined(CONFIG_USER_ONLY) */
3273 }
3274 #endif /* #if defined(TARGET_PPC64) */
3275
3276 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3277 {
3278 #if defined(TARGET_PPC64)
3279 if (ctx->has_cfar)
3280 tcg_gen_movi_tl(cpu_cfar, nip);
3281 #endif
3282 }
3283
3284 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3285 {
3286 if (unlikely(ctx->singlestep_enabled)) {
3287 return false;
3288 }
3289
3290 #ifndef CONFIG_USER_ONLY
3291 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3292 #else
3293 return true;
3294 #endif
3295 }
3296
3297 /*** Branch ***/
3298 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3299 {
3300 if (NARROW_MODE(ctx)) {
3301 dest = (uint32_t) dest;
3302 }
3303 if (use_goto_tb(ctx, dest)) {
3304 tcg_gen_goto_tb(n);
3305 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3306 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3307 } else {
3308 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3309 if (unlikely(ctx->singlestep_enabled)) {
3310 if ((ctx->singlestep_enabled &
3311 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3312 (ctx->exception == POWERPC_EXCP_BRANCH ||
3313 ctx->exception == POWERPC_EXCP_TRACE)) {
3314 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3315 }
3316 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3317 gen_debug_exception(ctx);
3318 }
3319 }
3320 tcg_gen_exit_tb(0);
3321 }
3322 }
3323
3324 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3325 {
3326 if (NARROW_MODE(ctx)) {
3327 nip = (uint32_t)nip;
3328 }
3329 tcg_gen_movi_tl(cpu_lr, nip);
3330 }
3331
3332 /* b ba bl bla */
3333 static void gen_b(DisasContext *ctx)
3334 {
3335 target_ulong li, target;
3336
3337 ctx->exception = POWERPC_EXCP_BRANCH;
3338 /* sign extend LI */
3339 li = LI(ctx->opcode);
3340 li = (li ^ 0x02000000) - 0x02000000;
3341 if (likely(AA(ctx->opcode) == 0)) {
3342 target = ctx->nip + li - 4;
3343 } else {
3344 target = li;
3345 }
3346 if (LK(ctx->opcode)) {
3347 gen_setlr(ctx, ctx->nip);
3348 }
3349 gen_update_cfar(ctx, ctx->nip);
3350 gen_goto_tb(ctx, 0, target);
3351 }
3352
3353 #define BCOND_IM 0
3354 #define BCOND_LR 1
3355 #define BCOND_CTR 2
3356 #define BCOND_TAR 3
3357
3358 static inline void gen_bcond(DisasContext *ctx, int type)
3359 {
3360 uint32_t bo = BO(ctx->opcode);
3361 TCGLabel *l1;
3362 TCGv target;
3363
3364 ctx->exception = POWERPC_EXCP_BRANCH;
3365 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3366 target = tcg_temp_local_new();
3367 if (type == BCOND_CTR)
3368 tcg_gen_mov_tl(target, cpu_ctr);
3369 else if (type == BCOND_TAR)
3370 gen_load_spr(target, SPR_TAR);
3371 else
3372 tcg_gen_mov_tl(target, cpu_lr);
3373 } else {
3374 TCGV_UNUSED(target);
3375 }
3376 if (LK(ctx->opcode))
3377 gen_setlr(ctx, ctx->nip);
3378 l1 = gen_new_label();
3379 if ((bo & 0x4) == 0) {
3380 /* Decrement and test CTR */
3381 TCGv temp = tcg_temp_new();
3382 if (unlikely(type == BCOND_CTR)) {
3383 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3384 return;
3385 }
3386 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3387 if (NARROW_MODE(ctx)) {
3388 tcg_gen_ext32u_tl(temp, cpu_ctr);
3389 } else {
3390 tcg_gen_mov_tl(temp, cpu_ctr);
3391 }
3392 if (bo & 0x2) {
3393 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3394 } else {
3395 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3396 }
3397 tcg_temp_free(temp);
3398 }
3399 if ((bo & 0x10) == 0) {
3400 /* Test CR */
3401 uint32_t bi = BI(ctx->opcode);
3402 uint32_t mask = 0x08 >> (bi & 0x03);
3403 TCGv_i32 temp = tcg_temp_new_i32();
3404
3405 if (bo & 0x8) {
3406 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3407 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3408 } else {
3409 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3410 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3411 }
3412 tcg_temp_free_i32(temp);
3413 }
3414 gen_update_cfar(ctx, ctx->nip);
3415 if (type == BCOND_IM) {
3416 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3417 if (likely(AA(ctx->opcode) == 0)) {
3418 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3419 } else {
3420 gen_goto_tb(ctx, 0, li);
3421 }
3422 gen_set_label(l1);
3423 gen_goto_tb(ctx, 1, ctx->nip);
3424 } else {
3425 if (NARROW_MODE(ctx)) {
3426 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3427 } else {
3428 tcg_gen_andi_tl(cpu_nip, target, ~3);
3429 }
3430 tcg_gen_exit_tb(0);
3431 gen_set_label(l1);
3432 gen_update_nip(ctx, ctx->nip);
3433 tcg_gen_exit_tb(0);
3434 }
3435 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3436 tcg_temp_free(target);
3437 }
3438 }
3439
3440 static void gen_bc(DisasContext *ctx)
3441 {
3442 gen_bcond(ctx, BCOND_IM);
3443 }
3444
3445 static void gen_bcctr(DisasContext *ctx)
3446 {
3447 gen_bcond(ctx, BCOND_CTR);
3448 }
3449
3450 static void gen_bclr(DisasContext *ctx)
3451 {
3452 gen_bcond(ctx, BCOND_LR);
3453 }
3454
3455 static void gen_bctar(DisasContext *ctx)
3456 {
3457 gen_bcond(ctx, BCOND_TAR);
3458 }
3459
3460 /*** Condition register logical ***/
3461 #define GEN_CRLOGIC(name, tcg_op, opc) \
3462 static void glue(gen_, name)(DisasContext *ctx) \
3463 { \
3464 uint8_t bitmask; \
3465 int sh; \
3466 TCGv_i32 t0, t1; \
3467 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3468 t0 = tcg_temp_new_i32(); \
3469 if (sh > 0) \
3470 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3471 else if (sh < 0) \
3472 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3473 else \
3474 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3475 t1 = tcg_temp_new_i32(); \
3476 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3477 if (sh > 0) \
3478 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3479 else if (sh < 0) \
3480 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3481 else \
3482 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3483 tcg_op(t0, t0, t1); \
3484 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3485 tcg_gen_andi_i32(t0, t0, bitmask); \
3486 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3487 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3488 tcg_temp_free_i32(t0); \
3489 tcg_temp_free_i32(t1); \
3490 }
3491
3492 /* crand */
3493 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3494 /* crandc */
3495 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3496 /* creqv */
3497 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3498 /* crnand */
3499 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3500 /* crnor */
3501 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3502 /* cror */
3503 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3504 /* crorc */
3505 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3506 /* crxor */
3507 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3508
3509 /* mcrf */
3510 static void gen_mcrf(DisasContext *ctx)
3511 {
3512 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3513 }
3514
3515 /*** System linkage ***/
3516
3517 /* rfi (supervisor only) */
3518 static void gen_rfi(DisasContext *ctx)
3519 {
3520 #if defined(CONFIG_USER_ONLY)
3521 GEN_PRIV;
3522 #else
3523 /* FIXME: This instruction doesn't exist anymore on 64-bit server
3524 * processors compliant with arch 2.x, we should remove it there,
3525 * but we need to fix OpenBIOS not to use it on 970 first
3526 */
3527 /* Restore CPU state */
3528 CHK_SV;
3529 gen_update_cfar(ctx, ctx->nip);
3530 gen_helper_rfi(cpu_env);
3531 gen_sync_exception(ctx);
3532 #endif
3533 }
3534
3535 #if defined(TARGET_PPC64)
3536 static void gen_rfid(DisasContext *ctx)
3537 {
3538 #if defined(CONFIG_USER_ONLY)
3539 GEN_PRIV;
3540 #else
3541 /* Restore CPU state */
3542 CHK_SV;
3543 gen_update_cfar(ctx, ctx->nip);
3544 gen_helper_rfid(cpu_env);
3545 gen_sync_exception(ctx);
3546 #endif
3547 }
3548
3549 static void gen_hrfid(DisasContext *ctx)
3550 {
3551 #if defined(CONFIG_USER_ONLY)
3552 GEN_PRIV;
3553 #else
3554 /* Restore CPU state */
3555 CHK_HV;
3556 gen_helper_hrfid(cpu_env);
3557 gen_sync_exception(ctx);
3558 #endif
3559 }
3560 #endif
3561
3562 /* sc */
3563 #if defined(CONFIG_USER_ONLY)
3564 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3565 #else
3566 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3567 #endif
3568 static void gen_sc(DisasContext *ctx)
3569 {
3570 uint32_t lev;
3571
3572 lev = (ctx->opcode >> 5) & 0x7F;
3573 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3574 }
3575
3576 /*** Trap ***/
3577
3578 /* Check for unconditional traps (always or never) */
3579 static bool check_unconditional_trap(DisasContext *ctx)
3580 {
3581 /* Trap never */
3582 if (TO(ctx->opcode) == 0) {
3583 return true;
3584 }
3585 /* Trap always */
3586 if (TO(ctx->opcode) == 31) {
3587 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3588 return true;
3589 }
3590 return false;
3591 }
3592
3593 /* tw */
3594 static void gen_tw(DisasContext *ctx)
3595 {
3596 TCGv_i32 t0;
3597
3598 if (check_unconditional_trap(ctx)) {
3599 return;
3600 }
3601 t0 = tcg_const_i32(TO(ctx->opcode));
3602 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3603 t0);
3604 tcg_temp_free_i32(t0);
3605 }
3606
3607 /* twi */
3608 static void gen_twi(DisasContext *ctx)
3609 {
3610 TCGv t0;
3611 TCGv_i32 t1;
3612
3613 if (check_unconditional_trap(ctx)) {
3614 return;
3615 }
3616 t0 = tcg_const_tl(SIMM(ctx->opcode));
3617 t1 = tcg_const_i32(TO(ctx->opcode));
3618 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3619 tcg_temp_free(t0);
3620 tcg_temp_free_i32(t1);
3621 }
3622
3623 #if defined(TARGET_PPC64)
3624 /* td */
3625 static void gen_td(DisasContext *ctx)
3626 {
3627 TCGv_i32 t0;
3628
3629 if (check_unconditional_trap(ctx)) {
3630 return;
3631 }
3632 t0 = tcg_const_i32(TO(ctx->opcode));
3633 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3634 t0);
3635 tcg_temp_free_i32(t0);
3636 }
3637
3638 /* tdi */
3639 static void gen_tdi(DisasContext *ctx)
3640 {
3641 TCGv t0;
3642 TCGv_i32 t1;
3643
3644 if (check_unconditional_trap(ctx)) {
3645 return;
3646 }
3647 t0 = tcg_const_tl(SIMM(ctx->opcode));
3648 t1 = tcg_const_i32(TO(ctx->opcode));
3649 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3650 tcg_temp_free(t0);
3651 tcg_temp_free_i32(t1);
3652 }
3653 #endif
3654
3655 /*** Processor control ***/
3656
3657 static void gen_read_xer(TCGv dst)
3658 {
3659 TCGv t0 = tcg_temp_new();
3660 TCGv t1 = tcg_temp_new();
3661 TCGv t2 = tcg_temp_new();
3662 tcg_gen_mov_tl(dst, cpu_xer);
3663 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3664 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3665 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3666 tcg_gen_or_tl(t0, t0, t1);
3667 tcg_gen_or_tl(dst, dst, t2);
3668 tcg_gen_or_tl(dst, dst, t0);
3669 tcg_temp_free(t0);
3670 tcg_temp_free(t1);
3671 tcg_temp_free(t2);
3672 }
3673
3674 static void gen_write_xer(TCGv src)
3675 {
3676 tcg_gen_andi_tl(cpu_xer, src,
3677 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3678 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3679 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3680 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3681 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3682 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3683 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3684 }
3685
3686 /* mcrxr */
3687 static void gen_mcrxr(DisasContext *ctx)
3688 {
3689 TCGv_i32 t0 = tcg_temp_new_i32();
3690 TCGv_i32 t1 = tcg_temp_new_i32();
3691 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3692
3693 tcg_gen_trunc_tl_i32(t0, cpu_so);
3694 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3695 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3696 tcg_gen_shli_i32(t0, t0, 3);
3697 tcg_gen_shli_i32(t1, t1, 2);
3698 tcg_gen_shli_i32(dst, dst, 1);
3699 tcg_gen_or_i32(dst, dst, t0);
3700 tcg_gen_or_i32(dst, dst, t1);
3701 tcg_temp_free_i32(t0);
3702 tcg_temp_free_i32(t1);
3703
3704 tcg_gen_movi_tl(cpu_so, 0);
3705 tcg_gen_movi_tl(cpu_ov, 0);
3706 tcg_gen_movi_tl(cpu_ca, 0);
3707 }
3708
3709 /* mfcr mfocrf */
3710 static void gen_mfcr(DisasContext *ctx)
3711 {
3712 uint32_t crm, crn;
3713
3714 if (likely(ctx->opcode & 0x00100000)) {
3715 crm = CRM(ctx->opcode);
3716 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3717 crn = ctz32 (crm);
3718 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3719 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3720 cpu_gpr[rD(ctx->opcode)], crn * 4);
3721 }
3722 } else {
3723 TCGv_i32 t0 = tcg_temp_new_i32();
3724 tcg_gen_mov_i32(t0, cpu_crf[0]);
3725 tcg_gen_shli_i32(t0, t0, 4);
3726 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3727 tcg_gen_shli_i32(t0, t0, 4);
3728 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3729 tcg_gen_shli_i32(t0, t0, 4);
3730 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3731 tcg_gen_shli_i32(t0, t0, 4);
3732 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3733 tcg_gen_shli_i32(t0, t0, 4);
3734 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3735 tcg_gen_shli_i32(t0, t0, 4);
3736 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3737 tcg_gen_shli_i32(t0, t0, 4);
3738 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3739 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3740 tcg_temp_free_i32(t0);
3741 }
3742 }
3743
3744 /* mfmsr */
3745 static void gen_mfmsr(DisasContext *ctx)
3746 {
3747 CHK_SV;
3748 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3749 }
3750
3751 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3752 {
3753 #if 0
3754 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3755 printf("ERROR: try to access SPR %d !\n", sprn);
3756 #endif
3757 }
3758 #define SPR_NOACCESS (&spr_noaccess)
3759
3760 /* mfspr */
3761 static inline void gen_op_mfspr(DisasContext *ctx)
3762 {
3763 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
3764 uint32_t sprn = SPR(ctx->opcode);
3765
3766 #if defined(CONFIG_USER_ONLY)
3767 read_cb = ctx->spr_cb[sprn].uea_read;
3768 #else
3769 if (ctx->pr) {
3770 read_cb = ctx->spr_cb[sprn].uea_read;
3771 } else if (ctx->hv) {
3772 read_cb = ctx->spr_cb[sprn].hea_read;
3773 } else {
3774 read_cb = ctx->spr_cb[sprn].oea_read;
3775 }
3776 #endif
3777 if (likely(read_cb != NULL)) {
3778 if (likely(read_cb != SPR_NOACCESS)) {
3779 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3780 } else {
3781 /* Privilege exception */
3782 /* This is a hack to avoid warnings when running Linux:
3783 * this OS breaks the PowerPC virtualisation model,
3784 * allowing userland application to read the PVR
3785 */
3786 if (sprn != SPR_PVR) {
3787 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
3788 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3789 if (qemu_log_separate()) {
3790 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3791 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3792 }
3793 }
3794 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3795 }
3796 } else {
3797 /* ISA 2.07 defines these as no-ops */
3798 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3799 (sprn >= 808 && sprn <= 811)) {
3800 /* This is a nop */
3801 return;
3802 }
3803 /* Not defined */
3804 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
3805 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3806 if (qemu_log_separate()) {
3807 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3808 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3809 }
3810
3811 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3812 * it can generate a priv, a hv emu or a no-op
3813 */
3814 if (sprn & 0x10) {
3815 if (ctx->pr) {
3816 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3817 }
3818 } else {
3819 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3820 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3821 }
3822 }
3823 }
3824 }
3825
3826 static void gen_mfspr(DisasContext *ctx)
3827 {
3828 gen_op_mfspr(ctx);
3829 }
3830
3831 /* mftb */
3832 static void gen_mftb(DisasContext *ctx)
3833 {
3834 gen_op_mfspr(ctx);
3835 }
3836
3837 /* mtcrf mtocrf*/
3838 static void gen_mtcrf(DisasContext *ctx)
3839 {
3840 uint32_t crm, crn;
3841
3842 crm = CRM(ctx->opcode);
3843 if (likely((ctx->opcode & 0x00100000))) {
3844 if (crm && ((crm & (crm - 1)) == 0)) {
3845 TCGv_i32 temp = tcg_temp_new_i32();
3846 crn = ctz32 (crm);
3847 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3848 tcg_gen_shri_i32(temp, temp, crn * 4);
3849 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3850 tcg_temp_free_i32(temp);
3851 }
3852 } else {
3853 TCGv_i32 temp = tcg_temp_new_i32();
3854 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3855 for (crn = 0 ; crn < 8 ; crn++) {
3856 if (crm & (1 << crn)) {
3857 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3858 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3859 }
3860 }
3861 tcg_temp_free_i32(temp);
3862 }
3863 }
3864
3865 /* mtmsr */
3866 #if defined(TARGET_PPC64)
3867 static void gen_mtmsrd(DisasContext *ctx)
3868 {
3869 CHK_SV;
3870
3871 #if !defined(CONFIG_USER_ONLY)
3872 if (ctx->opcode & 0x00010000) {
3873 /* Special form that does not need any synchronisation */
3874 TCGv t0 = tcg_temp_new();
3875 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3876 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3877 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3878 tcg_temp_free(t0);
3879 } else {
3880 /* XXX: we need to update nip before the store
3881 * if we enter power saving mode, we will exit the loop
3882 * directly from ppc_store_msr
3883 */
3884 gen_update_nip(ctx, ctx->nip);
3885 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3886 /* Must stop the translation as machine state (may have) changed */
3887 /* Note that mtmsr is not always defined as context-synchronizing */
3888 gen_stop_exception(ctx);
3889 }
3890 #endif /* !defined(CONFIG_USER_ONLY) */
3891 }
3892 #endif /* defined(TARGET_PPC64) */
3893
3894 static void gen_mtmsr(DisasContext *ctx)
3895 {
3896 CHK_SV;
3897
3898 #if !defined(CONFIG_USER_ONLY)
3899 if (ctx->opcode & 0x00010000) {
3900 /* Special form that does not need any synchronisation */
3901 TCGv t0 = tcg_temp_new();
3902 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3903 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3904 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3905 tcg_temp_free(t0);
3906 } else {
3907 TCGv msr = tcg_temp_new();
3908
3909 /* XXX: we need to update nip before the store
3910 * if we enter power saving mode, we will exit the loop
3911 * directly from ppc_store_msr
3912 */
3913 gen_update_nip(ctx, ctx->nip);
3914 #if defined(TARGET_PPC64)
3915 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3916 #else
3917 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3918 #endif
3919 gen_helper_store_msr(cpu_env, msr);
3920 tcg_temp_free(msr);
3921 /* Must stop the translation as machine state (may have) changed */
3922 /* Note that mtmsr is not always defined as context-synchronizing */
3923 gen_stop_exception(ctx);
3924 }
3925 #endif
3926 }
3927
3928 /* mtspr */
3929 static void gen_mtspr(DisasContext *ctx)
3930 {
3931 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
3932 uint32_t sprn = SPR(ctx->opcode);
3933
3934 #if defined(CONFIG_USER_ONLY)
3935 write_cb = ctx->spr_cb[sprn].uea_write;
3936 #else
3937 if (ctx->pr) {
3938 write_cb = ctx->spr_cb[sprn].uea_write;
3939 } else if (ctx->hv) {
3940 write_cb = ctx->spr_cb[sprn].hea_write;
3941 } else {
3942 write_cb = ctx->spr_cb[sprn].oea_write;
3943 }
3944 #endif
3945 if (likely(write_cb != NULL)) {
3946 if (likely(write_cb != SPR_NOACCESS)) {
3947 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3948 } else {
3949 /* Privilege exception */
3950 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
3951 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3952 if (qemu_log_separate()) {
3953 qemu_log("Trying to write privileged spr %d (0x%03x) at "
3954 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3955 }
3956 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3957 }
3958 } else {
3959 /* ISA 2.07 defines these as no-ops */
3960 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3961 (sprn >= 808 && sprn <= 811)) {
3962 /* This is a nop */
3963 return;
3964 }
3965
3966 /* Not defined */
3967 if (qemu_log_separate()) {
3968 qemu_log("Trying to write invalid spr %d (0x%03x) at "
3969 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3970 }
3971 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
3972 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3973
3974
3975 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3976 * it can generate a priv, a hv emu or a no-op
3977 */
3978 if (sprn & 0x10) {
3979 if (ctx->pr) {
3980 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3981 }
3982 } else {
3983 if (ctx->pr || sprn == 0) {
3984 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3985 }
3986 }
3987 }
3988 }
3989
3990 #if defined(TARGET_PPC64)
3991 /* setb */
3992 static void gen_setb(DisasContext *ctx)
3993 {
3994 TCGv_i32 t0 = tcg_temp_new_i32();
3995 TCGv_i32 t8 = tcg_temp_new_i32();
3996 TCGv_i32 tm1 = tcg_temp_new_i32();
3997 int crf = crfS(ctx->opcode);
3998
3999 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4000 tcg_gen_movi_i32(t8, 8);
4001 tcg_gen_movi_i32(tm1, -1);
4002 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4003 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4004
4005 tcg_temp_free_i32(t0);
4006 tcg_temp_free_i32(t8);
4007 tcg_temp_free_i32(tm1);
4008 }
4009 #endif
4010
4011 /*** Cache management ***/
4012
4013 /* dcbf */
4014 static void gen_dcbf(DisasContext *ctx)
4015 {
4016 /* XXX: specification says this is treated as a load by the MMU */
4017 TCGv t0;
4018 gen_set_access_type(ctx, ACCESS_CACHE);
4019 t0 = tcg_temp_new();
4020 gen_addr_reg_index(ctx, t0);
4021 gen_qemu_ld8u(ctx, t0, t0);
4022 tcg_temp_free(t0);
4023 }
4024
4025 /* dcbi (Supervisor only) */
4026 static void gen_dcbi(DisasContext *ctx)
4027 {
4028 #if defined(CONFIG_USER_ONLY)
4029 GEN_PRIV;
4030 #else
4031 TCGv EA, val;
4032
4033 CHK_SV;
4034 EA = tcg_temp_new();
4035 gen_set_access_type(ctx, ACCESS_CACHE);
4036 gen_addr_reg_index(ctx, EA);
4037 val = tcg_temp_new();
4038 /* XXX: specification says this should be treated as a store by the MMU */
4039 gen_qemu_ld8u(ctx, val, EA);
4040 gen_qemu_st8(ctx, val, EA);
4041 tcg_temp_free(val);
4042 tcg_temp_free(EA);
4043 #endif /* defined(CONFIG_USER_ONLY) */
4044 }
4045
4046 /* dcdst */
4047 static void gen_dcbst(DisasContext *ctx)
4048 {
4049 /* XXX: specification say this is treated as a load by the MMU */
4050 TCGv t0;
4051 gen_set_access_type(ctx, ACCESS_CACHE);
4052 t0 = tcg_temp_new();
4053 gen_addr_reg_index(ctx, t0);
4054 gen_qemu_ld8u(ctx, t0, t0);
4055 tcg_temp_free(t0);
4056 }
4057
4058 /* dcbt */
4059 static void gen_dcbt(DisasContext *ctx)
4060 {
4061 /* interpreted as no-op */
4062 /* XXX: specification say this is treated as a load by the MMU
4063 * but does not generate any exception
4064 */
4065 }
4066
4067 /* dcbtst */
4068 static void gen_dcbtst(DisasContext *ctx)
4069 {
4070 /* interpreted as no-op */
4071 /* XXX: specification say this is treated as a load by the MMU
4072 * but does not generate any exception
4073 */
4074 }
4075
4076 /* dcbtls */
4077 static void gen_dcbtls(DisasContext *ctx)
4078 {
4079 /* Always fails locking the cache */
4080 TCGv t0 = tcg_temp_new();
4081 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4082 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4083 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4084 tcg_temp_free(t0);
4085 }
4086
4087 /* dcbz */
4088 static void gen_dcbz(DisasContext *ctx)
4089 {
4090 TCGv tcgv_addr;
4091 TCGv_i32 tcgv_op;
4092
4093 gen_set_access_type(ctx, ACCESS_CACHE);
4094 tcgv_addr = tcg_temp_new();
4095 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4096 gen_addr_reg_index(ctx, tcgv_addr);
4097 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4098 tcg_temp_free(tcgv_addr);
4099 tcg_temp_free_i32(tcgv_op);
4100 }
4101
4102 /* dst / dstt */
4103 static void gen_dst(DisasContext *ctx)
4104 {
4105 if (rA(ctx->opcode) == 0) {
4106 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4107 } else {
4108 /* interpreted as no-op */
4109 }
4110 }
4111
4112 /* dstst /dststt */
4113 static void gen_dstst(DisasContext *ctx)
4114 {
4115 if (rA(ctx->opcode) == 0) {
4116 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4117 } else {
4118 /* interpreted as no-op */
4119 }
4120
4121 }
4122
4123 /* dss / dssall */
4124 static void gen_dss(DisasContext *ctx)
4125 {
4126 /* interpreted as no-op */
4127 }
4128
4129 /* icbi */
4130 static void gen_icbi(DisasContext *ctx)
4131 {
4132 TCGv t0;
4133 gen_set_access_type(ctx, ACCESS_CACHE);
4134 t0 = tcg_temp_new();
4135 gen_addr_reg_index(ctx, t0);
4136 gen_helper_icbi(cpu_env, t0);
4137 tcg_temp_free(t0);
4138 }
4139
4140 /* Optional: */
4141 /* dcba */
4142 static void gen_dcba(DisasContext *ctx)
4143 {
4144 /* interpreted as no-op */
4145 /* XXX: specification say this is treated as a store by the MMU
4146 * but does not generate any exception
4147 */
4148 }
4149
4150 /*** Segment register manipulation ***/
4151 /* Supervisor only: */
4152
4153 /* mfsr */
4154 static void gen_mfsr(DisasContext *ctx)
4155 {
4156 #if defined(CONFIG_USER_ONLY)
4157 GEN_PRIV;
4158 #else
4159 TCGv t0;
4160
4161 CHK_SV;
4162 t0 = tcg_const_tl(SR(ctx->opcode));
4163 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4164 tcg_temp_free(t0);
4165 #endif /* defined(CONFIG_USER_ONLY) */
4166 }
4167
4168 /* mfsrin */
4169 static void gen_mfsrin(DisasContext *ctx)
4170 {
4171 #if defined(CONFIG_USER_ONLY)
4172 GEN_PRIV;
4173 #else
4174 TCGv t0;
4175
4176 CHK_SV;
4177 t0 = tcg_temp_new();
4178 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4179 tcg_gen_andi_tl(t0, t0, 0xF);
4180 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4181 tcg_temp_free(t0);
4182 #endif /* defined(CONFIG_USER_ONLY) */
4183 }
4184
4185 /* mtsr */
4186 static void gen_mtsr(DisasContext *ctx)
4187 {
4188 #if defined(CONFIG_USER_ONLY)
4189 GEN_PRIV;
4190 #else
4191 TCGv t0;
4192
4193 CHK_SV;
4194 t0 = tcg_const_tl(SR(ctx->opcode));
4195 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4196 tcg_temp_free(t0);
4197 #endif /* defined(CONFIG_USER_ONLY) */
4198 }
4199
4200 /* mtsrin */
4201 static void gen_mtsrin(DisasContext *ctx)
4202 {
4203 #if defined(CONFIG_USER_ONLY)
4204 GEN_PRIV;
4205 #else
4206 TCGv t0;
4207 CHK_SV;
4208
4209 t0 = tcg_temp_new();
4210 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4211 tcg_gen_andi_tl(t0, t0, 0xF);
4212 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4213 tcg_temp_free(t0);
4214 #endif /* defined(CONFIG_USER_ONLY) */
4215 }
4216
4217 #if defined(TARGET_PPC64)
4218 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4219
4220 /* mfsr */
4221 static void gen_mfsr_64b(DisasContext *ctx)
4222 {
4223 #if defined(CONFIG_USER_ONLY)
4224 GEN_PRIV;
4225 #else
4226 TCGv t0;
4227
4228 CHK_SV;
4229 t0 = tcg_const_tl(SR(ctx->opcode));
4230 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4231 tcg_temp_free(t0);
4232 #endif /* defined(CONFIG_USER_ONLY) */
4233 }
4234
4235 /* mfsrin */
4236 static void gen_mfsrin_64b(DisasContext *ctx)
4237 {
4238 #if defined(CONFIG_USER_ONLY)
4239 GEN_PRIV;
4240 #else
4241 TCGv t0;
4242
4243 CHK_SV;
4244 t0 = tcg_temp_new();
4245 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4246 tcg_gen_andi_tl(t0, t0, 0xF);
4247 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4248 tcg_temp_free(t0);
4249 #endif /* defined(CONFIG_USER_ONLY) */
4250 }
4251
4252 /* mtsr */
4253 static void gen_mtsr_64b(DisasContext *ctx)
4254 {
4255 #if defined(CONFIG_USER_ONLY)
4256 GEN_PRIV;
4257 #else
4258 TCGv t0;
4259
4260 CHK_SV;
4261 t0 = tcg_const_tl(SR(ctx->opcode));
4262 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4263 tcg_temp_free(t0);
4264 #endif /* defined(CONFIG_USER_ONLY) */
4265 }
4266
4267 /* mtsrin */
4268 static void gen_mtsrin_64b(DisasContext *ctx)
4269 {
4270 #if defined(CONFIG_USER_ONLY)
4271 GEN_PRIV;
4272 #else
4273 TCGv t0;
4274
4275 CHK_SV;
4276 t0 = tcg_temp_new();
4277 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4278 tcg_gen_andi_tl(t0, t0, 0xF);
4279 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4280 tcg_temp_free(t0);
4281 #endif /* defined(CONFIG_USER_ONLY) */
4282 }
4283
4284 /* slbmte */
4285 static void gen_slbmte(DisasContext *ctx)
4286 {
4287 #if defined(CONFIG_USER_ONLY)
4288 GEN_PRIV;
4289 #else
4290 CHK_SV;
4291
4292 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4293 cpu_gpr[rS(ctx->opcode)]);
4294 #endif /* defined(CONFIG_USER_ONLY) */
4295 }
4296
4297 static void gen_slbmfee(DisasContext *ctx)
4298 {
4299 #if defined(CONFIG_USER_ONLY)
4300 GEN_PRIV;
4301 #else
4302 CHK_SV;
4303
4304 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4305 cpu_gpr[rB(ctx->opcode)]);
4306 #endif /* defined(CONFIG_USER_ONLY) */
4307 }
4308
4309 static void gen_slbmfev(DisasContext *ctx)
4310 {
4311 #if defined(CONFIG_USER_ONLY)
4312 GEN_PRIV;
4313 #else
4314 CHK_SV;
4315
4316 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4317 cpu_gpr[rB(ctx->opcode)]);
4318 #endif /* defined(CONFIG_USER_ONLY) */
4319 }
4320
4321 static void gen_slbfee_(DisasContext *ctx)
4322 {
4323 #if defined(CONFIG_USER_ONLY)
4324 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4325 #else
4326 TCGLabel *l1, *l2;
4327
4328 if (unlikely(ctx->pr)) {
4329 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4330 return;
4331 }
4332 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4333 cpu_gpr[rB(ctx->opcode)]);
4334 l1 = gen_new_label();
4335 l2 = gen_new_label();
4336 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4337 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4338 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
4339 tcg_gen_br(l2);
4340 gen_set_label(l1);
4341 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4342 gen_set_label(l2);
4343 #endif
4344 }
4345 #endif /* defined(TARGET_PPC64) */
4346
4347 /*** Lookaside buffer management ***/
4348 /* Optional & supervisor only: */
4349
4350 /* tlbia */
4351 static void gen_tlbia(DisasContext *ctx)
4352 {
4353 #if defined(CONFIG_USER_ONLY)
4354 GEN_PRIV;
4355 #else
4356 CHK_HV;
4357
4358 gen_helper_tlbia(cpu_env);
4359 #endif /* defined(CONFIG_USER_ONLY) */
4360 }
4361
4362 /* tlbiel */
4363 static void gen_tlbiel(DisasContext *ctx)
4364 {
4365 #if defined(CONFIG_USER_ONLY)
4366 GEN_PRIV;
4367 #else
4368 CHK_SV;
4369
4370 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4371 #endif /* defined(CONFIG_USER_ONLY) */
4372 }
4373
4374 /* tlbie */
4375 static void gen_tlbie(DisasContext *ctx)
4376 {
4377 #if defined(CONFIG_USER_ONLY)
4378 GEN_PRIV;
4379 #else
4380 CHK_HV;
4381
4382 if (NARROW_MODE(ctx)) {
4383 TCGv t0 = tcg_temp_new();
4384 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4385 gen_helper_tlbie(cpu_env, t0);
4386 tcg_temp_free(t0);
4387 } else {
4388 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4389 }
4390 #endif /* defined(CONFIG_USER_ONLY) */
4391 }
4392
4393 /* tlbsync */
4394 static void gen_tlbsync(DisasContext *ctx)
4395 {
4396 #if defined(CONFIG_USER_ONLY)
4397 GEN_PRIV;
4398 #else
4399 CHK_HV;
4400
4401 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4402 * embedded however needs to deal with tlbsync. We don't try to be
4403 * fancy and swallow the overhead of checking for both.
4404 */
4405 gen_check_tlb_flush(ctx);
4406 #endif /* defined(CONFIG_USER_ONLY) */
4407 }
4408
4409 #if defined(TARGET_PPC64)
4410 /* slbia */
4411 static void gen_slbia(DisasContext *ctx)
4412 {
4413 #if defined(CONFIG_USER_ONLY)
4414 GEN_PRIV;
4415 #else
4416 CHK_SV;
4417
4418 gen_helper_slbia(cpu_env);
4419 #endif /* defined(CONFIG_USER_ONLY) */
4420 }
4421
4422 /* slbie */
4423 static void gen_slbie(DisasContext *ctx)
4424 {
4425 #if defined(CONFIG_USER_ONLY)
4426 GEN_PRIV;
4427 #else
4428 CHK_SV;
4429
4430 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4431 #endif /* defined(CONFIG_USER_ONLY) */
4432 }
4433 #endif /* defined(TARGET_PPC64) */
4434
4435 /*** External control ***/
4436 /* Optional: */
4437
4438 /* eciwx */
4439 static void gen_eciwx(DisasContext *ctx)
4440 {
4441 TCGv t0;
4442 /* Should check EAR[E] ! */
4443 gen_set_access_type(ctx, ACCESS_EXT);
4444 t0 = tcg_temp_new();
4445 gen_addr_reg_index(ctx, t0);
4446 gen_check_align(ctx, t0, 0x03);
4447 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4448 tcg_temp_free(t0);
4449 }
4450
4451 /* ecowx */
4452 static void gen_ecowx(DisasContext *ctx)
4453 {
4454 TCGv t0;
4455 /* Should check EAR[E] ! */
4456 gen_set_access_type(ctx, ACCESS_EXT);
4457 t0 = tcg_temp_new();
4458 gen_addr_reg_index(ctx, t0);
4459 gen_check_align(ctx, t0, 0x03);
4460 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4461 tcg_temp_free(t0);
4462 }
4463
4464 /* PowerPC 601 specific instructions */
4465
4466 /* abs - abs. */
4467 static void gen_abs(DisasContext *ctx)
4468 {
4469 TCGLabel *l1 = gen_new_label();
4470 TCGLabel *l2 = gen_new_label();
4471 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4472 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4473 tcg_gen_br(l2);
4474 gen_set_label(l1);
4475 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4476 gen_set_label(l2);
4477 if (unlikely(Rc(ctx->opcode) != 0))
4478 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4479 }
4480
4481 /* abso - abso. */
4482 static void gen_abso(DisasContext *ctx)
4483 {
4484 TCGLabel *l1 = gen_new_label();
4485 TCGLabel *l2 = gen_new_label();
4486 TCGLabel *l3 = gen_new_label();
4487 /* Start with XER OV disabled, the most likely case */
4488 tcg_gen_movi_tl(cpu_ov, 0);
4489 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4490 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4491 tcg_gen_movi_tl(cpu_ov, 1);
4492 tcg_gen_movi_tl(cpu_so, 1);
4493 tcg_gen_br(l2);
4494 gen_set_label(l1);
4495 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4496 tcg_gen_br(l3);
4497 gen_set_label(l2);
4498 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4499 gen_set_label(l3);
4500 if (unlikely(Rc(ctx->opcode) != 0))
4501 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4502 }
4503
4504 /* clcs */
4505 static void gen_clcs(DisasContext *ctx)
4506 {
4507 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4508 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4509 tcg_temp_free_i32(t0);
4510 /* Rc=1 sets CR0 to an undefined state */
4511 }
4512
4513 /* div - div. */
4514 static void gen_div(DisasContext *ctx)
4515 {
4516 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4517 cpu_gpr[rB(ctx->opcode)]);
4518 if (unlikely(Rc(ctx->opcode) != 0))
4519 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4520 }
4521
4522 /* divo - divo. */
4523 static void gen_divo(DisasContext *ctx)
4524 {
4525 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4526 cpu_gpr[rB(ctx->opcode)]);
4527 if (unlikely(Rc(ctx->opcode) != 0))
4528 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4529 }
4530
4531 /* divs - divs. */
4532 static void gen_divs(DisasContext *ctx)
4533 {
4534 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4535 cpu_gpr[rB(ctx->opcode)]);
4536 if (unlikely(Rc(ctx->opcode) != 0))
4537 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4538 }
4539
4540 /* divso - divso. */
4541 static void gen_divso(DisasContext *ctx)
4542 {
4543 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4544 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4545 if (unlikely(Rc(ctx->opcode) != 0))
4546 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4547 }
4548
4549 /* doz - doz. */
4550 static void gen_doz(DisasContext *ctx)
4551 {
4552 TCGLabel *l1 = gen_new_label();
4553 TCGLabel *l2 = gen_new_label();
4554 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4555 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4556 tcg_gen_br(l2);
4557 gen_set_label(l1);
4558 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4559 gen_set_label(l2);
4560 if (unlikely(Rc(ctx->opcode) != 0))
4561 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4562 }
4563
4564 /* dozo - dozo. */
4565 static void gen_dozo(DisasContext *ctx)
4566 {
4567 TCGLabel *l1 = gen_new_label();
4568 TCGLabel *l2 = gen_new_label();
4569 TCGv t0 = tcg_temp_new();
4570 TCGv t1 = tcg_temp_new();
4571 TCGv t2 = tcg_temp_new();
4572 /* Start with XER OV disabled, the most likely case */
4573 tcg_gen_movi_tl(cpu_ov, 0);
4574 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4575 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4576 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4577 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4578 tcg_gen_andc_tl(t1, t1, t2);
4579 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4580 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4581 tcg_gen_movi_tl(cpu_ov, 1);
4582 tcg_gen_movi_tl(cpu_so, 1);
4583 tcg_gen_br(l2);
4584 gen_set_label(l1);
4585 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4586 gen_set_label(l2);
4587 tcg_temp_free(t0);
4588 tcg_temp_free(t1);
4589 tcg_temp_free(t2);
4590 if (unlikely(Rc(ctx->opcode) != 0))
4591 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4592 }
4593
4594 /* dozi */
4595 static void gen_dozi(DisasContext *ctx)
4596 {
4597 target_long simm = SIMM(ctx->opcode);
4598 TCGLabel *l1 = gen_new_label();
4599 TCGLabel *l2 = gen_new_label();
4600 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4601 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4602 tcg_gen_br(l2);
4603 gen_set_label(l1);
4604 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4605 gen_set_label(l2);
4606 if (unlikely(Rc(ctx->opcode) != 0))
4607 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4608 }
4609
4610 /* lscbx - lscbx. */
4611 static void gen_lscbx(DisasContext *ctx)
4612 {
4613 TCGv t0 = tcg_temp_new();
4614 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4615 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4616 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4617
4618 gen_addr_reg_index(ctx, t0);
4619 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4620 tcg_temp_free_i32(t1);
4621 tcg_temp_free_i32(t2);
4622 tcg_temp_free_i32(t3);
4623 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4624 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4625 if (unlikely(Rc(ctx->opcode) != 0))
4626 gen_set_Rc0(ctx, t0);
4627 tcg_temp_free(t0);
4628 }
4629
4630 /* maskg - maskg. */
4631 static void gen_maskg(DisasContext *ctx)
4632 {
4633 TCGLabel *l1 = gen_new_label();
4634 TCGv t0 = tcg_temp_new();
4635 TCGv t1 = tcg_temp_new();
4636 TCGv t2 = tcg_temp_new();
4637 TCGv t3 = tcg_temp_new();
4638 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4639 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4640 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4641 tcg_gen_addi_tl(t2, t0, 1);
4642 tcg_gen_shr_tl(t2, t3, t2);
4643 tcg_gen_shr_tl(t3, t3, t1);
4644 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4645 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4646 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4647 gen_set_label(l1);
4648 tcg_temp_free(t0);
4649 tcg_temp_free(t1);
4650 tcg_temp_free(t2);
4651 tcg_temp_free(t3);
4652 if (unlikely(Rc(ctx->opcode) != 0))
4653 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4654 }
4655
4656 /* maskir - maskir. */
4657 static void gen_maskir(DisasContext *ctx)
4658 {
4659 TCGv t0 = tcg_temp_new();
4660 TCGv t1 = tcg_temp_new();
4661 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4662 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4663 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4664 tcg_temp_free(t0);
4665 tcg_temp_free(t1);
4666 if (unlikely(Rc(ctx->opcode) != 0))
4667 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4668 }
4669
4670 /* mul - mul. */
4671 static void gen_mul(DisasContext *ctx)
4672 {
4673 TCGv_i64 t0 = tcg_temp_new_i64();
4674 TCGv_i64 t1 = tcg_temp_new_i64();
4675 TCGv t2 = tcg_temp_new();
4676 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4677 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4678 tcg_gen_mul_i64(t0, t0, t1);
4679 tcg_gen_trunc_i64_tl(t2, t0);
4680 gen_store_spr(SPR_MQ, t2);
4681 tcg_gen_shri_i64(t1, t0, 32);
4682 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4683 tcg_temp_free_i64(t0);
4684 tcg_temp_free_i64(t1);
4685 tcg_temp_free(t2);
4686 if (unlikely(Rc(ctx->opcode) != 0))
4687 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4688 }
4689
4690 /* mulo - mulo. */
4691 static void gen_mulo(DisasContext *ctx)
4692 {
4693 TCGLabel *l1 = gen_new_label();
4694 TCGv_i64 t0 = tcg_temp_new_i64();
4695 TCGv_i64 t1 = tcg_temp_new_i64();
4696 TCGv t2 = tcg_temp_new();
4697 /* Start with XER OV disabled, the most likely case */
4698 tcg_gen_movi_tl(cpu_ov, 0);
4699 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4700 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4701 tcg_gen_mul_i64(t0, t0, t1);
4702 tcg_gen_trunc_i64_tl(t2, t0);
4703 gen_store_spr(SPR_MQ, t2);
4704 tcg_gen_shri_i64(t1, t0, 32);
4705 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4706 tcg_gen_ext32s_i64(t1, t0);
4707 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4708 tcg_gen_movi_tl(cpu_ov, 1);
4709 tcg_gen_movi_tl(cpu_so, 1);
4710 gen_set_label(l1);
4711 tcg_temp_free_i64(t0);
4712 tcg_temp_free_i64(t1);
4713 tcg_temp_free(t2);
4714 if (unlikely(Rc(ctx->opcode) != 0))
4715 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4716 }
4717
4718 /* nabs - nabs. */
4719 static void gen_nabs(DisasContext *ctx)
4720 {
4721 TCGLabel *l1 = gen_new_label();
4722 TCGLabel *l2 = gen_new_label();
4723 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4724 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4725 tcg_gen_br(l2);
4726 gen_set_label(l1);
4727 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4728 gen_set_label(l2);
4729 if (unlikely(Rc(ctx->opcode) != 0))
4730 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4731 }
4732
4733 /* nabso - nabso. */
4734 static void gen_nabso(DisasContext *ctx)
4735 {
4736 TCGLabel *l1 = gen_new_label();
4737 TCGLabel *l2 = gen_new_label();
4738 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4739 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4740 tcg_gen_br(l2);
4741 gen_set_label(l1);
4742 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4743 gen_set_label(l2);
4744 /* nabs never overflows */
4745 tcg_gen_movi_tl(cpu_ov, 0);
4746 if (unlikely(Rc(ctx->opcode) != 0))
4747 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4748 }
4749
4750 /* rlmi - rlmi. */
4751 static void gen_rlmi(DisasContext *ctx)
4752 {
4753 uint32_t mb = MB(ctx->opcode);
4754 uint32_t me = ME(ctx->opcode);
4755 TCGv t0 = tcg_temp_new();
4756 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4757 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4758 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4759 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4760 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4761 tcg_temp_free(t0);
4762 if (unlikely(Rc(ctx->opcode) != 0))
4763 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4764 }
4765
4766 /* rrib - rrib. */
4767 static void gen_rrib(DisasContext *ctx)
4768 {
4769 TCGv t0 = tcg_temp_new();
4770 TCGv t1 = tcg_temp_new();
4771 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4772 tcg_gen_movi_tl(t1, 0x80000000);
4773 tcg_gen_shr_tl(t1, t1, t0);
4774 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4775 tcg_gen_and_tl(t0, t0, t1);
4776 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4777 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4778 tcg_temp_free(t0);
4779 tcg_temp_free(t1);
4780 if (unlikely(Rc(ctx->opcode) != 0))
4781 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4782 }
4783
4784 /* sle - sle. */
4785 static void gen_sle(DisasContext *ctx)
4786 {
4787 TCGv t0 = tcg_temp_new();
4788 TCGv t1 = tcg_temp_new();
4789 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4790 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4791 tcg_gen_subfi_tl(t1, 32, t1);
4792 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4793 tcg_gen_or_tl(t1, t0, t1);
4794 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4795 gen_store_spr(SPR_MQ, t1);
4796 tcg_temp_free(t0);
4797 tcg_temp_free(t1);
4798 if (unlikely(Rc(ctx->opcode) != 0))
4799 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4800 }
4801
4802 /* sleq - sleq. */
4803 static void gen_sleq(DisasContext *ctx)
4804 {
4805 TCGv t0 = tcg_temp_new();
4806 TCGv t1 = tcg_temp_new();
4807 TCGv t2 = tcg_temp_new();
4808 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4809 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4810 tcg_gen_shl_tl(t2, t2, t0);
4811 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4812 gen_load_spr(t1, SPR_MQ);
4813 gen_store_spr(SPR_MQ, t0);
4814 tcg_gen_and_tl(t0, t0, t2);
4815 tcg_gen_andc_tl(t1, t1, t2);
4816 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4817 tcg_temp_free(t0);
4818 tcg_temp_free(t1);
4819 tcg_temp_free(t2);
4820 if (unlikely(Rc(ctx->opcode) != 0))
4821 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4822 }
4823
4824 /* sliq - sliq. */
4825 static void gen_sliq(DisasContext *ctx)
4826 {
4827 int sh = SH(ctx->opcode);
4828 TCGv t0 = tcg_temp_new();
4829 TCGv t1 = tcg_temp_new();
4830 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4831 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4832 tcg_gen_or_tl(t1, t0, t1);
4833 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4834 gen_store_spr(SPR_MQ, t1);
4835 tcg_temp_free(t0);
4836 tcg_temp_free(t1);
4837 if (unlikely(Rc(ctx->opcode) != 0))
4838 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4839 }
4840
4841 /* slliq - slliq. */
4842 static void gen_slliq(DisasContext *ctx)
4843 {
4844 int sh = SH(ctx->opcode);
4845 TCGv t0 = tcg_temp_new();
4846 TCGv t1 = tcg_temp_new();
4847 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4848 gen_load_spr(t1, SPR_MQ);
4849 gen_store_spr(SPR_MQ, t0);
4850 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4851 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4852 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4853 tcg_temp_free(t0);
4854 tcg_temp_free(t1);
4855 if (unlikely(Rc(ctx->opcode) != 0))
4856 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4857 }
4858
4859 /* sllq - sllq. */
4860 static void gen_sllq(DisasContext *ctx)
4861 {
4862 TCGLabel *l1 = gen_new_label();
4863 TCGLabel *l2 = gen_new_label();
4864 TCGv t0 = tcg_temp_local_new();
4865 TCGv t1 = tcg_temp_local_new();
4866 TCGv t2 = tcg_temp_local_new();
4867 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4868 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4869 tcg_gen_shl_tl(t1, t1, t2);
4870 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4871 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4872 gen_load_spr(t0, SPR_MQ);
4873 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4874 tcg_gen_br(l2);
4875 gen_set_label(l1);
4876 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4877 gen_load_spr(t2, SPR_MQ);
4878 tcg_gen_andc_tl(t1, t2, t1);
4879 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4880 gen_set_label(l2);
4881 tcg_temp_free(t0);
4882 tcg_temp_free(t1);
4883 tcg_temp_free(t2);
4884 if (unlikely(Rc(ctx->opcode) != 0))
4885 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4886 }
4887
4888 /* slq - slq. */
4889 static void gen_slq(DisasContext *ctx)
4890 {
4891 TCGLabel *l1 = gen_new_label();
4892 TCGv t0 = tcg_temp_new();
4893 TCGv t1 = tcg_temp_new();
4894 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4895 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4896 tcg_gen_subfi_tl(t1, 32, t1);
4897 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4898 tcg_gen_or_tl(t1, t0, t1);
4899 gen_store_spr(SPR_MQ, t1);
4900 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4901 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4902 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4903 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4904 gen_set_label(l1);
4905 tcg_temp_free(t0);
4906 tcg_temp_free(t1);
4907 if (unlikely(Rc(ctx->opcode) != 0))
4908 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4909 }
4910
4911 /* sraiq - sraiq. */
4912 static void gen_sraiq(DisasContext *ctx)
4913 {
4914 int sh = SH(ctx->opcode);
4915 TCGLabel *l1 = gen_new_label();
4916 TCGv t0 = tcg_temp_new();
4917 TCGv t1 = tcg_temp_new();
4918 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4919 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4920 tcg_gen_or_tl(t0, t0, t1);
4921 gen_store_spr(SPR_MQ, t0);
4922 tcg_gen_movi_tl(cpu_ca, 0);
4923 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4924 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4925 tcg_gen_movi_tl(cpu_ca, 1);
4926 gen_set_label(l1);
4927 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4928 tcg_temp_free(t0);
4929 tcg_temp_free(t1);
4930 if (unlikely(Rc(ctx->opcode) != 0))
4931 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4932 }
4933
4934 /* sraq - sraq. */
4935 static void gen_sraq(DisasContext *ctx)
4936 {
4937 TCGLabel *l1 = gen_new_label();
4938 TCGLabel *l2 = gen_new_label();
4939 TCGv t0 = tcg_temp_new();
4940 TCGv t1 = tcg_temp_local_new();
4941 TCGv t2 = tcg_temp_local_new();
4942 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4943 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4944 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4945 tcg_gen_subfi_tl(t2, 32, t2);
4946 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4947 tcg_gen_or_tl(t0, t0, t2);
4948 gen_store_spr(SPR_MQ, t0);
4949 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4950 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4951 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4952 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4953 gen_set_label(l1);
4954 tcg_temp_free(t0);
4955 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4956 tcg_gen_movi_tl(cpu_ca, 0);
4957 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4958 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4959 tcg_gen_movi_tl(cpu_ca, 1);
4960 gen_set_label(l2);
4961 tcg_temp_free(t1);
4962 tcg_temp_free(t2);
4963 if (unlikely(Rc(ctx->opcode) != 0))
4964 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4965 }
4966
4967 /* sre - sre. */
4968 static void gen_sre(DisasContext *ctx)
4969 {
4970 TCGv t0 = tcg_temp_new();
4971 TCGv t1 = tcg_temp_new();
4972 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4973 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4974 tcg_gen_subfi_tl(t1, 32, t1);
4975 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4976 tcg_gen_or_tl(t1, t0, t1);
4977 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4978 gen_store_spr(SPR_MQ, t1);
4979 tcg_temp_free(t0);
4980 tcg_temp_free(t1);
4981 if (unlikely(Rc(ctx->opcode) != 0))
4982 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4983 }
4984
4985 /* srea - srea. */
4986 static void gen_srea(DisasContext *ctx)
4987 {
4988 TCGv t0 = tcg_temp_new();
4989 TCGv t1 = tcg_temp_new();
4990 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4991 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4992 gen_store_spr(SPR_MQ, t0);
4993 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4994 tcg_temp_free(t0);
4995 tcg_temp_free(t1);
4996 if (unlikely(Rc(ctx->opcode) != 0))
4997 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4998 }
4999
5000 /* sreq */
5001 static void gen_sreq(DisasContext *ctx)
5002 {
5003 TCGv t0 = tcg_temp_new();
5004 TCGv t1 = tcg_temp_new();
5005 TCGv t2 = tcg_temp_new();
5006 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5007 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5008 tcg_gen_shr_tl(t1, t1, t0);
5009 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5010 gen_load_spr(t2, SPR_MQ);
5011 gen_store_spr(SPR_MQ, t0);
5012 tcg_gen_and_tl(t0, t0, t1);
5013 tcg_gen_andc_tl(t2, t2, t1);
5014 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5015 tcg_temp_free(t0);
5016 tcg_temp_free(t1);
5017 tcg_temp_free(t2);
5018 if (unlikely(Rc(ctx->opcode) != 0))
5019 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5020 }
5021
5022 /* sriq */
5023 static void gen_sriq(DisasContext *ctx)
5024 {
5025 int sh = SH(ctx->opcode);
5026 TCGv t0 = tcg_temp_new();
5027 TCGv t1 = tcg_temp_new();
5028 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5029 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5030 tcg_gen_or_tl(t1, t0, t1);
5031 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5032 gen_store_spr(SPR_MQ, t1);
5033 tcg_temp_free(t0);
5034 tcg_temp_free(t1);
5035 if (unlikely(Rc(ctx->opcode) != 0))
5036 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5037 }
5038
5039 /* srliq */
5040 static void gen_srliq(DisasContext *ctx)
5041 {
5042 int sh = SH(ctx->opcode);
5043 TCGv t0 = tcg_temp_new();
5044 TCGv t1 = tcg_temp_new();
5045 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5046 gen_load_spr(t1, SPR_MQ);
5047 gen_store_spr(SPR_MQ, t0);
5048 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5049 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5050 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5051 tcg_temp_free(t0);
5052 tcg_temp_free(t1);
5053 if (unlikely(Rc(ctx->opcode) != 0))
5054 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5055 }
5056
5057 /* srlq */
5058 static void gen_srlq(DisasContext *ctx)
5059 {
5060 TCGLabel *l1 = gen_new_label();
5061 TCGLabel *l2 = gen_new_label();
5062 TCGv t0 = tcg_temp_local_new();
5063 TCGv t1 = tcg_temp_local_new();
5064 TCGv t2 = tcg_temp_local_new();
5065 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5066 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5067 tcg_gen_shr_tl(t2, t1, t2);
5068 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5069 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5070 gen_load_spr(t0, SPR_MQ);
5071 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5072 tcg_gen_br(l2);
5073 gen_set_label(l1);
5074 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5075 tcg_gen_and_tl(t0, t0, t2);
5076 gen_load_spr(t1, SPR_MQ);
5077 tcg_gen_andc_tl(t1, t1, t2);
5078 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5079 gen_set_label(l2);
5080 tcg_temp_free(t0);
5081 tcg_temp_free(t1);
5082 tcg_temp_free(t2);
5083 if (unlikely(Rc(ctx->opcode) != 0))
5084 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5085 }
5086
5087 /* srq */
5088 static void gen_srq(DisasContext *ctx)
5089 {
5090 TCGLabel *l1 = gen_new_label();
5091 TCGv t0 = tcg_temp_new();
5092 TCGv t1 = tcg_temp_new();
5093 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5094 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5095 tcg_gen_subfi_tl(t1, 32, t1);
5096 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5097 tcg_gen_or_tl(t1, t0, t1);
5098 gen_store_spr(SPR_MQ, t1);
5099 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5100 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5101 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5102 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5103 gen_set_label(l1);
5104 tcg_temp_free(t0);
5105 tcg_temp_free(t1);
5106 if (unlikely(Rc(ctx->opcode) != 0))
5107 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5108 }
5109
5110 /* PowerPC 602 specific instructions */
5111
5112 /* dsa */
5113 static void gen_dsa(DisasContext *ctx)
5114 {
5115 /* XXX: TODO */
5116 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5117 }
5118
5119 /* esa */
5120 static void gen_esa(DisasContext *ctx)
5121 {
5122 /* XXX: TODO */
5123 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5124 }
5125
5126 /* mfrom */
5127 static void gen_mfrom(DisasContext *ctx)
5128 {
5129 #if defined(CONFIG_USER_ONLY)
5130 GEN_PRIV;
5131 #else
5132 CHK_SV;
5133 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5134 #endif /* defined(CONFIG_USER_ONLY) */
5135 }
5136
5137 /* 602 - 603 - G2 TLB management */
5138
5139 /* tlbld */
5140 static void gen_tlbld_6xx(DisasContext *ctx)
5141 {
5142 #if defined(CONFIG_USER_ONLY)
5143 GEN_PRIV;
5144 #else
5145 CHK_SV;
5146 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5147 #endif /* defined(CONFIG_USER_ONLY) */
5148 }
5149
5150 /* tlbli */
5151 static void gen_tlbli_6xx(DisasContext *ctx)
5152 {
5153 #if defined(CONFIG_USER_ONLY)
5154 GEN_PRIV;
5155 #else
5156 CHK_SV;
5157 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5158 #endif /* defined(CONFIG_USER_ONLY) */
5159 }
5160
5161 /* 74xx TLB management */
5162
5163 /* tlbld */
5164 static void gen_tlbld_74xx(DisasContext *ctx)
5165 {
5166 #if defined(CONFIG_USER_ONLY)
5167 GEN_PRIV;
5168 #else
5169 CHK_SV;
5170 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5171 #endif /* defined(CONFIG_USER_ONLY) */
5172 }
5173
5174 /* tlbli */
5175 static void gen_tlbli_74xx(DisasContext *ctx)
5176 {
5177 #if defined(CONFIG_USER_ONLY)
5178 GEN_PRIV;
5179 #else
5180 CHK_SV;
5181 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5182 #endif /* defined(CONFIG_USER_ONLY) */
5183 }
5184
5185 /* POWER instructions not in PowerPC 601 */
5186
5187 /* clf */
5188 static void gen_clf(DisasContext *ctx)
5189 {
5190 /* Cache line flush: implemented as no-op */
5191 }
5192
5193 /* cli */
5194 static void gen_cli(DisasContext *ctx)
5195 {
5196 #if defined(CONFIG_USER_ONLY)
5197 GEN_PRIV;
5198 #else
5199 /* Cache line invalidate: privileged and treated as no-op */
5200 CHK_SV;
5201 #endif /* defined(CONFIG_USER_ONLY) */
5202 }
5203
5204 /* dclst */
5205 static void gen_dclst(DisasContext *ctx)
5206 {
5207 /* Data cache line store: treated as no-op */
5208 }
5209
5210 static void gen_mfsri(DisasContext *ctx)
5211 {
5212 #if defined(CONFIG_USER_ONLY)
5213 GEN_PRIV;
5214 #else
5215 int ra = rA(ctx->opcode);
5216 int rd = rD(ctx->opcode);
5217 TCGv t0;
5218
5219 CHK_SV;
5220 t0 = tcg_temp_new();
5221 gen_addr_reg_index(ctx, t0);
5222 tcg_gen_shri_tl(t0, t0, 28);
5223 tcg_gen_andi_tl(t0, t0, 0xF);
5224 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5225 tcg_temp_free(t0);
5226 if (ra != 0 && ra != rd)
5227 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5228 #endif /* defined(CONFIG_USER_ONLY) */
5229 }
5230
5231 static void gen_rac(DisasContext *ctx)
5232 {
5233 #if defined(CONFIG_USER_ONLY)
5234 GEN_PRIV;
5235 #else
5236 TCGv t0;
5237
5238 CHK_SV;
5239 t0 = tcg_temp_new();
5240 gen_addr_reg_index(ctx, t0);
5241 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5242 tcg_temp_free(t0);
5243 #endif /* defined(CONFIG_USER_ONLY) */
5244 }
5245
5246 static void gen_rfsvc(DisasContext *ctx)
5247 {
5248 #if defined(CONFIG_USER_ONLY)
5249 GEN_PRIV;
5250 #else
5251 CHK_SV;
5252
5253 gen_helper_rfsvc(cpu_env);
5254 gen_sync_exception(ctx);
5255 #endif /* defined(CONFIG_USER_ONLY) */
5256 }
5257
5258 #include "translate/fp-impl.c"
5259
5260 #include "translate/vmx-impl.c"
5261
5262 #include "translate/vsx-impl.c"
5263
5264 /* svc is not implemented for now */
5265
5266 /* BookE specific instructions */
5267
5268 /* XXX: not implemented on 440 ? */
5269 static void gen_mfapidi(DisasContext *ctx)
5270 {
5271 /* XXX: TODO */
5272 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5273 }
5274
5275 /* XXX: not implemented on 440 ? */
5276 static void gen_tlbiva(DisasContext *ctx)
5277 {
5278 #if defined(CONFIG_USER_ONLY)
5279 GEN_PRIV;
5280 #else
5281 TCGv t0;
5282
5283 CHK_SV;
5284 t0 = tcg_temp_new();
5285 gen_addr_reg_index(ctx, t0);
5286 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5287 tcg_temp_free(t0);
5288 #endif /* defined(CONFIG_USER_ONLY) */
5289 }
5290
5291 /* All 405 MAC instructions are translated here */
5292 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5293 int ra, int rb, int rt, int Rc)
5294 {
5295 TCGv t0, t1;
5296
5297 t0 = tcg_temp_local_new();
5298 t1 = tcg_temp_local_new();
5299
5300 switch (opc3 & 0x0D) {
5301 case 0x05:
5302 /* macchw - macchw. - macchwo - macchwo. */
5303 /* macchws - macchws. - macchwso - macchwso. */
5304 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5305 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5306 /* mulchw - mulchw. */
5307 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5308 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5309 tcg_gen_ext16s_tl(t1, t1);
5310 break;
5311 case 0x04:
5312 /* macchwu - macchwu. - macchwuo - macchwuo. */
5313 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5314 /* mulchwu - mulchwu. */
5315 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5316 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5317 tcg_gen_ext16u_tl(t1, t1);
5318 break;
5319 case 0x01:
5320 /* machhw - machhw. - machhwo - machhwo. */
5321 /* machhws - machhws. - machhwso - machhwso. */
5322 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5323 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5324 /* mulhhw - mulhhw. */
5325 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5326 tcg_gen_ext16s_tl(t0, t0);
5327 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5328 tcg_gen_ext16s_tl(t1, t1);
5329 break;
5330 case 0x00:
5331 /* machhwu - machhwu. - machhwuo - machhwuo. */
5332 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5333 /* mulhhwu - mulhhwu. */
5334 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5335 tcg_gen_ext16u_tl(t0, t0);
5336 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5337 tcg_gen_ext16u_tl(t1, t1);
5338 break;
5339 case 0x0D:
5340 /* maclhw - maclhw. - maclhwo - maclhwo. */
5341 /* maclhws - maclhws. - maclhwso - maclhwso. */
5342 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5343 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5344 /* mullhw - mullhw. */
5345 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5346 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5347 break;
5348 case 0x0C:
5349 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5350 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5351 /* mullhwu - mullhwu. */
5352 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5353 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5354 break;
5355 }
5356 if (opc2 & 0x04) {
5357 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5358 tcg_gen_mul_tl(t1, t0, t1);
5359 if (opc2 & 0x02) {
5360 /* nmultiply-and-accumulate (0x0E) */
5361 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5362 } else {
5363 /* multiply-and-accumulate (0x0C) */
5364 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5365 }
5366
5367 if (opc3 & 0x12) {
5368 /* Check overflow and/or saturate */
5369 TCGLabel *l1 = gen_new_label();
5370
5371 if (opc3 & 0x10) {
5372 /* Start with XER OV disabled, the most likely case */
5373 tcg_gen_movi_tl(cpu_ov, 0);
5374 }
5375 if (opc3 & 0x01) {
5376 /* Signed */
5377 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5378 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5379 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5380 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5381 if (opc3 & 0x02) {
5382 /* Saturate */
5383 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5384 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5385 }
5386 } else {
5387 /* Unsigned */
5388 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5389 if (opc3 & 0x02) {
5390 /* Saturate */
5391 tcg_gen_movi_tl(t0, UINT32_MAX);
5392 }
5393 }
5394 if (opc3 & 0x10) {
5395 /* Check overflow */
5396 tcg_gen_movi_tl(cpu_ov, 1);
5397 tcg_gen_movi_tl(cpu_so, 1);
5398 }
5399 gen_set_label(l1);
5400 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5401 }
5402 } else {
5403 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5404 }
5405 tcg_temp_free(t0);
5406 tcg_temp_free(t1);
5407 if (unlikely(Rc) != 0) {
5408 /* Update Rc0 */
5409 gen_set_Rc0(ctx, cpu_gpr[rt]);
5410 }
5411 }
5412
5413 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5414 static void glue(gen_, name)(DisasContext *ctx) \
5415 { \
5416 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5417 rD(ctx->opcode), Rc(ctx->opcode)); \
5418 }
5419
5420 /* macchw - macchw. */
5421 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5422 /* macchwo - macchwo. */
5423 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5424 /* macchws - macchws. */
5425 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5426 /* macchwso - macchwso. */
5427 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5428 /* macchwsu - macchwsu. */
5429 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5430 /* macchwsuo - macchwsuo. */
5431 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5432 /* macchwu - macchwu. */
5433 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5434 /* macchwuo - macchwuo. */
5435 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5436 /* machhw - machhw. */
5437 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5438 /* machhwo - machhwo. */
5439 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5440 /* machhws - machhws. */
5441 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5442 /* machhwso - machhwso. */
5443 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5444 /* machhwsu - machhwsu. */
5445 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5446 /* machhwsuo - machhwsuo. */
5447 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5448 /* machhwu - machhwu. */
5449 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5450 /* machhwuo - machhwuo. */
5451 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5452 /* maclhw - maclhw. */
5453 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5454 /* maclhwo - maclhwo. */
5455 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5456 /* maclhws - maclhws. */
5457 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5458 /* maclhwso - maclhwso. */
5459 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5460 /* maclhwu - maclhwu. */
5461 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5462 /* maclhwuo - maclhwuo. */
5463 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5464 /* maclhwsu - maclhwsu. */
5465 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5466 /* maclhwsuo - maclhwsuo. */
5467 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5468 /* nmacchw - nmacchw. */
5469 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5470 /* nmacchwo - nmacchwo. */
5471 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5472 /* nmacchws - nmacchws. */
5473 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5474 /* nmacchwso - nmacchwso. */
5475 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5476 /* nmachhw - nmachhw. */
5477 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5478 /* nmachhwo - nmachhwo. */
5479 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5480 /* nmachhws - nmachhws. */
5481 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5482 /* nmachhwso - nmachhwso. */
5483 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5484 /* nmaclhw - nmaclhw. */
5485 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5486 /* nmaclhwo - nmaclhwo. */
5487 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5488 /* nmaclhws - nmaclhws. */
5489 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5490 /* nmaclhwso - nmaclhwso. */
5491 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5492
5493 /* mulchw - mulchw. */
5494 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5495 /* mulchwu - mulchwu. */
5496 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5497 /* mulhhw - mulhhw. */
5498 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5499 /* mulhhwu - mulhhwu. */
5500 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5501 /* mullhw - mullhw. */
5502 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5503 /* mullhwu - mullhwu. */
5504 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5505
5506 /* mfdcr */
5507 static void gen_mfdcr(DisasContext *ctx)
5508 {
5509 #if defined(CONFIG_USER_ONLY)
5510 GEN_PRIV;
5511 #else
5512 TCGv dcrn;
5513
5514 CHK_SV;
5515 dcrn = tcg_const_tl(SPR(ctx->opcode));
5516 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5517 tcg_temp_free(dcrn);
5518 #endif /* defined(CONFIG_USER_ONLY) */
5519 }
5520
5521 /* mtdcr */
5522 static void gen_mtdcr(DisasContext *ctx)
5523 {
5524 #if defined(CONFIG_USER_ONLY)
5525 GEN_PRIV;
5526 #else
5527 TCGv dcrn;
5528
5529 CHK_SV;
5530 dcrn = tcg_const_tl(SPR(ctx->opcode));
5531 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5532 tcg_temp_free(dcrn);
5533 #endif /* defined(CONFIG_USER_ONLY) */
5534 }
5535
5536 /* mfdcrx */
5537 /* XXX: not implemented on 440 ? */
5538 static void gen_mfdcrx(DisasContext *ctx)
5539 {
5540 #if defined(CONFIG_USER_ONLY)
5541 GEN_PRIV;
5542 #else
5543 CHK_SV;
5544 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5545 cpu_gpr[rA(ctx->opcode)]);
5546 /* Note: Rc update flag set leads to undefined state of Rc0 */
5547 #endif /* defined(CONFIG_USER_ONLY) */
5548 }
5549
5550 /* mtdcrx */
5551 /* XXX: not implemented on 440 ? */
5552 static void gen_mtdcrx(DisasContext *ctx)
5553 {
5554 #if defined(CONFIG_USER_ONLY)
5555 GEN_PRIV;
5556 #else
5557 CHK_SV;
5558 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5559 cpu_gpr[rS(ctx->opcode)]);
5560 /* Note: Rc update flag set leads to undefined state of Rc0 */
5561 #endif /* defined(CONFIG_USER_ONLY) */
5562 }
5563
5564 /* mfdcrux (PPC 460) : user-mode access to DCR */
5565 static void gen_mfdcrux(DisasContext *ctx)
5566 {
5567 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5568 cpu_gpr[rA(ctx->opcode)]);
5569 /* Note: Rc update flag set leads to undefined state of Rc0 */
5570 }
5571
5572 /* mtdcrux (PPC 460) : user-mode access to DCR */
5573 static void gen_mtdcrux(DisasContext *ctx)
5574 {
5575 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5576 cpu_gpr[rS(ctx->opcode)]);
5577 /* Note: Rc update flag set leads to undefined state of Rc0 */
5578 }
5579
5580 /* dccci */
5581 static void gen_dccci(DisasContext *ctx)
5582 {
5583 CHK_SV;
5584 /* interpreted as no-op */
5585 }
5586
5587 /* dcread */
5588 static void gen_dcread(DisasContext *ctx)
5589 {
5590 #if defined(CONFIG_USER_ONLY)
5591 GEN_PRIV;
5592 #else
5593 TCGv EA, val;
5594
5595 CHK_SV;
5596 gen_set_access_type(ctx, ACCESS_CACHE);
5597 EA = tcg_temp_new();
5598 gen_addr_reg_index(ctx, EA);
5599 val = tcg_temp_new();
5600 gen_qemu_ld32u(ctx, val, EA);
5601 tcg_temp_free(val);
5602 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5603 tcg_temp_free(EA);
5604 #endif /* defined(CONFIG_USER_ONLY) */
5605 }
5606
5607 /* icbt */
5608 static void gen_icbt_40x(DisasContext *ctx)
5609 {
5610 /* interpreted as no-op */
5611 /* XXX: specification say this is treated as a load by the MMU
5612 * but does not generate any exception
5613 */
5614 }
5615
5616 /* iccci */
5617 static void gen_iccci(DisasContext *ctx)
5618 {
5619 CHK_SV;
5620 /* interpreted as no-op */
5621 }
5622
5623 /* icread */
5624 static void gen_icread(DisasContext *ctx)
5625 {
5626 CHK_SV;
5627 /* interpreted as no-op */
5628 }
5629
5630 /* rfci (supervisor only) */
5631 static void gen_rfci_40x(DisasContext *ctx)
5632 {
5633 #if defined(CONFIG_USER_ONLY)
5634 GEN_PRIV;
5635 #else
5636 CHK_SV;
5637 /* Restore CPU state */
5638 gen_helper_40x_rfci(cpu_env);
5639 gen_sync_exception(ctx);
5640 #endif /* defined(CONFIG_USER_ONLY) */
5641 }
5642
5643 static void gen_rfci(DisasContext *ctx)
5644 {
5645 #if defined(CONFIG_USER_ONLY)
5646 GEN_PRIV;
5647 #else
5648 CHK_SV;
5649 /* Restore CPU state */
5650 gen_helper_rfci(cpu_env);
5651 gen_sync_exception(ctx);
5652 #endif /* defined(CONFIG_USER_ONLY) */
5653 }
5654
5655 /* BookE specific */
5656
5657 /* XXX: not implemented on 440 ? */
5658 static void gen_rfdi(DisasContext *ctx)
5659 {
5660 #if defined(CONFIG_USER_ONLY)
5661 GEN_PRIV;
5662 #else
5663 CHK_SV;
5664 /* Restore CPU state */
5665 gen_helper_rfdi(cpu_env);
5666 gen_sync_exception(ctx);
5667 #endif /* defined(CONFIG_USER_ONLY) */
5668 }
5669
5670 /* XXX: not implemented on 440 ? */
5671 static void gen_rfmci(DisasContext *ctx)
5672 {
5673 #if defined(CONFIG_USER_ONLY)
5674 GEN_PRIV;
5675 #else
5676 CHK_SV;
5677 /* Restore CPU state */
5678 gen_helper_rfmci(cpu_env);
5679 gen_sync_exception(ctx);
5680 #endif /* defined(CONFIG_USER_ONLY) */
5681 }
5682
5683 /* TLB management - PowerPC 405 implementation */
5684
5685 /* tlbre */
5686 static void gen_tlbre_40x(DisasContext *ctx)
5687 {
5688 #if defined(CONFIG_USER_ONLY)
5689 GEN_PRIV;
5690 #else
5691 CHK_SV;
5692 switch (rB(ctx->opcode)) {
5693 case 0:
5694 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5695 cpu_gpr[rA(ctx->opcode)]);
5696 break;
5697 case 1:
5698 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5699 cpu_gpr[rA(ctx->opcode)]);
5700 break;
5701 default:
5702 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5703 break;
5704 }
5705 #endif /* defined(CONFIG_USER_ONLY) */
5706 }
5707
5708 /* tlbsx - tlbsx. */
5709 static void gen_tlbsx_40x(DisasContext *ctx)
5710 {
5711 #if defined(CONFIG_USER_ONLY)
5712 GEN_PRIV;
5713 #else
5714 TCGv t0;
5715
5716 CHK_SV;
5717 t0 = tcg_temp_new();
5718 gen_addr_reg_index(ctx, t0);
5719 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5720 tcg_temp_free(t0);
5721 if (Rc(ctx->opcode)) {
5722 TCGLabel *l1 = gen_new_label();
5723 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5724 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5725 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5726 gen_set_label(l1);
5727 }
5728 #endif /* defined(CONFIG_USER_ONLY) */
5729 }
5730
5731 /* tlbwe */
5732 static void gen_tlbwe_40x(DisasContext *ctx)
5733 {
5734 #if defined(CONFIG_USER_ONLY)
5735 GEN_PRIV;
5736 #else
5737 CHK_SV;
5738
5739 switch (rB(ctx->opcode)) {
5740 case 0:
5741 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5742 cpu_gpr[rS(ctx->opcode)]);
5743 break;
5744 case 1:
5745 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5746 cpu_gpr[rS(ctx->opcode)]);
5747 break;
5748 default:
5749 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5750 break;
5751 }
5752 #endif /* defined(CONFIG_USER_ONLY) */
5753 }
5754
5755 /* TLB management - PowerPC 440 implementation */
5756
5757 /* tlbre */
5758 static void gen_tlbre_440(DisasContext *ctx)
5759 {
5760 #if defined(CONFIG_USER_ONLY)
5761 GEN_PRIV;
5762 #else
5763 CHK_SV;
5764
5765 switch (rB(ctx->opcode)) {
5766 case 0:
5767 case 1:
5768 case 2:
5769 {
5770 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5771 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5772 t0, cpu_gpr[rA(ctx->opcode)]);
5773 tcg_temp_free_i32(t0);
5774 }
5775 break;
5776 default:
5777 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5778 break;
5779 }
5780 #endif /* defined(CONFIG_USER_ONLY) */
5781 }
5782
5783 /* tlbsx - tlbsx. */
5784 static void gen_tlbsx_440(DisasContext *ctx)
5785 {
5786 #if defined(CONFIG_USER_ONLY)
5787 GEN_PRIV;
5788 #else
5789 TCGv t0;
5790
5791 CHK_SV;
5792 t0 = tcg_temp_new();
5793 gen_addr_reg_index(ctx, t0);
5794 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5795 tcg_temp_free(t0);
5796 if (Rc(ctx->opcode)) {
5797 TCGLabel *l1 = gen_new_label();
5798 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5799 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5800 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5801 gen_set_label(l1);
5802 }
5803 #endif /* defined(CONFIG_USER_ONLY) */
5804 }
5805
5806 /* tlbwe */
5807 static void gen_tlbwe_440(DisasContext *ctx)
5808 {
5809 #if defined(CONFIG_USER_ONLY)
5810 GEN_PRIV;
5811 #else
5812 CHK_SV;
5813 switch (rB(ctx->opcode)) {
5814 case 0:
5815 case 1:
5816 case 2:
5817 {
5818 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5819 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5820 cpu_gpr[rS(ctx->opcode)]);
5821 tcg_temp_free_i32(t0);
5822 }
5823 break;
5824 default:
5825 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5826 break;
5827 }
5828 #endif /* defined(CONFIG_USER_ONLY) */
5829 }
5830
5831 /* TLB management - PowerPC BookE 2.06 implementation */
5832
5833 /* tlbre */
5834 static void gen_tlbre_booke206(DisasContext *ctx)
5835 {
5836 #if defined(CONFIG_USER_ONLY)
5837 GEN_PRIV;
5838 #else
5839 CHK_SV;
5840 gen_helper_booke206_tlbre(cpu_env);
5841 #endif /* defined(CONFIG_USER_ONLY) */
5842 }
5843
5844 /* tlbsx - tlbsx. */
5845 static void gen_tlbsx_booke206(DisasContext *ctx)
5846 {
5847 #if defined(CONFIG_USER_ONLY)
5848 GEN_PRIV;
5849 #else
5850 TCGv t0;
5851
5852 CHK_SV;
5853 if (rA(ctx->opcode)) {
5854 t0 = tcg_temp_new();
5855 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
5856 } else {
5857 t0 = tcg_const_tl(0);
5858 }
5859
5860 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
5861 gen_helper_booke206_tlbsx(cpu_env, t0);
5862 tcg_temp_free(t0);
5863 #endif /* defined(CONFIG_USER_ONLY) */
5864 }
5865
5866 /* tlbwe */
5867 static void gen_tlbwe_booke206(DisasContext *ctx)
5868 {
5869 #if defined(CONFIG_USER_ONLY)
5870 GEN_PRIV;
5871 #else
5872 CHK_SV;
5873 gen_helper_booke206_tlbwe(cpu_env);
5874 #endif /* defined(CONFIG_USER_ONLY) */
5875 }
5876
5877 static void gen_tlbivax_booke206(DisasContext *ctx)
5878 {
5879 #if defined(CONFIG_USER_ONLY)
5880 GEN_PRIV;
5881 #else
5882 TCGv t0;
5883
5884 CHK_SV;
5885 t0 = tcg_temp_new();
5886 gen_addr_reg_index(ctx, t0);
5887 gen_helper_booke206_tlbivax(cpu_env, t0);
5888 tcg_temp_free(t0);
5889 #endif /* defined(CONFIG_USER_ONLY) */
5890 }
5891
5892 static void gen_tlbilx_booke206(DisasContext *ctx)
5893 {
5894 #if defined(CONFIG_USER_ONLY)
5895 GEN_PRIV;
5896 #else
5897 TCGv t0;
5898
5899 CHK_SV;
5900 t0 = tcg_temp_new();
5901 gen_addr_reg_index(ctx, t0);
5902
5903 switch((ctx->opcode >> 21) & 0x3) {
5904 case 0:
5905 gen_helper_booke206_tlbilx0(cpu_env, t0);
5906 break;
5907 case 1:
5908 gen_helper_booke206_tlbilx1(cpu_env, t0);
5909 break;
5910 case 3:
5911 gen_helper_booke206_tlbilx3(cpu_env, t0);
5912 break;
5913 default:
5914 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5915 break;
5916 }
5917
5918 tcg_temp_free(t0);
5919 #endif /* defined(CONFIG_USER_ONLY) */
5920 }
5921
5922
5923 /* wrtee */
5924 static void gen_wrtee(DisasContext *ctx)
5925 {
5926 #if defined(CONFIG_USER_ONLY)
5927 GEN_PRIV;
5928 #else
5929 TCGv t0;
5930
5931 CHK_SV;
5932 t0 = tcg_temp_new();
5933 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
5934 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5935 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
5936 tcg_temp_free(t0);
5937 /* Stop translation to have a chance to raise an exception
5938 * if we just set msr_ee to 1
5939 */
5940 gen_stop_exception(ctx);
5941 #endif /* defined(CONFIG_USER_ONLY) */
5942 }
5943
5944 /* wrteei */
5945 static void gen_wrteei(DisasContext *ctx)
5946 {
5947 #if defined(CONFIG_USER_ONLY)
5948 GEN_PRIV;
5949 #else
5950 CHK_SV;
5951 if (ctx->opcode & 0x00008000) {
5952 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
5953 /* Stop translation to have a chance to raise an exception */
5954 gen_stop_exception(ctx);
5955 } else {
5956 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5957 }
5958 #endif /* defined(CONFIG_USER_ONLY) */
5959 }
5960
5961 /* PowerPC 440 specific instructions */
5962
5963 /* dlmzb */
5964 static void gen_dlmzb(DisasContext *ctx)
5965 {
5966 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
5967 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
5968 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
5969 tcg_temp_free_i32(t0);
5970 }
5971
5972 /* mbar replaces eieio on 440 */
5973 static void gen_mbar(DisasContext *ctx)
5974 {
5975 /* interpreted as no-op */
5976 }
5977
5978 /* msync replaces sync on 440 */
5979 static void gen_msync_4xx(DisasContext *ctx)
5980 {
5981 /* interpreted as no-op */
5982 }
5983
5984 /* icbt */
5985 static void gen_icbt_440(DisasContext *ctx)
5986 {
5987 /* interpreted as no-op */
5988 /* XXX: specification say this is treated as a load by the MMU
5989 * but does not generate any exception
5990 */
5991 }
5992
5993 /* Embedded.Processor Control */
5994
5995 static void gen_msgclr(DisasContext *ctx)
5996 {
5997 #if defined(CONFIG_USER_ONLY)
5998 GEN_PRIV;
5999 #else
6000 CHK_SV;
6001 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6002 #endif /* defined(CONFIG_USER_ONLY) */
6003 }
6004
6005 static void gen_msgsnd(DisasContext *ctx)
6006 {
6007 #if defined(CONFIG_USER_ONLY)
6008 GEN_PRIV;
6009 #else
6010 CHK_SV;
6011 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6012 #endif /* defined(CONFIG_USER_ONLY) */
6013 }
6014
6015
6016 #if defined(TARGET_PPC64)
6017 static void gen_maddld(DisasContext *ctx)
6018 {
6019 TCGv_i64 t1 = tcg_temp_new_i64();
6020
6021 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6022 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6023 tcg_temp_free_i64(t1);
6024 }
6025
6026 /* maddhd maddhdu */
6027 static void gen_maddhd_maddhdu(DisasContext *ctx)
6028 {
6029 TCGv_i64 lo = tcg_temp_new_i64();
6030 TCGv_i64 hi = tcg_temp_new_i64();
6031 TCGv_i64 t1 = tcg_temp_new_i64();
6032
6033 if (Rc(ctx->opcode)) {
6034 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6035 cpu_gpr[rB(ctx->opcode)]);
6036 tcg_gen_movi_i64(t1, 0);
6037 } else {
6038 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6039 cpu_gpr[rB(ctx->opcode)]);
6040 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6041 }
6042 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6043 cpu_gpr[rC(ctx->opcode)], t1);
6044 tcg_temp_free_i64(lo);
6045 tcg_temp_free_i64(hi);
6046 tcg_temp_free_i64(t1);
6047 }
6048 #endif /* defined(TARGET_PPC64) */
6049
6050 #include "translate/dfp-impl.c"
6051
6052 #include "translate/spe-impl.c"
6053
6054 static void gen_tbegin(DisasContext *ctx)
6055 {
6056 if (unlikely(!ctx->tm_enabled)) {
6057 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6058 return;
6059 }
6060 gen_helper_tbegin(cpu_env);
6061 }
6062
6063 #define GEN_TM_NOOP(name) \
6064 static inline void gen_##name(DisasContext *ctx) \
6065 { \
6066 if (unlikely(!ctx->tm_enabled)) { \
6067 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6068 return; \
6069 } \
6070 /* Because tbegin always fails in QEMU, these user \
6071 * space instructions all have a simple implementation: \
6072 * \
6073 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6074 * = 0b0 || 0b00 || 0b0 \
6075 */ \
6076 tcg_gen_movi_i32(cpu_crf[0], 0); \
6077 }
6078
6079 GEN_TM_NOOP(tend);
6080 GEN_TM_NOOP(tabort);
6081 GEN_TM_NOOP(tabortwc);
6082 GEN_TM_NOOP(tabortwci);
6083 GEN_TM_NOOP(tabortdc);
6084 GEN_TM_NOOP(tabortdci);
6085 GEN_TM_NOOP(tsr);
6086
6087 static void gen_tcheck(DisasContext *ctx)
6088 {
6089 if (unlikely(!ctx->tm_enabled)) {
6090 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6091 return;
6092 }
6093 /* Because tbegin always fails, the tcheck implementation
6094 * is simple:
6095 *
6096 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6097 * = 0b1 || 0b00 || 0b0
6098 */
6099 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6100 }
6101
6102 #if defined(CONFIG_USER_ONLY)
6103 #define GEN_TM_PRIV_NOOP(name) \
6104 static inline void gen_##name(DisasContext *ctx) \
6105 { \
6106 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6107 }
6108
6109 #else
6110
6111 #define GEN_TM_PRIV_NOOP(name) \
6112 static inline void gen_##name(DisasContext *ctx) \
6113 { \
6114 CHK_SV; \
6115 if (unlikely(!ctx->tm_enabled)) { \
6116 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6117 return; \
6118 } \
6119 /* Because tbegin always fails, the implementation is \
6120 * simple: \
6121 * \
6122 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6123 * = 0b0 || 0b00 | 0b0 \
6124 */ \
6125 tcg_gen_movi_i32(cpu_crf[0], 0); \
6126 }
6127
6128 #endif
6129
6130 GEN_TM_PRIV_NOOP(treclaim);
6131 GEN_TM_PRIV_NOOP(trechkpt);
6132
6133 static opcode_t opcodes[] = {
6134 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6135 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6136 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6137 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
6138 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6139 #if defined(TARGET_PPC64)
6140 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6141 #endif
6142 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6143 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6144 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6145 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6146 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6147 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6148 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6149 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6150 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6151 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6152 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6153 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6154 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6155 #if defined(TARGET_PPC64)
6156 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6157 #endif
6158 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6159 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6160 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6161 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6162 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6163 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6164 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6165 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6166 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6167 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6168 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6169 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6170 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6171 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6172 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6173 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6174 #if defined(TARGET_PPC64)
6175 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6176 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6177 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6178 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6179 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6180 #endif
6181 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6182 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6183 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6184 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6185 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6186 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6187 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6188 #if defined(TARGET_PPC64)
6189 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6190 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6191 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6192 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6193 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6194 #endif
6195 #if defined(TARGET_PPC64)
6196 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6197 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6198 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6199 #endif
6200 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6201 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6202 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6203 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6204 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6205 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6206 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
6207 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6208 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6209 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6210 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6211 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6212 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6213 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6214 #if defined(TARGET_PPC64)
6215 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6216 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6217 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6218 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6219 #endif
6220 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6221 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6222 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6223 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6224 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6225 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6226 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
6227 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6228 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6229 #if defined(TARGET_PPC64)
6230 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6231 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6232 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6233 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6234 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6235 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6236 #endif
6237 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6238 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6239 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6240 #if defined(TARGET_PPC64)
6241 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6242 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6243 #endif
6244 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6245 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6246 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6247 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6248 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6249 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6250 #if defined(TARGET_PPC64)
6251 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6252 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6253 #endif
6254 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6255 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6256 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6257 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6258 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6259 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6260 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6261 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6262 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6263 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6264 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
6265 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6266 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6267 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6268 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6269 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6270 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6271 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6272 #if defined(TARGET_PPC64)
6273 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6274 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6275 PPC_SEGMENT_64B),
6276 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6277 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6278 PPC_SEGMENT_64B),
6279 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6280 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6281 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6282 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6283 #endif
6284 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6285 /* XXX Those instructions will need to be handled differently for
6286 * different ISA versions */
6287 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6288 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6289 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6290 #if defined(TARGET_PPC64)
6291 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6292 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6293 #endif
6294 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6295 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6296 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6297 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6298 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6299 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6300 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6301 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6302 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6303 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6304 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6305 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6306 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6307 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6308 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6309 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6310 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6311 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6312 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6313 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6314 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6315 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6316 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6317 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6318 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6319 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6320 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6321 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6322 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6323 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6324 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6325 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6326 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6327 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6328 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6329 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6330 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6331 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6332 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6333 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6334 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6335 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6336 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6337 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6338 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6339 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6340 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6341 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6342 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6343 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6344 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6345 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6346 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6347 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6348 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6349 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6350 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6351 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6352 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6353 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6354 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6355 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6356 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6357 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6358 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6359 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6360 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6361 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6362 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6363 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6364 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6365 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6366 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6367 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6368 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6369 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6370 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6371 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6372 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6373 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6374 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6375 PPC_NONE, PPC2_BOOKE206),
6376 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6377 PPC_NONE, PPC2_BOOKE206),
6378 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6379 PPC_NONE, PPC2_BOOKE206),
6380 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6381 PPC_NONE, PPC2_BOOKE206),
6382 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6383 PPC_NONE, PPC2_BOOKE206),
6384 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6385 PPC_NONE, PPC2_PRCNTL),
6386 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6387 PPC_NONE, PPC2_PRCNTL),
6388 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6389 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6390 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6391 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6392 PPC_BOOKE, PPC2_BOOKE206),
6393 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6394 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6395 PPC_BOOKE, PPC2_BOOKE206),
6396 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6397 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6398 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6399 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6400 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6401 #if defined(TARGET_PPC64)
6402 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6403 PPC2_ISA300),
6404 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6405 #endif
6406
6407 #undef GEN_INT_ARITH_ADD
6408 #undef GEN_INT_ARITH_ADD_CONST
6409 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6410 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6411 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6412 add_ca, compute_ca, compute_ov) \
6413 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6414 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6415 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6416 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6417 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6418 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6419 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6420 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6421 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6422 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6423 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6424
6425 #undef GEN_INT_ARITH_DIVW
6426 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6427 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6428 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6429 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6430 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6431 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6432 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6433 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6434 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6435 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6436 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6437 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6438
6439 #if defined(TARGET_PPC64)
6440 #undef GEN_INT_ARITH_DIVD
6441 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6442 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6443 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6444 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6445 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6446 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6447
6448 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6449 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6450 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6451 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6452 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6453 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6454
6455 #undef GEN_INT_ARITH_MUL_HELPER
6456 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6457 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6458 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6459 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6460 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6461 #endif
6462
6463 #undef GEN_INT_ARITH_SUBF
6464 #undef GEN_INT_ARITH_SUBF_CONST
6465 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6466 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6467 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6468 add_ca, compute_ca, compute_ov) \
6469 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6470 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6471 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6472 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6473 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6474 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6475 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6476 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6477 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6478 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6479 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6480
6481 #undef GEN_LOGICAL1
6482 #undef GEN_LOGICAL2
6483 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6484 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6485 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6486 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6487 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6488 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6489 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6490 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6491 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6492 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6493 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6494 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6495 #if defined(TARGET_PPC64)
6496 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6497 #endif
6498
6499 #if defined(TARGET_PPC64)
6500 #undef GEN_PPC64_R2
6501 #undef GEN_PPC64_R4
6502 #define GEN_PPC64_R2(name, opc1, opc2) \
6503 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6504 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6505 PPC_64B)
6506 #define GEN_PPC64_R4(name, opc1, opc2) \
6507 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6508 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6509 PPC_64B), \
6510 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6511 PPC_64B), \
6512 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6513 PPC_64B)
6514 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6515 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6516 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6517 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6518 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6519 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6520 #endif
6521
6522 #undef GEN_LD
6523 #undef GEN_LDU
6524 #undef GEN_LDUX
6525 #undef GEN_LDX_E
6526 #undef GEN_LDS
6527 #define GEN_LD(name, ldop, opc, type) \
6528 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6529 #define GEN_LDU(name, ldop, opc, type) \
6530 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6531 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6532 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6533 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6534 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6535 #define GEN_LDS(name, ldop, op, type) \
6536 GEN_LD(name, ldop, op | 0x20, type) \
6537 GEN_LDU(name, ldop, op | 0x21, type) \
6538 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6539 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6540
6541 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6542 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6543 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6544 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6545 #if defined(TARGET_PPC64)
6546 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6547 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6548 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
6549 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
6550 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6551
6552 /* HV/P7 and later only */
6553 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
6554 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6555 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6556 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6557 #endif
6558 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6559 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6560
6561 #undef GEN_ST
6562 #undef GEN_STU
6563 #undef GEN_STUX
6564 #undef GEN_STX_E
6565 #undef GEN_STS
6566 #define GEN_ST(name, stop, opc, type) \
6567 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6568 #define GEN_STU(name, stop, opc, type) \
6569 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6570 #define GEN_STUX(name, stop, opc2, opc3, type) \
6571 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6572 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6573 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6574 #define GEN_STS(name, stop, op, type) \
6575 GEN_ST(name, stop, op | 0x20, type) \
6576 GEN_STU(name, stop, op | 0x21, type) \
6577 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6578 GEN_STX(name, stop, 0x17, op | 0x00, type)
6579
6580 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6581 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6582 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6583 #if defined(TARGET_PPC64)
6584 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
6585 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
6586 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6587 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
6588 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6589 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6590 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6591 #endif
6592 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6593 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6594
6595 #undef GEN_CRLOGIC
6596 #define GEN_CRLOGIC(name, tcg_op, opc) \
6597 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6598 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6599 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6600 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6601 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6602 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6603 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6604 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6605 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6606
6607 #undef GEN_MAC_HANDLER
6608 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6609 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6610 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6611 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6612 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6613 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6614 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6615 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6616 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6617 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6618 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6619 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6620 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6621 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6622 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6623 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6624 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6625 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6626 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6627 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6628 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6629 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6630 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6631 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6632 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6633 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6634 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6635 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6636 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6637 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6638 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6639 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6640 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6641 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6642 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6643 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6644 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6645 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6646 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6647 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6648 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6649 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6650 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6651 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6652
6653 #include "translate/fp-ops.c"
6654
6655 #include "translate/vmx-ops.c"
6656
6657 #include "translate/vsx-ops.c"
6658
6659 #include "translate/dfp-ops.c"
6660
6661 #include "translate/spe-ops.c"
6662
6663 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6664 PPC_NONE, PPC2_TM),
6665 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6666 PPC_NONE, PPC2_TM),
6667 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6668 PPC_NONE, PPC2_TM),
6669 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6670 PPC_NONE, PPC2_TM),
6671 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6672 PPC_NONE, PPC2_TM),
6673 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6674 PPC_NONE, PPC2_TM),
6675 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6676 PPC_NONE, PPC2_TM),
6677 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6678 PPC_NONE, PPC2_TM),
6679 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6680 PPC_NONE, PPC2_TM),
6681 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6682 PPC_NONE, PPC2_TM),
6683 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6684 PPC_NONE, PPC2_TM),
6685 };
6686
6687 #include "helper_regs.h"
6688 #include "translate_init.c"
6689
6690 /*****************************************************************************/
6691 /* Misc PowerPC helpers */
6692 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6693 int flags)
6694 {
6695 #define RGPL 4
6696 #define RFPL 4
6697
6698 PowerPCCPU *cpu = POWERPC_CPU(cs);
6699 CPUPPCState *env = &cpu->env;
6700 int i;
6701
6702 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
6703 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
6704 env->nip, env->lr, env->ctr, cpu_read_xer(env),
6705 cs->cpu_index);
6706 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
6707 TARGET_FMT_lx " iidx %d didx %d\n",
6708 env->msr, env->spr[SPR_HID0],
6709 env->hflags, env->immu_idx, env->dmmu_idx);
6710 #if !defined(NO_TIMER_DUMP)
6711 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
6712 #if !defined(CONFIG_USER_ONLY)
6713 " DECR %08" PRIu32
6714 #endif
6715 "\n",
6716 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6717 #if !defined(CONFIG_USER_ONLY)
6718 , cpu_ppc_load_decr(env)
6719 #endif
6720 );
6721 #endif
6722 for (i = 0; i < 32; i++) {
6723 if ((i & (RGPL - 1)) == 0)
6724 cpu_fprintf(f, "GPR%02d", i);
6725 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
6726 if ((i & (RGPL - 1)) == (RGPL - 1))
6727 cpu_fprintf(f, "\n");
6728 }
6729 cpu_fprintf(f, "CR ");
6730 for (i = 0; i < 8; i++)
6731 cpu_fprintf(f, "%01x", env->crf[i]);
6732 cpu_fprintf(f, " [");
6733 for (i = 0; i < 8; i++) {
6734 char a = '-';
6735 if (env->crf[i] & 0x08)
6736 a = 'L';
6737 else if (env->crf[i] & 0x04)
6738 a = 'G';
6739 else if (env->crf[i] & 0x02)
6740 a = 'E';
6741 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6742 }
6743 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
6744 env->reserve_addr);
6745 for (i = 0; i < 32; i++) {
6746 if ((i & (RFPL - 1)) == 0)
6747 cpu_fprintf(f, "FPR%02d", i);
6748 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6749 if ((i & (RFPL - 1)) == (RFPL - 1))
6750 cpu_fprintf(f, "\n");
6751 }
6752 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
6753 #if !defined(CONFIG_USER_ONLY)
6754 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
6755 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
6756 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
6757 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
6758
6759 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
6760 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
6761 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
6762 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
6763
6764 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
6765 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
6766 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
6767 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
6768
6769 #if defined(TARGET_PPC64)
6770 if (env->excp_model == POWERPC_EXCP_POWER7 ||
6771 env->excp_model == POWERPC_EXCP_POWER8) {
6772 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
6773 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
6774 }
6775 #endif
6776 if (env->excp_model == POWERPC_EXCP_BOOKE) {
6777 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
6778 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
6779 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
6780 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
6781
6782 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
6783 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
6784 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
6785 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
6786
6787 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
6788 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
6789 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
6790 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
6791
6792 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
6793 " EPR " TARGET_FMT_lx "\n",
6794 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
6795 env->spr[SPR_BOOKE_EPR]);
6796
6797 /* FSL-specific */
6798 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
6799 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
6800 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
6801 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
6802
6803 /*
6804 * IVORs are left out as they are large and do not change often --
6805 * they can be read with "p $ivor0", "p $ivor1", etc.
6806 */
6807 }
6808
6809 #if defined(TARGET_PPC64)
6810 if (env->flags & POWERPC_FLAG_CFAR) {
6811 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
6812 }
6813 #endif
6814
6815 switch (env->mmu_model) {
6816 case POWERPC_MMU_32B:
6817 case POWERPC_MMU_601:
6818 case POWERPC_MMU_SOFT_6xx:
6819 case POWERPC_MMU_SOFT_74xx:
6820 #if defined(TARGET_PPC64)
6821 case POWERPC_MMU_64B:
6822 case POWERPC_MMU_2_03:
6823 case POWERPC_MMU_2_06:
6824 case POWERPC_MMU_2_06a:
6825 case POWERPC_MMU_2_07:
6826 case POWERPC_MMU_2_07a:
6827 #endif
6828 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
6829 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
6830 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
6831 break;
6832 case POWERPC_MMU_BOOKE206:
6833 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
6834 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
6835 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
6836 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
6837
6838 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
6839 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
6840 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
6841 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
6842
6843 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
6844 " TLB1CFG " TARGET_FMT_lx "\n",
6845 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
6846 env->spr[SPR_BOOKE_TLB1CFG]);
6847 break;
6848 default:
6849 break;
6850 }
6851 #endif
6852
6853 #undef RGPL
6854 #undef RFPL
6855 }
6856
6857 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
6858 fprintf_function cpu_fprintf, int flags)
6859 {
6860 #if defined(DO_PPC_STATISTICS)
6861 PowerPCCPU *cpu = POWERPC_CPU(cs);
6862 opc_handler_t **t1, **t2, **t3, *handler;
6863 int op1, op2, op3;
6864
6865 t1 = cpu->env.opcodes;
6866 for (op1 = 0; op1 < 64; op1++) {
6867 handler = t1[op1];
6868 if (is_indirect_opcode(handler)) {
6869 t2 = ind_table(handler);
6870 for (op2 = 0; op2 < 32; op2++) {
6871 handler = t2[op2];
6872 if (is_indirect_opcode(handler)) {
6873 t3 = ind_table(handler);
6874 for (op3 = 0; op3 < 32; op3++) {
6875 handler = t3[op3];
6876 if (handler->count == 0)
6877 continue;
6878 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6879 "%016" PRIx64 " %" PRId64 "\n",
6880 op1, op2, op3, op1, (op3 << 5) | op2,
6881 handler->oname,
6882 handler->count, handler->count);
6883 }
6884 } else {
6885 if (handler->count == 0)
6886 continue;
6887 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6888 "%016" PRIx64 " %" PRId64 "\n",
6889 op1, op2, op1, op2, handler->oname,
6890 handler->count, handler->count);
6891 }
6892 }
6893 } else {
6894 if (handler->count == 0)
6895 continue;
6896 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
6897 " %" PRId64 "\n",
6898 op1, op1, handler->oname,
6899 handler->count, handler->count);
6900 }
6901 }
6902 #endif
6903 }
6904
6905 /*****************************************************************************/
6906 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
6907 {
6908 PowerPCCPU *cpu = ppc_env_get_cpu(env);
6909 CPUState *cs = CPU(cpu);
6910 DisasContext ctx, *ctxp = &ctx;
6911 opc_handler_t **table, *handler;
6912 target_ulong pc_start;
6913 int num_insns;
6914 int max_insns;
6915
6916 pc_start = tb->pc;
6917 ctx.nip = pc_start;
6918 ctx.tb = tb;
6919 ctx.exception = POWERPC_EXCP_NONE;
6920 ctx.spr_cb = env->spr_cb;
6921 ctx.pr = msr_pr;
6922 ctx.mem_idx = env->dmmu_idx;
6923 ctx.dr = msr_dr;
6924 #if !defined(CONFIG_USER_ONLY)
6925 ctx.hv = msr_hv || !env->has_hv_mode;
6926 #endif
6927 ctx.insns_flags = env->insns_flags;
6928 ctx.insns_flags2 = env->insns_flags2;
6929 ctx.access_type = -1;
6930 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
6931 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
6932 #if defined(TARGET_PPC64)
6933 ctx.sf_mode = msr_is_64bit(env, env->msr);
6934 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
6935 #endif
6936 if (env->mmu_model == POWERPC_MMU_32B ||
6937 env->mmu_model == POWERPC_MMU_601 ||
6938 (env->mmu_model & POWERPC_MMU_64B))
6939 ctx.lazy_tlb_flush = true;
6940
6941 ctx.fpu_enabled = !!msr_fp;
6942 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
6943 ctx.spe_enabled = !!msr_spe;
6944 else
6945 ctx.spe_enabled = false;
6946 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6947 ctx.altivec_enabled = !!msr_vr;
6948 else
6949 ctx.altivec_enabled = false;
6950 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
6951 ctx.vsx_enabled = !!msr_vsx;
6952 } else {
6953 ctx.vsx_enabled = false;
6954 }
6955 #if defined(TARGET_PPC64)
6956 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
6957 ctx.tm_enabled = !!msr_tm;
6958 } else {
6959 ctx.tm_enabled = false;
6960 }
6961 #endif
6962 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
6963 ctx.singlestep_enabled = CPU_SINGLE_STEP;
6964 else
6965 ctx.singlestep_enabled = 0;
6966 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
6967 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
6968 if (unlikely(cs->singlestep_enabled)) {
6969 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
6970 }
6971 #if defined (DO_SINGLE_STEP) && 0
6972 /* Single step trace mode */
6973 msr_se = 1;
6974 #endif
6975 num_insns = 0;
6976 max_insns = tb->cflags & CF_COUNT_MASK;
6977 if (max_insns == 0) {
6978 max_insns = CF_COUNT_MASK;
6979 }
6980 if (max_insns > TCG_MAX_INSNS) {
6981 max_insns = TCG_MAX_INSNS;
6982 }
6983
6984 gen_tb_start(tb);
6985 tcg_clear_temp_count();
6986 /* Set env in case of segfault during code fetch */
6987 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
6988 tcg_gen_insn_start(ctx.nip);
6989 num_insns++;
6990
6991 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
6992 gen_debug_exception(ctxp);
6993 /* The address covered by the breakpoint must be included in
6994 [tb->pc, tb->pc + tb->size) in order to for it to be
6995 properly cleared -- thus we increment the PC here so that
6996 the logic setting tb->size below does the right thing. */
6997 ctx.nip += 4;
6998 break;
6999 }
7000
7001 LOG_DISAS("----------------\n");
7002 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7003 ctx.nip, ctx.mem_idx, (int)msr_ir);
7004 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
7005 gen_io_start();
7006 if (unlikely(need_byteswap(&ctx))) {
7007 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
7008 } else {
7009 ctx.opcode = cpu_ldl_code(env, ctx.nip);
7010 }
7011 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7012 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7013 opc3(ctx.opcode), opc4(ctx.opcode),
7014 ctx.le_mode ? "little" : "big");
7015 ctx.nip += 4;
7016 table = env->opcodes;
7017 handler = table[opc1(ctx.opcode)];
7018 if (is_indirect_opcode(handler)) {
7019 table = ind_table(handler);
7020 handler = table[opc2(ctx.opcode)];
7021 if (is_indirect_opcode(handler)) {
7022 table = ind_table(handler);
7023 handler = table[opc3(ctx.opcode)];
7024 if (is_indirect_opcode(handler)) {
7025 table = ind_table(handler);
7026 handler = table[opc4(ctx.opcode)];
7027 }
7028 }
7029 }
7030 /* Is opcode *REALLY* valid ? */
7031 if (unlikely(handler->handler == &gen_invalid)) {
7032 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7033 "%02x - %02x - %02x - %02x (%08x) "
7034 TARGET_FMT_lx " %d\n",
7035 opc1(ctx.opcode), opc2(ctx.opcode),
7036 opc3(ctx.opcode), opc4(ctx.opcode),
7037 ctx.opcode, ctx.nip - 4, (int)msr_ir);
7038 } else {
7039 uint32_t inval;
7040
7041 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
7042 inval = handler->inval2;
7043 } else {
7044 inval = handler->inval1;
7045 }
7046
7047 if (unlikely((ctx.opcode & inval) != 0)) {
7048 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7049 "%02x - %02x - %02x - %02x (%08x) "
7050 TARGET_FMT_lx "\n", ctx.opcode & inval,
7051 opc1(ctx.opcode), opc2(ctx.opcode),
7052 opc3(ctx.opcode), opc4(ctx.opcode),
7053 ctx.opcode, ctx.nip - 4);
7054 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
7055 break;
7056 }
7057 }
7058 (*(handler->handler))(&ctx);
7059 #if defined(DO_PPC_STATISTICS)
7060 handler->count++;
7061 #endif
7062 /* Check trace mode exceptions */
7063 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7064 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7065 ctx.exception != POWERPC_SYSCALL &&
7066 ctx.exception != POWERPC_EXCP_TRAP &&
7067 ctx.exception != POWERPC_EXCP_BRANCH)) {
7068 gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
7069 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7070 (cs->singlestep_enabled) ||
7071 singlestep ||
7072 num_insns >= max_insns)) {
7073 /* if we reach a page boundary or are single stepping, stop
7074 * generation
7075 */
7076 break;
7077 }
7078 if (tcg_check_temp_count()) {
7079 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
7080 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
7081 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
7082 exit(1);
7083 }
7084 }
7085 if (tb->cflags & CF_LAST_IO)
7086 gen_io_end();
7087 if (ctx.exception == POWERPC_EXCP_NONE) {
7088 gen_goto_tb(&ctx, 0, ctx.nip);
7089 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7090 if (unlikely(cs->singlestep_enabled)) {
7091 gen_debug_exception(ctxp);
7092 }
7093 /* Generate the return instruction */
7094 tcg_gen_exit_tb(0);
7095 }
7096 gen_tb_end(tb, num_insns);
7097
7098 tb->size = ctx.nip - pc_start;
7099 tb->icount = num_insns;
7100
7101 #if defined(DEBUG_DISAS)
7102 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
7103 && qemu_log_in_addr_range(pc_start)) {
7104 int flags;
7105 flags = env->bfd_mach;
7106 flags |= ctx.le_mode << 16;
7107 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7108 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
7109 qemu_log("\n");
7110 }
7111 #endif
7112 }
7113
7114 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7115 target_ulong *data)
7116 {
7117 env->nip = data[0];
7118 }
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