hw/timer/xlnx-zynqmp-rtc.c

   1 /*
   2  * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC).
   3  *
   4  * Copyright (c) 2017 Xilinx Inc.
   5  *
   6  * Written-by: Alistair Francis <alistair.francis@xilinx.com>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "hw/sysbus.h"
  29 #include "hw/register.h"
  30 #include "qemu/bitops.h"
  31 #include "qemu/log.h"
  32 #include "hw/ptimer.h"
  33 #include "qemu/cutils.h"
  34 #include "sysemu/sysemu.h"
  35 #include "trace.h"
  36 #include "hw/timer/xlnx-zynqmp-rtc.h"
  37
  38 #ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG
  39 #define XLNX_ZYNQMP_RTC_ERR_DEBUG 0
  40 #endif
  41
  42 static void rtc_int_update_irq(XlnxZynqMPRTC *s)
  43 {
  44     bool pending = s->regs[R_RTC_INT_STATUS] & ~s->regs[R_RTC_INT_MASK];
  45     qemu_set_irq(s->irq_rtc_int, pending);
  46 }
  47
  48 static void addr_error_int_update_irq(XlnxZynqMPRTC *s)
  49 {
  50     bool pending = s->regs[R_ADDR_ERROR] & ~s->regs[R_ADDR_ERROR_INT_MASK];
  51     qemu_set_irq(s->irq_addr_error_int, pending);
  52 }
  53
  54 static uint32_t rtc_get_count(XlnxZynqMPRTC *s)
  55 {
  56     int64_t now = qemu_clock_get_ns(rtc_clock);
  57     return s->tick_offset + now / NANOSECONDS_PER_SECOND;
  58 }
  59
  60 static uint64_t current_time_postr(RegisterInfo *reg, uint64_t val64)
  61 {
  62     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  63
  64     return rtc_get_count(s);
  65 }
  66
  67 static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64)
  68 {
  69     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  70     rtc_int_update_irq(s);
  71 }
  72
  73 static uint64_t rtc_int_en_prew(RegisterInfo *reg, uint64_t val64)
  74 {
  75     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  76
  77     s->regs[R_RTC_INT_MASK] &= (uint32_t) ~val64;
  78     rtc_int_update_irq(s);
  79     return 0;
  80 }
  81
  82 static uint64_t rtc_int_dis_prew(RegisterInfo *reg, uint64_t val64)
  83 {
  84     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  85
  86     s->regs[R_RTC_INT_MASK] |= (uint32_t) val64;
  87     rtc_int_update_irq(s);
  88     return 0;
  89 }
  90
  91 static void addr_error_postw(RegisterInfo *reg, uint64_t val64)
  92 {
  93     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  94     addr_error_int_update_irq(s);
  95 }
  96
  97 static uint64_t addr_error_int_en_prew(RegisterInfo *reg, uint64_t val64)
  98 {
  99     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
 100
 101     s->regs[R_ADDR_ERROR_INT_MASK] &= (uint32_t) ~val64;
 102     addr_error_int_update_irq(s);
 103     return 0;
 104 }
 105
 106 static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64)
 107 {
 108     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
 109
 110     s->regs[R_ADDR_ERROR_INT_MASK] |= (uint32_t) val64;
 111     addr_error_int_update_irq(s);
 112     return 0;
 113 }
 114
 115 static const RegisterAccessInfo rtc_regs_info[] = {
 116     {   .name = "SET_TIME_WRITE",  .addr = A_SET_TIME_WRITE,
 117         .unimp = MAKE_64BIT_MASK(0, 32),
 118     },{ .name = "SET_TIME_READ",  .addr = A_SET_TIME_READ,
 119         .ro = 0xffffffff,
 120         .post_read = current_time_postr,
 121     },{ .name = "CALIB_WRITE",  .addr = A_CALIB_WRITE,
 122         .unimp = MAKE_64BIT_MASK(0, 32),
 123     },{ .name = "CALIB_READ",  .addr = A_CALIB_READ,
 124         .ro = 0x1fffff,
 125     },{ .name = "CURRENT_TIME",  .addr = A_CURRENT_TIME,
 126         .ro = 0xffffffff,
 127         .post_read = current_time_postr,
 128     },{ .name = "CURRENT_TICK",  .addr = A_CURRENT_TICK,
 129         .ro = 0xffff,
 130     },{ .name = "ALARM",  .addr = A_ALARM,
 131     },{ .name = "RTC_INT_STATUS",  .addr = A_RTC_INT_STATUS,
 132         .w1c = 0x3,
 133         .post_write = rtc_int_status_postw,
 134     },{ .name = "RTC_INT_MASK",  .addr = A_RTC_INT_MASK,
 135         .reset = 0x3,
 136         .ro = 0x3,
 137     },{ .name = "RTC_INT_EN",  .addr = A_RTC_INT_EN,
 138         .pre_write = rtc_int_en_prew,
 139     },{ .name = "RTC_INT_DIS",  .addr = A_RTC_INT_DIS,
 140         .pre_write = rtc_int_dis_prew,
 141     },{ .name = "ADDR_ERROR",  .addr = A_ADDR_ERROR,
 142         .w1c = 0x1,
 143         .post_write = addr_error_postw,
 144     },{ .name = "ADDR_ERROR_INT_MASK",  .addr = A_ADDR_ERROR_INT_MASK,
 145         .reset = 0x1,
 146         .ro = 0x1,
 147     },{ .name = "ADDR_ERROR_INT_EN",  .addr = A_ADDR_ERROR_INT_EN,
 148         .pre_write = addr_error_int_en_prew,
 149     },{ .name = "ADDR_ERROR_INT_DIS",  .addr = A_ADDR_ERROR_INT_DIS,
 150         .pre_write = addr_error_int_dis_prew,
 151     },{ .name = "CONTROL",  .addr = A_CONTROL,
 152         .reset = 0x1000000,
 153         .rsvd = 0x70fffffe,
 154     },{ .name = "SAFETY_CHK",  .addr = A_SAFETY_CHK,
 155     }
 156 };
 157
 158 static void rtc_reset(DeviceState *dev)
 159 {
 160     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(dev);
 161     unsigned int i;
 162
 163     for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
 164         register_reset(&s->regs_info[i]);
 165     }
 166
 167     rtc_int_update_irq(s);
 168     addr_error_int_update_irq(s);
 169 }
 170
 171 static const MemoryRegionOps rtc_ops = {
 172     .read = register_read_memory,
 173     .write = register_write_memory,
 174     .endianness = DEVICE_LITTLE_ENDIAN,
 175     .valid = {
 176         .min_access_size = 4,
 177         .max_access_size = 4,
 178     },
 179 };
 180
 181 static void rtc_init(Object *obj)
 182 {
 183     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(obj);
 184     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 185     RegisterInfoArray *reg_array;
 186     struct tm current_tm;
 187
 188     memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_RTC,
 189                        XLNX_ZYNQMP_RTC_R_MAX * 4);
 190     reg_array =
 191         register_init_block32(DEVICE(obj), rtc_regs_info,
 192                               ARRAY_SIZE(rtc_regs_info),
 193                               s->regs_info, s->regs,
 194                               &rtc_ops,
 195                               XLNX_ZYNQMP_RTC_ERR_DEBUG,
 196                               XLNX_ZYNQMP_RTC_R_MAX * 4);
 197     memory_region_add_subregion(&s->iomem,
 198                                 0x0,
 199                                 &reg_array->mem);
 200     sysbus_init_mmio(sbd, &s->iomem);
 201     sysbus_init_irq(sbd, &s->irq_rtc_int);
 202     sysbus_init_irq(sbd, &s->irq_addr_error_int);
 203
 204     qemu_get_timedate(&current_tm, 0);
 205     s->tick_offset = mktimegm(&current_tm) -
 206         qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
 207
 208     trace_xlnx_zynqmp_rtc_gettime(current_tm.tm_year, current_tm.tm_mon,
 209                                   current_tm.tm_mday, current_tm.tm_hour,
 210                                   current_tm.tm_min, current_tm.tm_sec);
 211 }
 212
 213 static int rtc_pre_save(void *opaque)
 214 {
 215     XlnxZynqMPRTC *s = opaque;
 216     int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
 217
 218     /* Add the time at migration */
 219     s->tick_offset = s->tick_offset + now;
 220
 221     return 0;
 222 }
 223
 224 static int rtc_post_load(void *opaque, int version_id)
 225 {
 226     XlnxZynqMPRTC *s = opaque;
 227     int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
 228
 229     /* Subtract the time after migration. This combined with the pre_save
 230      * action results in us having subtracted the time that the guest was
 231      * stopped to the offset.
 232      */
 233     s->tick_offset = s->tick_offset - now;
 234
 235     return 0;
 236 }
 237
 238 static const VMStateDescription vmstate_rtc = {
 239     .name = TYPE_XLNX_ZYNQMP_RTC,
 240     .version_id = 1,
 241     .minimum_version_id = 1,
 242     .pre_save = rtc_pre_save,
 243     .post_load = rtc_post_load,
 244     .fields = (VMStateField[]) {
 245         VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPRTC, XLNX_ZYNQMP_RTC_R_MAX),
 246         VMSTATE_UINT32(tick_offset, XlnxZynqMPRTC),
 247         VMSTATE_END_OF_LIST(),
 248     }
 249 };
 250
 251 static void rtc_class_init(ObjectClass *klass, void *data)
 252 {
 253     DeviceClass *dc = DEVICE_CLASS(klass);
 254
 255     dc->reset = rtc_reset;
 256     dc->vmsd = &vmstate_rtc;
 257 }
 258
 259 static const TypeInfo rtc_info = {
 260     .name          = TYPE_XLNX_ZYNQMP_RTC,
 261     .parent        = TYPE_SYS_BUS_DEVICE,
 262     .instance_size = sizeof(XlnxZynqMPRTC),
 263     .class_init    = rtc_class_init,
 264     .instance_init = rtc_init,
 265 };
 266
 267 static void rtc_register_types(void)
 268 {
 269     type_register_static(&rtc_info);
 270 }
 271
 272 type_init(rtc_register_types)