hw/mips/cps.c

   1 /*
   2  * Coherent Processing System emulation.
   3  *
   4  * Copyright (c) 2016 Imagination Technologies
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "hw/mips/cps.h"
  23 #include "hw/mips/mips.h"
  24 #include "hw/mips/cpudevs.h"
  25 #include "sysemu/kvm.h"
  26
  27 qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
  28 {
  29     assert(pin_number < s->num_irq);
  30     return s->gic.irq_state[pin_number].irq;
  31 }
  32
  33 static void mips_cps_init(Object *obj)
  34 {
  35     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  36     MIPSCPSState *s = MIPS_CPS(obj);
  37
  38     /* Cover entire address space as there do not seem to be any
  39      * constraints for the base address of CPC and GIC. */
  40     memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX);
  41     sysbus_init_mmio(sbd, &s->container);
  42 }
  43
  44 static void main_cpu_reset(void *opaque)
  45 {
  46     MIPSCPU *cpu = opaque;
  47     CPUState *cs = CPU(cpu);
  48
  49     cpu_reset(cs);
  50
  51     /* All VPs are halted on reset. Leave powering up to CPC. */
  52     cs->halted = 1;
  53 }
  54
  55 static bool cpu_mips_itu_supported(CPUMIPSState *env)
  56 {
  57     bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) ||
  58                  (env->CP0_Config3 & (1 << CP0C3_MT));
  59
  60     return is_mt && !kvm_enabled();
  61 }
  62
  63 static void mips_cps_realize(DeviceState *dev, Error **errp)
  64 {
  65     MIPSCPSState *s = MIPS_CPS(dev);
  66     CPUMIPSState *env;
  67     MIPSCPU *cpu;
  68     int i;
  69     Error *err = NULL;
  70     target_ulong gcr_base;
  71     bool itu_present = false;
  72     bool saar_present = false;
  73
  74     for (i = 0; i < s->num_vp; i++) {
  75         cpu = MIPS_CPU(cpu_create(s->cpu_type));
  76
  77         /* Init internal devices */
  78         cpu_mips_irq_init_cpu(cpu);
  79         cpu_mips_clock_init(cpu);
  80
  81         env = &cpu->env;
  82         if (cpu_mips_itu_supported(env)) {
  83             itu_present = true;
  84             /* Attach ITC Tag to the VP */
  85             env->itc_tag = mips_itu_get_tag_region(&s->itu);
  86             env->itu = &s->itu;
  87         }
  88         qemu_register_reset(main_cpu_reset, cpu);
  89     }
  90
  91     cpu = MIPS_CPU(first_cpu);
  92     env = &cpu->env;
  93     saar_present = (bool)env->saarp;
  94
  95     /* Inter-Thread Communication Unit */
  96     if (itu_present) {
  97         object_initialize(&s->itu, sizeof(s->itu), TYPE_MIPS_ITU);
  98         qdev_set_parent_bus(DEVICE(&s->itu), sysbus_get_default());
  99
 100         object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err);
 101         object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err);
 102         object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present",
 103                                  &err);
 104         if (saar_present) {
 105             qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *)&env->CP0_SAAR);
 106         }
 107         object_property_set_bool(OBJECT(&s->itu), true, "realized", &err);
 108         if (err != NULL) {
 109             error_propagate(errp, err);
 110             return;
 111         }
 112
 113         memory_region_add_subregion(&s->container, 0,
 114                            sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0));
 115     }
 116
 117     /* Cluster Power Controller */
 118     object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC);
 119     qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default());
 120
 121     object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err);
 122     object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err);
 123     object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err);
 124     if (err != NULL) {
 125         error_propagate(errp, err);
 126         return;
 127     }
 128
 129     memory_region_add_subregion(&s->container, 0,
 130                             sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
 131
 132     /* Global Interrupt Controller */
 133     object_initialize(&s->gic, sizeof(s->gic), TYPE_MIPS_GIC);
 134     qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
 135
 136     object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp", &err);
 137     object_property_set_int(OBJECT(&s->gic), 128, "num-irq", &err);
 138     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
 139     if (err != NULL) {
 140         error_propagate(errp, err);
 141         return;
 142     }
 143
 144     memory_region_add_subregion(&s->container, 0,
 145                             sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0));
 146
 147     /* Global Configuration Registers */
 148     gcr_base = env->CP0_CMGCRBase << 4;
 149
 150     object_initialize(&s->gcr, sizeof(s->gcr), TYPE_MIPS_GCR);
 151     qdev_set_parent_bus(DEVICE(&s->gcr), sysbus_get_default());
 152
 153     object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err);
 154     object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err);
 155     object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err);
 156     object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->gic.mr), "gic", &err);
 157     object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", &err);
 158     object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err);
 159     if (err != NULL) {
 160         error_propagate(errp, err);
 161         return;
 162     }
 163
 164     memory_region_add_subregion(&s->container, gcr_base,
 165                             sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));
 166 }
 167
 168 static Property mips_cps_properties[] = {
 169     DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
 170     DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
 171     DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type),
 172     DEFINE_PROP_END_OF_LIST()
 173 };
 174
 175 static void mips_cps_class_init(ObjectClass *klass, void *data)
 176 {
 177     DeviceClass *dc = DEVICE_CLASS(klass);
 178
 179     dc->realize = mips_cps_realize;
 180     dc->props = mips_cps_properties;
 181 }
 182
 183 static const TypeInfo mips_cps_info = {
 184     .name = TYPE_MIPS_CPS,
 185     .parent = TYPE_SYS_BUS_DEVICE,
 186     .instance_size = sizeof(MIPSCPSState),
 187     .instance_init = mips_cps_init,
 188     .class_init = mips_cps_class_init,
 189 };
 190
 191 static void mips_cps_register_types(void)
 192 {
 193     type_register_static(&mips_cps_info);
 194 }
 195
 196 type_init(mips_cps_register_types)