hw/net/opencores_eth.c

   1 /*
   2  * OpenCores Ethernet MAC 10/100 + subset of
   3  * National Semiconductors DP83848C 10/100 PHY
   4  *
   5  * http://opencores.org/svnget,ethmac?file=%2Ftrunk%2F%2Fdoc%2Feth_speci.pdf
   6  * http://cache.national.com/ds/DP/DP83848C.pdf
   7  *
   8  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   9  * All rights reserved.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions are met:
  13  *     * Redistributions of source code must retain the above copyright
  14  *       notice, this list of conditions and the following disclaimer.
  15  *     * Redistributions in binary form must reproduce the above copyright
  16  *       notice, this list of conditions and the following disclaimer in the
  17  *       documentation and/or other materials provided with the distribution.
  18  *     * Neither the name of the Open Source and Linux Lab nor the
  19  *       names of its contributors may be used to endorse or promote products
  20  *       derived from this software without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  26  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  27  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  29  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  31  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include "qemu/osdep.h"
  35 #include "hw/hw.h"
  36 #include "hw/sysbus.h"
  37 #include "net/net.h"
  38 #include "sysemu/sysemu.h"
  39 #include "trace.h"
  40
  41 /* RECSMALL is not used because it breaks tap networking in linux:
  42  * incoming ARP responses are too short
  43  */
  44 #undef USE_RECSMALL
  45
  46 #define GET_FIELD(v, field) (((v) & (field)) >> (field ## _LBN))
  47 #define GET_REGBIT(s, reg, field) ((s)->regs[reg] & (reg ## _ ## field))
  48 #define GET_REGFIELD(s, reg, field) \
  49     GET_FIELD((s)->regs[reg], reg ## _ ## field)
  50
  51 #define SET_FIELD(v, field, data) \
  52     ((v) = (((v) & ~(field)) | (((data) << (field ## _LBN)) & (field))))
  53 #define SET_REGFIELD(s, reg, field, data) \
  54     SET_FIELD((s)->regs[reg], reg ## _ ## field, data)
  55
  56 /* PHY MII registers */
  57 enum {
  58     MII_BMCR,
  59     MII_BMSR,
  60     MII_PHYIDR1,
  61     MII_PHYIDR2,
  62     MII_ANAR,
  63     MII_ANLPAR,
  64     MII_REG_MAX = 16,
  65 };
  66
  67 typedef struct Mii {
  68     uint16_t regs[MII_REG_MAX];
  69     bool link_ok;
  70 } Mii;
  71
  72 static void mii_set_link(Mii *s, bool link_ok)
  73 {
  74     if (link_ok) {
  75         s->regs[MII_BMSR] |= 0x4;
  76         s->regs[MII_ANLPAR] |= 0x01e1;
  77     } else {
  78         s->regs[MII_BMSR] &= ~0x4;
  79         s->regs[MII_ANLPAR] &= 0x01ff;
  80     }
  81     s->link_ok = link_ok;
  82 }
  83
  84 static void mii_reset(Mii *s)
  85 {
  86     memset(s->regs, 0, sizeof(s->regs));
  87     s->regs[MII_BMCR] = 0x1000;
  88     s->regs[MII_BMSR] = 0x7848; /* no ext regs */
  89     s->regs[MII_PHYIDR1] = 0x2000;
  90     s->regs[MII_PHYIDR2] = 0x5c90;
  91     s->regs[MII_ANAR] = 0x01e1;
  92     mii_set_link(s, s->link_ok);
  93 }
  94
  95 static void mii_ro(Mii *s, uint16_t v)
  96 {
  97 }
  98
  99 static void mii_write_bmcr(Mii *s, uint16_t v)
 100 {
 101     if (v & 0x8000) {
 102         mii_reset(s);
 103     } else {
 104         s->regs[MII_BMCR] = v;
 105     }
 106 }
 107
 108 static void mii_write_host(Mii *s, unsigned idx, uint16_t v)
 109 {
 110     static void (*reg_write[MII_REG_MAX])(Mii *s, uint16_t v) = {
 111         [MII_BMCR] = mii_write_bmcr,
 112         [MII_BMSR] = mii_ro,
 113         [MII_PHYIDR1] = mii_ro,
 114         [MII_PHYIDR2] = mii_ro,
 115     };
 116
 117     if (idx < MII_REG_MAX) {
 118         trace_open_eth_mii_write(idx, v);
 119         if (reg_write[idx]) {
 120             reg_write[idx](s, v);
 121         } else {
 122             s->regs[idx] = v;
 123         }
 124     }
 125 }
 126
 127 static uint16_t mii_read_host(Mii *s, unsigned idx)
 128 {
 129     trace_open_eth_mii_read(idx, s->regs[idx]);
 130     return s->regs[idx];
 131 }
 132
 133 /* OpenCores Ethernet registers */
 134 enum {
 135     MODER,
 136     INT_SOURCE,
 137     INT_MASK,
 138     IPGT,
 139     IPGR1,
 140     IPGR2,
 141     PACKETLEN,
 142     COLLCONF,
 143     TX_BD_NUM,
 144     CTRLMODER,
 145     MIIMODER,
 146     MIICOMMAND,
 147     MIIADDRESS,
 148     MIITX_DATA,
 149     MIIRX_DATA,
 150     MIISTATUS,
 151     MAC_ADDR0,
 152     MAC_ADDR1,
 153     HASH0,
 154     HASH1,
 155     TXCTRL,
 156     REG_MAX,
 157 };
 158
 159 enum {
 160     MODER_RECSMALL = 0x10000,
 161     MODER_PAD = 0x8000,
 162     MODER_HUGEN = 0x4000,
 163     MODER_RST = 0x800,
 164     MODER_LOOPBCK = 0x80,
 165     MODER_PRO = 0x20,
 166     MODER_IAM = 0x10,
 167     MODER_BRO = 0x8,
 168     MODER_TXEN = 0x2,
 169     MODER_RXEN = 0x1,
 170 };
 171
 172 enum {
 173     INT_SOURCE_BUSY = 0x10,
 174     INT_SOURCE_RXB = 0x4,
 175     INT_SOURCE_TXB = 0x1,
 176 };
 177
 178 enum {
 179     PACKETLEN_MINFL = 0xffff0000,
 180     PACKETLEN_MINFL_LBN = 16,
 181     PACKETLEN_MAXFL = 0xffff,
 182     PACKETLEN_MAXFL_LBN = 0,
 183 };
 184
 185 enum {
 186     MIICOMMAND_WCTRLDATA = 0x4,
 187     MIICOMMAND_RSTAT = 0x2,
 188     MIICOMMAND_SCANSTAT = 0x1,
 189 };
 190
 191 enum {
 192     MIIADDRESS_RGAD = 0x1f00,
 193     MIIADDRESS_RGAD_LBN = 8,
 194     MIIADDRESS_FIAD = 0x1f,
 195     MIIADDRESS_FIAD_LBN = 0,
 196 };
 197
 198 enum {
 199     MIITX_DATA_CTRLDATA = 0xffff,
 200     MIITX_DATA_CTRLDATA_LBN = 0,
 201 };
 202
 203 enum {
 204     MIIRX_DATA_PRSD = 0xffff,
 205     MIIRX_DATA_PRSD_LBN = 0,
 206 };
 207
 208 enum {
 209     MIISTATUS_LINKFAIL = 0x1,
 210     MIISTATUS_LINKFAIL_LBN = 0,
 211 };
 212
 213 enum {
 214     MAC_ADDR0_BYTE2 = 0xff000000,
 215     MAC_ADDR0_BYTE2_LBN = 24,
 216     MAC_ADDR0_BYTE3 = 0xff0000,
 217     MAC_ADDR0_BYTE3_LBN = 16,
 218     MAC_ADDR0_BYTE4 = 0xff00,
 219     MAC_ADDR0_BYTE4_LBN = 8,
 220     MAC_ADDR0_BYTE5 = 0xff,
 221     MAC_ADDR0_BYTE5_LBN = 0,
 222 };
 223
 224 enum {
 225     MAC_ADDR1_BYTE0 = 0xff00,
 226     MAC_ADDR1_BYTE0_LBN = 8,
 227     MAC_ADDR1_BYTE1 = 0xff,
 228     MAC_ADDR1_BYTE1_LBN = 0,
 229 };
 230
 231 enum {
 232     TXD_LEN = 0xffff0000,
 233     TXD_LEN_LBN = 16,
 234     TXD_RD = 0x8000,
 235     TXD_IRQ = 0x4000,
 236     TXD_WR = 0x2000,
 237     TXD_PAD = 0x1000,
 238     TXD_CRC = 0x800,
 239     TXD_UR = 0x100,
 240     TXD_RTRY = 0xf0,
 241     TXD_RTRY_LBN = 4,
 242     TXD_RL = 0x8,
 243     TXD_LC = 0x4,
 244     TXD_DF = 0x2,
 245     TXD_CS = 0x1,
 246 };
 247
 248 enum {
 249     RXD_LEN = 0xffff0000,
 250     RXD_LEN_LBN = 16,
 251     RXD_E = 0x8000,
 252     RXD_IRQ = 0x4000,
 253     RXD_WRAP = 0x2000,
 254     RXD_CF = 0x100,
 255     RXD_M = 0x80,
 256     RXD_OR = 0x40,
 257     RXD_IS = 0x20,
 258     RXD_DN = 0x10,
 259     RXD_TL = 0x8,
 260     RXD_SF = 0x4,
 261     RXD_CRC = 0x2,
 262     RXD_LC = 0x1,
 263 };
 264
 265 typedef struct desc {
 266     uint32_t len_flags;
 267     uint32_t buf_ptr;
 268 } desc;
 269
 270 #define DEFAULT_PHY 1
 271
 272 #define TYPE_OPEN_ETH "open_eth"
 273 #define OPEN_ETH(obj) OBJECT_CHECK(OpenEthState, (obj), TYPE_OPEN_ETH)
 274
 275 typedef struct OpenEthState {
 276     SysBusDevice parent_obj;
 277
 278     NICState *nic;
 279     NICConf conf;
 280     MemoryRegion reg_io;
 281     MemoryRegion desc_io;
 282     qemu_irq irq;
 283
 284     Mii mii;
 285     uint32_t regs[REG_MAX];
 286     unsigned tx_desc;
 287     unsigned rx_desc;
 288     desc desc[128];
 289 } OpenEthState;
 290
 291 static desc *rx_desc(OpenEthState *s)
 292 {
 293     return s->desc + s->rx_desc;
 294 }
 295
 296 static desc *tx_desc(OpenEthState *s)
 297 {
 298     return s->desc + s->tx_desc;
 299 }
 300
 301 static void open_eth_update_irq(OpenEthState *s,
 302         uint32_t old, uint32_t new)
 303 {
 304     if (!old != !new) {
 305         trace_open_eth_update_irq(new);
 306         qemu_set_irq(s->irq, new);
 307     }
 308 }
 309
 310 static void open_eth_int_source_write(OpenEthState *s,
 311         uint32_t val)
 312 {
 313     uint32_t old_val = s->regs[INT_SOURCE];
 314
 315     s->regs[INT_SOURCE] = val;
 316     open_eth_update_irq(s, old_val & s->regs[INT_MASK],
 317             s->regs[INT_SOURCE] & s->regs[INT_MASK]);
 318 }
 319
 320 static void open_eth_set_link_status(NetClientState *nc)
 321 {
 322     OpenEthState *s = qemu_get_nic_opaque(nc);
 323
 324     if (GET_REGBIT(s, MIICOMMAND, SCANSTAT)) {
 325         SET_REGFIELD(s, MIISTATUS, LINKFAIL, nc->link_down);
 326     }
 327     mii_set_link(&s->mii, !nc->link_down);
 328 }
 329
 330 static void open_eth_reset(void *opaque)
 331 {
 332     OpenEthState *s = opaque;
 333
 334     memset(s->regs, 0, sizeof(s->regs));
 335     s->regs[MODER] = 0xa000;
 336     s->regs[IPGT] = 0x12;
 337     s->regs[IPGR1] = 0xc;
 338     s->regs[IPGR2] = 0x12;
 339     s->regs[PACKETLEN] = 0x400600;
 340     s->regs[COLLCONF] = 0xf003f;
 341     s->regs[TX_BD_NUM] = 0x40;
 342     s->regs[MIIMODER] = 0x64;
 343
 344     s->tx_desc = 0;
 345     s->rx_desc = 0x40;
 346
 347     mii_reset(&s->mii);
 348     open_eth_set_link_status(qemu_get_queue(s->nic));
 349 }
 350
 351 static int open_eth_can_receive(NetClientState *nc)
 352 {
 353     OpenEthState *s = qemu_get_nic_opaque(nc);
 354
 355     return GET_REGBIT(s, MODER, RXEN) &&
 356         (s->regs[TX_BD_NUM] < 0x80);
 357 }
 358
 359 static ssize_t open_eth_receive(NetClientState *nc,
 360         const uint8_t *buf, size_t size)
 361 {
 362     OpenEthState *s = qemu_get_nic_opaque(nc);
 363     size_t maxfl = GET_REGFIELD(s, PACKETLEN, MAXFL);
 364     size_t minfl = GET_REGFIELD(s, PACKETLEN, MINFL);
 365     size_t fcsl = 4;
 366     bool miss = true;
 367
 368     trace_open_eth_receive((unsigned)size);
 369
 370     if (size >= 6) {
 371         static const uint8_t bcast_addr[] = {
 372             0xff, 0xff, 0xff, 0xff, 0xff, 0xff
 373         };
 374         if (memcmp(buf, bcast_addr, sizeof(bcast_addr)) == 0) {
 375             miss = GET_REGBIT(s, MODER, BRO);
 376         } else if ((buf[0] & 0x1) || GET_REGBIT(s, MODER, IAM)) {
 377             unsigned mcast_idx = compute_mcast_idx(buf);
 378             miss = !(s->regs[HASH0 + mcast_idx / 32] &
 379                     (1 << (mcast_idx % 32)));
 380             trace_open_eth_receive_mcast(
 381                     mcast_idx, s->regs[HASH0], s->regs[HASH1]);
 382         } else {
 383             miss = GET_REGFIELD(s, MAC_ADDR1, BYTE0) != buf[0] ||
 384                 GET_REGFIELD(s, MAC_ADDR1, BYTE1) != buf[1] ||
 385                 GET_REGFIELD(s, MAC_ADDR0, BYTE2) != buf[2] ||
 386                 GET_REGFIELD(s, MAC_ADDR0, BYTE3) != buf[3] ||
 387                 GET_REGFIELD(s, MAC_ADDR0, BYTE4) != buf[4] ||
 388                 GET_REGFIELD(s, MAC_ADDR0, BYTE5) != buf[5];
 389         }
 390     }
 391
 392     if (miss && !GET_REGBIT(s, MODER, PRO)) {
 393         trace_open_eth_receive_reject();
 394         return size;
 395     }
 396
 397 #ifdef USE_RECSMALL
 398     if (GET_REGBIT(s, MODER, RECSMALL) || size >= minfl) {
 399 #else
 400     {
 401 #endif
 402         static const uint8_t zero[64] = {0};
 403         desc *desc = rx_desc(s);
 404         size_t copy_size = GET_REGBIT(s, MODER, HUGEN) ? 65536 : maxfl;
 405
 406         if (!(desc->len_flags & RXD_E)) {
 407             open_eth_int_source_write(s,
 408                     s->regs[INT_SOURCE] | INT_SOURCE_BUSY);
 409             return size;
 410         }
 411
 412         desc->len_flags &= ~(RXD_CF | RXD_M | RXD_OR |
 413                 RXD_IS | RXD_DN | RXD_TL | RXD_SF | RXD_CRC | RXD_LC);
 414
 415         if (copy_size > size) {
 416             copy_size = size;
 417         } else {
 418             fcsl = 0;
 419         }
 420         if (miss) {
 421             desc->len_flags |= RXD_M;
 422         }
 423         if (GET_REGBIT(s, MODER, HUGEN) && size > maxfl) {
 424             desc->len_flags |= RXD_TL;
 425         }
 426 #ifdef USE_RECSMALL
 427         if (size < minfl) {
 428             desc->len_flags |= RXD_SF;
 429         }
 430 #endif
 431
 432         cpu_physical_memory_write(desc->buf_ptr, buf, copy_size);
 433
 434         if (GET_REGBIT(s, MODER, PAD) && copy_size < minfl) {
 435             if (minfl - copy_size > fcsl) {
 436                 fcsl = 0;
 437             } else {
 438                 fcsl -= minfl - copy_size;
 439             }
 440             while (copy_size < minfl) {
 441                 size_t zero_sz = minfl - copy_size < sizeof(zero) ?
 442                     minfl - copy_size : sizeof(zero);
 443
 444                 cpu_physical_memory_write(desc->buf_ptr + copy_size,
 445                         zero, zero_sz);
 446                 copy_size += zero_sz;
 447             }
 448         }
 449
 450         /* There's no FCS in the frames handed to us by the QEMU, zero fill it.
 451          * Don't do it if the frame is cut at the MAXFL or padded with 4 or
 452          * more bytes to the MINFL.
 453          */
 454         cpu_physical_memory_write(desc->buf_ptr + copy_size, zero, fcsl);
 455         copy_size += fcsl;
 456
 457         SET_FIELD(desc->len_flags, RXD_LEN, copy_size);
 458
 459         if ((desc->len_flags & RXD_WRAP) || s->rx_desc == 0x7f) {
 460             s->rx_desc = s->regs[TX_BD_NUM];
 461         } else {
 462             ++s->rx_desc;
 463         }
 464         desc->len_flags &= ~RXD_E;
 465
 466         trace_open_eth_receive_desc(desc->buf_ptr, desc->len_flags);
 467
 468         if (desc->len_flags & RXD_IRQ) {
 469             open_eth_int_source_write(s,
 470                     s->regs[INT_SOURCE] | INT_SOURCE_RXB);
 471         }
 472     }
 473     return size;
 474 }
 475
 476 static NetClientInfo net_open_eth_info = {
 477     .type = NET_CLIENT_OPTIONS_KIND_NIC,
 478     .size = sizeof(NICState),
 479     .can_receive = open_eth_can_receive,
 480     .receive = open_eth_receive,
 481     .link_status_changed = open_eth_set_link_status,
 482 };
 483
 484 static void open_eth_start_xmit(OpenEthState *s, desc *tx)
 485 {
 486     uint8_t buf[65536];
 487     unsigned len = GET_FIELD(tx->len_flags, TXD_LEN);
 488     unsigned tx_len = len;
 489
 490     if ((tx->len_flags & TXD_PAD) &&
 491             tx_len < GET_REGFIELD(s, PACKETLEN, MINFL)) {
 492         tx_len = GET_REGFIELD(s, PACKETLEN, MINFL);
 493     }
 494     if (!GET_REGBIT(s, MODER, HUGEN) &&
 495             tx_len > GET_REGFIELD(s, PACKETLEN, MAXFL)) {
 496         tx_len = GET_REGFIELD(s, PACKETLEN, MAXFL);
 497     }
 498
 499     trace_open_eth_start_xmit(tx->buf_ptr, len, tx_len);
 500
 501     if (len > tx_len) {
 502         len = tx_len;
 503     }
 504     cpu_physical_memory_read(tx->buf_ptr, buf, len);
 505     if (tx_len > len) {
 506         memset(buf + len, 0, tx_len - len);
 507     }
 508     qemu_send_packet(qemu_get_queue(s->nic), buf, tx_len);
 509
 510     if (tx->len_flags & TXD_WR) {
 511         s->tx_desc = 0;
 512     } else {
 513         ++s->tx_desc;
 514         if (s->tx_desc >= s->regs[TX_BD_NUM]) {
 515             s->tx_desc = 0;
 516         }
 517     }
 518     tx->len_flags &= ~(TXD_RD | TXD_UR |
 519             TXD_RTRY | TXD_RL | TXD_LC | TXD_DF | TXD_CS);
 520     if (tx->len_flags & TXD_IRQ) {
 521         open_eth_int_source_write(s, s->regs[INT_SOURCE] | INT_SOURCE_TXB);
 522     }
 523
 524 }
 525
 526 static void open_eth_check_start_xmit(OpenEthState *s)
 527 {
 528     desc *tx = tx_desc(s);
 529     if (GET_REGBIT(s, MODER, TXEN) && s->regs[TX_BD_NUM] > 0 &&
 530             (tx->len_flags & TXD_RD) &&
 531             GET_FIELD(tx->len_flags, TXD_LEN) > 4) {
 532         open_eth_start_xmit(s, tx);
 533     }
 534 }
 535
 536 static uint64_t open_eth_reg_read(void *opaque,
 537         hwaddr addr, unsigned int size)
 538 {
 539     static uint32_t (*reg_read[REG_MAX])(OpenEthState *s) = {
 540     };
 541     OpenEthState *s = opaque;
 542     unsigned idx = addr / 4;
 543     uint64_t v = 0;
 544
 545     if (idx < REG_MAX) {
 546         if (reg_read[idx]) {
 547             v = reg_read[idx](s);
 548         } else {
 549             v = s->regs[idx];
 550         }
 551     }
 552     trace_open_eth_reg_read((uint32_t)addr, (uint32_t)v);
 553     return v;
 554 }
 555
 556 static void open_eth_notify_can_receive(OpenEthState *s)
 557 {
 558     NetClientState *nc = qemu_get_queue(s->nic);
 559
 560     if (open_eth_can_receive(nc)) {
 561         qemu_flush_queued_packets(nc);
 562     }
 563 }
 564
 565 static void open_eth_ro(OpenEthState *s, uint32_t val)
 566 {
 567 }
 568
 569 static void open_eth_moder_host_write(OpenEthState *s, uint32_t val)
 570 {
 571     uint32_t set = val & ~s->regs[MODER];
 572
 573     if (set & MODER_RST) {
 574         open_eth_reset(s);
 575     }
 576
 577     s->regs[MODER] = val;
 578
 579     if (set & MODER_RXEN) {
 580         s->rx_desc = s->regs[TX_BD_NUM];
 581         open_eth_notify_can_receive(s);
 582     }
 583     if (set & MODER_TXEN) {
 584         s->tx_desc = 0;
 585         open_eth_check_start_xmit(s);
 586     }
 587 }
 588
 589 static void open_eth_int_source_host_write(OpenEthState *s, uint32_t val)
 590 {
 591     uint32_t old = s->regs[INT_SOURCE];
 592
 593     s->regs[INT_SOURCE] &= ~val;
 594     open_eth_update_irq(s, old & s->regs[INT_MASK],
 595             s->regs[INT_SOURCE] & s->regs[INT_MASK]);
 596 }
 597
 598 static void open_eth_int_mask_host_write(OpenEthState *s, uint32_t val)
 599 {
 600     uint32_t old = s->regs[INT_MASK];
 601
 602     s->regs[INT_MASK] = val;
 603     open_eth_update_irq(s, s->regs[INT_SOURCE] & old,
 604             s->regs[INT_SOURCE] & s->regs[INT_MASK]);
 605 }
 606
 607 static void open_eth_tx_bd_num_host_write(OpenEthState *s, uint32_t val)
 608 {
 609     if (val < 0x80) {
 610         bool enable = s->regs[TX_BD_NUM] == 0x80;
 611
 612         s->regs[TX_BD_NUM] = val;
 613         if (enable) {
 614             open_eth_notify_can_receive(s);
 615         }
 616     }
 617 }
 618
 619 static void open_eth_mii_command_host_write(OpenEthState *s, uint32_t val)
 620 {
 621     unsigned fiad = GET_REGFIELD(s, MIIADDRESS, FIAD);
 622     unsigned rgad = GET_REGFIELD(s, MIIADDRESS, RGAD);
 623
 624     if (val & MIICOMMAND_WCTRLDATA) {
 625         if (fiad == DEFAULT_PHY) {
 626             mii_write_host(&s->mii, rgad,
 627                     GET_REGFIELD(s, MIITX_DATA, CTRLDATA));
 628         }
 629     }
 630     if (val & MIICOMMAND_RSTAT) {
 631         if (fiad == DEFAULT_PHY) {
 632             SET_REGFIELD(s, MIIRX_DATA, PRSD,
 633                     mii_read_host(&s->mii, rgad));
 634         } else {
 635             s->regs[MIIRX_DATA] = 0xffff;
 636         }
 637         SET_REGFIELD(s, MIISTATUS, LINKFAIL, qemu_get_queue(s->nic)->link_down);
 638     }
 639 }
 640
 641 static void open_eth_mii_tx_host_write(OpenEthState *s, uint32_t val)
 642 {
 643     SET_REGFIELD(s, MIITX_DATA, CTRLDATA, val);
 644     if (GET_REGFIELD(s, MIIADDRESS, FIAD) == DEFAULT_PHY) {
 645         mii_write_host(&s->mii, GET_REGFIELD(s, MIIADDRESS, RGAD),
 646                 GET_REGFIELD(s, MIITX_DATA, CTRLDATA));
 647     }
 648 }
 649
 650 static void open_eth_reg_write(void *opaque,
 651         hwaddr addr, uint64_t val, unsigned int size)
 652 {
 653     static void (*reg_write[REG_MAX])(OpenEthState *s, uint32_t val) = {
 654         [MODER] = open_eth_moder_host_write,
 655         [INT_SOURCE] = open_eth_int_source_host_write,
 656         [INT_MASK] = open_eth_int_mask_host_write,
 657         [TX_BD_NUM] = open_eth_tx_bd_num_host_write,
 658         [MIICOMMAND] = open_eth_mii_command_host_write,
 659         [MIITX_DATA] = open_eth_mii_tx_host_write,
 660         [MIISTATUS] = open_eth_ro,
 661     };
 662     OpenEthState *s = opaque;
 663     unsigned idx = addr / 4;
 664
 665     if (idx < REG_MAX) {
 666         trace_open_eth_reg_write((uint32_t)addr, (uint32_t)val);
 667         if (reg_write[idx]) {
 668             reg_write[idx](s, val);
 669         } else {
 670             s->regs[idx] = val;
 671         }
 672     }
 673 }
 674
 675 static uint64_t open_eth_desc_read(void *opaque,
 676         hwaddr addr, unsigned int size)
 677 {
 678     OpenEthState *s = opaque;
 679     uint64_t v = 0;
 680
 681     addr &= 0x3ff;
 682     memcpy(&v, (uint8_t *)s->desc + addr, size);
 683     trace_open_eth_desc_read((uint32_t)addr, (uint32_t)v);
 684     return v;
 685 }
 686
 687 static void open_eth_desc_write(void *opaque,
 688         hwaddr addr, uint64_t val, unsigned int size)
 689 {
 690     OpenEthState *s = opaque;
 691
 692     addr &= 0x3ff;
 693     trace_open_eth_desc_write((uint32_t)addr, (uint32_t)val);
 694     memcpy((uint8_t *)s->desc + addr, &val, size);
 695     open_eth_check_start_xmit(s);
 696 }
 697
 698
 699 static const MemoryRegionOps open_eth_reg_ops = {
 700     .read = open_eth_reg_read,
 701     .write = open_eth_reg_write,
 702 };
 703
 704 static const MemoryRegionOps open_eth_desc_ops = {
 705     .read = open_eth_desc_read,
 706     .write = open_eth_desc_write,
 707 };
 708
 709 static int sysbus_open_eth_init(SysBusDevice *sbd)
 710 {
 711     DeviceState *dev = DEVICE(sbd);
 712     OpenEthState *s = OPEN_ETH(dev);
 713
 714     memory_region_init_io(&s->reg_io, OBJECT(dev), &open_eth_reg_ops, s,
 715             "open_eth.regs", 0x54);
 716     sysbus_init_mmio(sbd, &s->reg_io);
 717
 718     memory_region_init_io(&s->desc_io, OBJECT(dev), &open_eth_desc_ops, s,
 719             "open_eth.desc", 0x400);
 720     sysbus_init_mmio(sbd, &s->desc_io);
 721
 722     sysbus_init_irq(sbd, &s->irq);
 723
 724     s->nic = qemu_new_nic(&net_open_eth_info, &s->conf,
 725                           object_get_typename(OBJECT(s)), dev->id, s);
 726     return 0;
 727 }
 728
 729 static void qdev_open_eth_reset(DeviceState *dev)
 730 {
 731     OpenEthState *d = OPEN_ETH(dev);
 732
 733     open_eth_reset(d);
 734 }
 735
 736 static Property open_eth_properties[] = {
 737     DEFINE_NIC_PROPERTIES(OpenEthState, conf),
 738     DEFINE_PROP_END_OF_LIST(),
 739 };
 740
 741 static void open_eth_class_init(ObjectClass *klass, void *data)
 742 {
 743     DeviceClass *dc = DEVICE_CLASS(klass);
 744     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 745
 746     k->init = sysbus_open_eth_init;
 747     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 748     dc->desc = "Opencores 10/100 Mbit Ethernet";
 749     dc->reset = qdev_open_eth_reset;
 750     dc->props = open_eth_properties;
 751 }
 752
 753 static const TypeInfo open_eth_info = {
 754     .name          = TYPE_OPEN_ETH,
 755     .parent        = TYPE_SYS_BUS_DEVICE,
 756     .instance_size = sizeof(OpenEthState),
 757     .class_init    = open_eth_class_init,
 758 };
 759
 760 static void open_eth_register_types(void)
 761 {
 762     type_register_static(&open_eth_info);
 763 }
 764
 765 type_init(open_eth_register_types)