hw/net/milkymist-minimac2.c

   1 /*
   2  *  QEMU model of the Milkymist minimac2 block.
   3  *
   4  *  Copyright (c) 2011 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   not available yet
  22  *
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/hw.h"
  27 #include "hw/sysbus.h"
  28 #include "trace.h"
  29 #include "net/net.h"
  30 #include "qemu/error-report.h"
  31
  32 #include <zlib.h>
  33
  34 enum {
  35     R_SETUP = 0,
  36     R_MDIO,
  37     R_STATE0,
  38     R_COUNT0,
  39     R_STATE1,
  40     R_COUNT1,
  41     R_TXCOUNT,
  42     R_MAX
  43 };
  44
  45 enum {
  46     SETUP_PHY_RST = (1<<0),
  47 };
  48
  49 enum {
  50     MDIO_DO  = (1<<0),
  51     MDIO_DI  = (1<<1),
  52     MDIO_OE  = (1<<2),
  53     MDIO_CLK = (1<<3),
  54 };
  55
  56 enum {
  57     STATE_EMPTY   = 0,
  58     STATE_LOADED  = 1,
  59     STATE_PENDING = 2,
  60 };
  61
  62 enum {
  63     MDIO_OP_WRITE = 1,
  64     MDIO_OP_READ  = 2,
  65 };
  66
  67 enum mdio_state {
  68     MDIO_STATE_IDLE,
  69     MDIO_STATE_READING,
  70     MDIO_STATE_WRITING,
  71 };
  72
  73 enum {
  74     R_PHY_ID1  = 2,
  75     R_PHY_ID2  = 3,
  76     R_PHY_MAX  = 32
  77 };
  78
  79 #define MINIMAC2_MTU 1530
  80 #define MINIMAC2_BUFFER_SIZE 2048
  81
  82 struct MilkymistMinimac2MdioState {
  83     int last_clk;
  84     int count;
  85     uint32_t data;
  86     uint16_t data_out;
  87     int state;
  88
  89     uint8_t phy_addr;
  90     uint8_t reg_addr;
  91 };
  92 typedef struct MilkymistMinimac2MdioState MilkymistMinimac2MdioState;
  93
  94 #define TYPE_MILKYMIST_MINIMAC2 "milkymist-minimac2"
  95 #define MILKYMIST_MINIMAC2(obj) \
  96     OBJECT_CHECK(MilkymistMinimac2State, (obj), TYPE_MILKYMIST_MINIMAC2)
  97
  98 struct MilkymistMinimac2State {
  99     SysBusDevice parent_obj;
 100
 101     NICState *nic;
 102     NICConf conf;
 103     char *phy_model;
 104     MemoryRegion buffers;
 105     MemoryRegion regs_region;
 106
 107     qemu_irq rx_irq;
 108     qemu_irq tx_irq;
 109
 110     uint32_t regs[R_MAX];
 111
 112     MilkymistMinimac2MdioState mdio;
 113
 114     uint16_t phy_regs[R_PHY_MAX];
 115
 116     uint8_t *rx0_buf;
 117     uint8_t *rx1_buf;
 118     uint8_t *tx_buf;
 119 };
 120 typedef struct MilkymistMinimac2State MilkymistMinimac2State;
 121
 122 static const uint8_t preamble_sfd[] = {
 123         0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xd5
 124 };
 125
 126 static void minimac2_mdio_write_reg(MilkymistMinimac2State *s,
 127         uint8_t phy_addr, uint8_t reg_addr, uint16_t value)
 128 {
 129     trace_milkymist_minimac2_mdio_write(phy_addr, reg_addr, value);
 130
 131     /* nop */
 132 }
 133
 134 static uint16_t minimac2_mdio_read_reg(MilkymistMinimac2State *s,
 135         uint8_t phy_addr, uint8_t reg_addr)
 136 {
 137     uint16_t r = s->phy_regs[reg_addr];
 138
 139     trace_milkymist_minimac2_mdio_read(phy_addr, reg_addr, r);
 140
 141     return r;
 142 }
 143
 144 static void minimac2_update_mdio(MilkymistMinimac2State *s)
 145 {
 146     MilkymistMinimac2MdioState *m = &s->mdio;
 147
 148     /* detect rising clk edge */
 149     if (m->last_clk == 0 && (s->regs[R_MDIO] & MDIO_CLK)) {
 150         /* shift data in */
 151         int bit = ((s->regs[R_MDIO] & MDIO_DO)
 152                    && (s->regs[R_MDIO] & MDIO_OE)) ? 1 : 0;
 153         m->data = (m->data << 1) | bit;
 154
 155         /* check for sync */
 156         if (m->data == 0xffffffff) {
 157             m->count = 32;
 158         }
 159
 160         if (m->count == 16) {
 161             uint8_t start = (m->data >> 14) & 0x3;
 162             uint8_t op = (m->data >> 12) & 0x3;
 163             uint8_t ta = (m->data) & 0x3;
 164
 165             if (start == 1 && op == MDIO_OP_WRITE && ta == 2) {
 166                 m->state = MDIO_STATE_WRITING;
 167             } else if (start == 1 && op == MDIO_OP_READ && (ta & 1) == 0) {
 168                 m->state = MDIO_STATE_READING;
 169             } else {
 170                 m->state = MDIO_STATE_IDLE;
 171             }
 172
 173             if (m->state != MDIO_STATE_IDLE) {
 174                 m->phy_addr = (m->data >> 7) & 0x1f;
 175                 m->reg_addr = (m->data >> 2) & 0x1f;
 176             }
 177
 178             if (m->state == MDIO_STATE_READING) {
 179                 m->data_out = minimac2_mdio_read_reg(s, m->phy_addr,
 180                         m->reg_addr);
 181             }
 182         }
 183
 184         if (m->count < 16 && m->state == MDIO_STATE_READING) {
 185             int bit = (m->data_out & 0x8000) ? 1 : 0;
 186             m->data_out <<= 1;
 187
 188             if (bit) {
 189                 s->regs[R_MDIO] |= MDIO_DI;
 190             } else {
 191                 s->regs[R_MDIO] &= ~MDIO_DI;
 192             }
 193         }
 194
 195         if (m->count == 0 && m->state) {
 196             if (m->state == MDIO_STATE_WRITING) {
 197                 uint16_t data = m->data & 0xffff;
 198                 minimac2_mdio_write_reg(s, m->phy_addr, m->reg_addr, data);
 199             }
 200             m->state = MDIO_STATE_IDLE;
 201         }
 202         m->count--;
 203     }
 204
 205     m->last_clk = (s->regs[R_MDIO] & MDIO_CLK) ? 1 : 0;
 206 }
 207
 208 static size_t assemble_frame(uint8_t *buf, size_t size,
 209         const uint8_t *payload, size_t payload_size)
 210 {
 211     uint32_t crc;
 212
 213     if (size < payload_size + 12) {
 214         error_report("milkymist_minimac2: received too big ethernet frame");
 215         return 0;
 216     }
 217
 218     /* prepend preamble and sfd */
 219     memcpy(buf, preamble_sfd, 8);
 220
 221     /* now copy the payload */
 222     memcpy(buf + 8, payload, payload_size);
 223
 224     /* pad frame if needed */
 225     if (payload_size < 60) {
 226         memset(buf + payload_size + 8, 0, 60 - payload_size);
 227         payload_size = 60;
 228     }
 229
 230     /* append fcs */
 231     crc = cpu_to_le32(crc32(0, buf + 8, payload_size));
 232     memcpy(buf + payload_size + 8, &crc, 4);
 233
 234     return payload_size + 12;
 235 }
 236
 237 static void minimac2_tx(MilkymistMinimac2State *s)
 238 {
 239     uint32_t txcount = s->regs[R_TXCOUNT];
 240     uint8_t *buf = s->tx_buf;
 241
 242     if (txcount < 64) {
 243         error_report("milkymist_minimac2: ethernet frame too small (%u < %u)",
 244                 txcount, 64);
 245         goto err;
 246     }
 247
 248     if (txcount > MINIMAC2_MTU) {
 249         error_report("milkymist_minimac2: MTU exceeded (%u > %u)",
 250                 txcount, MINIMAC2_MTU);
 251         goto err;
 252     }
 253
 254     if (memcmp(buf, preamble_sfd, 8) != 0) {
 255         error_report("milkymist_minimac2: frame doesn't contain the preamble "
 256                 "and/or the SFD (%02x %02x %02x %02x %02x %02x %02x %02x)",
 257                 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
 258         goto err;
 259     }
 260
 261     trace_milkymist_minimac2_tx_frame(txcount - 12);
 262
 263     /* send packet, skipping preamble and sfd */
 264     qemu_send_packet_raw(qemu_get_queue(s->nic), buf + 8, txcount - 12);
 265
 266     s->regs[R_TXCOUNT] = 0;
 267
 268 err:
 269     trace_milkymist_minimac2_pulse_irq_tx();
 270     qemu_irq_pulse(s->tx_irq);
 271 }
 272
 273 static void update_rx_interrupt(MilkymistMinimac2State *s)
 274 {
 275     if (s->regs[R_STATE0] == STATE_PENDING
 276             || s->regs[R_STATE1] == STATE_PENDING) {
 277         trace_milkymist_minimac2_raise_irq_rx();
 278         qemu_irq_raise(s->rx_irq);
 279     } else {
 280         trace_milkymist_minimac2_lower_irq_rx();
 281         qemu_irq_lower(s->rx_irq);
 282     }
 283 }
 284
 285 static ssize_t minimac2_rx(NetClientState *nc, const uint8_t *buf, size_t size)
 286 {
 287     MilkymistMinimac2State *s = qemu_get_nic_opaque(nc);
 288
 289     uint32_t r_count;
 290     uint32_t r_state;
 291     uint8_t *rx_buf;
 292
 293     size_t frame_size;
 294
 295     trace_milkymist_minimac2_rx_frame(buf, size);
 296
 297     /* choose appropriate slot */
 298     if (s->regs[R_STATE0] == STATE_LOADED) {
 299         r_count = R_COUNT0;
 300         r_state = R_STATE0;
 301         rx_buf = s->rx0_buf;
 302     } else if (s->regs[R_STATE1] == STATE_LOADED) {
 303         r_count = R_COUNT1;
 304         r_state = R_STATE1;
 305         rx_buf = s->rx1_buf;
 306     } else {
 307         return 0;
 308     }
 309
 310     /* assemble frame */
 311     frame_size = assemble_frame(rx_buf, MINIMAC2_BUFFER_SIZE, buf, size);
 312
 313     if (frame_size == 0) {
 314         return size;
 315     }
 316
 317     trace_milkymist_minimac2_rx_transfer(rx_buf, frame_size);
 318
 319     /* update slot */
 320     s->regs[r_count] = frame_size;
 321     s->regs[r_state] = STATE_PENDING;
 322
 323     update_rx_interrupt(s);
 324
 325     return size;
 326 }
 327
 328 static uint64_t
 329 minimac2_read(void *opaque, hwaddr addr, unsigned size)
 330 {
 331     MilkymistMinimac2State *s = opaque;
 332     uint32_t r = 0;
 333
 334     addr >>= 2;
 335     switch (addr) {
 336     case R_SETUP:
 337     case R_MDIO:
 338     case R_STATE0:
 339     case R_COUNT0:
 340     case R_STATE1:
 341     case R_COUNT1:
 342     case R_TXCOUNT:
 343         r = s->regs[addr];
 344         break;
 345
 346     default:
 347         error_report("milkymist_minimac2: read access to unknown register 0x"
 348                 TARGET_FMT_plx, addr << 2);
 349         break;
 350     }
 351
 352     trace_milkymist_minimac2_memory_read(addr << 2, r);
 353
 354     return r;
 355 }
 356
 357 static int minimac2_can_rx(MilkymistMinimac2State *s)
 358 {
 359     if (s->regs[R_STATE0] == STATE_LOADED) {
 360         return 1;
 361     }
 362     if (s->regs[R_STATE1] == STATE_LOADED) {
 363         return 1;
 364     }
 365
 366     return 0;
 367 }
 368
 369 static void
 370 minimac2_write(void *opaque, hwaddr addr, uint64_t value,
 371                unsigned size)
 372 {
 373     MilkymistMinimac2State *s = opaque;
 374
 375     trace_milkymist_minimac2_memory_write(addr, value);
 376
 377     addr >>= 2;
 378     switch (addr) {
 379     case R_MDIO:
 380     {
 381         /* MDIO_DI is read only */
 382         int mdio_di = (s->regs[R_MDIO] & MDIO_DI);
 383         s->regs[R_MDIO] = value;
 384         if (mdio_di) {
 385             s->regs[R_MDIO] |= mdio_di;
 386         } else {
 387             s->regs[R_MDIO] &= ~mdio_di;
 388         }
 389
 390         minimac2_update_mdio(s);
 391     } break;
 392     case R_TXCOUNT:
 393         s->regs[addr] = value;
 394         if (value > 0) {
 395             minimac2_tx(s);
 396         }
 397         break;
 398     case R_STATE0:
 399     case R_STATE1:
 400         s->regs[addr] = value;
 401         update_rx_interrupt(s);
 402         if (minimac2_can_rx(s)) {
 403             qemu_flush_queued_packets(qemu_get_queue(s->nic));
 404         }
 405         break;
 406     case R_SETUP:
 407     case R_COUNT0:
 408     case R_COUNT1:
 409         s->regs[addr] = value;
 410         break;
 411
 412     default:
 413         error_report("milkymist_minimac2: write access to unknown register 0x"
 414                 TARGET_FMT_plx, addr << 2);
 415         break;
 416     }
 417 }
 418
 419 static const MemoryRegionOps minimac2_ops = {
 420     .read = minimac2_read,
 421     .write = minimac2_write,
 422     .valid = {
 423         .min_access_size = 4,
 424         .max_access_size = 4,
 425     },
 426     .endianness = DEVICE_NATIVE_ENDIAN,
 427 };
 428
 429 static void milkymist_minimac2_reset(DeviceState *d)
 430 {
 431     MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(d);
 432     int i;
 433
 434     for (i = 0; i < R_MAX; i++) {
 435         s->regs[i] = 0;
 436     }
 437     for (i = 0; i < R_PHY_MAX; i++) {
 438         s->phy_regs[i] = 0;
 439     }
 440
 441     /* defaults */
 442     s->phy_regs[R_PHY_ID1] = 0x0022; /* Micrel KSZ8001L */
 443     s->phy_regs[R_PHY_ID2] = 0x161a;
 444 }
 445
 446 static NetClientInfo net_milkymist_minimac2_info = {
 447     .type = NET_CLIENT_OPTIONS_KIND_NIC,
 448     .size = sizeof(NICState),
 449     .receive = minimac2_rx,
 450 };
 451
 452 static int milkymist_minimac2_init(SysBusDevice *sbd)
 453 {
 454     DeviceState *dev = DEVICE(sbd);
 455     MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(dev);
 456     size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE);
 457
 458     sysbus_init_irq(sbd, &s->rx_irq);
 459     sysbus_init_irq(sbd, &s->tx_irq);
 460
 461     memory_region_init_io(&s->regs_region, OBJECT(dev), &minimac2_ops, s,
 462                           "milkymist-minimac2", R_MAX * 4);
 463     sysbus_init_mmio(sbd, &s->regs_region);
 464
 465     /* register buffers memory */
 466     memory_region_init_ram(&s->buffers, OBJECT(dev), "milkymist-minimac2.buffers",
 467                            buffers_size, &error_fatal);
 468     vmstate_register_ram_global(&s->buffers);
 469     s->rx0_buf = memory_region_get_ram_ptr(&s->buffers);
 470     s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE;
 471     s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE;
 472
 473     sysbus_init_mmio(sbd, &s->buffers);
 474
 475     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 476     s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf,
 477                           object_get_typename(OBJECT(dev)), dev->id, s);
 478     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 479
 480     return 0;
 481 }
 482
 483 static const VMStateDescription vmstate_milkymist_minimac2_mdio = {
 484     .name = "milkymist-minimac2-mdio",
 485     .version_id = 1,
 486     .minimum_version_id = 1,
 487     .fields = (VMStateField[]) {
 488         VMSTATE_INT32(last_clk, MilkymistMinimac2MdioState),
 489         VMSTATE_INT32(count, MilkymistMinimac2MdioState),
 490         VMSTATE_UINT32(data, MilkymistMinimac2MdioState),
 491         VMSTATE_UINT16(data_out, MilkymistMinimac2MdioState),
 492         VMSTATE_INT32(state, MilkymistMinimac2MdioState),
 493         VMSTATE_UINT8(phy_addr, MilkymistMinimac2MdioState),
 494         VMSTATE_UINT8(reg_addr, MilkymistMinimac2MdioState),
 495         VMSTATE_END_OF_LIST()
 496     }
 497 };
 498
 499 static const VMStateDescription vmstate_milkymist_minimac2 = {
 500     .name = "milkymist-minimac2",
 501     .version_id = 1,
 502     .minimum_version_id = 1,
 503     .fields = (VMStateField[]) {
 504         VMSTATE_UINT32_ARRAY(regs, MilkymistMinimac2State, R_MAX),
 505         VMSTATE_UINT16_ARRAY(phy_regs, MilkymistMinimac2State, R_PHY_MAX),
 506         VMSTATE_STRUCT(mdio, MilkymistMinimac2State, 0,
 507                 vmstate_milkymist_minimac2_mdio, MilkymistMinimac2MdioState),
 508         VMSTATE_END_OF_LIST()
 509     }
 510 };
 511
 512 static Property milkymist_minimac2_properties[] = {
 513     DEFINE_NIC_PROPERTIES(MilkymistMinimac2State, conf),
 514     DEFINE_PROP_STRING("phy_model", MilkymistMinimac2State, phy_model),
 515     DEFINE_PROP_END_OF_LIST(),
 516 };
 517
 518 static void milkymist_minimac2_class_init(ObjectClass *klass, void *data)
 519 {
 520     DeviceClass *dc = DEVICE_CLASS(klass);
 521     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 522
 523     k->init = milkymist_minimac2_init;
 524     dc->reset = milkymist_minimac2_reset;
 525     dc->vmsd = &vmstate_milkymist_minimac2;
 526     dc->props = milkymist_minimac2_properties;
 527 }
 528
 529 static const TypeInfo milkymist_minimac2_info = {
 530     .name          = TYPE_MILKYMIST_MINIMAC2,
 531     .parent        = TYPE_SYS_BUS_DEVICE,
 532     .instance_size = sizeof(MilkymistMinimac2State),
 533     .class_init    = milkymist_minimac2_class_init,
 534 };
 535
 536 static void milkymist_minimac2_register_types(void)
 537 {
 538     type_register_static(&milkymist_minimac2_info);
 539 }
 540
 541 type_init(milkymist_minimac2_register_types)