Merge remote-tracking branch 'remotes/kraxel/tags/pull-usb-20160622-2' into staging
[qemu/kevin.git] / hw / i386 / pc.c
blob7198ed533cc47bfdc1c2719ec4cb22da8348cfa9
1 /*
2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "hw/i386/pc.h"
27 #include "hw/char/serial.h"
28 #include "hw/i386/apic.h"
29 #include "hw/i386/topology.h"
30 #include "sysemu/cpus.h"
31 #include "hw/block/fdc.h"
32 #include "hw/ide.h"
33 #include "hw/pci/pci.h"
34 #include "hw/pci/pci_bus.h"
35 #include "hw/nvram/fw_cfg.h"
36 #include "hw/timer/hpet.h"
37 #include "hw/smbios/smbios.h"
38 #include "hw/loader.h"
39 #include "elf.h"
40 #include "multiboot.h"
41 #include "hw/timer/mc146818rtc.h"
42 #include "hw/timer/i8254.h"
43 #include "hw/audio/pcspk.h"
44 #include "hw/pci/msi.h"
45 #include "hw/sysbus.h"
46 #include "sysemu/sysemu.h"
47 #include "sysemu/numa.h"
48 #include "sysemu/kvm.h"
49 #include "sysemu/qtest.h"
50 #include "kvm_i386.h"
51 #include "hw/xen/xen.h"
52 #include "sysemu/block-backend.h"
53 #include "hw/block/block.h"
54 #include "ui/qemu-spice.h"
55 #include "exec/memory.h"
56 #include "exec/address-spaces.h"
57 #include "sysemu/arch_init.h"
58 #include "qemu/bitmap.h"
59 #include "qemu/config-file.h"
60 #include "qemu/error-report.h"
61 #include "hw/acpi/acpi.h"
62 #include "hw/acpi/cpu_hotplug.h"
63 #include "hw/boards.h"
64 #include "hw/pci/pci_host.h"
65 #include "acpi-build.h"
66 #include "hw/mem/pc-dimm.h"
67 #include "qapi/visitor.h"
68 #include "qapi-visit.h"
69 #include "qom/cpu.h"
70 #include "hw/nmi.h"
72 /* debug PC/ISA interrupts */
73 //#define DEBUG_IRQ
75 #ifdef DEBUG_IRQ
76 #define DPRINTF(fmt, ...) \
77 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
78 #else
79 #define DPRINTF(fmt, ...)
80 #endif
82 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
83 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
84 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
85 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
86 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
88 #define E820_NR_ENTRIES 16
90 struct e820_entry {
91 uint64_t address;
92 uint64_t length;
93 uint32_t type;
94 } QEMU_PACKED __attribute((__aligned__(4)));
96 struct e820_table {
97 uint32_t count;
98 struct e820_entry entry[E820_NR_ENTRIES];
99 } QEMU_PACKED __attribute((__aligned__(4)));
101 static struct e820_table e820_reserve;
102 static struct e820_entry *e820_table;
103 static unsigned e820_entries;
104 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
106 void gsi_handler(void *opaque, int n, int level)
108 GSIState *s = opaque;
110 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
111 if (n < ISA_NUM_IRQS) {
112 qemu_set_irq(s->i8259_irq[n], level);
114 qemu_set_irq(s->ioapic_irq[n], level);
117 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
118 unsigned size)
122 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
124 return 0xffffffffffffffffULL;
127 /* MSDOS compatibility mode FPU exception support */
128 static qemu_irq ferr_irq;
130 void pc_register_ferr_irq(qemu_irq irq)
132 ferr_irq = irq;
135 /* XXX: add IGNNE support */
136 void cpu_set_ferr(CPUX86State *s)
138 qemu_irq_raise(ferr_irq);
141 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
142 unsigned size)
144 qemu_irq_lower(ferr_irq);
147 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
149 return 0xffffffffffffffffULL;
152 /* TSC handling */
153 uint64_t cpu_get_tsc(CPUX86State *env)
155 return cpu_get_ticks();
158 /* IRQ handling */
159 int cpu_get_pic_interrupt(CPUX86State *env)
161 X86CPU *cpu = x86_env_get_cpu(env);
162 int intno;
164 intno = apic_get_interrupt(cpu->apic_state);
165 if (intno >= 0) {
166 return intno;
168 /* read the irq from the PIC */
169 if (!apic_accept_pic_intr(cpu->apic_state)) {
170 return -1;
173 intno = pic_read_irq(isa_pic);
174 return intno;
177 static void pic_irq_request(void *opaque, int irq, int level)
179 CPUState *cs = first_cpu;
180 X86CPU *cpu = X86_CPU(cs);
182 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
183 if (cpu->apic_state) {
184 CPU_FOREACH(cs) {
185 cpu = X86_CPU(cs);
186 if (apic_accept_pic_intr(cpu->apic_state)) {
187 apic_deliver_pic_intr(cpu->apic_state, level);
190 } else {
191 if (level) {
192 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
193 } else {
194 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
199 /* PC cmos mappings */
201 #define REG_EQUIPMENT_BYTE 0x14
203 int cmos_get_fd_drive_type(FloppyDriveType fd0)
205 int val;
207 switch (fd0) {
208 case FLOPPY_DRIVE_TYPE_144:
209 /* 1.44 Mb 3"5 drive */
210 val = 4;
211 break;
212 case FLOPPY_DRIVE_TYPE_288:
213 /* 2.88 Mb 3"5 drive */
214 val = 5;
215 break;
216 case FLOPPY_DRIVE_TYPE_120:
217 /* 1.2 Mb 5"5 drive */
218 val = 2;
219 break;
220 case FLOPPY_DRIVE_TYPE_NONE:
221 default:
222 val = 0;
223 break;
225 return val;
228 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
229 int16_t cylinders, int8_t heads, int8_t sectors)
231 rtc_set_memory(s, type_ofs, 47);
232 rtc_set_memory(s, info_ofs, cylinders);
233 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
234 rtc_set_memory(s, info_ofs + 2, heads);
235 rtc_set_memory(s, info_ofs + 3, 0xff);
236 rtc_set_memory(s, info_ofs + 4, 0xff);
237 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
238 rtc_set_memory(s, info_ofs + 6, cylinders);
239 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
240 rtc_set_memory(s, info_ofs + 8, sectors);
243 /* convert boot_device letter to something recognizable by the bios */
244 static int boot_device2nibble(char boot_device)
246 switch(boot_device) {
247 case 'a':
248 case 'b':
249 return 0x01; /* floppy boot */
250 case 'c':
251 return 0x02; /* hard drive boot */
252 case 'd':
253 return 0x03; /* CD-ROM boot */
254 case 'n':
255 return 0x04; /* Network boot */
257 return 0;
260 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
262 #define PC_MAX_BOOT_DEVICES 3
263 int nbds, bds[3] = { 0, };
264 int i;
266 nbds = strlen(boot_device);
267 if (nbds > PC_MAX_BOOT_DEVICES) {
268 error_setg(errp, "Too many boot devices for PC");
269 return;
271 for (i = 0; i < nbds; i++) {
272 bds[i] = boot_device2nibble(boot_device[i]);
273 if (bds[i] == 0) {
274 error_setg(errp, "Invalid boot device for PC: '%c'",
275 boot_device[i]);
276 return;
279 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
280 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
283 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
285 set_boot_dev(opaque, boot_device, errp);
288 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
290 int val, nb, i;
291 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
292 FLOPPY_DRIVE_TYPE_NONE };
294 /* floppy type */
295 if (floppy) {
296 for (i = 0; i < 2; i++) {
297 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
300 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
301 cmos_get_fd_drive_type(fd_type[1]);
302 rtc_set_memory(rtc_state, 0x10, val);
304 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
305 nb = 0;
306 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
307 nb++;
309 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
310 nb++;
312 switch (nb) {
313 case 0:
314 break;
315 case 1:
316 val |= 0x01; /* 1 drive, ready for boot */
317 break;
318 case 2:
319 val |= 0x41; /* 2 drives, ready for boot */
320 break;
322 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
325 typedef struct pc_cmos_init_late_arg {
326 ISADevice *rtc_state;
327 BusState *idebus[2];
328 } pc_cmos_init_late_arg;
330 typedef struct check_fdc_state {
331 ISADevice *floppy;
332 bool multiple;
333 } CheckFdcState;
335 static int check_fdc(Object *obj, void *opaque)
337 CheckFdcState *state = opaque;
338 Object *fdc;
339 uint32_t iobase;
340 Error *local_err = NULL;
342 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
343 if (!fdc) {
344 return 0;
347 iobase = object_property_get_int(obj, "iobase", &local_err);
348 if (local_err || iobase != 0x3f0) {
349 error_free(local_err);
350 return 0;
353 if (state->floppy) {
354 state->multiple = true;
355 } else {
356 state->floppy = ISA_DEVICE(obj);
358 return 0;
361 static const char * const fdc_container_path[] = {
362 "/unattached", "/peripheral", "/peripheral-anon"
366 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
367 * and ACPI objects.
369 ISADevice *pc_find_fdc0(void)
371 int i;
372 Object *container;
373 CheckFdcState state = { 0 };
375 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
376 container = container_get(qdev_get_machine(), fdc_container_path[i]);
377 object_child_foreach(container, check_fdc, &state);
380 if (state.multiple) {
381 error_report("warning: multiple floppy disk controllers with "
382 "iobase=0x3f0 have been found");
383 error_printf("the one being picked for CMOS setup might not reflect "
384 "your intent");
387 return state.floppy;
390 static void pc_cmos_init_late(void *opaque)
392 pc_cmos_init_late_arg *arg = opaque;
393 ISADevice *s = arg->rtc_state;
394 int16_t cylinders;
395 int8_t heads, sectors;
396 int val;
397 int i, trans;
399 val = 0;
400 if (ide_get_geometry(arg->idebus[0], 0,
401 &cylinders, &heads, &sectors) >= 0) {
402 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
403 val |= 0xf0;
405 if (ide_get_geometry(arg->idebus[0], 1,
406 &cylinders, &heads, &sectors) >= 0) {
407 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
408 val |= 0x0f;
410 rtc_set_memory(s, 0x12, val);
412 val = 0;
413 for (i = 0; i < 4; i++) {
414 /* NOTE: ide_get_geometry() returns the physical
415 geometry. It is always such that: 1 <= sects <= 63, 1
416 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
417 geometry can be different if a translation is done. */
418 if (ide_get_geometry(arg->idebus[i / 2], i % 2,
419 &cylinders, &heads, &sectors) >= 0) {
420 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
421 assert((trans & ~3) == 0);
422 val |= trans << (i * 2);
425 rtc_set_memory(s, 0x39, val);
427 pc_cmos_init_floppy(s, pc_find_fdc0());
429 qemu_unregister_reset(pc_cmos_init_late, opaque);
432 void pc_cmos_init(PCMachineState *pcms,
433 BusState *idebus0, BusState *idebus1,
434 ISADevice *s)
436 int val;
437 static pc_cmos_init_late_arg arg;
439 /* various important CMOS locations needed by PC/Bochs bios */
441 /* memory size */
442 /* base memory (first MiB) */
443 val = MIN(pcms->below_4g_mem_size / 1024, 640);
444 rtc_set_memory(s, 0x15, val);
445 rtc_set_memory(s, 0x16, val >> 8);
446 /* extended memory (next 64MiB) */
447 if (pcms->below_4g_mem_size > 1024 * 1024) {
448 val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024;
449 } else {
450 val = 0;
452 if (val > 65535)
453 val = 65535;
454 rtc_set_memory(s, 0x17, val);
455 rtc_set_memory(s, 0x18, val >> 8);
456 rtc_set_memory(s, 0x30, val);
457 rtc_set_memory(s, 0x31, val >> 8);
458 /* memory between 16MiB and 4GiB */
459 if (pcms->below_4g_mem_size > 16 * 1024 * 1024) {
460 val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536;
461 } else {
462 val = 0;
464 if (val > 65535)
465 val = 65535;
466 rtc_set_memory(s, 0x34, val);
467 rtc_set_memory(s, 0x35, val >> 8);
468 /* memory above 4GiB */
469 val = pcms->above_4g_mem_size / 65536;
470 rtc_set_memory(s, 0x5b, val);
471 rtc_set_memory(s, 0x5c, val >> 8);
472 rtc_set_memory(s, 0x5d, val >> 16);
474 /* set the number of CPU */
475 rtc_set_memory(s, 0x5f, smp_cpus - 1);
477 object_property_add_link(OBJECT(pcms), "rtc_state",
478 TYPE_ISA_DEVICE,
479 (Object **)&pcms->rtc,
480 object_property_allow_set_link,
481 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
482 object_property_set_link(OBJECT(pcms), OBJECT(s),
483 "rtc_state", &error_abort);
485 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
487 val = 0;
488 val |= 0x02; /* FPU is there */
489 val |= 0x04; /* PS/2 mouse installed */
490 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
492 /* hard drives and FDC */
493 arg.rtc_state = s;
494 arg.idebus[0] = idebus0;
495 arg.idebus[1] = idebus1;
496 qemu_register_reset(pc_cmos_init_late, &arg);
499 #define TYPE_PORT92 "port92"
500 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
502 /* port 92 stuff: could be split off */
503 typedef struct Port92State {
504 ISADevice parent_obj;
506 MemoryRegion io;
507 uint8_t outport;
508 qemu_irq *a20_out;
509 } Port92State;
511 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
512 unsigned size)
514 Port92State *s = opaque;
515 int oldval = s->outport;
517 DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
518 s->outport = val;
519 qemu_set_irq(*s->a20_out, (val >> 1) & 1);
520 if ((val & 1) && !(oldval & 1)) {
521 qemu_system_reset_request();
525 static uint64_t port92_read(void *opaque, hwaddr addr,
526 unsigned size)
528 Port92State *s = opaque;
529 uint32_t ret;
531 ret = s->outport;
532 DPRINTF("port92: read 0x%02x\n", ret);
533 return ret;
536 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
538 Port92State *s = PORT92(dev);
540 s->a20_out = a20_out;
543 static const VMStateDescription vmstate_port92_isa = {
544 .name = "port92",
545 .version_id = 1,
546 .minimum_version_id = 1,
547 .fields = (VMStateField[]) {
548 VMSTATE_UINT8(outport, Port92State),
549 VMSTATE_END_OF_LIST()
553 static void port92_reset(DeviceState *d)
555 Port92State *s = PORT92(d);
557 s->outport &= ~1;
560 static const MemoryRegionOps port92_ops = {
561 .read = port92_read,
562 .write = port92_write,
563 .impl = {
564 .min_access_size = 1,
565 .max_access_size = 1,
567 .endianness = DEVICE_LITTLE_ENDIAN,
570 static void port92_initfn(Object *obj)
572 Port92State *s = PORT92(obj);
574 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
576 s->outport = 0;
579 static void port92_realizefn(DeviceState *dev, Error **errp)
581 ISADevice *isadev = ISA_DEVICE(dev);
582 Port92State *s = PORT92(dev);
584 isa_register_ioport(isadev, &s->io, 0x92);
587 static void port92_class_initfn(ObjectClass *klass, void *data)
589 DeviceClass *dc = DEVICE_CLASS(klass);
591 dc->realize = port92_realizefn;
592 dc->reset = port92_reset;
593 dc->vmsd = &vmstate_port92_isa;
595 * Reason: unlike ordinary ISA devices, this one needs additional
596 * wiring: its A20 output line needs to be wired up by
597 * port92_init().
599 dc->cannot_instantiate_with_device_add_yet = true;
602 static const TypeInfo port92_info = {
603 .name = TYPE_PORT92,
604 .parent = TYPE_ISA_DEVICE,
605 .instance_size = sizeof(Port92State),
606 .instance_init = port92_initfn,
607 .class_init = port92_class_initfn,
610 static void port92_register_types(void)
612 type_register_static(&port92_info);
615 type_init(port92_register_types)
617 static void handle_a20_line_change(void *opaque, int irq, int level)
619 X86CPU *cpu = opaque;
621 /* XXX: send to all CPUs ? */
622 /* XXX: add logic to handle multiple A20 line sources */
623 x86_cpu_set_a20(cpu, level);
626 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
628 int index = le32_to_cpu(e820_reserve.count);
629 struct e820_entry *entry;
631 if (type != E820_RAM) {
632 /* old FW_CFG_E820_TABLE entry -- reservations only */
633 if (index >= E820_NR_ENTRIES) {
634 return -EBUSY;
636 entry = &e820_reserve.entry[index++];
638 entry->address = cpu_to_le64(address);
639 entry->length = cpu_to_le64(length);
640 entry->type = cpu_to_le32(type);
642 e820_reserve.count = cpu_to_le32(index);
645 /* new "etc/e820" file -- include ram too */
646 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
647 e820_table[e820_entries].address = cpu_to_le64(address);
648 e820_table[e820_entries].length = cpu_to_le64(length);
649 e820_table[e820_entries].type = cpu_to_le32(type);
650 e820_entries++;
652 return e820_entries;
655 int e820_get_num_entries(void)
657 return e820_entries;
660 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
662 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
663 *address = le64_to_cpu(e820_table[idx].address);
664 *length = le64_to_cpu(e820_table[idx].length);
665 return true;
667 return false;
670 /* Enables contiguous-apic-ID mode, for compatibility */
671 static bool compat_apic_id_mode;
673 void enable_compat_apic_id_mode(void)
675 compat_apic_id_mode = true;
678 /* Calculates initial APIC ID for a specific CPU index
680 * Currently we need to be able to calculate the APIC ID from the CPU index
681 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
682 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
683 * all CPUs up to max_cpus.
685 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
687 uint32_t correct_id;
688 static bool warned;
690 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
691 if (compat_apic_id_mode) {
692 if (cpu_index != correct_id && !warned && !qtest_enabled()) {
693 error_report("APIC IDs set in compatibility mode, "
694 "CPU topology won't match the configuration");
695 warned = true;
697 return cpu_index;
698 } else {
699 return correct_id;
703 static void pc_build_smbios(FWCfgState *fw_cfg)
705 uint8_t *smbios_tables, *smbios_anchor;
706 size_t smbios_tables_len, smbios_anchor_len;
707 struct smbios_phys_mem_area *mem_array;
708 unsigned i, array_count;
710 smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
711 if (smbios_tables) {
712 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
713 smbios_tables, smbios_tables_len);
716 /* build the array of physical mem area from e820 table */
717 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
718 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
719 uint64_t addr, len;
721 if (e820_get_entry(i, E820_RAM, &addr, &len)) {
722 mem_array[array_count].address = addr;
723 mem_array[array_count].length = len;
724 array_count++;
727 smbios_get_tables(mem_array, array_count,
728 &smbios_tables, &smbios_tables_len,
729 &smbios_anchor, &smbios_anchor_len);
730 g_free(mem_array);
732 if (smbios_anchor) {
733 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
734 smbios_tables, smbios_tables_len);
735 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
736 smbios_anchor, smbios_anchor_len);
740 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
742 FWCfgState *fw_cfg;
743 uint64_t *numa_fw_cfg;
744 int i, j;
746 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
748 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
750 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
751 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
752 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
753 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
754 * may see".
756 * So, this means we must not use max_cpus, here, but the maximum possible
757 * APIC ID value, plus one.
759 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
760 * the APIC ID, not the "CPU index"
762 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
763 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
764 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
765 acpi_tables, acpi_tables_len);
766 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
768 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
769 &e820_reserve, sizeof(e820_reserve));
770 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
771 sizeof(struct e820_entry) * e820_entries);
773 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
774 /* allocate memory for the NUMA channel: one (64bit) word for the number
775 * of nodes, one word for each VCPU->node and one word for each node to
776 * hold the amount of memory.
778 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
779 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
780 for (i = 0; i < max_cpus; i++) {
781 unsigned int apic_id = x86_cpu_apic_id_from_index(i);
782 assert(apic_id < pcms->apic_id_limit);
783 for (j = 0; j < nb_numa_nodes; j++) {
784 if (test_bit(i, numa_info[j].node_cpu)) {
785 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j);
786 break;
790 for (i = 0; i < nb_numa_nodes; i++) {
791 numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
792 cpu_to_le64(numa_info[i].node_mem);
794 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
795 (1 + pcms->apic_id_limit + nb_numa_nodes) *
796 sizeof(*numa_fw_cfg));
798 return fw_cfg;
801 static long get_file_size(FILE *f)
803 long where, size;
805 /* XXX: on Unix systems, using fstat() probably makes more sense */
807 where = ftell(f);
808 fseek(f, 0, SEEK_END);
809 size = ftell(f);
810 fseek(f, where, SEEK_SET);
812 return size;
815 static void load_linux(PCMachineState *pcms,
816 FWCfgState *fw_cfg)
818 uint16_t protocol;
819 int setup_size, kernel_size, initrd_size = 0, cmdline_size;
820 uint32_t initrd_max;
821 uint8_t header[8192], *setup, *kernel, *initrd_data;
822 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
823 FILE *f;
824 char *vmode;
825 MachineState *machine = MACHINE(pcms);
826 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
827 const char *kernel_filename = machine->kernel_filename;
828 const char *initrd_filename = machine->initrd_filename;
829 const char *kernel_cmdline = machine->kernel_cmdline;
831 /* Align to 16 bytes as a paranoia measure */
832 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
834 /* load the kernel header */
835 f = fopen(kernel_filename, "rb");
836 if (!f || !(kernel_size = get_file_size(f)) ||
837 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
838 MIN(ARRAY_SIZE(header), kernel_size)) {
839 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
840 kernel_filename, strerror(errno));
841 exit(1);
844 /* kernel protocol version */
845 #if 0
846 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
847 #endif
848 if (ldl_p(header+0x202) == 0x53726448) {
849 protocol = lduw_p(header+0x206);
850 } else {
851 /* This looks like a multiboot kernel. If it is, let's stop
852 treating it like a Linux kernel. */
853 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
854 kernel_cmdline, kernel_size, header)) {
855 return;
857 protocol = 0;
860 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
861 /* Low kernel */
862 real_addr = 0x90000;
863 cmdline_addr = 0x9a000 - cmdline_size;
864 prot_addr = 0x10000;
865 } else if (protocol < 0x202) {
866 /* High but ancient kernel */
867 real_addr = 0x90000;
868 cmdline_addr = 0x9a000 - cmdline_size;
869 prot_addr = 0x100000;
870 } else {
871 /* High and recent kernel */
872 real_addr = 0x10000;
873 cmdline_addr = 0x20000;
874 prot_addr = 0x100000;
877 #if 0
878 fprintf(stderr,
879 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
880 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
881 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
882 real_addr,
883 cmdline_addr,
884 prot_addr);
885 #endif
887 /* highest address for loading the initrd */
888 if (protocol >= 0x203) {
889 initrd_max = ldl_p(header+0x22c);
890 } else {
891 initrd_max = 0x37ffffff;
894 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
895 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
898 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
899 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
900 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
902 if (protocol >= 0x202) {
903 stl_p(header+0x228, cmdline_addr);
904 } else {
905 stw_p(header+0x20, 0xA33F);
906 stw_p(header+0x22, cmdline_addr-real_addr);
909 /* handle vga= parameter */
910 vmode = strstr(kernel_cmdline, "vga=");
911 if (vmode) {
912 unsigned int video_mode;
913 /* skip "vga=" */
914 vmode += 4;
915 if (!strncmp(vmode, "normal", 6)) {
916 video_mode = 0xffff;
917 } else if (!strncmp(vmode, "ext", 3)) {
918 video_mode = 0xfffe;
919 } else if (!strncmp(vmode, "ask", 3)) {
920 video_mode = 0xfffd;
921 } else {
922 video_mode = strtol(vmode, NULL, 0);
924 stw_p(header+0x1fa, video_mode);
927 /* loader type */
928 /* High nybble = B reserved for QEMU; low nybble is revision number.
929 If this code is substantially changed, you may want to consider
930 incrementing the revision. */
931 if (protocol >= 0x200) {
932 header[0x210] = 0xB0;
934 /* heap */
935 if (protocol >= 0x201) {
936 header[0x211] |= 0x80; /* CAN_USE_HEAP */
937 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
940 /* load initrd */
941 if (initrd_filename) {
942 if (protocol < 0x200) {
943 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
944 exit(1);
947 initrd_size = get_image_size(initrd_filename);
948 if (initrd_size < 0) {
949 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
950 initrd_filename, strerror(errno));
951 exit(1);
954 initrd_addr = (initrd_max-initrd_size) & ~4095;
956 initrd_data = g_malloc(initrd_size);
957 load_image(initrd_filename, initrd_data);
959 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
960 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
961 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
963 stl_p(header+0x218, initrd_addr);
964 stl_p(header+0x21c, initrd_size);
967 /* load kernel and setup */
968 setup_size = header[0x1f1];
969 if (setup_size == 0) {
970 setup_size = 4;
972 setup_size = (setup_size+1)*512;
973 if (setup_size > kernel_size) {
974 fprintf(stderr, "qemu: invalid kernel header\n");
975 exit(1);
977 kernel_size -= setup_size;
979 setup = g_malloc(setup_size);
980 kernel = g_malloc(kernel_size);
981 fseek(f, 0, SEEK_SET);
982 if (fread(setup, 1, setup_size, f) != setup_size) {
983 fprintf(stderr, "fread() failed\n");
984 exit(1);
986 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
987 fprintf(stderr, "fread() failed\n");
988 exit(1);
990 fclose(f);
991 memcpy(setup, header, MIN(sizeof(header), setup_size));
993 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
994 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
995 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
997 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
998 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
999 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1001 option_rom[nb_option_roms].name = "linuxboot.bin";
1002 option_rom[nb_option_roms].bootindex = 0;
1003 nb_option_roms++;
1006 #define NE2000_NB_MAX 6
1008 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1009 0x280, 0x380 };
1010 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1012 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
1014 static int nb_ne2k = 0;
1016 if (nb_ne2k == NE2000_NB_MAX)
1017 return;
1018 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
1019 ne2000_irq[nb_ne2k], nd);
1020 nb_ne2k++;
1023 DeviceState *cpu_get_current_apic(void)
1025 if (current_cpu) {
1026 X86CPU *cpu = X86_CPU(current_cpu);
1027 return cpu->apic_state;
1028 } else {
1029 return NULL;
1033 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
1035 X86CPU *cpu = opaque;
1037 if (level) {
1038 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
1042 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id,
1043 Error **errp)
1045 X86CPU *cpu = NULL;
1046 Error *local_err = NULL;
1048 cpu = cpu_x86_create(cpu_model, &local_err);
1049 if (local_err != NULL) {
1050 goto out;
1053 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err);
1054 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
1056 out:
1057 if (local_err) {
1058 error_propagate(errp, local_err);
1059 object_unref(OBJECT(cpu));
1060 cpu = NULL;
1062 return cpu;
1065 void pc_hot_add_cpu(const int64_t id, Error **errp)
1067 X86CPU *cpu;
1068 MachineState *machine = MACHINE(qdev_get_machine());
1069 int64_t apic_id = x86_cpu_apic_id_from_index(id);
1070 Error *local_err = NULL;
1072 if (id < 0) {
1073 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1074 return;
1077 if (cpu_exists(apic_id)) {
1078 error_setg(errp, "Unable to add CPU: %" PRIi64
1079 ", it already exists", id);
1080 return;
1083 if (id >= max_cpus) {
1084 error_setg(errp, "Unable to add CPU: %" PRIi64
1085 ", max allowed: %d", id, max_cpus - 1);
1086 return;
1089 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1090 error_setg(errp, "Unable to add CPU: %" PRIi64
1091 ", resulting APIC ID (%" PRIi64 ") is too large",
1092 id, apic_id);
1093 return;
1096 cpu = pc_new_cpu(machine->cpu_model, apic_id, &local_err);
1097 if (local_err) {
1098 error_propagate(errp, local_err);
1099 return;
1101 object_unref(OBJECT(cpu));
1104 void pc_cpus_init(PCMachineState *pcms)
1106 int i;
1107 X86CPU *cpu = NULL;
1108 MachineState *machine = MACHINE(pcms);
1110 /* init CPUs */
1111 if (machine->cpu_model == NULL) {
1112 #ifdef TARGET_X86_64
1113 machine->cpu_model = "qemu64";
1114 #else
1115 machine->cpu_model = "qemu32";
1116 #endif
1119 /* Calculates the limit to CPU APIC ID values
1121 * Limit for the APIC ID value, so that all
1122 * CPU APIC IDs are < pcms->apic_id_limit.
1124 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1126 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
1127 if (pcms->apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) {
1128 error_report("max_cpus is too large. APIC ID of last CPU is %u",
1129 pcms->apic_id_limit - 1);
1130 exit(1);
1133 pcms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
1134 sizeof(CPUArchId) * max_cpus);
1135 for (i = 0; i < max_cpus; i++) {
1136 pcms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
1137 pcms->possible_cpus->len++;
1138 if (i < smp_cpus) {
1139 cpu = pc_new_cpu(machine->cpu_model, x86_cpu_apic_id_from_index(i),
1140 &error_fatal);
1141 pcms->possible_cpus->cpus[i].cpu = CPU(cpu);
1142 object_unref(OBJECT(cpu));
1146 /* tell smbios about cpuid version and features */
1147 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
1150 static
1151 void pc_machine_done(Notifier *notifier, void *data)
1153 PCMachineState *pcms = container_of(notifier,
1154 PCMachineState, machine_done);
1155 PCIBus *bus = pcms->bus;
1157 if (bus) {
1158 int extra_hosts = 0;
1160 QLIST_FOREACH(bus, &bus->child, sibling) {
1161 /* look for expander root buses */
1162 if (pci_bus_is_root(bus)) {
1163 extra_hosts++;
1166 if (extra_hosts && pcms->fw_cfg) {
1167 uint64_t *val = g_malloc(sizeof(*val));
1168 *val = cpu_to_le64(extra_hosts);
1169 fw_cfg_add_file(pcms->fw_cfg,
1170 "etc/extra-pci-roots", val, sizeof(*val));
1174 acpi_setup();
1175 if (pcms->fw_cfg) {
1176 pc_build_smbios(pcms->fw_cfg);
1180 void pc_guest_info_init(PCMachineState *pcms)
1182 int i, j;
1184 pcms->apic_xrupt_override = kvm_allows_irq0_override();
1185 pcms->numa_nodes = nb_numa_nodes;
1186 pcms->node_mem = g_malloc0(pcms->numa_nodes *
1187 sizeof *pcms->node_mem);
1188 for (i = 0; i < nb_numa_nodes; i++) {
1189 pcms->node_mem[i] = numa_info[i].node_mem;
1192 pcms->node_cpu = g_malloc0(pcms->apic_id_limit *
1193 sizeof *pcms->node_cpu);
1195 for (i = 0; i < max_cpus; i++) {
1196 unsigned int apic_id = x86_cpu_apic_id_from_index(i);
1197 assert(apic_id < pcms->apic_id_limit);
1198 for (j = 0; j < nb_numa_nodes; j++) {
1199 if (test_bit(i, numa_info[j].node_cpu)) {
1200 pcms->node_cpu[apic_id] = j;
1201 break;
1206 pcms->machine_done.notify = pc_machine_done;
1207 qemu_add_machine_init_done_notifier(&pcms->machine_done);
1210 /* setup pci memory address space mapping into system address space */
1211 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1212 MemoryRegion *pci_address_space)
1214 /* Set to lower priority than RAM */
1215 memory_region_add_subregion_overlap(system_memory, 0x0,
1216 pci_address_space, -1);
1219 void pc_acpi_init(const char *default_dsdt)
1221 char *filename;
1223 if (acpi_tables != NULL) {
1224 /* manually set via -acpitable, leave it alone */
1225 return;
1228 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1229 if (filename == NULL) {
1230 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt);
1231 } else {
1232 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0,
1233 &error_abort);
1234 Error *err = NULL;
1236 qemu_opt_set(opts, "file", filename, &error_abort);
1238 acpi_table_add_builtin(opts, &err);
1239 if (err) {
1240 error_reportf_err(err, "WARNING: failed to load %s: ",
1241 filename);
1243 g_free(filename);
1247 void xen_load_linux(PCMachineState *pcms)
1249 int i;
1250 FWCfgState *fw_cfg;
1252 assert(MACHINE(pcms)->kernel_filename != NULL);
1254 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
1255 rom_set_fw(fw_cfg);
1257 load_linux(pcms, fw_cfg);
1258 for (i = 0; i < nb_option_roms; i++) {
1259 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1260 !strcmp(option_rom[i].name, "multiboot.bin"));
1261 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1263 pcms->fw_cfg = fw_cfg;
1266 void pc_memory_init(PCMachineState *pcms,
1267 MemoryRegion *system_memory,
1268 MemoryRegion *rom_memory,
1269 MemoryRegion **ram_memory)
1271 int linux_boot, i;
1272 MemoryRegion *ram, *option_rom_mr;
1273 MemoryRegion *ram_below_4g, *ram_above_4g;
1274 FWCfgState *fw_cfg;
1275 MachineState *machine = MACHINE(pcms);
1276 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1278 assert(machine->ram_size == pcms->below_4g_mem_size +
1279 pcms->above_4g_mem_size);
1281 linux_boot = (machine->kernel_filename != NULL);
1283 /* Allocate RAM. We allocate it as a single memory region and use
1284 * aliases to address portions of it, mostly for backwards compatibility
1285 * with older qemus that used qemu_ram_alloc().
1287 ram = g_malloc(sizeof(*ram));
1288 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1289 machine->ram_size);
1290 *ram_memory = ram;
1291 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1292 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1293 0, pcms->below_4g_mem_size);
1294 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1295 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
1296 if (pcms->above_4g_mem_size > 0) {
1297 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1298 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1299 pcms->below_4g_mem_size,
1300 pcms->above_4g_mem_size);
1301 memory_region_add_subregion(system_memory, 0x100000000ULL,
1302 ram_above_4g);
1303 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
1306 if (!pcmc->has_reserved_memory &&
1307 (machine->ram_slots ||
1308 (machine->maxram_size > machine->ram_size))) {
1309 MachineClass *mc = MACHINE_GET_CLASS(machine);
1311 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1312 mc->name);
1313 exit(EXIT_FAILURE);
1316 /* initialize hotplug memory address space */
1317 if (pcmc->has_reserved_memory &&
1318 (machine->ram_size < machine->maxram_size)) {
1319 ram_addr_t hotplug_mem_size =
1320 machine->maxram_size - machine->ram_size;
1322 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1323 error_report("unsupported amount of memory slots: %"PRIu64,
1324 machine->ram_slots);
1325 exit(EXIT_FAILURE);
1328 if (QEMU_ALIGN_UP(machine->maxram_size,
1329 TARGET_PAGE_SIZE) != machine->maxram_size) {
1330 error_report("maximum memory size must by aligned to multiple of "
1331 "%d bytes", TARGET_PAGE_SIZE);
1332 exit(EXIT_FAILURE);
1335 pcms->hotplug_memory.base =
1336 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30);
1338 if (pcmc->enforce_aligned_dimm) {
1339 /* size hotplug region assuming 1G page max alignment per slot */
1340 hotplug_mem_size += (1ULL << 30) * machine->ram_slots;
1343 if ((pcms->hotplug_memory.base + hotplug_mem_size) <
1344 hotplug_mem_size) {
1345 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1346 machine->maxram_size);
1347 exit(EXIT_FAILURE);
1350 memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms),
1351 "hotplug-memory", hotplug_mem_size);
1352 memory_region_add_subregion(system_memory, pcms->hotplug_memory.base,
1353 &pcms->hotplug_memory.mr);
1356 /* Initialize PC system firmware */
1357 pc_system_firmware_init(rom_memory, !pcmc->pci_enabled);
1359 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1360 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1361 &error_fatal);
1362 vmstate_register_ram_global(option_rom_mr);
1363 memory_region_add_subregion_overlap(rom_memory,
1364 PC_ROM_MIN_VGA,
1365 option_rom_mr,
1368 fw_cfg = bochs_bios_init(&address_space_memory, pcms);
1370 rom_set_fw(fw_cfg);
1372 if (pcmc->has_reserved_memory && pcms->hotplug_memory.base) {
1373 uint64_t *val = g_malloc(sizeof(*val));
1374 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1375 uint64_t res_mem_end = pcms->hotplug_memory.base;
1377 if (!pcmc->broken_reserved_end) {
1378 res_mem_end += memory_region_size(&pcms->hotplug_memory.mr);
1380 *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30));
1381 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1384 if (linux_boot) {
1385 load_linux(pcms, fw_cfg);
1388 for (i = 0; i < nb_option_roms; i++) {
1389 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1391 pcms->fw_cfg = fw_cfg;
1394 qemu_irq pc_allocate_cpu_irq(void)
1396 return qemu_allocate_irq(pic_irq_request, NULL, 0);
1399 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1401 DeviceState *dev = NULL;
1403 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1404 if (pci_bus) {
1405 PCIDevice *pcidev = pci_vga_init(pci_bus);
1406 dev = pcidev ? &pcidev->qdev : NULL;
1407 } else if (isa_bus) {
1408 ISADevice *isadev = isa_vga_init(isa_bus);
1409 dev = isadev ? DEVICE(isadev) : NULL;
1411 rom_reset_order_override();
1412 return dev;
1415 static const MemoryRegionOps ioport80_io_ops = {
1416 .write = ioport80_write,
1417 .read = ioport80_read,
1418 .endianness = DEVICE_NATIVE_ENDIAN,
1419 .impl = {
1420 .min_access_size = 1,
1421 .max_access_size = 1,
1425 static const MemoryRegionOps ioportF0_io_ops = {
1426 .write = ioportF0_write,
1427 .read = ioportF0_read,
1428 .endianness = DEVICE_NATIVE_ENDIAN,
1429 .impl = {
1430 .min_access_size = 1,
1431 .max_access_size = 1,
1435 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1436 ISADevice **rtc_state,
1437 bool create_fdctrl,
1438 bool no_vmport,
1439 uint32_t hpet_irqs)
1441 int i;
1442 DriveInfo *fd[MAX_FD];
1443 DeviceState *hpet = NULL;
1444 int pit_isa_irq = 0;
1445 qemu_irq pit_alt_irq = NULL;
1446 qemu_irq rtc_irq = NULL;
1447 qemu_irq *a20_line;
1448 ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1449 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1450 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1452 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1453 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1455 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1456 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1459 * Check if an HPET shall be created.
1461 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1462 * when the HPET wants to take over. Thus we have to disable the latter.
1464 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1465 /* In order to set property, here not using sysbus_try_create_simple */
1466 hpet = qdev_try_create(NULL, TYPE_HPET);
1467 if (hpet) {
1468 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1469 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1470 * IRQ8 and IRQ2.
1472 uint8_t compat = object_property_get_int(OBJECT(hpet),
1473 HPET_INTCAP, NULL);
1474 if (!compat) {
1475 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1477 qdev_init_nofail(hpet);
1478 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1480 for (i = 0; i < GSI_NUM_PINS; i++) {
1481 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1483 pit_isa_irq = -1;
1484 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1485 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1488 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1490 qemu_register_boot_set(pc_boot_set, *rtc_state);
1492 if (!xen_enabled()) {
1493 if (kvm_pit_in_kernel()) {
1494 pit = kvm_pit_init(isa_bus, 0x40);
1495 } else {
1496 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1498 if (hpet) {
1499 /* connect PIT to output control line of the HPET */
1500 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1502 pcspk_init(isa_bus, pit);
1505 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS);
1506 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1508 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1509 i8042 = isa_create_simple(isa_bus, "i8042");
1510 i8042_setup_a20_line(i8042, &a20_line[0]);
1511 if (!no_vmport) {
1512 vmport_init(isa_bus);
1513 vmmouse = isa_try_create(isa_bus, "vmmouse");
1514 } else {
1515 vmmouse = NULL;
1517 if (vmmouse) {
1518 DeviceState *dev = DEVICE(vmmouse);
1519 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1520 qdev_init_nofail(dev);
1522 port92 = isa_create_simple(isa_bus, "port92");
1523 port92_init(port92, &a20_line[1]);
1525 DMA_init(isa_bus, 0);
1527 for(i = 0; i < MAX_FD; i++) {
1528 fd[i] = drive_get(IF_FLOPPY, 0, i);
1529 create_fdctrl |= !!fd[i];
1531 if (create_fdctrl) {
1532 fdctrl_init_isa(isa_bus, fd);
1536 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
1538 int i;
1540 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1541 for (i = 0; i < nb_nics; i++) {
1542 NICInfo *nd = &nd_table[i];
1544 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
1545 pc_init_ne2k_isa(isa_bus, nd);
1546 } else {
1547 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL);
1550 rom_reset_order_override();
1553 void pc_pci_device_init(PCIBus *pci_bus)
1555 int max_bus;
1556 int bus;
1558 max_bus = drive_get_max_bus(IF_SCSI);
1559 for (bus = 0; bus <= max_bus; bus++) {
1560 pci_create_simple(pci_bus, -1, "lsi53c895a");
1564 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1566 DeviceState *dev;
1567 SysBusDevice *d;
1568 unsigned int i;
1570 if (kvm_ioapic_in_kernel()) {
1571 dev = qdev_create(NULL, "kvm-ioapic");
1572 } else {
1573 dev = qdev_create(NULL, "ioapic");
1575 if (parent_name) {
1576 object_property_add_child(object_resolve_path(parent_name, NULL),
1577 "ioapic", OBJECT(dev), NULL);
1579 qdev_init_nofail(dev);
1580 d = SYS_BUS_DEVICE(dev);
1581 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1583 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1584 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1588 static void pc_dimm_plug(HotplugHandler *hotplug_dev,
1589 DeviceState *dev, Error **errp)
1591 HotplugHandlerClass *hhc;
1592 Error *local_err = NULL;
1593 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1594 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1595 PCDIMMDevice *dimm = PC_DIMM(dev);
1596 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
1597 MemoryRegion *mr = ddc->get_memory_region(dimm);
1598 uint64_t align = TARGET_PAGE_SIZE;
1600 if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) {
1601 align = memory_region_get_alignment(mr);
1604 if (!pcms->acpi_dev) {
1605 error_setg(&local_err,
1606 "memory hotplug is not enabled: missing acpi device");
1607 goto out;
1610 pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err);
1611 if (local_err) {
1612 goto out;
1615 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1616 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1617 out:
1618 error_propagate(errp, local_err);
1621 static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev,
1622 DeviceState *dev, Error **errp)
1624 HotplugHandlerClass *hhc;
1625 Error *local_err = NULL;
1626 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1628 if (!pcms->acpi_dev) {
1629 error_setg(&local_err,
1630 "memory hotplug is not enabled: missing acpi device");
1631 goto out;
1634 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1635 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1637 out:
1638 error_propagate(errp, local_err);
1641 static void pc_dimm_unplug(HotplugHandler *hotplug_dev,
1642 DeviceState *dev, Error **errp)
1644 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1645 PCDIMMDevice *dimm = PC_DIMM(dev);
1646 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
1647 MemoryRegion *mr = ddc->get_memory_region(dimm);
1648 HotplugHandlerClass *hhc;
1649 Error *local_err = NULL;
1651 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1652 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1654 if (local_err) {
1655 goto out;
1658 pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr);
1659 object_unparent(OBJECT(dev));
1661 out:
1662 error_propagate(errp, local_err);
1665 static int pc_apic_cmp(const void *a, const void *b)
1667 CPUArchId *apic_a = (CPUArchId *)a;
1668 CPUArchId *apic_b = (CPUArchId *)b;
1670 return apic_a->arch_id - apic_b->arch_id;
1673 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1674 DeviceState *dev, Error **errp)
1676 CPUClass *cc = CPU_GET_CLASS(dev);
1677 CPUArchId apic_id, *found_cpu;
1678 HotplugHandlerClass *hhc;
1679 Error *local_err = NULL;
1680 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1682 if (!dev->hotplugged) {
1683 goto out;
1686 if (!pcms->acpi_dev) {
1687 error_setg(&local_err,
1688 "cpu hotplug is not enabled: missing acpi device");
1689 goto out;
1692 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1693 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1694 if (local_err) {
1695 goto out;
1698 /* increment the number of CPUs */
1699 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1);
1701 apic_id.arch_id = cc->get_arch_id(CPU(dev));
1702 found_cpu = bsearch(&apic_id, pcms->possible_cpus->cpus,
1703 pcms->possible_cpus->len, sizeof(*pcms->possible_cpus->cpus),
1704 pc_apic_cmp);
1705 assert(found_cpu);
1706 found_cpu->cpu = CPU(dev);
1707 out:
1708 error_propagate(errp, local_err);
1711 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1712 DeviceState *dev, Error **errp)
1714 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1715 pc_dimm_plug(hotplug_dev, dev, errp);
1716 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1717 pc_cpu_plug(hotplug_dev, dev, errp);
1721 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1722 DeviceState *dev, Error **errp)
1724 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1725 pc_dimm_unplug_request(hotplug_dev, dev, errp);
1726 } else {
1727 error_setg(errp, "acpi: device unplug request for not supported device"
1728 " type: %s", object_get_typename(OBJECT(dev)));
1732 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1733 DeviceState *dev, Error **errp)
1735 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1736 pc_dimm_unplug(hotplug_dev, dev, errp);
1737 } else {
1738 error_setg(errp, "acpi: device unplug for not supported device"
1739 " type: %s", object_get_typename(OBJECT(dev)));
1743 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine,
1744 DeviceState *dev)
1746 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1748 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1749 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1750 return HOTPLUG_HANDLER(machine);
1753 return pcmc->get_hotplug_handler ?
1754 pcmc->get_hotplug_handler(machine, dev) : NULL;
1757 static void
1758 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v,
1759 const char *name, void *opaque,
1760 Error **errp)
1762 PCMachineState *pcms = PC_MACHINE(obj);
1763 int64_t value = memory_region_size(&pcms->hotplug_memory.mr);
1765 visit_type_int(v, name, &value, errp);
1768 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1769 const char *name, void *opaque,
1770 Error **errp)
1772 PCMachineState *pcms = PC_MACHINE(obj);
1773 uint64_t value = pcms->max_ram_below_4g;
1775 visit_type_size(v, name, &value, errp);
1778 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1779 const char *name, void *opaque,
1780 Error **errp)
1782 PCMachineState *pcms = PC_MACHINE(obj);
1783 Error *error = NULL;
1784 uint64_t value;
1786 visit_type_size(v, name, &value, &error);
1787 if (error) {
1788 error_propagate(errp, error);
1789 return;
1791 if (value > (1ULL << 32)) {
1792 error_setg(&error,
1793 "Machine option 'max-ram-below-4g=%"PRIu64
1794 "' expects size less than or equal to 4G", value);
1795 error_propagate(errp, error);
1796 return;
1799 if (value < (1ULL << 20)) {
1800 error_report("Warning: small max_ram_below_4g(%"PRIu64
1801 ") less than 1M. BIOS may not work..",
1802 value);
1805 pcms->max_ram_below_4g = value;
1808 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1809 void *opaque, Error **errp)
1811 PCMachineState *pcms = PC_MACHINE(obj);
1812 OnOffAuto vmport = pcms->vmport;
1814 visit_type_OnOffAuto(v, name, &vmport, errp);
1817 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1818 void *opaque, Error **errp)
1820 PCMachineState *pcms = PC_MACHINE(obj);
1822 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1825 bool pc_machine_is_smm_enabled(PCMachineState *pcms)
1827 bool smm_available = false;
1829 if (pcms->smm == ON_OFF_AUTO_OFF) {
1830 return false;
1833 if (tcg_enabled() || qtest_enabled()) {
1834 smm_available = true;
1835 } else if (kvm_enabled()) {
1836 smm_available = kvm_has_smm();
1839 if (smm_available) {
1840 return true;
1843 if (pcms->smm == ON_OFF_AUTO_ON) {
1844 error_report("System Management Mode not supported by this hypervisor.");
1845 exit(1);
1847 return false;
1850 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
1851 void *opaque, Error **errp)
1853 PCMachineState *pcms = PC_MACHINE(obj);
1854 OnOffAuto smm = pcms->smm;
1856 visit_type_OnOffAuto(v, name, &smm, errp);
1859 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
1860 void *opaque, Error **errp)
1862 PCMachineState *pcms = PC_MACHINE(obj);
1864 visit_type_OnOffAuto(v, name, &pcms->smm, errp);
1867 static bool pc_machine_get_nvdimm(Object *obj, Error **errp)
1869 PCMachineState *pcms = PC_MACHINE(obj);
1871 return pcms->acpi_nvdimm_state.is_enabled;
1874 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp)
1876 PCMachineState *pcms = PC_MACHINE(obj);
1878 pcms->acpi_nvdimm_state.is_enabled = value;
1881 static void pc_machine_initfn(Object *obj)
1883 PCMachineState *pcms = PC_MACHINE(obj);
1885 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int",
1886 pc_machine_get_hotplug_memory_region_size,
1887 NULL, NULL, NULL, &error_abort);
1889 pcms->max_ram_below_4g = 0xe0000000; /* 3.5G */
1890 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1891 pc_machine_get_max_ram_below_4g,
1892 pc_machine_set_max_ram_below_4g,
1893 NULL, NULL, &error_abort);
1894 object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G,
1895 "Maximum ram below the 4G boundary (32bit boundary)",
1896 &error_abort);
1898 pcms->smm = ON_OFF_AUTO_AUTO;
1899 object_property_add(obj, PC_MACHINE_SMM, "OnOffAuto",
1900 pc_machine_get_smm,
1901 pc_machine_set_smm,
1902 NULL, NULL, &error_abort);
1903 object_property_set_description(obj, PC_MACHINE_SMM,
1904 "Enable SMM (pc & q35)",
1905 &error_abort);
1907 pcms->vmport = ON_OFF_AUTO_AUTO;
1908 object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto",
1909 pc_machine_get_vmport,
1910 pc_machine_set_vmport,
1911 NULL, NULL, &error_abort);
1912 object_property_set_description(obj, PC_MACHINE_VMPORT,
1913 "Enable vmport (pc & q35)",
1914 &error_abort);
1916 /* nvdimm is disabled on default. */
1917 pcms->acpi_nvdimm_state.is_enabled = false;
1918 object_property_add_bool(obj, PC_MACHINE_NVDIMM, pc_machine_get_nvdimm,
1919 pc_machine_set_nvdimm, &error_abort);
1922 static void pc_machine_reset(void)
1924 CPUState *cs;
1925 X86CPU *cpu;
1927 qemu_devices_reset();
1929 /* Reset APIC after devices have been reset to cancel
1930 * any changes that qemu_devices_reset() might have done.
1932 CPU_FOREACH(cs) {
1933 cpu = X86_CPU(cs);
1935 if (cpu->apic_state) {
1936 device_reset(cpu->apic_state);
1941 static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index)
1943 X86CPUTopoInfo topo;
1944 x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index,
1945 &topo);
1946 return topo.pkg_id;
1949 static CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *machine)
1951 PCMachineState *pcms = PC_MACHINE(machine);
1952 int len = sizeof(CPUArchIdList) +
1953 sizeof(CPUArchId) * (pcms->possible_cpus->len);
1954 CPUArchIdList *list = g_malloc(len);
1956 memcpy(list, pcms->possible_cpus, len);
1957 return list;
1960 static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
1962 /* cpu index isn't used */
1963 CPUState *cs;
1965 CPU_FOREACH(cs) {
1966 X86CPU *cpu = X86_CPU(cs);
1968 if (!cpu->apic_state) {
1969 cpu_interrupt(cs, CPU_INTERRUPT_NMI);
1970 } else {
1971 apic_deliver_nmi(cpu->apic_state);
1976 static void pc_machine_class_init(ObjectClass *oc, void *data)
1978 MachineClass *mc = MACHINE_CLASS(oc);
1979 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1980 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1981 NMIClass *nc = NMI_CLASS(oc);
1983 pcmc->get_hotplug_handler = mc->get_hotplug_handler;
1984 pcmc->pci_enabled = true;
1985 pcmc->has_acpi_build = true;
1986 pcmc->rsdp_in_ram = true;
1987 pcmc->smbios_defaults = true;
1988 pcmc->smbios_uuid_encoded = true;
1989 pcmc->gigabyte_align = true;
1990 pcmc->has_reserved_memory = true;
1991 pcmc->kvmclock_enabled = true;
1992 pcmc->enforce_aligned_dimm = true;
1993 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1994 * to be used at the moment, 32K should be enough for a while. */
1995 pcmc->acpi_data_size = 0x20000 + 0x8000;
1996 pcmc->save_tsc_khz = true;
1997 mc->get_hotplug_handler = pc_get_hotpug_handler;
1998 mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id;
1999 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
2000 mc->default_boot_order = "cad";
2001 mc->hot_add_cpu = pc_hot_add_cpu;
2002 mc->max_cpus = 255;
2003 mc->reset = pc_machine_reset;
2004 hc->plug = pc_machine_device_plug_cb;
2005 hc->unplug_request = pc_machine_device_unplug_request_cb;
2006 hc->unplug = pc_machine_device_unplug_cb;
2007 nc->nmi_monitor_handler = x86_nmi;
2010 static const TypeInfo pc_machine_info = {
2011 .name = TYPE_PC_MACHINE,
2012 .parent = TYPE_MACHINE,
2013 .abstract = true,
2014 .instance_size = sizeof(PCMachineState),
2015 .instance_init = pc_machine_initfn,
2016 .class_size = sizeof(PCMachineClass),
2017 .class_init = pc_machine_class_init,
2018 .interfaces = (InterfaceInfo[]) {
2019 { TYPE_HOTPLUG_HANDLER },
2020 { TYPE_NMI },
2025 static void pc_machine_register_types(void)
2027 type_register_static(&pc_machine_info);
2030 type_init(pc_machine_register_types)