target/microblaze/cpu.c

   1 /*
   2  * QEMU MicroBlaze CPU
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias
   5  * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  * Copyright (c) 2012 SUSE LINUX Products GmbH
   7  * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2.1 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see
  21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qemu/log.h"
  26 #include "qapi/error.h"
  27 #include "cpu.h"
  28 #include "qemu/module.h"
  29 #include "hw/qdev-properties.h"
  30 #include "exec/exec-all.h"
  31 #include "exec/gdbstub.h"
  32 #include "fpu/softfloat-helpers.h"
  33 #include "tcg/tcg.h"
  34
  35 static const struct {
  36     const char *name;
  37     uint8_t version_id;
  38 } mb_cpu_lookup[] = {
  39     /* These key value are as per MBV field in PVR0 */
  40     {"5.00.a", 0x01},
  41     {"5.00.b", 0x02},
  42     {"5.00.c", 0x03},
  43     {"6.00.a", 0x04},
  44     {"6.00.b", 0x06},
  45     {"7.00.a", 0x05},
  46     {"7.00.b", 0x07},
  47     {"7.10.a", 0x08},
  48     {"7.10.b", 0x09},
  49     {"7.10.c", 0x0a},
  50     {"7.10.d", 0x0b},
  51     {"7.20.a", 0x0c},
  52     {"7.20.b", 0x0d},
  53     {"7.20.c", 0x0e},
  54     {"7.20.d", 0x0f},
  55     {"7.30.a", 0x10},
  56     {"7.30.b", 0x11},
  57     {"8.00.a", 0x12},
  58     {"8.00.b", 0x13},
  59     {"8.10.a", 0x14},
  60     {"8.20.a", 0x15},
  61     {"8.20.b", 0x16},
  62     {"8.30.a", 0x17},
  63     {"8.40.a", 0x18},
  64     {"8.40.b", 0x19},
  65     {"8.50.a", 0x1A},
  66     {"9.0", 0x1B},
  67     {"9.1", 0x1D},
  68     {"9.2", 0x1F},
  69     {"9.3", 0x20},
  70     {"9.4", 0x21},
  71     {"9.5", 0x22},
  72     {"9.6", 0x23},
  73     {"10.0", 0x24},
  74     {NULL, 0},
  75 };
  76
  77 /* If no specific version gets selected, default to the following.  */
  78 #define DEFAULT_CPU_VERSION "10.0"
  79
  80 static void mb_cpu_set_pc(CPUState *cs, vaddr value)
  81 {
  82     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  83
  84     cpu->env.pc = value;
  85     /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */
  86     cpu->env.iflags = 0;
  87 }
  88
  89 static vaddr mb_cpu_get_pc(CPUState *cs)
  90 {
  91     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  92
  93     return cpu->env.pc;
  94 }
  95
  96 static void mb_cpu_synchronize_from_tb(CPUState *cs,
  97                                        const TranslationBlock *tb)
  98 {
  99     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 100
 101     tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
 102     cpu->env.pc = tb->pc;
 103     cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
 104 }
 105
 106 static void mb_restore_state_to_opc(CPUState *cs,
 107                                     const TranslationBlock *tb,
 108                                     const uint64_t *data)
 109 {
 110     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 111
 112     cpu->env.pc = data[0];
 113     cpu->env.iflags = data[1];
 114 }
 115
 116 static bool mb_cpu_has_work(CPUState *cs)
 117 {
 118     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
 119 }
 120
 121 #ifndef CONFIG_USER_ONLY
 122 static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level)
 123 {
 124     MicroBlazeCPU *cpu = opaque;
 125     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK;
 126
 127     cpu->ns_axi_dp = level & en;
 128 }
 129
 130 static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level)
 131 {
 132     MicroBlazeCPU *cpu = opaque;
 133     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK;
 134
 135     cpu->ns_axi_ip = level & en;
 136 }
 137
 138 static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level)
 139 {
 140     MicroBlazeCPU *cpu = opaque;
 141     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK;
 142
 143     cpu->ns_axi_dc = level & en;
 144 }
 145
 146 static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level)
 147 {
 148     MicroBlazeCPU *cpu = opaque;
 149     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK;
 150
 151     cpu->ns_axi_ic = level & en;
 152 }
 153
 154 static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
 155 {
 156     MicroBlazeCPU *cpu = opaque;
 157     CPUState *cs = CPU(cpu);
 158     int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
 159
 160     if (level) {
 161         cpu_interrupt(cs, type);
 162     } else {
 163         cpu_reset_interrupt(cs, type);
 164     }
 165 }
 166 #endif
 167
 168 static void mb_cpu_reset_hold(Object *obj)
 169 {
 170     CPUState *s = CPU(obj);
 171     MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
 172     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
 173     CPUMBState *env = &cpu->env;
 174
 175     if (mcc->parent_phases.hold) {
 176         mcc->parent_phases.hold(obj);
 177     }
 178
 179     memset(env, 0, offsetof(CPUMBState, end_reset_fields));
 180     env->res_addr = RES_ADDR_NONE;
 181
 182     /* Disable stack protector.  */
 183     env->shr = ~0;
 184
 185     env->pc = cpu->cfg.base_vectors;
 186
 187 #if defined(CONFIG_USER_ONLY)
 188     /* start in user mode with interrupts enabled.  */
 189     mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM);
 190 #else
 191     mb_cpu_write_msr(env, 0);
 192     mmu_init(&env->mmu);
 193 #endif
 194 }
 195
 196 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
 197 {
 198     info->mach = bfd_arch_microblaze;
 199     info->print_insn = print_insn_microblaze;
 200 }
 201
 202 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 203 {
 204     CPUState *cs = CPU(dev);
 205     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
 206     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 207     uint8_t version_code = 0;
 208     const char *version;
 209     int i = 0;
 210     Error *local_err = NULL;
 211
 212     cpu_exec_realizefn(cs, &local_err);
 213     if (local_err != NULL) {
 214         error_propagate(errp, local_err);
 215         return;
 216     }
 217
 218     if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) {
 219         error_setg(errp, "addr-size %d is out of range (32 - 64)",
 220                    cpu->cfg.addr_size);
 221         return;
 222     }
 223
 224     qemu_init_vcpu(cs);
 225
 226     version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;
 227     for (i = 0; mb_cpu_lookup[i].name && version; i++) {
 228         if (strcmp(mb_cpu_lookup[i].name, version) == 0) {
 229             version_code = mb_cpu_lookup[i].version_id;
 230             break;
 231         }
 232     }
 233
 234     if (!version_code) {
 235         qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
 236     }
 237
 238     cpu->cfg.pvr_regs[0] =
 239         (PVR0_USE_EXC_MASK |
 240          PVR0_USE_ICACHE_MASK |
 241          PVR0_USE_DCACHE_MASK |
 242          (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
 243          (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
 244          (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) |
 245          (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |
 246          (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |
 247          (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
 248          (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
 249          (version_code << PVR0_VERSION_SHIFT) |
 250          (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
 251          cpu->cfg.pvr_user1);
 252
 253     cpu->cfg.pvr_regs[1] = cpu->cfg.pvr_user2;
 254
 255     cpu->cfg.pvr_regs[2] =
 256         (PVR2_D_OPB_MASK |
 257          PVR2_D_LMB_MASK |
 258          PVR2_I_OPB_MASK |
 259          PVR2_I_LMB_MASK |
 260          PVR2_FPU_EXC_MASK |
 261          (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
 262          (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
 263          (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
 264          (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
 265          (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
 266          (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
 267          (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
 268          (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) |
 269          (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) |
 270          (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) |
 271          (cpu->cfg.div_zero_exception ? PVR2_DIV_ZERO_EXC_MASK : 0) |
 272          (cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) |
 273          (cpu->cfg.unaligned_exceptions ? PVR2_UNALIGNED_EXC_MASK : 0) |
 274          (cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0));
 275
 276     cpu->cfg.pvr_regs[5] |=
 277         cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0;
 278
 279     cpu->cfg.pvr_regs[10] =
 280         (0x0c000000 | /* Default to spartan 3a dsp family.  */
 281          (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT);
 282
 283     cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
 284                              16 << 17);
 285
 286     cpu->cfg.mmu = 3;
 287     cpu->cfg.mmu_tlb_access = 3;
 288     cpu->cfg.mmu_zones = 16;
 289     cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
 290
 291     mcc->parent_realize(dev, errp);
 292 }
 293
 294 static void mb_cpu_initfn(Object *obj)
 295 {
 296     MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
 297     CPUMBState *env = &cpu->env;
 298
 299     cpu_set_cpustate_pointers(cpu);
 300     gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect,
 301                              mb_cpu_gdb_write_stack_protect, 2,
 302                              "microblaze-stack-protect.xml", 0);
 303
 304     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 305
 306 #ifndef CONFIG_USER_ONLY
 307     /* Inbound IRQ and FIR lines */
 308     qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
 309     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1);
 310     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1);
 311     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1);
 312     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1);
 313 #endif
 314 }
 315
 316 static Property mb_properties[] = {
 317     DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
 318     DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
 319                      false),
 320     /*
 321      * This is the C_ADDR_SIZE synth-time configuration option of the
 322      * MicroBlaze cores. Supported values range between 32 and 64.
 323      *
 324      * When set to > 32, 32bit MicroBlaze can emit load/stores
 325      * with extended addressing.
 326      */
 327     DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32),
 328     /* If use-fpu > 0 - FPU is enabled
 329      * If use-fpu = 2 - Floating point conversion and square root instructions
 330      *                  are enabled
 331      */
 332     DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
 333     /* If use-hw-mul > 0 - Multiplier is enabled
 334      * If use-hw-mul = 2 - 64-bit multiplier is enabled
 335      */
 336     DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
 337     DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
 338     DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
 339     DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
 340     DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
 341     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
 342     /*
 343      * use-non-secure enables/disables the use of the non_secure[3:0] signals.
 344      * It is a bitfield where 1 = non-secure for the following bits and their
 345      * corresponding interfaces:
 346      * 0x1 - M_AXI_DP
 347      * 0x2 - M_AXI_IP
 348      * 0x4 - M_AXI_DC
 349      * 0x8 - M_AXI_IC
 350      */
 351     DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0),
 352     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
 353                      false),
 354     DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
 355     /* Enables bus exceptions on failed data accesses (load/stores).  */
 356     DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
 357                      cfg.dopb_bus_exception, false),
 358     /* Enables bus exceptions on failed instruction fetches.  */
 359     DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
 360                      cfg.iopb_bus_exception, false),
 361     DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
 362                      cfg.illegal_opcode_exception, false),
 363     DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
 364                      cfg.div_zero_exception, false),
 365     DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
 366                      cfg.unaligned_exceptions, false),
 367     DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
 368                      cfg.opcode_0_illegal, false),
 369     DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
 370     DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
 371     DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
 372     DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
 373     DEFINE_PROP_END_OF_LIST(),
 374 };
 375
 376 static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
 377 {
 378     return object_class_by_name(TYPE_MICROBLAZE_CPU);
 379 }
 380
 381 #ifndef CONFIG_USER_ONLY
 382 #include "hw/core/sysemu-cpu-ops.h"
 383
 384 static const struct SysemuCPUOps mb_sysemu_ops = {
 385     .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,
 386 };
 387 #endif
 388
 389 #include "hw/core/tcg-cpu-ops.h"
 390
 391 static const struct TCGCPUOps mb_tcg_ops = {
 392     .initialize = mb_tcg_init,
 393     .synchronize_from_tb = mb_cpu_synchronize_from_tb,
 394     .restore_state_to_opc = mb_restore_state_to_opc,
 395
 396 #ifndef CONFIG_USER_ONLY
 397     .tlb_fill = mb_cpu_tlb_fill,
 398     .cpu_exec_interrupt = mb_cpu_exec_interrupt,
 399     .do_interrupt = mb_cpu_do_interrupt,
 400     .do_transaction_failed = mb_cpu_transaction_failed,
 401     .do_unaligned_access = mb_cpu_do_unaligned_access,
 402 #endif /* !CONFIG_USER_ONLY */
 403 };
 404
 405 static void mb_cpu_class_init(ObjectClass *oc, void *data)
 406 {
 407     DeviceClass *dc = DEVICE_CLASS(oc);
 408     CPUClass *cc = CPU_CLASS(oc);
 409     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
 410     ResettableClass *rc = RESETTABLE_CLASS(oc);
 411
 412     device_class_set_parent_realize(dc, mb_cpu_realizefn,
 413                                     &mcc->parent_realize);
 414     resettable_class_set_parent_phases(rc, NULL, mb_cpu_reset_hold, NULL,
 415                                        &mcc->parent_phases);
 416
 417     cc->class_by_name = mb_cpu_class_by_name;
 418     cc->has_work = mb_cpu_has_work;
 419
 420     cc->dump_state = mb_cpu_dump_state;
 421     cc->set_pc = mb_cpu_set_pc;
 422     cc->get_pc = mb_cpu_get_pc;
 423     cc->gdb_read_register = mb_cpu_gdb_read_register;
 424     cc->gdb_write_register = mb_cpu_gdb_write_register;
 425
 426 #ifndef CONFIG_USER_ONLY
 427     dc->vmsd = &vmstate_mb_cpu;
 428     cc->sysemu_ops = &mb_sysemu_ops;
 429 #endif
 430     device_class_set_props(dc, mb_properties);
 431     cc->gdb_num_core_regs = 32 + 25;
 432     cc->gdb_core_xml_file = "microblaze-core.xml";
 433
 434     cc->disas_set_info = mb_disas_set_info;
 435     cc->tcg_ops = &mb_tcg_ops;
 436 }
 437
 438 static const TypeInfo mb_cpu_type_info = {
 439     .name = TYPE_MICROBLAZE_CPU,
 440     .parent = TYPE_CPU,
 441     .instance_size = sizeof(MicroBlazeCPU),
 442     .instance_init = mb_cpu_initfn,
 443     .class_size = sizeof(MicroBlazeCPUClass),
 444     .class_init = mb_cpu_class_init,
 445 };
 446
 447 static void mb_cpu_register_types(void)
 448 {
 449     type_register_static(&mb_cpu_type_info);
 450 }
 451
 452 type_init(mb_cpu_register_types)