target/hexagon/genptr.h

   1 /*
   2  *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef HEXAGON_GENPTR_H
  19 #define HEXAGON_GENPTR_H
  20
  21 #include "insn.h"
  22 #include "tcg/tcg.h"
  23 #include "translate.h"
  24
  25 extern const SemanticInsn opcode_genptr[];
  26
  27 void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot);
  28 void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot);
  29 void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot);
  30 void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot);
  31 void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot);
  32 void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
  33 void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
  34 void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
  35 void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot);
  36 TCGv gen_read_reg(TCGv result, int num);
  37 TCGv gen_read_preg(TCGv pred, uint8_t num);
  38 TCGv get_result_gpr(DisasContext *ctx, int rnum);
  39 TCGv get_result_pred(DisasContext *ctx, int pnum);
  40 void gen_log_reg_write(DisasContext *ctx, int rnum, TCGv val);
  41 void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val);
  42 void gen_set_usr_field(DisasContext *ctx, int field, TCGv val);
  43 void gen_set_usr_fieldi(DisasContext *ctx, int field, int x);
  44 void gen_set_usr_field_if(DisasContext *ctx, int field, TCGv val);
  45 void gen_sat_i32(TCGv dest, TCGv source, int width);
  46 void gen_sat_i32_ovfl(TCGv ovfl, TCGv dest, TCGv source, int width);
  47 void gen_satu_i32(TCGv dest, TCGv source, int width);
  48 void gen_satu_i32_ovfl(TCGv ovfl, TCGv dest, TCGv source, int width);
  49 void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width);
  50 void gen_sat_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width);
  51 void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width);
  52 void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width);
  53 void gen_add_sat_i64(DisasContext *ctx, TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b);
  54 TCGv gen_8bitsof(TCGv result, TCGv value);
  55 void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src);
  56 TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign);
  57 TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign);
  58 TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign);
  59 void gen_set_half(int N, TCGv result, TCGv src);
  60 void gen_set_half_i64(int N, TCGv_i64 result, TCGv src);
  61 void probe_noshuf_load(TCGv va, int s, int mi);
  62
  63 extern const target_ulong reg_immut_masks[TOTAL_PER_THREAD_REGS];
  64
  65 #endif