target/avr/helper.c

   1 /*
   2  * QEMU AVR CPU helpers
   3  *
   4  * Copyright (c) 2016-2020 Michael Rolnik
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/log.h"
  23 #include "qemu/error-report.h"
  24 #include "cpu.h"
  25 #include "hw/core/tcg-cpu-ops.h"
  26 #include "exec/exec-all.h"
  27 #include "exec/cpu_ldst.h"
  28 #include "exec/address-spaces.h"
  29 #include "exec/helper-proto.h"
  30
  31 bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
  32 {
  33     AVRCPU *cpu = AVR_CPU(cs);
  34     CPUAVRState *env = &cpu->env;
  35
  36     /*
  37      * We cannot separate a skip from the next instruction,
  38      * as the skip would not be preserved across the interrupt.
  39      * Separating the two insn normally only happens at page boundaries.
  40      */
  41     if (env->skip) {
  42         return false;
  43     }
  44
  45     if (interrupt_request & CPU_INTERRUPT_RESET) {
  46         if (cpu_interrupts_enabled(env)) {
  47             cs->exception_index = EXCP_RESET;
  48             avr_cpu_do_interrupt(cs);
  49
  50             cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
  51             return true;
  52         }
  53     }
  54     if (interrupt_request & CPU_INTERRUPT_HARD) {
  55         if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
  56             int index = ctz64(env->intsrc);
  57             cs->exception_index = EXCP_INT(index);
  58             avr_cpu_do_interrupt(cs);
  59
  60             env->intsrc &= env->intsrc - 1; /* clear the interrupt */
  61             if (!env->intsrc) {
  62                 cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
  63             }
  64             return true;
  65         }
  66     }
  67     return false;
  68 }
  69
  70 void avr_cpu_do_interrupt(CPUState *cs)
  71 {
  72     AVRCPU *cpu = AVR_CPU(cs);
  73     CPUAVRState *env = &cpu->env;
  74
  75     uint32_t ret = env->pc_w;
  76     int vector = 0;
  77     int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1;
  78     int base = 0;
  79
  80     if (cs->exception_index == EXCP_RESET) {
  81         vector = 0;
  82     } else if (env->intsrc != 0) {
  83         vector = ctz64(env->intsrc) + 1;
  84     }
  85
  86     if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
  87         cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
  88         cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
  89         cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16);
  90     } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) {
  91         cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
  92         cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
  93     } else {
  94         cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
  95     }
  96
  97     env->pc_w = base + vector * size;
  98     env->sregI = 0; /* clear Global Interrupt Flag */
  99
 100     cs->exception_index = -1;
 101 }
 102
 103 hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 104 {
 105     return addr; /* I assume 1:1 address correspondence */
 106 }
 107
 108 bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 109                       MMUAccessType access_type, int mmu_idx,
 110                       bool probe, uintptr_t retaddr)
 111 {
 112     int prot, page_size = TARGET_PAGE_SIZE;
 113     uint32_t paddr;
 114
 115     address &= TARGET_PAGE_MASK;
 116
 117     if (mmu_idx == MMU_CODE_IDX) {
 118         /* Access to code in flash. */
 119         paddr = OFFSET_CODE + address;
 120         prot = PAGE_READ | PAGE_EXEC;
 121         if (paddr >= OFFSET_DATA) {
 122             /*
 123              * This should not be possible via any architectural operations.
 124              * There is certainly not an exception that we can deliver.
 125              * Accept probing that might come from generic code.
 126              */
 127             if (probe) {
 128                 return false;
 129             }
 130             error_report("execution left flash memory");
 131             abort();
 132         }
 133     } else {
 134         /* Access to memory. */
 135         paddr = OFFSET_DATA + address;
 136         prot = PAGE_READ | PAGE_WRITE;
 137         if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
 138             /*
 139              * Access to CPU registers, exit and rebuilt this TB to use
 140              * full access in case it touches specially handled registers
 141              * like SREG or SP.  For probing, set page_size = 1, in order
 142              * to force tlb_fill to be called for the next access.
 143              */
 144             if (probe) {
 145                 page_size = 1;
 146             } else {
 147                 AVRCPU *cpu = AVR_CPU(cs);
 148                 CPUAVRState *env = &cpu->env;
 149                 env->fullacc = 1;
 150                 cpu_loop_exit_restore(cs, retaddr);
 151             }
 152         }
 153     }
 154
 155     tlb_set_page(cs, address, paddr, prot, mmu_idx, page_size);
 156     return true;
 157 }
 158
 159 /*
 160  *  helpers
 161  */
 162
 163 void helper_sleep(CPUAVRState *env)
 164 {
 165     CPUState *cs = env_cpu(env);
 166
 167     cs->exception_index = EXCP_HLT;
 168     cpu_loop_exit(cs);
 169 }
 170
 171 void helper_unsupported(CPUAVRState *env)
 172 {
 173     CPUState *cs = env_cpu(env);
 174
 175     /*
 176      *  I count not find what happens on the real platform, so
 177      *  it's EXCP_DEBUG for meanwhile
 178      */
 179     cs->exception_index = EXCP_DEBUG;
 180     if (qemu_loglevel_mask(LOG_UNIMP)) {
 181         qemu_log("UNSUPPORTED\n");
 182         cpu_dump_state(cs, stderr, 0);
 183     }
 184     cpu_loop_exit(cs);
 185 }
 186
 187 void helper_debug(CPUAVRState *env)
 188 {
 189     CPUState *cs = env_cpu(env);
 190
 191     cs->exception_index = EXCP_DEBUG;
 192     cpu_loop_exit(cs);
 193 }
 194
 195 void helper_break(CPUAVRState *env)
 196 {
 197     CPUState *cs = env_cpu(env);
 198
 199     cs->exception_index = EXCP_DEBUG;
 200     cpu_loop_exit(cs);
 201 }
 202
 203 void helper_wdr(CPUAVRState *env)
 204 {
 205     qemu_log_mask(LOG_UNIMP, "WDG reset (not implemented)\n");
 206 }
 207
 208 /*
 209  * This function implements IN instruction
 210  *
 211  * It does the following
 212  * a.  if an IO register belongs to CPU, its value is read and returned
 213  * b.  otherwise io address is translated to mem address and physical memory
 214  *     is read.
 215  * c.  it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
 216  *
 217  */
 218 target_ulong helper_inb(CPUAVRState *env, uint32_t port)
 219 {
 220     target_ulong data = 0;
 221
 222     switch (port) {
 223     case 0x38: /* RAMPD */
 224         data = 0xff & (env->rampD >> 16);
 225         break;
 226     case 0x39: /* RAMPX */
 227         data = 0xff & (env->rampX >> 16);
 228         break;
 229     case 0x3a: /* RAMPY */
 230         data = 0xff & (env->rampY >> 16);
 231         break;
 232     case 0x3b: /* RAMPZ */
 233         data = 0xff & (env->rampZ >> 16);
 234         break;
 235     case 0x3c: /* EIND */
 236         data = 0xff & (env->eind >> 16);
 237         break;
 238     case 0x3d: /* SPL */
 239         data = env->sp & 0x00ff;
 240         break;
 241     case 0x3e: /* SPH */
 242         data = env->sp >> 8;
 243         break;
 244     case 0x3f: /* SREG */
 245         data = cpu_get_sreg(env);
 246         break;
 247     default:
 248         /* not a special register, pass to normal memory access */
 249         data = address_space_ldub(&address_space_memory,
 250                                   OFFSET_IO_REGISTERS + port,
 251                                   MEMTXATTRS_UNSPECIFIED, NULL);
 252     }
 253
 254     return data;
 255 }
 256
 257 /*
 258  *  This function implements OUT instruction
 259  *
 260  *  It does the following
 261  *  a.  if an IO register belongs to CPU, its value is written into the register
 262  *  b.  otherwise io address is translated to mem address and physical memory
 263  *      is written.
 264  *  c.  it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
 265  *
 266  */
 267 void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data)
 268 {
 269     data &= 0x000000ff;
 270
 271     switch (port) {
 272     case 0x38: /* RAMPD */
 273         if (avr_feature(env, AVR_FEATURE_RAMPD)) {
 274             env->rampD = (data & 0xff) << 16;
 275         }
 276         break;
 277     case 0x39: /* RAMPX */
 278         if (avr_feature(env, AVR_FEATURE_RAMPX)) {
 279             env->rampX = (data & 0xff) << 16;
 280         }
 281         break;
 282     case 0x3a: /* RAMPY */
 283         if (avr_feature(env, AVR_FEATURE_RAMPY)) {
 284             env->rampY = (data & 0xff) << 16;
 285         }
 286         break;
 287     case 0x3b: /* RAMPZ */
 288         if (avr_feature(env, AVR_FEATURE_RAMPZ)) {
 289             env->rampZ = (data & 0xff) << 16;
 290         }
 291         break;
 292     case 0x3c: /* EIDN */
 293         env->eind = (data & 0xff) << 16;
 294         break;
 295     case 0x3d: /* SPL */
 296         env->sp = (env->sp & 0xff00) | (data);
 297         break;
 298     case 0x3e: /* SPH */
 299         if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) {
 300             env->sp = (env->sp & 0x00ff) | (data << 8);
 301         }
 302         break;
 303     case 0x3f: /* SREG */
 304         cpu_set_sreg(env, data);
 305         break;
 306     default:
 307         /* not a special register, pass to normal memory access */
 308         address_space_stb(&address_space_memory, OFFSET_IO_REGISTERS + port,
 309                           data, MEMTXATTRS_UNSPECIFIED, NULL);
 310     }
 311 }
 312
 313 /*
 314  *  this function implements LD instruction when there is a possibility to read
 315  *  from a CPU register
 316  */
 317 target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr)
 318 {
 319     uint8_t data;
 320
 321     env->fullacc = false;
 322
 323     if (addr < NUMBER_OF_CPU_REGISTERS) {
 324         /* CPU registers */
 325         data = env->r[addr];
 326     } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
 327         /* IO registers */
 328         data = helper_inb(env, addr - NUMBER_OF_CPU_REGISTERS);
 329     } else {
 330         /* memory */
 331         data = address_space_ldub(&address_space_memory, OFFSET_DATA + addr,
 332                                   MEMTXATTRS_UNSPECIFIED, NULL);
 333     }
 334     return data;
 335 }
 336
 337 /*
 338  *  this function implements ST instruction when there is a possibility to write
 339  *  into a CPU register
 340  */
 341 void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr)
 342 {
 343     env->fullacc = false;
 344
 345     /* Following logic assumes this: */
 346     assert(OFFSET_CPU_REGISTERS == OFFSET_DATA);
 347     assert(OFFSET_IO_REGISTERS == OFFSET_CPU_REGISTERS +
 348                                   NUMBER_OF_CPU_REGISTERS);
 349
 350     if (addr < NUMBER_OF_CPU_REGISTERS) {
 351         /* CPU registers */
 352         env->r[addr] = data;
 353     } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
 354         /* IO registers */
 355         helper_outb(env, addr - NUMBER_OF_CPU_REGISTERS, data);
 356     } else {
 357         /* memory */
 358         address_space_stb(&address_space_memory, OFFSET_DATA + addr, data,
 359                           MEMTXATTRS_UNSPECIFIED, NULL);
 360     }
 361 }