2 * QEMU Sun4u/Sun4v System Emulator
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu-common.h"
29 #include "hw/pci/pci.h"
30 #include "hw/pci-host/apb.h"
31 #include "hw/i386/pc.h"
32 #include "hw/char/serial.h"
33 #include "hw/timer/m48t59.h"
34 #include "hw/block/fdc.h"
36 #include "qemu/timer.h"
37 #include "sysemu/sysemu.h"
38 #include "hw/boards.h"
39 #include "hw/nvram/sun_nvram.h"
40 #include "hw/nvram/chrp_nvram.h"
41 #include "hw/nvram/fw_cfg.h"
42 #include "hw/sysbus.h"
44 #include "hw/loader.h"
46 #include "sysemu/block-backend.h"
47 #include "exec/address-spaces.h"
48 #include "qemu/cutils.h"
55 #define CPUIRQ_DPRINTF(fmt, ...) \
56 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
58 #define CPUIRQ_DPRINTF(fmt, ...)
62 #define EBUS_DPRINTF(fmt, ...) \
63 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
65 #define EBUS_DPRINTF(fmt, ...)
69 #define TIMER_DPRINTF(fmt, ...) \
70 do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
72 #define TIMER_DPRINTF(fmt, ...)
75 #define KERNEL_LOAD_ADDR 0x00404000
76 #define CMDLINE_ADDR 0x003ff000
77 #define PROM_SIZE_MAX (4 * 1024 * 1024)
78 #define PROM_VADDR 0x000ffd00000ULL
79 #define APB_SPECIAL_BASE 0x1fe00000000ULL
80 #define APB_MEM_BASE 0x1ff00000000ULL
81 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL)
82 #define PROM_FILENAME "openbios-sparc64"
83 #define NVRAM_SIZE 0x2000
85 #define BIOS_CFG_IOPORT 0x510
86 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
87 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
88 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
92 #define TICK_MAX 0x7fffffffffffffffULL
95 const char * const default_cpu_model
;
98 uint64_t console_serial_base
;
101 typedef struct EbusState
{
107 void DMA_init(ISABus
*bus
, int high_page_enable
)
111 static void fw_cfg_boot_set(void *opaque
, const char *boot_device
,
114 fw_cfg_modify_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
117 static int sun4u_NVRAM_set_params(Nvram
*nvram
, uint16_t NVRAM_size
,
118 const char *arch
, ram_addr_t RAM_size
,
119 const char *boot_devices
,
120 uint32_t kernel_image
, uint32_t kernel_size
,
122 uint32_t initrd_image
, uint32_t initrd_size
,
123 uint32_t NVRAM_image
,
124 int width
, int height
, int depth
,
125 const uint8_t *macaddr
)
129 uint8_t image
[0x1ff0];
130 NvramClass
*k
= NVRAM_GET_CLASS(nvram
);
132 memset(image
, '\0', sizeof(image
));
134 /* OpenBIOS nvram variables partition */
135 sysp_end
= chrp_nvram_create_system_partition(image
, 0);
137 /* Free space partition */
138 chrp_nvram_create_free_partition(&image
[sysp_end
], 0x1fd0 - sysp_end
);
140 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
, 0x80);
142 for (i
= 0; i
< sizeof(image
); i
++) {
143 (k
->write
)(nvram
, i
, image
[i
]);
149 static uint64_t sun4u_load_kernel(const char *kernel_filename
,
150 const char *initrd_filename
,
151 ram_addr_t RAM_size
, uint64_t *initrd_size
,
152 uint64_t *initrd_addr
, uint64_t *kernel_addr
,
153 uint64_t *kernel_entry
)
161 linux_boot
= (kernel_filename
!= NULL
);
172 kernel_size
= load_elf(kernel_filename
, NULL
, NULL
, kernel_entry
,
173 kernel_addr
, &kernel_top
, 1, EM_SPARCV9
, 0, 0);
174 if (kernel_size
< 0) {
175 *kernel_addr
= KERNEL_LOAD_ADDR
;
176 *kernel_entry
= KERNEL_LOAD_ADDR
;
177 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
178 RAM_size
- KERNEL_LOAD_ADDR
, bswap_needed
,
181 if (kernel_size
< 0) {
182 kernel_size
= load_image_targphys(kernel_filename
,
184 RAM_size
- KERNEL_LOAD_ADDR
);
186 if (kernel_size
< 0) {
187 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
191 /* load initrd above kernel */
193 if (initrd_filename
) {
194 *initrd_addr
= TARGET_PAGE_ALIGN(kernel_top
);
196 *initrd_size
= load_image_targphys(initrd_filename
,
198 RAM_size
- *initrd_addr
);
199 if ((int)*initrd_size
< 0) {
200 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
205 if (*initrd_size
> 0) {
206 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
207 ptr
= rom_ptr(*kernel_addr
+ i
);
208 if (ldl_p(ptr
+ 8) == 0x48647253) { /* HdrS */
209 stl_p(ptr
+ 24, *initrd_addr
+ *kernel_addr
);
210 stl_p(ptr
+ 28, *initrd_size
);
219 void cpu_check_irqs(CPUSPARCState
*env
)
222 uint32_t pil
= env
->pil_in
|
223 (env
->softint
& ~(SOFTINT_TIMER
| SOFTINT_STIMER
));
225 /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
226 if (env
->ivec_status
& 0x20) {
229 cs
= CPU(sparc_env_get_cpu(env
));
230 /* check if TM or SM in SOFTINT are set
231 setting these also causes interrupt 14 */
232 if (env
->softint
& (SOFTINT_TIMER
| SOFTINT_STIMER
)) {
236 /* The bit corresponding to psrpil is (1<< psrpil), the next bit
238 if (pil
< (2 << env
->psrpil
)){
239 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
240 CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
241 env
->interrupt_index
);
242 env
->interrupt_index
= 0;
243 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
248 if (cpu_interrupts_enabled(env
)) {
252 for (i
= 15; i
> env
->psrpil
; i
--) {
253 if (pil
& (1 << i
)) {
254 int old_interrupt
= env
->interrupt_index
;
255 int new_interrupt
= TT_EXTINT
| i
;
257 if (unlikely(env
->tl
> 0 && cpu_tsptr(env
)->tt
> new_interrupt
258 && ((cpu_tsptr(env
)->tt
& 0x1f0) == TT_EXTINT
))) {
259 CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
260 "current %x >= pending %x\n",
261 env
->tl
, cpu_tsptr(env
)->tt
, new_interrupt
);
262 } else if (old_interrupt
!= new_interrupt
) {
263 env
->interrupt_index
= new_interrupt
;
264 CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i
,
265 old_interrupt
, new_interrupt
);
266 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
271 } else if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
272 CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
273 "current interrupt %x\n",
274 pil
, env
->pil_in
, env
->softint
, env
->interrupt_index
);
275 env
->interrupt_index
= 0;
276 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
280 static void cpu_kick_irq(SPARCCPU
*cpu
)
282 CPUState
*cs
= CPU(cpu
);
283 CPUSPARCState
*env
= &cpu
->env
;
290 static void cpu_set_ivec_irq(void *opaque
, int irq
, int level
)
292 SPARCCPU
*cpu
= opaque
;
293 CPUSPARCState
*env
= &cpu
->env
;
297 if (!(env
->ivec_status
& 0x20)) {
298 CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq
);
301 env
->interrupt_index
= TT_IVEC
;
302 env
->ivec_status
|= 0x20;
303 env
->ivec_data
[0] = (0x1f << 6) | irq
;
304 env
->ivec_data
[1] = 0;
305 env
->ivec_data
[2] = 0;
306 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
309 if (env
->ivec_status
& 0x20) {
310 CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq
);
312 env
->ivec_status
&= ~0x20;
313 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
318 typedef struct ResetData
{
323 static CPUTimer
*cpu_timer_create(const char *name
, SPARCCPU
*cpu
,
324 QEMUBHFunc
*cb
, uint32_t frequency
,
325 uint64_t disabled_mask
, uint64_t npt_mask
)
327 CPUTimer
*timer
= g_malloc0(sizeof (CPUTimer
));
330 timer
->frequency
= frequency
;
331 timer
->disabled_mask
= disabled_mask
;
332 timer
->npt_mask
= npt_mask
;
336 timer
->clock_offset
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
338 timer
->qtimer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, cb
, cpu
);
343 static void cpu_timer_reset(CPUTimer
*timer
)
346 timer
->clock_offset
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
348 timer_del(timer
->qtimer
);
351 static void main_cpu_reset(void *opaque
)
353 ResetData
*s
= (ResetData
*)opaque
;
354 CPUSPARCState
*env
= &s
->cpu
->env
;
355 static unsigned int nr_resets
;
357 cpu_reset(CPU(s
->cpu
));
359 cpu_timer_reset(env
->tick
);
360 cpu_timer_reset(env
->stick
);
361 cpu_timer_reset(env
->hstick
);
363 env
->gregs
[1] = 0; // Memory start
364 env
->gregs
[2] = ram_size
; // Memory size
365 env
->gregs
[3] = 0; // Machine description XXX
366 if (nr_resets
++ == 0) {
368 env
->pc
= s
->prom_addr
+ 0x20ULL
;
370 env
->pc
= s
->prom_addr
+ 0x40ULL
;
372 env
->npc
= env
->pc
+ 4;
375 static void tick_irq(void *opaque
)
377 SPARCCPU
*cpu
= opaque
;
378 CPUSPARCState
*env
= &cpu
->env
;
380 CPUTimer
* timer
= env
->tick
;
382 if (timer
->disabled
) {
383 CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
386 CPUIRQ_DPRINTF("tick: fire\n");
389 env
->softint
|= SOFTINT_TIMER
;
393 static void stick_irq(void *opaque
)
395 SPARCCPU
*cpu
= opaque
;
396 CPUSPARCState
*env
= &cpu
->env
;
398 CPUTimer
* timer
= env
->stick
;
400 if (timer
->disabled
) {
401 CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
404 CPUIRQ_DPRINTF("stick: fire\n");
407 env
->softint
|= SOFTINT_STIMER
;
411 static void hstick_irq(void *opaque
)
413 SPARCCPU
*cpu
= opaque
;
414 CPUSPARCState
*env
= &cpu
->env
;
416 CPUTimer
* timer
= env
->hstick
;
418 if (timer
->disabled
) {
419 CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
422 CPUIRQ_DPRINTF("hstick: fire\n");
425 env
->softint
|= SOFTINT_STIMER
;
429 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks
, uint32_t frequency
)
431 return muldiv64(cpu_ticks
, NANOSECONDS_PER_SECOND
, frequency
);
434 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks
, uint32_t frequency
)
436 return muldiv64(timer_ticks
, frequency
, NANOSECONDS_PER_SECOND
);
439 void cpu_tick_set_count(CPUTimer
*timer
, uint64_t count
)
441 uint64_t real_count
= count
& ~timer
->npt_mask
;
442 uint64_t npt_bit
= count
& timer
->npt_mask
;
444 int64_t vm_clock_offset
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) -
445 cpu_to_timer_ticks(real_count
, timer
->frequency
);
447 TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n",
448 timer
->name
, real_count
,
449 timer
->npt
? "disabled" : "enabled", timer
);
451 timer
->npt
= npt_bit
? 1 : 0;
452 timer
->clock_offset
= vm_clock_offset
;
455 uint64_t cpu_tick_get_count(CPUTimer
*timer
)
457 uint64_t real_count
= timer_to_cpu_ticks(
458 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) - timer
->clock_offset
,
461 TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n",
462 timer
->name
, real_count
,
463 timer
->npt
? "disabled" : "enabled", timer
);
466 real_count
|= timer
->npt_mask
;
472 void cpu_tick_set_limit(CPUTimer
*timer
, uint64_t limit
)
474 int64_t now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
476 uint64_t real_limit
= limit
& ~timer
->disabled_mask
;
477 timer
->disabled
= (limit
& timer
->disabled_mask
) ? 1 : 0;
479 int64_t expires
= cpu_to_timer_ticks(real_limit
, timer
->frequency
) +
486 TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
487 "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
488 timer
->name
, real_limit
,
489 timer
->disabled
?"disabled":"enabled",
491 timer_to_cpu_ticks(now
- timer
->clock_offset
,
493 timer_to_cpu_ticks(expires
- now
, timer
->frequency
));
496 TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
498 timer_del(timer
->qtimer
);
499 } else if (timer
->disabled
) {
500 timer_del(timer
->qtimer
);
502 timer_mod(timer
->qtimer
, expires
);
506 static void isa_irq_handler(void *opaque
, int n
, int level
)
508 static const int isa_irq_to_ivec
[16] = {
509 [1] = 0x29, /* keyboard */
510 [4] = 0x2b, /* serial */
511 [6] = 0x27, /* floppy */
512 [7] = 0x22, /* parallel */
513 [12] = 0x2a, /* mouse */
515 qemu_irq
*irqs
= opaque
;
519 ivec
= isa_irq_to_ivec
[n
];
520 EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n
, level
, ivec
);
522 qemu_set_irq(irqs
[ivec
], level
);
526 /* EBUS (Eight bit bus) bridge */
528 pci_ebus_init(PCIBus
*bus
, int devfn
, qemu_irq
*irqs
)
534 pci_dev
= pci_create_simple(bus
, devfn
, "ebus");
535 isa_bus
= ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev
), "isa.0"));
536 isa_irq
= qemu_allocate_irqs(isa_irq_handler
, irqs
, 16);
537 isa_bus_irqs(isa_bus
, isa_irq
);
541 static void pci_ebus_realize(PCIDevice
*pci_dev
, Error
**errp
)
543 EbusState
*s
= DO_UPCAST(EbusState
, pci_dev
, pci_dev
);
545 if (!isa_bus_new(DEVICE(pci_dev
), get_system_memory(),
546 pci_address_space_io(pci_dev
), errp
)) {
550 pci_dev
->config
[0x04] = 0x06; // command = bus master, pci mem
551 pci_dev
->config
[0x05] = 0x00;
552 pci_dev
->config
[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
553 pci_dev
->config
[0x07] = 0x03; // status = medium devsel
554 pci_dev
->config
[0x09] = 0x00; // programming i/f
555 pci_dev
->config
[0x0D] = 0x0a; // latency_timer
557 memory_region_init_alias(&s
->bar0
, OBJECT(s
), "bar0", get_system_io(),
559 pci_register_bar(pci_dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar0
);
560 memory_region_init_alias(&s
->bar1
, OBJECT(s
), "bar1", get_system_io(),
562 pci_register_bar(pci_dev
, 1, PCI_BASE_ADDRESS_SPACE_IO
, &s
->bar1
);
565 static void ebus_class_init(ObjectClass
*klass
, void *data
)
567 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
569 k
->realize
= pci_ebus_realize
;
570 k
->vendor_id
= PCI_VENDOR_ID_SUN
;
571 k
->device_id
= PCI_DEVICE_ID_SUN_EBUS
;
573 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
576 static const TypeInfo ebus_info
= {
578 .parent
= TYPE_PCI_DEVICE
,
579 .instance_size
= sizeof(EbusState
),
580 .class_init
= ebus_class_init
,
583 #define TYPE_OPENPROM "openprom"
584 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
586 typedef struct PROMState
{
587 SysBusDevice parent_obj
;
592 static uint64_t translate_prom_address(void *opaque
, uint64_t addr
)
594 hwaddr
*base_addr
= (hwaddr
*)opaque
;
595 return addr
+ *base_addr
- PROM_VADDR
;
598 /* Boot PROM (OpenBIOS) */
599 static void prom_init(hwaddr addr
, const char *bios_name
)
606 dev
= qdev_create(NULL
, TYPE_OPENPROM
);
607 qdev_init_nofail(dev
);
608 s
= SYS_BUS_DEVICE(dev
);
610 sysbus_mmio_map(s
, 0, addr
);
613 if (bios_name
== NULL
) {
614 bios_name
= PROM_FILENAME
;
616 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
618 ret
= load_elf(filename
, translate_prom_address
, &addr
,
619 NULL
, NULL
, NULL
, 1, EM_SPARCV9
, 0, 0);
620 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
621 ret
= load_image_targphys(filename
, addr
, PROM_SIZE_MAX
);
627 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
628 fprintf(stderr
, "qemu: could not load prom '%s'\n", bios_name
);
633 static int prom_init1(SysBusDevice
*dev
)
635 PROMState
*s
= OPENPROM(dev
);
637 memory_region_init_ram(&s
->prom
, OBJECT(s
), "sun4u.prom", PROM_SIZE_MAX
,
639 vmstate_register_ram_global(&s
->prom
);
640 memory_region_set_readonly(&s
->prom
, true);
641 sysbus_init_mmio(dev
, &s
->prom
);
645 static Property prom_properties
[] = {
646 {/* end of property list */},
649 static void prom_class_init(ObjectClass
*klass
, void *data
)
651 DeviceClass
*dc
= DEVICE_CLASS(klass
);
652 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
654 k
->init
= prom_init1
;
655 dc
->props
= prom_properties
;
658 static const TypeInfo prom_info
= {
659 .name
= TYPE_OPENPROM
,
660 .parent
= TYPE_SYS_BUS_DEVICE
,
661 .instance_size
= sizeof(PROMState
),
662 .class_init
= prom_class_init
,
666 #define TYPE_SUN4U_MEMORY "memory"
667 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
669 typedef struct RamDevice
{
670 SysBusDevice parent_obj
;
677 static int ram_init1(SysBusDevice
*dev
)
679 RamDevice
*d
= SUN4U_RAM(dev
);
681 memory_region_init_ram(&d
->ram
, OBJECT(d
), "sun4u.ram", d
->size
,
683 vmstate_register_ram_global(&d
->ram
);
684 sysbus_init_mmio(dev
, &d
->ram
);
688 static void ram_init(hwaddr addr
, ram_addr_t RAM_size
)
695 dev
= qdev_create(NULL
, TYPE_SUN4U_MEMORY
);
696 s
= SYS_BUS_DEVICE(dev
);
700 qdev_init_nofail(dev
);
702 sysbus_mmio_map(s
, 0, addr
);
705 static Property ram_properties
[] = {
706 DEFINE_PROP_UINT64("size", RamDevice
, size
, 0),
707 DEFINE_PROP_END_OF_LIST(),
710 static void ram_class_init(ObjectClass
*klass
, void *data
)
712 DeviceClass
*dc
= DEVICE_CLASS(klass
);
713 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
716 dc
->props
= ram_properties
;
719 static const TypeInfo ram_info
= {
720 .name
= TYPE_SUN4U_MEMORY
,
721 .parent
= TYPE_SYS_BUS_DEVICE
,
722 .instance_size
= sizeof(RamDevice
),
723 .class_init
= ram_class_init
,
726 static SPARCCPU
*cpu_devinit(const char *cpu_model
, const struct hwdef
*hwdef
)
730 ResetData
*reset_info
;
732 uint32_t tick_frequency
= 100*1000000;
733 uint32_t stick_frequency
= 100*1000000;
734 uint32_t hstick_frequency
= 100*1000000;
736 if (cpu_model
== NULL
) {
737 cpu_model
= hwdef
->default_cpu_model
;
739 cpu
= cpu_sparc_init(cpu_model
);
741 fprintf(stderr
, "Unable to find Sparc CPU definition\n");
746 env
->tick
= cpu_timer_create("tick", cpu
, tick_irq
,
747 tick_frequency
, TICK_INT_DIS
,
750 env
->stick
= cpu_timer_create("stick", cpu
, stick_irq
,
751 stick_frequency
, TICK_INT_DIS
,
754 env
->hstick
= cpu_timer_create("hstick", cpu
, hstick_irq
,
755 hstick_frequency
, TICK_INT_DIS
,
758 reset_info
= g_malloc0(sizeof(ResetData
));
759 reset_info
->cpu
= cpu
;
760 reset_info
->prom_addr
= hwdef
->prom_addr
;
761 qemu_register_reset(main_cpu_reset
, reset_info
);
766 static void sun4uv_init(MemoryRegion
*address_space_mem
,
767 MachineState
*machine
,
768 const struct hwdef
*hwdef
)
773 uint64_t initrd_addr
, initrd_size
, kernel_addr
, kernel_size
, kernel_entry
;
774 PCIBus
*pci_bus
, *pci_bus2
, *pci_bus3
;
777 qemu_irq
*ivec_irqs
, *pbm_irqs
;
778 DriveInfo
*hd
[MAX_IDE_BUS
* MAX_IDE_DEVS
];
779 DriveInfo
*fd
[MAX_FD
];
784 cpu
= cpu_devinit(machine
->cpu_model
, hwdef
);
787 ram_init(0, machine
->ram_size
);
789 prom_init(hwdef
->prom_addr
, bios_name
);
791 ivec_irqs
= qemu_allocate_irqs(cpu_set_ivec_irq
, cpu
, IVEC_MAX
);
792 pci_bus
= pci_apb_init(APB_SPECIAL_BASE
, APB_MEM_BASE
, ivec_irqs
, &pci_bus2
,
793 &pci_bus3
, &pbm_irqs
);
794 pci_vga_init(pci_bus
);
796 // XXX Should be pci_bus3
797 isa_bus
= pci_ebus_init(pci_bus
, -1, pbm_irqs
);
800 if (hwdef
->console_serial_base
) {
801 serial_mm_init(address_space_mem
, hwdef
->console_serial_base
, 0,
802 NULL
, 115200, serial_hds
[i
], DEVICE_BIG_ENDIAN
);
806 serial_hds_isa_init(isa_bus
, i
, MAX_SERIAL_PORTS
);
807 parallel_hds_isa_init(isa_bus
, MAX_PARALLEL_PORTS
);
809 for(i
= 0; i
< nb_nics
; i
++)
810 pci_nic_init_nofail(&nd_table
[i
], pci_bus
, "ne2k_pci", NULL
);
812 ide_drive_get(hd
, ARRAY_SIZE(hd
));
814 pci_cmd646_ide_init(pci_bus
, hd
, 1);
816 isa_create_simple(isa_bus
, "i8042");
819 for(i
= 0; i
< MAX_FD
; i
++) {
820 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
822 dev
= DEVICE(isa_create(isa_bus
, TYPE_ISA_FDC
));
824 qdev_prop_set_drive(dev
, "driveA", blk_by_legacy_dinfo(fd
[0]),
828 qdev_prop_set_drive(dev
, "driveB", blk_by_legacy_dinfo(fd
[1]),
831 qdev_prop_set_uint32(dev
, "dma", -1);
832 qdev_init_nofail(dev
);
834 /* Map NVRAM into I/O (ebus) space */
835 nvram
= m48t59_init(NULL
, 0, 0, NVRAM_SIZE
, 1968, 59);
836 s
= SYS_BUS_DEVICE(nvram
);
837 memory_region_add_subregion(get_system_io(), 0x2000,
838 sysbus_mmio_get_region(s
, 0));
842 kernel_size
= sun4u_load_kernel(machine
->kernel_filename
,
843 machine
->initrd_filename
,
844 ram_size
, &initrd_size
, &initrd_addr
,
845 &kernel_addr
, &kernel_entry
);
847 sun4u_NVRAM_set_params(nvram
, NVRAM_SIZE
, "Sun4u", machine
->ram_size
,
849 kernel_addr
, kernel_size
,
850 machine
->kernel_cmdline
,
851 initrd_addr
, initrd_size
,
852 /* XXX: need an option to load a NVRAM image */
854 graphic_width
, graphic_height
, graphic_depth
,
855 (uint8_t *)&nd_table
[0].macaddr
);
857 fw_cfg
= fw_cfg_init_io(BIOS_CFG_IOPORT
);
858 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)max_cpus
);
859 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
860 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
861 fw_cfg_add_i64(fw_cfg
, FW_CFG_KERNEL_ADDR
, kernel_entry
);
862 fw_cfg_add_i64(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
863 if (machine
->kernel_cmdline
) {
864 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
865 strlen(machine
->kernel_cmdline
) + 1);
866 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, machine
->kernel_cmdline
);
868 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, 0);
870 fw_cfg_add_i64(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
871 fw_cfg_add_i64(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
872 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, machine
->boot_order
[0]);
874 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_WIDTH
, graphic_width
);
875 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_HEIGHT
, graphic_height
);
876 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_DEPTH
, graphic_depth
);
878 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
887 static const struct hwdef hwdefs
[] = {
888 /* Sun4u generic PC-like machine */
890 .default_cpu_model
= "TI UltraSparc IIi",
891 .machine_id
= sun4u_id
,
892 .prom_addr
= 0x1fff0000000ULL
,
893 .console_serial_base
= 0,
895 /* Sun4v generic PC-like machine */
897 .default_cpu_model
= "Sun UltraSparc T1",
898 .machine_id
= sun4v_id
,
899 .prom_addr
= 0x1fff0000000ULL
,
900 .console_serial_base
= 0,
902 /* Sun4v generic Niagara machine */
904 .default_cpu_model
= "Sun UltraSparc T1",
905 .machine_id
= niagara_id
,
906 .prom_addr
= 0xfff0000000ULL
,
907 .console_serial_base
= 0xfff0c2c000ULL
,
911 /* Sun4u hardware initialisation */
912 static void sun4u_init(MachineState
*machine
)
914 sun4uv_init(get_system_memory(), machine
, &hwdefs
[0]);
917 /* Sun4v hardware initialisation */
918 static void sun4v_init(MachineState
*machine
)
920 sun4uv_init(get_system_memory(), machine
, &hwdefs
[1]);
923 /* Niagara hardware initialisation */
924 static void niagara_init(MachineState
*machine
)
926 sun4uv_init(get_system_memory(), machine
, &hwdefs
[2]);
929 static void sun4u_class_init(ObjectClass
*oc
, void *data
)
931 MachineClass
*mc
= MACHINE_CLASS(oc
);
933 mc
->desc
= "Sun4u platform";
934 mc
->init
= sun4u_init
;
935 mc
->max_cpus
= 1; /* XXX for now */
937 mc
->default_boot_order
= "c";
940 static const TypeInfo sun4u_type
= {
941 .name
= MACHINE_TYPE_NAME("sun4u"),
942 .parent
= TYPE_MACHINE
,
943 .class_init
= sun4u_class_init
,
946 static void sun4v_class_init(ObjectClass
*oc
, void *data
)
948 MachineClass
*mc
= MACHINE_CLASS(oc
);
950 mc
->desc
= "Sun4v platform";
951 mc
->init
= sun4v_init
;
952 mc
->max_cpus
= 1; /* XXX for now */
953 mc
->default_boot_order
= "c";
956 static const TypeInfo sun4v_type
= {
957 .name
= MACHINE_TYPE_NAME("sun4v"),
958 .parent
= TYPE_MACHINE
,
959 .class_init
= sun4v_class_init
,
962 static void niagara_class_init(ObjectClass
*oc
, void *data
)
964 MachineClass
*mc
= MACHINE_CLASS(oc
);
966 mc
->desc
= "Sun4v platform, Niagara";
967 mc
->init
= niagara_init
;
968 mc
->max_cpus
= 1; /* XXX for now */
969 mc
->default_boot_order
= "c";
972 static const TypeInfo niagara_type
= {
973 .name
= MACHINE_TYPE_NAME("Niagara"),
974 .parent
= TYPE_MACHINE
,
975 .class_init
= niagara_class_init
,
978 static void sun4u_register_types(void)
980 type_register_static(&ebus_info
);
981 type_register_static(&prom_info
);
982 type_register_static(&ram_info
);
984 type_register_static(&sun4u_type
);
985 type_register_static(&sun4v_type
);
986 type_register_static(&niagara_type
);
989 type_init(sun4u_register_types
)