target-s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * Contributions after 2012-10-29 are licensed under the terms of the
  17  * GNU GPL, version 2 or (at your option) any later version.
  18  *
  19  * You should have received a copy of the GNU (Lesser) General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22 #ifndef CPU_S390X_H
  23 #define CPU_S390X_H
  24
  25 #include "config.h"
  26 #include "qemu-common.h"
  27
  28 #define TARGET_LONG_BITS 64
  29
  30 #define ELF_MACHINE     EM_S390
  31 #define ELF_MACHINE_UNAME "S390X"
  32
  33 #define CPUArchState struct CPUS390XState
  34
  35 #include "exec/cpu-defs.h"
  36 #define TARGET_PAGE_BITS 12
  37
  38 #define TARGET_PHYS_ADDR_SPACE_BITS 64
  39 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  40
  41 #include "exec/cpu-all.h"
  42
  43 #include "fpu/softfloat.h"
  44
  45 #define NB_MMU_MODES 3
  46
  47 #define MMU_MODE0_SUFFIX _primary
  48 #define MMU_MODE1_SUFFIX _secondary
  49 #define MMU_MODE2_SUFFIX _home
  50
  51 #define MMU_USER_IDX 1
  52
  53 #define MAX_EXT_QUEUE 16
  54 #define MAX_IO_QUEUE 16
  55 #define MAX_MCHK_QUEUE 16
  56
  57 #define PSW_MCHK_MASK 0x0004000000000000
  58 #define PSW_IO_MASK 0x0200000000000000
  59
  60 typedef struct PSW {
  61     uint64_t mask;
  62     uint64_t addr;
  63 } PSW;
  64
  65 typedef struct ExtQueue {
  66     uint32_t code;
  67     uint32_t param;
  68     uint32_t param64;
  69 } ExtQueue;
  70
  71 typedef struct IOIntQueue {
  72     uint16_t id;
  73     uint16_t nr;
  74     uint32_t parm;
  75     uint32_t word;
  76 } IOIntQueue;
  77
  78 typedef struct MchkQueue {
  79     uint16_t type;
  80 } MchkQueue;
  81
  82 typedef struct CPUS390XState {
  83     uint64_t regs[16];     /* GP registers */
  84     CPU_DoubleU fregs[16]; /* FP registers */
  85     uint32_t aregs[16];    /* access registers */
  86
  87     uint32_t fpc;          /* floating-point control register */
  88     uint32_t cc_op;
  89
  90     float_status fpu_status; /* passed to softfloat lib */
  91
  92     /* The low part of a 128-bit return, or remainder of a divide.  */
  93     uint64_t retxl;
  94
  95     PSW psw;
  96
  97     uint64_t cc_src;
  98     uint64_t cc_dst;
  99     uint64_t cc_vr;
 100
 101     uint64_t __excp_addr;
 102     uint64_t psa;
 103
 104     uint32_t int_pgm_code;
 105     uint32_t int_pgm_ilen;
 106
 107     uint32_t int_svc_code;
 108     uint32_t int_svc_ilen;
 109
 110     uint64_t cregs[16]; /* control registers */
 111
 112     ExtQueue ext_queue[MAX_EXT_QUEUE];
 113     IOIntQueue io_queue[MAX_IO_QUEUE][8];
 114     MchkQueue mchk_queue[MAX_MCHK_QUEUE];
 115
 116     int pending_int;
 117     int ext_index;
 118     int io_index[8];
 119     int mchk_index;
 120
 121     uint64_t ckc;
 122     uint64_t cputm;
 123     uint32_t todpr;
 124
 125     uint64_t pfault_token;
 126     uint64_t pfault_compare;
 127     uint64_t pfault_select;
 128
 129     uint64_t gbea;
 130     uint64_t pp;
 131
 132     CPU_COMMON
 133
 134     /* reset does memset(0) up to here */
 135
 136     uint32_t cpu_num;
 137     uint32_t machine_type;
 138
 139     uint8_t *storage_keys;
 140
 141     uint64_t tod_offset;
 142     uint64_t tod_basetime;
 143     QEMUTimer *tod_timer;
 144
 145     QEMUTimer *cpu_timer;
 146
 147     /*
 148      * The cpu state represents the logical state of a cpu. In contrast to other
 149      * architectures, there is a difference between a halt and a stop on s390.
 150      * If all cpus are either stopped (including check stop) or in the disabled
 151      * wait state, the vm can be shut down.
 152      */
 153 #define CPU_STATE_UNINITIALIZED        0x00
 154 #define CPU_STATE_STOPPED              0x01
 155 #define CPU_STATE_CHECK_STOP           0x02
 156 #define CPU_STATE_OPERATING            0x03
 157 #define CPU_STATE_LOAD                 0x04
 158     uint8_t cpu_state;
 159
 160     /* currently processed sigp order */
 161     uint8_t sigp_order;
 162
 163 } CPUS390XState;
 164
 165 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
 166 {
 167     return &cs->fregs[nr];
 168 }
 169
 170 #include "cpu-qom.h"
 171 #include <sysemu/kvm.h>
 172
 173 /* distinguish between 24 bit and 31 bit addressing */
 174 #define HIGH_ORDER_BIT 0x80000000
 175
 176 /* Interrupt Codes */
 177 /* Program Interrupts */
 178 #define PGM_OPERATION                   0x0001
 179 #define PGM_PRIVILEGED                  0x0002
 180 #define PGM_EXECUTE                     0x0003
 181 #define PGM_PROTECTION                  0x0004
 182 #define PGM_ADDRESSING                  0x0005
 183 #define PGM_SPECIFICATION               0x0006
 184 #define PGM_DATA                        0x0007
 185 #define PGM_FIXPT_OVERFLOW              0x0008
 186 #define PGM_FIXPT_DIVIDE                0x0009
 187 #define PGM_DEC_OVERFLOW                0x000a
 188 #define PGM_DEC_DIVIDE                  0x000b
 189 #define PGM_HFP_EXP_OVERFLOW            0x000c
 190 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 191 #define PGM_HFP_SIGNIFICANCE            0x000e
 192 #define PGM_HFP_DIVIDE                  0x000f
 193 #define PGM_SEGMENT_TRANS               0x0010
 194 #define PGM_PAGE_TRANS                  0x0011
 195 #define PGM_TRANS_SPEC                  0x0012
 196 #define PGM_SPECIAL_OP                  0x0013
 197 #define PGM_OPERAND                     0x0015
 198 #define PGM_TRACE_TABLE                 0x0016
 199 #define PGM_SPACE_SWITCH                0x001c
 200 #define PGM_HFP_SQRT                    0x001d
 201 #define PGM_PC_TRANS_SPEC               0x001f
 202 #define PGM_AFX_TRANS                   0x0020
 203 #define PGM_ASX_TRANS                   0x0021
 204 #define PGM_LX_TRANS                    0x0022
 205 #define PGM_EX_TRANS                    0x0023
 206 #define PGM_PRIM_AUTH                   0x0024
 207 #define PGM_SEC_AUTH                    0x0025
 208 #define PGM_ALET_SPEC                   0x0028
 209 #define PGM_ALEN_SPEC                   0x0029
 210 #define PGM_ALE_SEQ                     0x002a
 211 #define PGM_ASTE_VALID                  0x002b
 212 #define PGM_ASTE_SEQ                    0x002c
 213 #define PGM_EXT_AUTH                    0x002d
 214 #define PGM_STACK_FULL                  0x0030
 215 #define PGM_STACK_EMPTY                 0x0031
 216 #define PGM_STACK_SPEC                  0x0032
 217 #define PGM_STACK_TYPE                  0x0033
 218 #define PGM_STACK_OP                    0x0034
 219 #define PGM_ASCE_TYPE                   0x0038
 220 #define PGM_REG_FIRST_TRANS             0x0039
 221 #define PGM_REG_SEC_TRANS               0x003a
 222 #define PGM_REG_THIRD_TRANS             0x003b
 223 #define PGM_MONITOR                     0x0040
 224 #define PGM_PER                         0x0080
 225 #define PGM_CRYPTO                      0x0119
 226
 227 /* External Interrupts */
 228 #define EXT_INTERRUPT_KEY               0x0040
 229 #define EXT_CLOCK_COMP                  0x1004
 230 #define EXT_CPU_TIMER                   0x1005
 231 #define EXT_MALFUNCTION                 0x1200
 232 #define EXT_EMERGENCY                   0x1201
 233 #define EXT_EXTERNAL_CALL               0x1202
 234 #define EXT_ETR                         0x1406
 235 #define EXT_SERVICE                     0x2401
 236 #define EXT_VIRTIO                      0x2603
 237
 238 /* PSW defines */
 239 #undef PSW_MASK_PER
 240 #undef PSW_MASK_DAT
 241 #undef PSW_MASK_IO
 242 #undef PSW_MASK_EXT
 243 #undef PSW_MASK_KEY
 244 #undef PSW_SHIFT_KEY
 245 #undef PSW_MASK_MCHECK
 246 #undef PSW_MASK_WAIT
 247 #undef PSW_MASK_PSTATE
 248 #undef PSW_MASK_ASC
 249 #undef PSW_MASK_CC
 250 #undef PSW_MASK_PM
 251 #undef PSW_MASK_64
 252 #undef PSW_MASK_32
 253 #undef PSW_MASK_ESA_ADDR
 254
 255 #define PSW_MASK_PER            0x4000000000000000ULL
 256 #define PSW_MASK_DAT            0x0400000000000000ULL
 257 #define PSW_MASK_IO             0x0200000000000000ULL
 258 #define PSW_MASK_EXT            0x0100000000000000ULL
 259 #define PSW_MASK_KEY            0x00F0000000000000ULL
 260 #define PSW_SHIFT_KEY           56
 261 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 262 #define PSW_MASK_WAIT           0x0002000000000000ULL
 263 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 264 #define PSW_MASK_ASC            0x0000C00000000000ULL
 265 #define PSW_MASK_CC             0x0000300000000000ULL
 266 #define PSW_MASK_PM             0x00000F0000000000ULL
 267 #define PSW_MASK_64             0x0000000100000000ULL
 268 #define PSW_MASK_32             0x0000000080000000ULL
 269 #define PSW_MASK_ESA_ADDR       0x000000007fffffffULL
 270
 271 #undef PSW_ASC_PRIMARY
 272 #undef PSW_ASC_ACCREG
 273 #undef PSW_ASC_SECONDARY
 274 #undef PSW_ASC_HOME
 275
 276 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 277 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 278 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 279 #define PSW_ASC_HOME            0x0000C00000000000ULL
 280
 281 /* tb flags */
 282
 283 #define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)
 284 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)
 285 #define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)
 286 #define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)
 287 #define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)
 288 #define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)
 289 #define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)
 290 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)
 291 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)
 292 #define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)
 293 #define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)
 294 #define FLAG_MASK_64            (PSW_MASK_64     >> 32)
 295 #define FLAG_MASK_32            0x00001000
 296
 297 /* Control register 0 bits */
 298 #define CR0_LOWPROT             0x0000000010000000ULL
 299 #define CR0_EDAT                0x0000000000800000ULL
 300
 301 static inline int cpu_mmu_index (CPUS390XState *env)
 302 {
 303     if (env->psw.mask & PSW_MASK_PSTATE) {
 304         return 1;
 305     }
 306
 307     return 0;
 308 }
 309
 310 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 311                                         target_ulong *cs_base, int *flags)
 312 {
 313     *pc = env->psw.addr;
 314     *cs_base = 0;
 315     *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
 316              ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
 317 }
 318
 319 /* While the PoO talks about ILC (a number between 1-3) what is actually
 320    stored in LowCore is shifted left one bit (an even between 2-6).  As
 321    this is the actual length of the insn and therefore more useful, that
 322    is what we want to pass around and manipulate.  To make sure that we
 323    have applied this distinction universally, rename the "ILC" to "ILEN".  */
 324 static inline int get_ilen(uint8_t opc)
 325 {
 326     switch (opc >> 6) {
 327     case 0:
 328         return 2;
 329     case 1:
 330     case 2:
 331         return 4;
 332     default:
 333         return 6;
 334     }
 335 }
 336
 337 #ifndef CONFIG_USER_ONLY
 338 /* In several cases of runtime exceptions, we havn't recorded the true
 339    instruction length.  Use these codes when raising exceptions in order
 340    to re-compute the length by examining the insn in memory.  */
 341 #define ILEN_LATER       0x20
 342 #define ILEN_LATER_INC   0x21
 343 void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
 344 #endif
 345
 346 S390CPU *cpu_s390x_init(const char *cpu_model);
 347 void s390x_translate_init(void);
 348 int cpu_s390x_exec(CPUS390XState *s);
 349
 350 /* you can call this signal handler from your SIGBUS and SIGSEGV
 351    signal handlers to inform the virtual CPU of exceptions. non zero
 352    is returned if the signal was handled by the virtual CPU.  */
 353 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 354                            void *puc);
 355 int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 356                               int mmu_idx);
 357
 358 #include "ioinst.h"
 359
 360
 361 #ifndef CONFIG_USER_ONLY
 362 void do_restart_interrupt(CPUS390XState *env);
 363
 364 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
 365                                        uint8_t *ar)
 366 {
 367     hwaddr addr = 0;
 368     uint8_t reg;
 369
 370     reg = ipb >> 28;
 371     if (reg > 0) {
 372         addr = env->regs[reg];
 373     }
 374     addr += (ipb >> 16) & 0xfff;
 375     if (ar) {
 376         *ar = reg;
 377     }
 378
 379     return addr;
 380 }
 381
 382 /* Base/displacement are at the same locations. */
 383 #define decode_basedisp_rs decode_basedisp_s
 384
 385 /* helper functions for run_on_cpu() */
 386 static inline void s390_do_cpu_reset(void *arg)
 387 {
 388     CPUState *cs = arg;
 389     S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 390
 391     scc->cpu_reset(cs);
 392 }
 393 static inline void s390_do_cpu_full_reset(void *arg)
 394 {
 395     CPUState *cs = arg;
 396
 397     cpu_reset(cs);
 398 }
 399
 400 void s390x_tod_timer(void *opaque);
 401 void s390x_cpu_timer(void *opaque);
 402
 403 int s390_virtio_hypercall(CPUS390XState *env);
 404 void s390_virtio_irq(int config_change, uint64_t token);
 405
 406 #ifdef CONFIG_KVM
 407 void kvm_s390_virtio_irq(int config_change, uint64_t token);
 408 void kvm_s390_service_interrupt(uint32_t parm);
 409 void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
 410 void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
 411 int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
 412 void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
 413 int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
 414                     int len, bool is_write);
 415 int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
 416 int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
 417 #else
 418 static inline void kvm_s390_virtio_irq(int config_change, uint64_t token)
 419 {
 420 }
 421 static inline void kvm_s390_service_interrupt(uint32_t parm)
 422 {
 423 }
 424 static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
 425 {
 426     return -ENOSYS;
 427 }
 428 static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
 429 {
 430     return -ENOSYS;
 431 }
 432 static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
 433                                   void *hostbuf, int len, bool is_write)
 434 {
 435     return -ENOSYS;
 436 }
 437 static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
 438                                              uint64_t te_code)
 439 {
 440 }
 441 #endif
 442
 443 static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
 444 {
 445     if (kvm_enabled()) {
 446         return kvm_s390_get_clock(tod_high, tod_low);
 447     }
 448     /* Fixme TCG */
 449     *tod_high = 0;
 450     *tod_low = 0;
 451     return 0;
 452 }
 453
 454 static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
 455 {
 456     if (kvm_enabled()) {
 457         return kvm_s390_set_clock(tod_high, tod_low);
 458     }
 459     /* Fixme TCG */
 460     return 0;
 461 }
 462
 463 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 464 unsigned int s390_cpu_halt(S390CPU *cpu);
 465 void s390_cpu_unhalt(S390CPU *cpu);
 466 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
 467 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
 468 {
 469     return cpu->env.cpu_state;
 470 }
 471
 472 void gtod_save(QEMUFile *f, void *opaque);
 473 int gtod_load(QEMUFile *f, void *opaque, int version_id);
 474
 475 /* service interrupts are floating therefore we must not pass an cpustate */
 476 void s390_sclp_extint(uint32_t parm);
 477
 478 /* from s390-virtio-bus */
 479 extern const hwaddr virtio_size;
 480
 481 #else
 482 static inline unsigned int s390_cpu_halt(S390CPU *cpu)
 483 {
 484     return 0;
 485 }
 486
 487 static inline void s390_cpu_unhalt(S390CPU *cpu)
 488 {
 489 }
 490
 491 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
 492 {
 493     return 0;
 494 }
 495 #endif
 496 void cpu_lock(void);
 497 void cpu_unlock(void);
 498
 499 typedef struct SubchDev SubchDev;
 500
 501 #ifndef CONFIG_USER_ONLY
 502 extern void io_subsystem_reset(void);
 503 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 504                          uint16_t schid);
 505 bool css_subch_visible(SubchDev *sch);
 506 void css_conditional_io_interrupt(SubchDev *sch);
 507 int css_do_stsch(SubchDev *sch, SCHIB *schib);
 508 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
 509 int css_do_msch(SubchDev *sch, const SCHIB *schib);
 510 int css_do_xsch(SubchDev *sch);
 511 int css_do_csch(SubchDev *sch);
 512 int css_do_hsch(SubchDev *sch);
 513 int css_do_ssch(SubchDev *sch, ORB *orb);
 514 int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
 515 void css_do_tsch_update_subch(SubchDev *sch);
 516 int css_do_stcrw(CRW *crw);
 517 void css_undo_stcrw(CRW *crw);
 518 int css_do_tpi(IOIntCode *int_code, int lowcore);
 519 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
 520                          int rfmt, void *buf);
 521 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
 522 int css_enable_mcsse(void);
 523 int css_enable_mss(void);
 524 int css_do_rsch(SubchDev *sch);
 525 int css_do_rchp(uint8_t cssid, uint8_t chpid);
 526 bool css_present(uint8_t cssid);
 527 #endif
 528
 529 #define cpu_init(model) CPU(cpu_s390x_init(model))
 530 #define cpu_exec cpu_s390x_exec
 531 #define cpu_gen_code cpu_s390x_gen_code
 532 #define cpu_signal_handler cpu_s390x_signal_handler
 533
 534 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 535 #define cpu_list s390_cpu_list
 536
 537 #include "exec/exec-all.h"
 538
 539 #define EXCP_EXT 1 /* external interrupt */
 540 #define EXCP_SVC 2 /* supervisor call (syscall) */
 541 #define EXCP_PGM 3 /* program interruption */
 542 #define EXCP_IO  7 /* I/O interrupt */
 543 #define EXCP_MCHK 8 /* machine check */
 544
 545 #define INTERRUPT_EXT        (1 << 0)
 546 #define INTERRUPT_TOD        (1 << 1)
 547 #define INTERRUPT_CPUTIMER   (1 << 2)
 548 #define INTERRUPT_IO         (1 << 3)
 549 #define INTERRUPT_MCHK       (1 << 4)
 550
 551 /* Program Status Word.  */
 552 #define S390_PSWM_REGNUM 0
 553 #define S390_PSWA_REGNUM 1
 554 /* General Purpose Registers.  */
 555 #define S390_R0_REGNUM 2
 556 #define S390_R1_REGNUM 3
 557 #define S390_R2_REGNUM 4
 558 #define S390_R3_REGNUM 5
 559 #define S390_R4_REGNUM 6
 560 #define S390_R5_REGNUM 7
 561 #define S390_R6_REGNUM 8
 562 #define S390_R7_REGNUM 9
 563 #define S390_R8_REGNUM 10
 564 #define S390_R9_REGNUM 11
 565 #define S390_R10_REGNUM 12
 566 #define S390_R11_REGNUM 13
 567 #define S390_R12_REGNUM 14
 568 #define S390_R13_REGNUM 15
 569 #define S390_R14_REGNUM 16
 570 #define S390_R15_REGNUM 17
 571 /* Total Core Registers. */
 572 #define S390_NUM_CORE_REGS 18
 573
 574 /* CC optimization */
 575
 576 enum cc_op {
 577     CC_OP_CONST0 = 0,           /* CC is 0 */
 578     CC_OP_CONST1,               /* CC is 1 */
 579     CC_OP_CONST2,               /* CC is 2 */
 580     CC_OP_CONST3,               /* CC is 3 */
 581
 582     CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
 583     CC_OP_STATIC,               /* CC value is env->cc_op */
 584
 585     CC_OP_NZ,                   /* env->cc_dst != 0 */
 586     CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
 587     CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
 588     CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
 589     CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
 590     CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
 591     CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
 592
 593     CC_OP_ADD_64,               /* overflow on add (64bit) */
 594     CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
 595     CC_OP_ADDC_64,              /* overflow on unsigned add-carry (64bit) */
 596     CC_OP_SUB_64,               /* overflow on subtraction (64bit) */
 597     CC_OP_SUBU_64,              /* overflow on unsigned subtraction (64bit) */
 598     CC_OP_SUBB_64,              /* overflow on unsigned sub-borrow (64bit) */
 599     CC_OP_ABS_64,               /* sign eval on abs (64bit) */
 600     CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
 601
 602     CC_OP_ADD_32,               /* overflow on add (32bit) */
 603     CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
 604     CC_OP_ADDC_32,              /* overflow on unsigned add-carry (32bit) */
 605     CC_OP_SUB_32,               /* overflow on subtraction (32bit) */
 606     CC_OP_SUBU_32,              /* overflow on unsigned subtraction (32bit) */
 607     CC_OP_SUBB_32,              /* overflow on unsigned sub-borrow (32bit) */
 608     CC_OP_ABS_32,               /* sign eval on abs (64bit) */
 609     CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
 610
 611     CC_OP_COMP_32,              /* complement */
 612     CC_OP_COMP_64,              /* complement */
 613
 614     CC_OP_TM_32,                /* test under mask (32bit) */
 615     CC_OP_TM_64,                /* test under mask (64bit) */
 616
 617     CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
 618     CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
 619     CC_OP_NZ_F128,              /* FP dst != 0 (128bit) */
 620
 621     CC_OP_ICM,                  /* insert characters under mask */
 622     CC_OP_SLA_32,               /* Calculate shift left signed (32bit) */
 623     CC_OP_SLA_64,               /* Calculate shift left signed (64bit) */
 624     CC_OP_FLOGR,                /* find leftmost one */
 625     CC_OP_MAX
 626 };
 627
 628 static const char *cc_names[] = {
 629     [CC_OP_CONST0]    = "CC_OP_CONST0",
 630     [CC_OP_CONST1]    = "CC_OP_CONST1",
 631     [CC_OP_CONST2]    = "CC_OP_CONST2",
 632     [CC_OP_CONST3]    = "CC_OP_CONST3",
 633     [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 634     [CC_OP_STATIC]    = "CC_OP_STATIC",
 635     [CC_OP_NZ]        = "CC_OP_NZ",
 636     [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 637     [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 638     [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 639     [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 640     [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 641     [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 642     [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 643     [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 644     [CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 645     [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 646     [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 647     [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 648     [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 649     [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 650     [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 651     [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 652     [CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 653     [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 654     [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 655     [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 656     [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 657     [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 658     [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 659     [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 660     [CC_OP_TM_32]     = "CC_OP_TM_32",
 661     [CC_OP_TM_64]     = "CC_OP_TM_64",
 662     [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 663     [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 664     [CC_OP_NZ_F128]   = "CC_OP_NZ_F128",
 665     [CC_OP_ICM]       = "CC_OP_ICM",
 666     [CC_OP_SLA_32]    = "CC_OP_SLA_32",
 667     [CC_OP_SLA_64]    = "CC_OP_SLA_64",
 668     [CC_OP_FLOGR]     = "CC_OP_FLOGR",
 669 };
 670
 671 static inline const char *cc_name(int cc_op)
 672 {
 673     return cc_names[cc_op];
 674 }
 675
 676 static inline void setcc(S390CPU *cpu, uint64_t cc)
 677 {
 678     CPUS390XState *env = &cpu->env;
 679
 680     env->psw.mask &= ~(3ull << 44);
 681     env->psw.mask |= (cc & 3) << 44;
 682 }
 683
 684 typedef struct LowCore
 685 {
 686     /* prefix area: defined by architecture */
 687     uint32_t        ccw1[2];                  /* 0x000 */
 688     uint32_t        ccw2[4];                  /* 0x008 */
 689     uint8_t         pad1[0x80-0x18];          /* 0x018 */
 690     uint32_t        ext_params;               /* 0x080 */
 691     uint16_t        cpu_addr;                 /* 0x084 */
 692     uint16_t        ext_int_code;             /* 0x086 */
 693     uint16_t        svc_ilen;                 /* 0x088 */
 694     uint16_t        svc_code;                 /* 0x08a */
 695     uint16_t        pgm_ilen;                 /* 0x08c */
 696     uint16_t        pgm_code;                 /* 0x08e */
 697     uint32_t        data_exc_code;            /* 0x090 */
 698     uint16_t        mon_class_num;            /* 0x094 */
 699     uint16_t        per_perc_atmid;           /* 0x096 */
 700     uint64_t        per_address;              /* 0x098 */
 701     uint8_t         exc_access_id;            /* 0x0a0 */
 702     uint8_t         per_access_id;            /* 0x0a1 */
 703     uint8_t         op_access_id;             /* 0x0a2 */
 704     uint8_t         ar_access_id;             /* 0x0a3 */
 705     uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
 706     uint64_t        trans_exc_code;           /* 0x0a8 */
 707     uint64_t        monitor_code;             /* 0x0b0 */
 708     uint16_t        subchannel_id;            /* 0x0b8 */
 709     uint16_t        subchannel_nr;            /* 0x0ba */
 710     uint32_t        io_int_parm;              /* 0x0bc */
 711     uint32_t        io_int_word;              /* 0x0c0 */
 712     uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
 713     uint32_t        stfl_fac_list;            /* 0x0c8 */
 714     uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
 715     uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
 716     uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
 717     uint32_t        external_damage_code;     /* 0x0f4 */
 718     uint64_t        failing_storage_address;  /* 0x0f8 */
 719     uint8_t         pad6[0x120-0x100];        /* 0x100 */
 720     PSW             restart_old_psw;          /* 0x120 */
 721     PSW             external_old_psw;         /* 0x130 */
 722     PSW             svc_old_psw;              /* 0x140 */
 723     PSW             program_old_psw;          /* 0x150 */
 724     PSW             mcck_old_psw;             /* 0x160 */
 725     PSW             io_old_psw;               /* 0x170 */
 726     uint8_t         pad7[0x1a0-0x180];        /* 0x180 */
 727     PSW             restart_new_psw;          /* 0x1a0 */
 728     PSW             external_new_psw;         /* 0x1b0 */
 729     PSW             svc_new_psw;              /* 0x1c0 */
 730     PSW             program_new_psw;          /* 0x1d0 */
 731     PSW             mcck_new_psw;             /* 0x1e0 */
 732     PSW             io_new_psw;               /* 0x1f0 */
 733     PSW             return_psw;               /* 0x200 */
 734     uint8_t         irb[64];                  /* 0x210 */
 735     uint64_t        sync_enter_timer;         /* 0x250 */
 736     uint64_t        async_enter_timer;        /* 0x258 */
 737     uint64_t        exit_timer;               /* 0x260 */
 738     uint64_t        last_update_timer;        /* 0x268 */
 739     uint64_t        user_timer;               /* 0x270 */
 740     uint64_t        system_timer;             /* 0x278 */
 741     uint64_t        last_update_clock;        /* 0x280 */
 742     uint64_t        steal_clock;              /* 0x288 */
 743     PSW             return_mcck_psw;          /* 0x290 */
 744     uint8_t         pad8[0xc00-0x2a0];        /* 0x2a0 */
 745     /* System info area */
 746     uint64_t        save_area[16];            /* 0xc00 */
 747     uint8_t         pad9[0xd40-0xc80];        /* 0xc80 */
 748     uint64_t        kernel_stack;             /* 0xd40 */
 749     uint64_t        thread_info;              /* 0xd48 */
 750     uint64_t        async_stack;              /* 0xd50 */
 751     uint64_t        kernel_asce;              /* 0xd58 */
 752     uint64_t        user_asce;                /* 0xd60 */
 753     uint64_t        panic_stack;              /* 0xd68 */
 754     uint64_t        user_exec_asce;           /* 0xd70 */
 755     uint8_t         pad10[0xdc0-0xd78];       /* 0xd78 */
 756
 757     /* SMP info area: defined by DJB */
 758     uint64_t        clock_comparator;         /* 0xdc0 */
 759     uint64_t        ext_call_fast;            /* 0xdc8 */
 760     uint64_t        percpu_offset;            /* 0xdd0 */
 761     uint64_t        current_task;             /* 0xdd8 */
 762     uint32_t        softirq_pending;          /* 0xde0 */
 763     uint32_t        pad_0x0de4;               /* 0xde4 */
 764     uint64_t        int_clock;                /* 0xde8 */
 765     uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
 766
 767     /* 0xe00 is used as indicator for dump tools */
 768     /* whether the kernel died with panic() or not */
 769     uint32_t        panic_magic;              /* 0xe00 */
 770
 771     uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
 772
 773     /* 64 bit extparam used for pfault, diag 250 etc  */
 774     uint64_t        ext_params2;               /* 0x11B8 */
 775
 776     uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
 777
 778     /* System info area */
 779
 780     uint64_t        floating_pt_save_area[16]; /* 0x1200 */
 781     uint64_t        gpregs_save_area[16];      /* 0x1280 */
 782     uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
 783     uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
 784     uint32_t        prefixreg_save_area;       /* 0x1318 */
 785     uint32_t        fpt_creg_save_area;        /* 0x131c */
 786     uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
 787     uint32_t        tod_progreg_save_area;     /* 0x1324 */
 788     uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
 789     uint32_t        clock_comp_save_area[2];   /* 0x1330 */
 790     uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
 791     uint32_t        access_regs_save_area[16]; /* 0x1340 */
 792     uint64_t        cregs_save_area[16];       /* 0x1380 */
 793
 794     /* align to the top of the prefix area */
 795
 796     uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
 797 } QEMU_PACKED LowCore;
 798
 799 /* STSI */
 800 #define STSI_LEVEL_MASK         0x00000000f0000000ULL
 801 #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
 802 #define STSI_LEVEL_1            0x0000000010000000ULL
 803 #define STSI_LEVEL_2            0x0000000020000000ULL
 804 #define STSI_LEVEL_3            0x0000000030000000ULL
 805 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 806 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 807 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 808 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 809
 810 /* Basic Machine Configuration */
 811 struct sysib_111 {
 812     uint32_t res1[8];
 813     uint8_t  manuf[16];
 814     uint8_t  type[4];
 815     uint8_t  res2[12];
 816     uint8_t  model[16];
 817     uint8_t  sequence[16];
 818     uint8_t  plant[4];
 819     uint8_t  res3[156];
 820 };
 821
 822 /* Basic Machine CPU */
 823 struct sysib_121 {
 824     uint32_t res1[80];
 825     uint8_t  sequence[16];
 826     uint8_t  plant[4];
 827     uint8_t  res2[2];
 828     uint16_t cpu_addr;
 829     uint8_t  res3[152];
 830 };
 831
 832 /* Basic Machine CPUs */
 833 struct sysib_122 {
 834     uint8_t res1[32];
 835     uint32_t capability;
 836     uint16_t total_cpus;
 837     uint16_t active_cpus;
 838     uint16_t standby_cpus;
 839     uint16_t reserved_cpus;
 840     uint16_t adjustments[2026];
 841 };
 842
 843 /* LPAR CPU */
 844 struct sysib_221 {
 845     uint32_t res1[80];
 846     uint8_t  sequence[16];
 847     uint8_t  plant[4];
 848     uint16_t cpu_id;
 849     uint16_t cpu_addr;
 850     uint8_t  res3[152];
 851 };
 852
 853 /* LPAR CPUs */
 854 struct sysib_222 {
 855     uint32_t res1[32];
 856     uint16_t lpar_num;
 857     uint8_t  res2;
 858     uint8_t  lcpuc;
 859     uint16_t total_cpus;
 860     uint16_t conf_cpus;
 861     uint16_t standby_cpus;
 862     uint16_t reserved_cpus;
 863     uint8_t  name[8];
 864     uint32_t caf;
 865     uint8_t  res3[16];
 866     uint16_t dedicated_cpus;
 867     uint16_t shared_cpus;
 868     uint8_t  res4[180];
 869 };
 870
 871 /* VM CPUs */
 872 struct sysib_322 {
 873     uint8_t  res1[31];
 874     uint8_t  count;
 875     struct {
 876         uint8_t  res2[4];
 877         uint16_t total_cpus;
 878         uint16_t conf_cpus;
 879         uint16_t standby_cpus;
 880         uint16_t reserved_cpus;
 881         uint8_t  name[8];
 882         uint32_t caf;
 883         uint8_t  cpi[16];
 884         uint8_t res5[3];
 885         uint8_t ext_name_encoding;
 886         uint32_t res3;
 887         uint8_t uuid[16];
 888     } vm[8];
 889     uint8_t res4[1504];
 890     uint8_t ext_names[8][256];
 891 };
 892
 893 /* MMU defines */
 894 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 895 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 896 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 897 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 898 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 899 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 900 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 901 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 902 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 903 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 904 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 905 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 906
 907 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 908 #define _REGION_ENTRY_RO        0x200     /* region/segment protection bit    */
 909 #define _REGION_ENTRY_TF        0xc0      /* region/segment table offset      */
 910 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 911 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 912 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 913 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 914 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 915 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 916
 917 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 918 #define _SEGMENT_ENTRY_FC       0x400     /* format control                   */
 919 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 920 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 921
 922 #define _PAGE_RO        0x200            /* HW read-only bit  */
 923 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 924 #define _PAGE_RES0      0x800            /* bit must be zero  */
 925
 926 #define SK_C                    (0x1 << 1)
 927 #define SK_R                    (0x1 << 2)
 928 #define SK_F                    (0x1 << 3)
 929 #define SK_ACC_MASK             (0xf << 4)
 930
 931 /* SIGP order codes */
 932 #define SIGP_SENSE             0x01
 933 #define SIGP_EXTERNAL_CALL     0x02
 934 #define SIGP_EMERGENCY         0x03
 935 #define SIGP_START             0x04
 936 #define SIGP_STOP              0x05
 937 #define SIGP_RESTART           0x06
 938 #define SIGP_STOP_STORE_STATUS 0x09
 939 #define SIGP_INITIAL_CPU_RESET 0x0b
 940 #define SIGP_CPU_RESET         0x0c
 941 #define SIGP_SET_PREFIX        0x0d
 942 #define SIGP_STORE_STATUS_ADDR 0x0e
 943 #define SIGP_SET_ARCH          0x12
 944
 945 /* SIGP condition codes */
 946 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
 947 #define SIGP_CC_STATUS_STORED       1
 948 #define SIGP_CC_BUSY                2
 949 #define SIGP_CC_NOT_OPERATIONAL     3
 950
 951 /* SIGP status bits */
 952 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 953 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 954 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 955 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 956 #define SIGP_STAT_STOPPED           0x00000040UL
 957 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 958 #define SIGP_STAT_CHECK_STOP        0x00000010UL
 959 #define SIGP_STAT_INOPERATIVE       0x00000004UL
 960 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
 961 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 962
 963 /* SIGP SET ARCHITECTURE modes */
 964 #define SIGP_MODE_ESA_S390 0
 965 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
 966 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
 967
 968 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
 969 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 970                   target_ulong *raddr, int *flags, bool exc);
 971 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
 972 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
 973                  uint64_t vr);
 974
 975 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
 976                          int len, bool is_write);
 977
 978 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len)    \
 979         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
 980 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len)       \
 981         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
 982 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len)   \
 983         s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
 984
 985 /* The value of the TOD clock for 1.1.1970. */
 986 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
 987
 988 /* Converts ns to s390's clock format */
 989 static inline uint64_t time2tod(uint64_t ns) {
 990     return (ns << 9) / 125;
 991 }
 992
 993 static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
 994                                   uint64_t param64)
 995 {
 996     CPUS390XState *env = &cpu->env;
 997
 998     if (env->ext_index == MAX_EXT_QUEUE - 1) {
 999         /* ugh - can't queue anymore. Let's drop. */
1000         return;
1001     }
1002
1003     env->ext_index++;
1004     assert(env->ext_index < MAX_EXT_QUEUE);
1005
1006     env->ext_queue[env->ext_index].code = code;
1007     env->ext_queue[env->ext_index].param = param;
1008     env->ext_queue[env->ext_index].param64 = param64;
1009
1010     env->pending_int |= INTERRUPT_EXT;
1011     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1012 }
1013
1014 static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
1015                                  uint16_t subchannel_number,
1016                                  uint32_t io_int_parm, uint32_t io_int_word)
1017 {
1018     CPUS390XState *env = &cpu->env;
1019     int isc = IO_INT_WORD_ISC(io_int_word);
1020
1021     if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1022         /* ugh - can't queue anymore. Let's drop. */
1023         return;
1024     }
1025
1026     env->io_index[isc]++;
1027     assert(env->io_index[isc] < MAX_IO_QUEUE);
1028
1029     env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1030     env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1031     env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1032     env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1033
1034     env->pending_int |= INTERRUPT_IO;
1035     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1036 }
1037
1038 static inline void cpu_inject_crw_mchk(S390CPU *cpu)
1039 {
1040     CPUS390XState *env = &cpu->env;
1041
1042     if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1043         /* ugh - can't queue anymore. Let's drop. */
1044         return;
1045     }
1046
1047     env->mchk_index++;
1048     assert(env->mchk_index < MAX_MCHK_QUEUE);
1049
1050     env->mchk_queue[env->mchk_index].type = 1;
1051
1052     env->pending_int |= INTERRUPT_MCHK;
1053     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1054 }
1055
1056 /* from s390-virtio-ccw */
1057 #define MEM_SECTION_SIZE             0x10000000UL
1058 #define MAX_AVAIL_SLOTS              32
1059
1060 /* fpu_helper.c */
1061 uint32_t set_cc_nz_f32(float32 v);
1062 uint32_t set_cc_nz_f64(float64 v);
1063 uint32_t set_cc_nz_f128(float128 v);
1064
1065 /* misc_helper.c */
1066 #ifndef CONFIG_USER_ONLY
1067 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1068 #endif
1069 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1070 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1071                                      uintptr_t retaddr);
1072
1073 #ifdef CONFIG_KVM
1074 void kvm_s390_io_interrupt(uint16_t subchannel_id,
1075                            uint16_t subchannel_nr, uint32_t io_int_parm,
1076                            uint32_t io_int_word);
1077 void kvm_s390_crw_mchk(void);
1078 void kvm_s390_enable_css_support(S390CPU *cpu);
1079 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1080                                     int vq, bool assign);
1081 int kvm_s390_cpu_restart(S390CPU *cpu);
1082 int kvm_s390_get_memslot_count(KVMState *s);
1083 void kvm_s390_clear_cmma_callback(void *opaque);
1084 int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
1085 void kvm_s390_reset_vcpu(S390CPU *cpu);
1086 int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
1087 void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
1088 int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
1089 #else
1090 static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1091                                         uint16_t subchannel_nr,
1092                                         uint32_t io_int_parm,
1093                                         uint32_t io_int_word)
1094 {
1095 }
1096 static inline void kvm_s390_crw_mchk(void)
1097 {
1098 }
1099 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1100 {
1101 }
1102 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1103                                                   uint32_t sch, int vq,
1104                                                   bool assign)
1105 {
1106     return -ENOSYS;
1107 }
1108 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1109 {
1110     return -ENOSYS;
1111 }
1112 static inline void kvm_s390_clear_cmma_callback(void *opaque)
1113 {
1114 }
1115 static inline int kvm_s390_get_memslot_count(KVMState *s)
1116 {
1117   return MAX_AVAIL_SLOTS;
1118 }
1119 static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1120 {
1121     return -ENOSYS;
1122 }
1123 static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1124 {
1125 }
1126 static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1127                                          uint64_t *hw_limit)
1128 {
1129     return 0;
1130 }
1131 static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
1132 {
1133 }
1134 static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
1135 {
1136     return 0;
1137 }
1138 #endif
1139
1140 static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1141 {
1142     if (kvm_enabled()) {
1143         return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1144     }
1145     return 0;
1146 }
1147
1148 static inline void cmma_reset(S390CPU *cpu)
1149 {
1150     if (kvm_enabled()) {
1151         CPUState *cs = CPU(cpu);
1152         kvm_s390_clear_cmma_callback(cs->kvm_state);
1153     }
1154 }
1155
1156 static inline int s390_cpu_restart(S390CPU *cpu)
1157 {
1158     if (kvm_enabled()) {
1159         return kvm_s390_cpu_restart(cpu);
1160     }
1161     return -ENOSYS;
1162 }
1163
1164 static inline int s390_get_memslot_count(KVMState *s)
1165 {
1166     if (kvm_enabled()) {
1167         return kvm_s390_get_memslot_count(s);
1168     } else {
1169         return MAX_AVAIL_SLOTS;
1170     }
1171 }
1172
1173 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1174                        uint32_t io_int_parm, uint32_t io_int_word);
1175 void s390_crw_mchk(void);
1176
1177 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1178                                               uint32_t sch_id, int vq,
1179                                               bool assign)
1180 {
1181     if (kvm_enabled()) {
1182         return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1183     } else {
1184         return -ENOSYS;
1185     }
1186 }
1187
1188 #endif