hw/input/pckbd.c

   1 /*
   2  * QEMU PC keyboard emulation
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/log.h"
  27 #include "hw/isa/isa.h"
  28 #include "migration/vmstate.h"
  29 #include "hw/acpi/aml-build.h"
  30 #include "hw/input/ps2.h"
  31 #include "hw/irq.h"
  32 #include "hw/input/i8042.h"
  33 #include "sysemu/reset.h"
  34 #include "sysemu/runstate.h"
  35
  36 #include "trace.h"
  37
  38 /*      Keyboard Controller Commands */
  39 #define KBD_CCMD_READ_MODE      0x20    /* Read mode bits */
  40 #define KBD_CCMD_WRITE_MODE     0x60    /* Write mode bits */
  41 #define KBD_CCMD_GET_VERSION    0xA1    /* Get controller version */
  42 #define KBD_CCMD_MOUSE_DISABLE  0xA7    /* Disable mouse interface */
  43 #define KBD_CCMD_MOUSE_ENABLE   0xA8    /* Enable mouse interface */
  44 #define KBD_CCMD_TEST_MOUSE     0xA9    /* Mouse interface test */
  45 #define KBD_CCMD_SELF_TEST      0xAA    /* Controller self test */
  46 #define KBD_CCMD_KBD_TEST       0xAB    /* Keyboard interface test */
  47 #define KBD_CCMD_KBD_DISABLE    0xAD    /* Keyboard interface disable */
  48 #define KBD_CCMD_KBD_ENABLE     0xAE    /* Keyboard interface enable */
  49 #define KBD_CCMD_READ_INPORT    0xC0    /* read input port */
  50 #define KBD_CCMD_READ_OUTPORT   0xD0    /* read output port */
  51 #define KBD_CCMD_WRITE_OUTPORT  0xD1    /* write output port */
  52 #define KBD_CCMD_WRITE_OBUF     0xD2
  53 #define KBD_CCMD_WRITE_AUX_OBUF 0xD3    /* Write to output buffer as if
  54                                            initiated by the auxiliary device */
  55 #define KBD_CCMD_WRITE_MOUSE    0xD4    /* Write the following byte to the mouse */
  56 #define KBD_CCMD_DISABLE_A20    0xDD    /* HP vectra only ? */
  57 #define KBD_CCMD_ENABLE_A20     0xDF    /* HP vectra only ? */
  58 #define KBD_CCMD_PULSE_BITS_3_0 0xF0    /* Pulse bits 3-0 of the output port P2. */
  59 #define KBD_CCMD_RESET          0xFE    /* Pulse bit 0 of the output port P2 = CPU reset. */
  60 #define KBD_CCMD_NO_OP          0xFF    /* Pulse no bits of the output port P2. */
  61
  62 /* Keyboard Commands */
  63 #define KBD_CMD_SET_LEDS        0xED    /* Set keyboard leds */
  64 #define KBD_CMD_ECHO            0xEE
  65 #define KBD_CMD_GET_ID          0xF2    /* get keyboard ID */
  66 #define KBD_CMD_SET_RATE        0xF3    /* Set typematic rate */
  67 #define KBD_CMD_ENABLE          0xF4    /* Enable scanning */
  68 #define KBD_CMD_RESET_DISABLE   0xF5    /* reset and disable scanning */
  69 #define KBD_CMD_RESET_ENABLE    0xF6    /* reset and enable scanning */
  70 #define KBD_CMD_RESET           0xFF    /* Reset */
  71
  72 /* Keyboard Replies */
  73 #define KBD_REPLY_POR           0xAA    /* Power on reset */
  74 #define KBD_REPLY_ACK           0xFA    /* Command ACK */
  75 #define KBD_REPLY_RESEND        0xFE    /* Command NACK, send the cmd again */
  76
  77 /* Status Register Bits */
  78 #define KBD_STAT_OBF            0x01    /* Keyboard output buffer full */
  79 #define KBD_STAT_IBF            0x02    /* Keyboard input buffer full */
  80 #define KBD_STAT_SELFTEST       0x04    /* Self test successful */
  81 #define KBD_STAT_CMD            0x08    /* Last write was a command write (0=data) */
  82 #define KBD_STAT_UNLOCKED       0x10    /* Zero if keyboard locked */
  83 #define KBD_STAT_MOUSE_OBF      0x20    /* Mouse output buffer full */
  84 #define KBD_STAT_GTO            0x40    /* General receive/xmit timeout */
  85 #define KBD_STAT_PERR           0x80    /* Parity error */
  86
  87 /* Controller Mode Register Bits */
  88 #define KBD_MODE_KBD_INT        0x01    /* Keyboard data generate IRQ1 */
  89 #define KBD_MODE_MOUSE_INT      0x02    /* Mouse data generate IRQ12 */
  90 #define KBD_MODE_SYS            0x04    /* The system flag (?) */
  91 #define KBD_MODE_NO_KEYLOCK     0x08    /* The keylock doesn't affect the keyboard if set */
  92 #define KBD_MODE_DISABLE_KBD    0x10    /* Disable keyboard interface */
  93 #define KBD_MODE_DISABLE_MOUSE  0x20    /* Disable mouse interface */
  94 #define KBD_MODE_KCC            0x40    /* Scan code conversion to PC format */
  95 #define KBD_MODE_RFU            0x80
  96
  97 /* Output Port Bits */
  98 #define KBD_OUT_RESET           0x01    /* 1=normal mode, 0=reset */
  99 #define KBD_OUT_A20             0x02    /* x86 only */
 100 #define KBD_OUT_OBF             0x10    /* Keyboard output buffer full */
 101 #define KBD_OUT_MOUSE_OBF       0x20    /* Mouse output buffer full */
 102
 103 /* OSes typically write 0xdd/0xdf to turn the A20 line off and on.
 104  * We make the default value of the outport include these four bits,
 105  * so that the subsection is rarely necessary.
 106  */
 107 #define KBD_OUT_ONES            0xcc
 108
 109 /* Mouse Commands */
 110 #define AUX_SET_SCALE11         0xE6    /* Set 1:1 scaling */
 111 #define AUX_SET_SCALE21         0xE7    /* Set 2:1 scaling */
 112 #define AUX_SET_RES             0xE8    /* Set resolution */
 113 #define AUX_GET_SCALE           0xE9    /* Get scaling factor */
 114 #define AUX_SET_STREAM          0xEA    /* Set stream mode */
 115 #define AUX_POLL                0xEB    /* Poll */
 116 #define AUX_RESET_WRAP          0xEC    /* Reset wrap mode */
 117 #define AUX_SET_WRAP            0xEE    /* Set wrap mode */
 118 #define AUX_SET_REMOTE          0xF0    /* Set remote mode */
 119 #define AUX_GET_TYPE            0xF2    /* Get type */
 120 #define AUX_SET_SAMPLE          0xF3    /* Set sample rate */
 121 #define AUX_ENABLE_DEV          0xF4    /* Enable aux device */
 122 #define AUX_DISABLE_DEV         0xF5    /* Disable aux device */
 123 #define AUX_SET_DEFAULT         0xF6
 124 #define AUX_RESET               0xFF    /* Reset aux device */
 125 #define AUX_ACK                 0xFA    /* Command byte ACK. */
 126
 127 #define MOUSE_STATUS_REMOTE     0x40
 128 #define MOUSE_STATUS_ENABLED    0x20
 129 #define MOUSE_STATUS_SCALE21    0x10
 130
 131 #define KBD_PENDING_KBD         1
 132 #define KBD_PENDING_AUX         2
 133
 134 typedef struct KBDState {
 135     uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
 136     uint8_t status;
 137     uint8_t mode;
 138     uint8_t outport;
 139     bool outport_present;
 140     /* Bitmask of devices with data available.  */
 141     uint8_t pending;
 142     void *kbd;
 143     void *mouse;
 144
 145     qemu_irq irq_kbd;
 146     qemu_irq irq_mouse;
 147     qemu_irq a20_out;
 148     hwaddr mask;
 149 } KBDState;
 150
 151 /* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
 152    incorrect, but it avoids having to simulate exact delays */
 153 static void kbd_update_irq_lines(KBDState *s)
 154 {
 155     int irq_kbd_level, irq_mouse_level;
 156
 157     irq_kbd_level = 0;
 158     irq_mouse_level = 0;
 159
 160     if (s->status & KBD_STAT_OBF) {
 161         if (s->status & KBD_STAT_MOUSE_OBF) {
 162             if (s->mode & KBD_MODE_MOUSE_INT) {
 163                 irq_mouse_level = 1;
 164             }
 165         } else {
 166             if ((s->mode & KBD_MODE_KBD_INT) &&
 167                 !(s->mode & KBD_MODE_DISABLE_KBD)) {
 168                 irq_kbd_level = 1;
 169             }
 170         }
 171     }
 172     qemu_set_irq(s->irq_kbd, irq_kbd_level);
 173     qemu_set_irq(s->irq_mouse, irq_mouse_level);
 174 }
 175
 176 /* update irq and KBD_STAT_[MOUSE_]OBF */
 177 static void kbd_update_irq(KBDState *s)
 178 {
 179     s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
 180     s->outport &= ~(KBD_OUT_OBF | KBD_OUT_MOUSE_OBF);
 181     if (s->pending) {
 182         s->status |= KBD_STAT_OBF;
 183         s->outport |= KBD_OUT_OBF;
 184         /* kbd data takes priority over aux data.  */
 185         if (s->pending == KBD_PENDING_AUX) {
 186             s->status |= KBD_STAT_MOUSE_OBF;
 187             s->outport |= KBD_OUT_MOUSE_OBF;
 188         }
 189     }
 190     kbd_update_irq_lines(s);
 191 }
 192
 193 static void kbd_update_kbd_irq(void *opaque, int level)
 194 {
 195     KBDState *s = (KBDState *)opaque;
 196
 197     if (level)
 198         s->pending |= KBD_PENDING_KBD;
 199     else
 200         s->pending &= ~KBD_PENDING_KBD;
 201     kbd_update_irq(s);
 202 }
 203
 204 static void kbd_update_aux_irq(void *opaque, int level)
 205 {
 206     KBDState *s = (KBDState *)opaque;
 207
 208     if (level)
 209         s->pending |= KBD_PENDING_AUX;
 210     else
 211         s->pending &= ~KBD_PENDING_AUX;
 212     kbd_update_irq(s);
 213 }
 214
 215 static uint64_t kbd_read_status(void *opaque, hwaddr addr,
 216                                 unsigned size)
 217 {
 218     KBDState *s = opaque;
 219     int val;
 220     val = s->status;
 221     trace_pckbd_kbd_read_status(val);
 222     return val;
 223 }
 224
 225 static void kbd_queue(KBDState *s, int b, int aux)
 226 {
 227     if (aux)
 228         ps2_queue(s->mouse, b);
 229     else
 230         ps2_queue(s->kbd, b);
 231 }
 232
 233 static void outport_write(KBDState *s, uint32_t val)
 234 {
 235     trace_pckbd_outport_write(val);
 236     s->outport = val;
 237     qemu_set_irq(s->a20_out, (val >> 1) & 1);
 238     if (!(val & 1)) {
 239         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 240     }
 241 }
 242
 243 static void kbd_write_command(void *opaque, hwaddr addr,
 244                               uint64_t val, unsigned size)
 245 {
 246     KBDState *s = opaque;
 247
 248     trace_pckbd_kbd_write_command(val);
 249
 250     /* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed
 251      * low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE
 252      * command specify the output port bits to be pulsed.
 253      * 0: Bit should be pulsed. 1: Bit should not be modified.
 254      * The only useful version of this command is pulsing bit 0,
 255      * which does a CPU reset.
 256      */
 257     if((val & KBD_CCMD_PULSE_BITS_3_0) == KBD_CCMD_PULSE_BITS_3_0) {
 258         if(!(val & 1))
 259             val = KBD_CCMD_RESET;
 260         else
 261             val = KBD_CCMD_NO_OP;
 262     }
 263
 264     switch(val) {
 265     case KBD_CCMD_READ_MODE:
 266         kbd_queue(s, s->mode, 0);
 267         break;
 268     case KBD_CCMD_WRITE_MODE:
 269     case KBD_CCMD_WRITE_OBUF:
 270     case KBD_CCMD_WRITE_AUX_OBUF:
 271     case KBD_CCMD_WRITE_MOUSE:
 272     case KBD_CCMD_WRITE_OUTPORT:
 273         s->write_cmd = val;
 274         break;
 275     case KBD_CCMD_MOUSE_DISABLE:
 276         s->mode |= KBD_MODE_DISABLE_MOUSE;
 277         break;
 278     case KBD_CCMD_MOUSE_ENABLE:
 279         s->mode &= ~KBD_MODE_DISABLE_MOUSE;
 280         break;
 281     case KBD_CCMD_TEST_MOUSE:
 282         kbd_queue(s, 0x00, 0);
 283         break;
 284     case KBD_CCMD_SELF_TEST:
 285         s->status |= KBD_STAT_SELFTEST;
 286         kbd_queue(s, 0x55, 0);
 287         break;
 288     case KBD_CCMD_KBD_TEST:
 289         kbd_queue(s, 0x00, 0);
 290         break;
 291     case KBD_CCMD_KBD_DISABLE:
 292         s->mode |= KBD_MODE_DISABLE_KBD;
 293         kbd_update_irq(s);
 294         break;
 295     case KBD_CCMD_KBD_ENABLE:
 296         s->mode &= ~KBD_MODE_DISABLE_KBD;
 297         kbd_update_irq(s);
 298         break;
 299     case KBD_CCMD_READ_INPORT:
 300         kbd_queue(s, 0x80, 0);
 301         break;
 302     case KBD_CCMD_READ_OUTPORT:
 303         kbd_queue(s, s->outport, 0);
 304         break;
 305     case KBD_CCMD_ENABLE_A20:
 306         qemu_irq_raise(s->a20_out);
 307         s->outport |= KBD_OUT_A20;
 308         break;
 309     case KBD_CCMD_DISABLE_A20:
 310         qemu_irq_lower(s->a20_out);
 311         s->outport &= ~KBD_OUT_A20;
 312         break;
 313     case KBD_CCMD_RESET:
 314         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 315         break;
 316     case KBD_CCMD_NO_OP:
 317         /* ignore that */
 318         break;
 319     default:
 320         qemu_log_mask(LOG_GUEST_ERROR,
 321                       "unsupported keyboard cmd=0x%02" PRIx64 "\n", val);
 322         break;
 323     }
 324 }
 325
 326 static uint64_t kbd_read_data(void *opaque, hwaddr addr,
 327                               unsigned size)
 328 {
 329     KBDState *s = opaque;
 330     uint32_t val;
 331
 332     if (s->pending == KBD_PENDING_AUX)
 333         val = ps2_read_data(s->mouse);
 334     else
 335         val = ps2_read_data(s->kbd);
 336
 337     trace_pckbd_kbd_read_data(val);
 338     return val;
 339 }
 340
 341 static void kbd_write_data(void *opaque, hwaddr addr,
 342                            uint64_t val, unsigned size)
 343 {
 344     KBDState *s = opaque;
 345
 346     trace_pckbd_kbd_write_data(val);
 347
 348     switch(s->write_cmd) {
 349     case 0:
 350         ps2_write_keyboard(s->kbd, val);
 351         break;
 352     case KBD_CCMD_WRITE_MODE:
 353         s->mode = val;
 354         ps2_keyboard_set_translation(s->kbd, (s->mode & KBD_MODE_KCC) != 0);
 355         /* ??? */
 356         kbd_update_irq(s);
 357         break;
 358     case KBD_CCMD_WRITE_OBUF:
 359         kbd_queue(s, val, 0);
 360         break;
 361     case KBD_CCMD_WRITE_AUX_OBUF:
 362         kbd_queue(s, val, 1);
 363         break;
 364     case KBD_CCMD_WRITE_OUTPORT:
 365         outport_write(s, val);
 366         break;
 367     case KBD_CCMD_WRITE_MOUSE:
 368         ps2_write_mouse(s->mouse, val);
 369         break;
 370     default:
 371         break;
 372     }
 373     s->write_cmd = 0;
 374 }
 375
 376 static void kbd_reset(void *opaque)
 377 {
 378     KBDState *s = opaque;
 379
 380     s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
 381     s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
 382     s->outport = KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES;
 383     s->outport_present = false;
 384 }
 385
 386 static uint8_t kbd_outport_default(KBDState *s)
 387 {
 388     return KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES
 389            | (s->status & KBD_STAT_OBF ? KBD_OUT_OBF : 0)
 390            | (s->status & KBD_STAT_MOUSE_OBF ? KBD_OUT_MOUSE_OBF : 0);
 391 }
 392
 393 static int kbd_outport_post_load(void *opaque, int version_id)
 394 {
 395     KBDState *s = opaque;
 396     s->outport_present = true;
 397     return 0;
 398 }
 399
 400 static bool kbd_outport_needed(void *opaque)
 401 {
 402     KBDState *s = opaque;
 403     return s->outport != kbd_outport_default(s);
 404 }
 405
 406 static const VMStateDescription vmstate_kbd_outport = {
 407     .name = "pckbd_outport",
 408     .version_id = 1,
 409     .minimum_version_id = 1,
 410     .post_load = kbd_outport_post_load,
 411     .needed = kbd_outport_needed,
 412     .fields = (VMStateField[]) {
 413         VMSTATE_UINT8(outport, KBDState),
 414         VMSTATE_END_OF_LIST()
 415     }
 416 };
 417
 418 static int kbd_post_load(void *opaque, int version_id)
 419 {
 420     KBDState *s = opaque;
 421     if (!s->outport_present) {
 422         s->outport = kbd_outport_default(s);
 423     }
 424     s->outport_present = false;
 425     return 0;
 426 }
 427
 428 static const VMStateDescription vmstate_kbd = {
 429     .name = "pckbd",
 430     .version_id = 3,
 431     .minimum_version_id = 3,
 432     .post_load = kbd_post_load,
 433     .fields = (VMStateField[]) {
 434         VMSTATE_UINT8(write_cmd, KBDState),
 435         VMSTATE_UINT8(status, KBDState),
 436         VMSTATE_UINT8(mode, KBDState),
 437         VMSTATE_UINT8(pending, KBDState),
 438         VMSTATE_END_OF_LIST()
 439     },
 440     .subsections = (const VMStateDescription*[]) {
 441         &vmstate_kbd_outport,
 442         NULL
 443     }
 444 };
 445
 446 /* Memory mapped interface */
 447 static uint64_t kbd_mm_readfn(void *opaque, hwaddr addr, unsigned size)
 448 {
 449     KBDState *s = opaque;
 450
 451     if (addr & s->mask)
 452         return kbd_read_status(s, 0, 1) & 0xff;
 453     else
 454         return kbd_read_data(s, 0, 1) & 0xff;
 455 }
 456
 457 static void kbd_mm_writefn(void *opaque, hwaddr addr,
 458                            uint64_t value, unsigned size)
 459 {
 460     KBDState *s = opaque;
 461
 462     if (addr & s->mask)
 463         kbd_write_command(s, 0, value & 0xff, 1);
 464     else
 465         kbd_write_data(s, 0, value & 0xff, 1);
 466 }
 467
 468
 469 static const MemoryRegionOps i8042_mmio_ops = {
 470     .read = kbd_mm_readfn,
 471     .write = kbd_mm_writefn,
 472     .valid.min_access_size = 1,
 473     .valid.max_access_size = 4,
 474     .endianness = DEVICE_NATIVE_ENDIAN,
 475 };
 476
 477 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
 478                    MemoryRegion *region, ram_addr_t size,
 479                    hwaddr mask)
 480 {
 481     KBDState *s = g_malloc0(sizeof(KBDState));
 482
 483     s->irq_kbd = kbd_irq;
 484     s->irq_mouse = mouse_irq;
 485     s->mask = mask;
 486
 487     vmstate_register(NULL, 0, &vmstate_kbd, s);
 488
 489     memory_region_init_io(region, NULL, &i8042_mmio_ops, s, "i8042", size);
 490
 491     s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
 492     s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
 493     qemu_register_reset(kbd_reset, s);
 494 }
 495
 496 struct ISAKBDState {
 497     ISADevice parent_obj;
 498
 499     KBDState kbd;
 500     MemoryRegion io[2];
 501 };
 502
 503 void i8042_isa_mouse_fake_event(ISAKBDState *isa)
 504 {
 505     KBDState *s = &isa->kbd;
 506
 507     ps2_mouse_fake_event(s->mouse);
 508 }
 509
 510 void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out)
 511 {
 512     qdev_connect_gpio_out_named(DEVICE(dev), I8042_A20_LINE, 0, a20_out);
 513 }
 514
 515 static const VMStateDescription vmstate_kbd_isa = {
 516     .name = "pckbd",
 517     .version_id = 3,
 518     .minimum_version_id = 3,
 519     .fields = (VMStateField[]) {
 520         VMSTATE_STRUCT(kbd, ISAKBDState, 0, vmstate_kbd, KBDState),
 521         VMSTATE_END_OF_LIST()
 522     }
 523 };
 524
 525 static const MemoryRegionOps i8042_data_ops = {
 526     .read = kbd_read_data,
 527     .write = kbd_write_data,
 528     .impl = {
 529         .min_access_size = 1,
 530         .max_access_size = 1,
 531     },
 532     .endianness = DEVICE_LITTLE_ENDIAN,
 533 };
 534
 535 static const MemoryRegionOps i8042_cmd_ops = {
 536     .read = kbd_read_status,
 537     .write = kbd_write_command,
 538     .impl = {
 539         .min_access_size = 1,
 540         .max_access_size = 1,
 541     },
 542     .endianness = DEVICE_LITTLE_ENDIAN,
 543 };
 544
 545 static void i8042_initfn(Object *obj)
 546 {
 547     ISAKBDState *isa_s = I8042(obj);
 548     KBDState *s = &isa_s->kbd;
 549
 550     memory_region_init_io(isa_s->io + 0, obj, &i8042_data_ops, s,
 551                           "i8042-data", 1);
 552     memory_region_init_io(isa_s->io + 1, obj, &i8042_cmd_ops, s,
 553                           "i8042-cmd", 1);
 554
 555     qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, I8042_A20_LINE, 1);
 556 }
 557
 558 static void i8042_realizefn(DeviceState *dev, Error **errp)
 559 {
 560     ISADevice *isadev = ISA_DEVICE(dev);
 561     ISAKBDState *isa_s = I8042(dev);
 562     KBDState *s = &isa_s->kbd;
 563
 564     isa_init_irq(isadev, &s->irq_kbd, 1);
 565     isa_init_irq(isadev, &s->irq_mouse, 12);
 566
 567     isa_register_ioport(isadev, isa_s->io + 0, 0x60);
 568     isa_register_ioport(isadev, isa_s->io + 1, 0x64);
 569
 570     s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
 571     s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
 572     qemu_register_reset(kbd_reset, s);
 573 }
 574
 575 static void i8042_build_aml(ISADevice *isadev, Aml *scope)
 576 {
 577     Aml *kbd;
 578     Aml *mou;
 579     Aml *crs;
 580
 581     crs = aml_resource_template();
 582     aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
 583     aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
 584     aml_append(crs, aml_irq_no_flags(1));
 585
 586     kbd = aml_device("KBD");
 587     aml_append(kbd, aml_name_decl("_HID", aml_eisaid("PNP0303")));
 588     aml_append(kbd, aml_name_decl("_STA", aml_int(0xf)));
 589     aml_append(kbd, aml_name_decl("_CRS", crs));
 590
 591     crs = aml_resource_template();
 592     aml_append(crs, aml_irq_no_flags(12));
 593
 594     mou = aml_device("MOU");
 595     aml_append(mou, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
 596     aml_append(mou, aml_name_decl("_STA", aml_int(0xf)));
 597     aml_append(mou, aml_name_decl("_CRS", crs));
 598
 599     aml_append(scope, kbd);
 600     aml_append(scope, mou);
 601 }
 602
 603 static void i8042_class_initfn(ObjectClass *klass, void *data)
 604 {
 605     DeviceClass *dc = DEVICE_CLASS(klass);
 606     ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
 607
 608     dc->realize = i8042_realizefn;
 609     dc->vmsd = &vmstate_kbd_isa;
 610     isa->build_aml = i8042_build_aml;
 611     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 612 }
 613
 614 static const TypeInfo i8042_info = {
 615     .name          = TYPE_I8042,
 616     .parent        = TYPE_ISA_DEVICE,
 617     .instance_size = sizeof(ISAKBDState),
 618     .instance_init = i8042_initfn,
 619     .class_init    = i8042_class_initfn,
 620 };
 621
 622 static void i8042_register_types(void)
 623 {
 624     type_register_static(&i8042_info);
 625 }
 626
 627 type_init(i8042_register_types)