hw/isa/piix4.c

   1 /*
   2  * QEMU PIIX4 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2018 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "qapi/error.h"
  28 #include "hw/irq.h"
  29 #include "hw/southbridge/piix.h"
  30 #include "hw/pci/pci.h"
  31 #include "hw/isa/isa.h"
  32 #include "hw/intc/i8259.h"
  33 #include "hw/dma/i8257.h"
  34 #include "hw/timer/i8254.h"
  35 #include "hw/rtc/mc146818rtc.h"
  36 #include "hw/ide/pci.h"
  37 #include "hw/acpi/piix4.h"
  38 #include "hw/usb/hcd-uhci.h"
  39 #include "migration/vmstate.h"
  40 #include "sysemu/reset.h"
  41 #include "sysemu/runstate.h"
  42 #include "qom/object.h"
  43
  44 struct PIIX4State {
  45     PCIDevice dev;
  46     qemu_irq cpu_intr;
  47     qemu_irq *isa;
  48
  49     RTCState rtc;
  50     PCIIDEState ide;
  51     UHCIState uhci;
  52     /* Reset Control Register */
  53     MemoryRegion rcr_mem;
  54     uint8_t rcr;
  55 };
  56
  57 OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE)
  58
  59 static void piix4_set_irq(void *opaque, int irq_num, int level)
  60 {
  61     int i, pic_irq, pic_level;
  62     PIIX4State *s = opaque;
  63     PCIBus *bus = pci_get_bus(&s->dev);
  64
  65     /* now we change the pic irq level according to the piix irq mappings */
  66     /* XXX: optimize */
  67     pic_irq = s->dev.config[PIIX_PIRQCA + irq_num];
  68     if (pic_irq < ISA_NUM_IRQS) {
  69         /* The pic level is the logical OR of all the PCI irqs mapped to it. */
  70         pic_level = 0;
  71         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
  72             if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) {
  73                 pic_level |= pci_bus_get_irq_level(bus, i);
  74             }
  75         }
  76         qemu_set_irq(s->isa[pic_irq], pic_level);
  77     }
  78 }
  79
  80 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
  81 {
  82     int slot;
  83
  84     slot = PCI_SLOT(pci_dev->devfn);
  85
  86     switch (slot) {
  87     /* PIIX4 USB */
  88     case 10:
  89         return 3;
  90     /* AMD 79C973 Ethernet */
  91     case 11:
  92         return 1;
  93     /* Crystal 4281 Sound */
  94     case 12:
  95         return 2;
  96     /* PCI slot 1 to 4 */
  97     case 18 ... 21:
  98         return ((slot - 18) + irq_num) & 0x03;
  99     /* Unknown device, don't do any translation */
 100     default:
 101         return irq_num;
 102     }
 103 }
 104
 105 static void piix4_isa_reset(DeviceState *dev)
 106 {
 107     PIIX4State *d = PIIX4_PCI_DEVICE(dev);
 108     uint8_t *pci_conf = d->dev.config;
 109
 110     pci_conf[0x04] = 0x07; // master, memory and I/O
 111     pci_conf[0x05] = 0x00;
 112     pci_conf[0x06] = 0x00;
 113     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 114     pci_conf[0x4c] = 0x4d;
 115     pci_conf[0x4e] = 0x03;
 116     pci_conf[0x4f] = 0x00;
 117     pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
 118     pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
 119     pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
 120     pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
 121     pci_conf[0x69] = 0x02;
 122     pci_conf[0x70] = 0x80;
 123     pci_conf[0x76] = 0x0c;
 124     pci_conf[0x77] = 0x0c;
 125     pci_conf[0x78] = 0x02;
 126     pci_conf[0x79] = 0x00;
 127     pci_conf[0x80] = 0x00;
 128     pci_conf[0x82] = 0x00;
 129     pci_conf[0xa0] = 0x08;
 130     pci_conf[0xa2] = 0x00;
 131     pci_conf[0xa3] = 0x00;
 132     pci_conf[0xa4] = 0x00;
 133     pci_conf[0xa5] = 0x00;
 134     pci_conf[0xa6] = 0x00;
 135     pci_conf[0xa7] = 0x00;
 136     pci_conf[0xa8] = 0x0f;
 137     pci_conf[0xaa] = 0x00;
 138     pci_conf[0xab] = 0x00;
 139     pci_conf[0xac] = 0x00;
 140     pci_conf[0xae] = 0x00;
 141 }
 142
 143 static int piix4_ide_post_load(void *opaque, int version_id)
 144 {
 145     PIIX4State *s = opaque;
 146
 147     if (version_id == 2) {
 148         s->rcr = 0;
 149     }
 150
 151     return 0;
 152 }
 153
 154 static const VMStateDescription vmstate_piix4 = {
 155     .name = "PIIX4",
 156     .version_id = 3,
 157     .minimum_version_id = 2,
 158     .post_load = piix4_ide_post_load,
 159     .fields = (VMStateField[]) {
 160         VMSTATE_PCI_DEVICE(dev, PIIX4State),
 161         VMSTATE_UINT8_V(rcr, PIIX4State, 3),
 162         VMSTATE_END_OF_LIST()
 163     }
 164 };
 165
 166 static void piix4_request_i8259_irq(void *opaque, int irq, int level)
 167 {
 168     PIIX4State *s = opaque;
 169     qemu_set_irq(s->cpu_intr, level);
 170 }
 171
 172 static void piix4_set_i8259_irq(void *opaque, int irq, int level)
 173 {
 174     PIIX4State *s = opaque;
 175     qemu_set_irq(s->isa[irq], level);
 176 }
 177
 178 static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
 179                             unsigned int len)
 180 {
 181     PIIX4State *s = opaque;
 182
 183     if (val & 4) {
 184         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 185         return;
 186     }
 187
 188     s->rcr = val & 2; /* keep System Reset type only */
 189 }
 190
 191 static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
 192 {
 193     PIIX4State *s = opaque;
 194
 195     return s->rcr;
 196 }
 197
 198 static const MemoryRegionOps piix4_rcr_ops = {
 199     .read = piix4_rcr_read,
 200     .write = piix4_rcr_write,
 201     .endianness = DEVICE_LITTLE_ENDIAN,
 202     .impl = {
 203         .min_access_size = 1,
 204         .max_access_size = 1,
 205     },
 206 };
 207
 208 static void piix4_realize(PCIDevice *dev, Error **errp)
 209 {
 210     PIIX4State *s = PIIX4_PCI_DEVICE(dev);
 211     PCIBus *pci_bus = pci_get_bus(dev);
 212     ISABus *isa_bus;
 213     qemu_irq *i8259_out_irq;
 214
 215     isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
 216                           pci_address_space_io(dev), errp);
 217     if (!isa_bus) {
 218         return;
 219     }
 220
 221     qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
 222                             "isa", ISA_NUM_IRQS);
 223     qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
 224                              "intr", 1);
 225
 226     memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
 227                           "reset-control", 1);
 228     memory_region_add_subregion_overlap(pci_address_space_io(dev),
 229                                         PIIX_RCR_IOPORT, &s->rcr_mem, 1);
 230
 231     /* initialize i8259 pic */
 232     i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
 233     s->isa = i8259_init(isa_bus, *i8259_out_irq);
 234
 235     /* initialize ISA irqs */
 236     isa_bus_irqs(isa_bus, s->isa);
 237
 238     /* initialize pit */
 239     i8254_pit_init(isa_bus, 0x40, 0, NULL);
 240
 241     /* DMA */
 242     i8257_dma_init(isa_bus, 0);
 243
 244     /* RTC */
 245     qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
 246     if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
 247         return;
 248     }
 249     s->rtc.irq = isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq);
 250
 251     /* IDE */
 252     qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1);
 253     if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) {
 254         return;
 255     }
 256     pci_ide_create_devs(PCI_DEVICE(&s->ide));
 257
 258     /* USB */
 259     qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2);
 260     if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) {
 261         return;
 262     }
 263
 264     pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
 265 }
 266
 267 static void piix4_init(Object *obj)
 268 {
 269     PIIX4State *s = PIIX4_PCI_DEVICE(obj);
 270
 271     object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC);
 272     object_initialize_child(obj, "ide", &s->ide, "piix4-ide");
 273     object_initialize_child(obj, "uhci", &s->uhci, "piix4-usb-uhci");
 274 }
 275
 276 static void piix4_class_init(ObjectClass *klass, void *data)
 277 {
 278     DeviceClass *dc = DEVICE_CLASS(klass);
 279     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 280
 281     k->realize = piix4_realize;
 282     k->vendor_id = PCI_VENDOR_ID_INTEL;
 283     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
 284     k->class_id = PCI_CLASS_BRIDGE_ISA;
 285     dc->reset = piix4_isa_reset;
 286     dc->desc = "ISA bridge";
 287     dc->vmsd = &vmstate_piix4;
 288     /*
 289      * Reason: part of PIIX4 southbridge, needs to be wired up,
 290      * e.g. by mips_malta_init()
 291      */
 292     dc->user_creatable = false;
 293     dc->hotpluggable = false;
 294 }
 295
 296 static const TypeInfo piix4_info = {
 297     .name          = TYPE_PIIX4_PCI_DEVICE,
 298     .parent        = TYPE_PCI_DEVICE,
 299     .instance_size = sizeof(PIIX4State),
 300     .instance_init = piix4_init,
 301     .class_init    = piix4_class_init,
 302     .interfaces = (InterfaceInfo[]) {
 303         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 304         { },
 305     },
 306 };
 307
 308 static void piix4_register_types(void)
 309 {
 310     type_register_static(&piix4_info);
 311 }
 312
 313 type_init(piix4_register_types)
 314
 315 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
 316 {
 317     PCIDevice *pci;
 318     DeviceState *dev;
 319     int devfn = PCI_DEVFN(10, 0);
 320
 321     pci = pci_create_simple_multifunction(pci_bus, devfn,  true,
 322                                           TYPE_PIIX4_PCI_DEVICE);
 323     dev = DEVICE(pci);
 324
 325     if (isa_bus) {
 326         *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
 327     }
 328
 329     if (smbus) {
 330         pci = pci_new(devfn + 3, TYPE_PIIX4_PM);
 331         qdev_prop_set_uint32(DEVICE(pci), "smb_io_base", 0x1100);
 332         qdev_prop_set_bit(DEVICE(pci), "smm-enabled", 0);
 333         pci_realize_and_unref(pci, pci_bus, &error_fatal);
 334         qdev_connect_gpio_out(DEVICE(pci), 0,
 335                               qdev_get_gpio_in_named(dev, "isa", 9));
 336         *smbus = I2C_BUS(qdev_get_child_bus(DEVICE(pci), "i2c"));
 337     }
 338
 339     return dev;
 340 }