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i386/xen: handle VCPUOP_register_vcpu_info
[qemu/kevin.git] / hw / ppc / pegasos2.c
blob7cc375df05d13cad346b231a1f9b58ad1be6a86f
1 /*
2 * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator
3 *
4 * Copyright (c) 2018-2021 BALATON Zoltan
5 *
6 * This work is licensed under the GNU GPL license version 2 or later.
7 *
8 */
9
10 #include "qemu/osdep.h"
11 #include "qemu/units.h"
12 #include "qapi/error.h"
13 #include "hw/ppc/ppc.h"
14 #include "hw/sysbus.h"
15 #include "hw/pci/pci_host.h"
16 #include "hw/irq.h"
17 #include "hw/pci-host/mv64361.h"
18 #include "hw/isa/vt82c686.h"
19 #include "hw/ide/pci.h"
20 #include "hw/i2c/smbus_eeprom.h"
21 #include "hw/qdev-properties.h"
22 #include "sysemu/reset.h"
23 #include "sysemu/runstate.h"
24 #include "sysemu/qtest.h"
25 #include "hw/boards.h"
26 #include "hw/loader.h"
27 #include "hw/fw-path-provider.h"
28 #include "elf.h"
29 #include "qemu/log.h"
30 #include "qemu/error-report.h"
31 #include "sysemu/kvm.h"
32 #include "kvm_ppc.h"
33 #include "exec/address-spaces.h"
34 #include "qom/qom-qobject.h"
35 #include "qapi/qmp/qdict.h"
36 #include "trace.h"
37 #include "qemu/datadir.h"
38 #include "sysemu/device_tree.h"
39 #include "hw/ppc/vof.h"
40
41 #include <libfdt.h>
42
43 #define PROM_FILENAME "vof.bin"
44 #define PROM_ADDR 0xfff00000
45 #define PROM_SIZE 0x80000
46
47 #define KVMPPC_HCALL_BASE 0xf000
48 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
49 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5)
50
51 #define H_SUCCESS 0
52 #define H_PRIVILEGE -3 /* Caller not privileged */
53 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
54
55 #define BUS_FREQ_HZ 133333333
56
57 #define PCI0_CFG_ADDR 0xcf8
58 #define PCI0_MEM_BASE 0xc0000000
59 #define PCI0_MEM_SIZE 0x20000000
60 #define PCI0_IO_BASE 0xf8000000
61 #define PCI0_IO_SIZE 0x10000
62
63 #define PCI1_CFG_ADDR 0xc78
64 #define PCI1_MEM_BASE 0x80000000
65 #define PCI1_MEM_SIZE 0x40000000
66 #define PCI1_IO_BASE 0xfe000000
67 #define PCI1_IO_SIZE 0x10000
68
69 #define TYPE_PEGASOS2_MACHINE MACHINE_TYPE_NAME("pegasos2")
70 OBJECT_DECLARE_TYPE(Pegasos2MachineState, MachineClass, PEGASOS2_MACHINE)
71
72 struct Pegasos2MachineState {
73 MachineState parent_obj;
74 PowerPCCPU *cpu;
75 DeviceState *mv;
76 Vof *vof;
77 void *fdt_blob;
78 uint64_t kernel_addr;
79 uint64_t kernel_entry;
80 uint64_t kernel_size;
81 };
82
83 static void *build_fdt(MachineState *machine, int *fdt_size);
84
85 static void pegasos2_cpu_reset(void *opaque)
86 {
87 PowerPCCPU *cpu = opaque;
88 Pegasos2MachineState *pm = PEGASOS2_MACHINE(current_machine);
89
90 cpu_reset(CPU(cpu));
91 cpu->env.spr[SPR_HID1] = 7ULL << 28;
92 if (pm->vof) {
93 cpu->env.gpr[1] = 2 * VOF_STACK_SIZE - 0x20;
94 cpu->env.nip = 0x100;
95 }
96 }
97
98 static void pegasos2_init(MachineState *machine)
99 {
100 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
101 CPUPPCState *env;
102 MemoryRegion *rom = g_new(MemoryRegion, 1);
103 PCIBus *pci_bus;
104 Object *via;
105 PCIDevice *dev;
106 I2CBus *i2c_bus;
107 const char *fwname = machine->firmware ?: PROM_FILENAME;
108 char *filename;
109 int sz;
110 uint8_t *spd_data;
111
112 /* init CPU */
113 pm->cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
114 env = &pm->cpu->env;
115 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
116 error_report("Incompatible CPU, only 6xx bus supported");
117 exit(1);
118 }
119
120 /* Set time-base frequency */
121 cpu_ppc_tb_init(env, BUS_FREQ_HZ / 4);
122 qemu_register_reset(pegasos2_cpu_reset, pm->cpu);
123
124 /* RAM */
125 if (machine->ram_size > 2 * GiB) {
126 error_report("RAM size more than 2 GiB is not supported");
127 exit(1);
128 }
129 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
130
131 /* allocate and load firmware */
132 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, fwname);
133 if (!filename) {
134 error_report("Could not find firmware '%s'", fwname);
135 exit(1);
136 }
137 if (!machine->firmware && !pm->vof) {
138 pm->vof = g_malloc0(sizeof(*pm->vof));
139 }
140 memory_region_init_rom(rom, NULL, "pegasos2.rom", PROM_SIZE, &error_fatal);
141 memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom);
142 sz = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 1,
143 PPC_ELF_MACHINE, 0, 0);
144 if (sz <= 0) {
145 sz = load_image_targphys(filename, pm->vof ? 0 : PROM_ADDR, PROM_SIZE);
146 }
147 if (sz <= 0 || sz > PROM_SIZE) {
148 error_report("Could not load firmware '%s'", filename);
149 exit(1);
150 }
151 g_free(filename);
152 if (pm->vof) {
153 pm->vof->fw_size = sz;
154 }
155
156 /* Marvell Discovery II system controller */
157 pm->mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1,
158 qdev_get_gpio_in(DEVICE(pm->cpu), PPC6xx_INPUT_INT)));
159 pci_bus = mv64361_get_pci_bus(pm->mv, 1);
160
161 /* VIA VT8231 South Bridge (multifunction PCI device) */
162 via = OBJECT(pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0),
163 true, TYPE_VT8231_ISA));
164 object_property_add_alias(OBJECT(machine), "rtc-time",
165 object_resolve_path_component(via, "rtc"),
166 "date");
167 qdev_connect_gpio_out(DEVICE(via), 0,
168 qdev_get_gpio_in_named(pm->mv, "gpp", 31));
169
170 dev = PCI_DEVICE(object_resolve_path_component(via, "ide"));
171 pci_ide_create_devs(dev);
172
173 dev = PCI_DEVICE(object_resolve_path_component(via, "pm"));
174 i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c"));
175 spd_data = spd_data_generate(DDR, machine->ram_size);
176 smbus_eeprom_init_one(i2c_bus, 0x57, spd_data);
177
178 /* other PC hardware */
179 pci_vga_init(pci_bus);
180
181 if (machine->kernel_filename) {
182 sz = load_elf(machine->kernel_filename, NULL, NULL, NULL,
183 &pm->kernel_entry, &pm->kernel_addr, NULL, NULL, 1,
184 PPC_ELF_MACHINE, 0, 0);
185 if (sz <= 0) {
186 error_report("Could not load kernel '%s'",
187 machine->kernel_filename);
188 exit(1);
189 }
190 pm->kernel_size = sz;
191 if (!pm->vof) {
192 warn_report("Option -kernel may be ineffective with -bios.");
193 }
194 } else if (pm->vof && !qtest_enabled()) {
195 warn_report("Using Virtual OpenFirmware but no -kernel option.");
196 }
197
198 if (!pm->vof && machine->kernel_cmdline && machine->kernel_cmdline[0]) {
199 warn_report("Option -append may be ineffective with -bios.");
200 }
201 }
202
203 static uint32_t pegasos2_mv_reg_read(Pegasos2MachineState *pm,
204 uint32_t addr, uint32_t len)
205 {
206 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0);
207 uint64_t val = 0xffffffffULL;
208 memory_region_dispatch_read(r, addr, &val, size_memop(len) | MO_LE,
209 MEMTXATTRS_UNSPECIFIED);
210 return val;
211 }
212
213 static void pegasos2_mv_reg_write(Pegasos2MachineState *pm, uint32_t addr,
214 uint32_t len, uint32_t val)
215 {
216 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0);
217 memory_region_dispatch_write(r, addr, val, size_memop(len) | MO_LE,
218 MEMTXATTRS_UNSPECIFIED);
219 }
220
221 static uint32_t pegasos2_pci_config_read(Pegasos2MachineState *pm, int bus,
222 uint32_t addr, uint32_t len)
223 {
224 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR;
225 uint64_t val = 0xffffffffULL;
226
227 if (len <= 4) {
228 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31));
229 val = pegasos2_mv_reg_read(pm, pcicfg + 4, len);
230 }
231 return val;
232 }
233
234 static void pegasos2_pci_config_write(Pegasos2MachineState *pm, int bus,
235 uint32_t addr, uint32_t len, uint32_t val)
236 {
237 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR;
238
239 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31));
240 pegasos2_mv_reg_write(pm, pcicfg + 4, len, val);
241 }
242
243 static void pegasos2_machine_reset(MachineState *machine, ShutdownCause reason)
244 {
245 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
246 void *fdt;
247 uint64_t d[2];
248 int sz;
249
250 qemu_devices_reset(reason);
251 if (!pm->vof) {
252 return; /* Firmware should set up machine so nothing to do */
253 }
254
255 /* Otherwise, set up devices that board firmware would normally do */
256 pegasos2_mv_reg_write(pm, 0, 4, 0x28020ff);
257 pegasos2_mv_reg_write(pm, 0x278, 4, 0xa31fc);
258 pegasos2_mv_reg_write(pm, 0xf300, 4, 0x11ff0400);
259 pegasos2_mv_reg_write(pm, 0xf10c, 4, 0x80000000);
260 pegasos2_mv_reg_write(pm, 0x1c, 4, 0x8000000);
261 pegasos2_pci_config_write(pm, 0, PCI_COMMAND, 2, PCI_COMMAND_IO |
262 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
263 pegasos2_pci_config_write(pm, 1, PCI_COMMAND, 2, PCI_COMMAND_IO |
264 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
265
266 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
267 PCI_INTERRUPT_LINE, 2, 0x9);
268 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
269 0x50, 1, 0x2);
270
271 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
272 PCI_INTERRUPT_LINE, 2, 0x109);
273 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
274 PCI_CLASS_PROG, 1, 0xf);
275 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
276 0x40, 1, 0xb);
277 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
278 0x50, 4, 0x17171717);
279 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
280 PCI_COMMAND, 2, 0x87);
281
282 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) |
283 PCI_INTERRUPT_LINE, 2, 0x409);
284
285 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) |
286 PCI_INTERRUPT_LINE, 2, 0x409);
287
288 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
289 PCI_INTERRUPT_LINE, 2, 0x9);
290 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
291 0x48, 4, 0xf00);
292 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
293 0x40, 4, 0x558020);
294 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
295 0x90, 4, 0xd00);
296
297 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 5) << 8) |
298 PCI_INTERRUPT_LINE, 2, 0x309);
299
300 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 6) << 8) |
301 PCI_INTERRUPT_LINE, 2, 0x309);
302
303 /* Device tree and VOF set up */
304 vof_init(pm->vof, machine->ram_size, &error_fatal);
305 if (vof_claim(pm->vof, 0, VOF_STACK_SIZE, VOF_STACK_SIZE) == -1) {
306 error_report("Memory allocation for stack failed");
307 exit(1);
308 }
309 if (pm->kernel_size &&
310 vof_claim(pm->vof, pm->kernel_addr, pm->kernel_size, 0) == -1) {
311 error_report("Memory for kernel is in use");
312 exit(1);
313 }
314 fdt = build_fdt(machine, &sz);
315 /* FIXME: VOF assumes entry is same as load address */
316 d[0] = cpu_to_be64(pm->kernel_entry);
317 d[1] = cpu_to_be64(pm->kernel_size - (pm->kernel_entry - pm->kernel_addr));
318 qemu_fdt_setprop(fdt, "/chosen", "qemu,boot-kernel", d, sizeof(d));
319
320 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
321 g_free(pm->fdt_blob);
322 pm->fdt_blob = fdt;
323
324 vof_build_dt(fdt, pm->vof);
325 vof_client_open_store(fdt, pm->vof, "/chosen", "stdout", "/failsafe");
326
327 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
328 machine->fdt = fdt;
329
330 pm->cpu->vhyp = PPC_VIRTUAL_HYPERVISOR(machine);
331 }
332
333 enum pegasos2_rtas_tokens {
334 RTAS_RESTART_RTAS = 0,
335 RTAS_NVRAM_FETCH = 1,
336 RTAS_NVRAM_STORE = 2,
337 RTAS_GET_TIME_OF_DAY = 3,
338 RTAS_SET_TIME_OF_DAY = 4,
339 RTAS_EVENT_SCAN = 6,
340 RTAS_CHECK_EXCEPTION = 7,
341 RTAS_READ_PCI_CONFIG = 8,
342 RTAS_WRITE_PCI_CONFIG = 9,
343 RTAS_DISPLAY_CHARACTER = 10,
344 RTAS_SET_INDICATOR = 11,
345 RTAS_POWER_OFF = 17,
346 RTAS_SUSPEND = 18,
347 RTAS_HIBERNATE = 19,
348 RTAS_SYSTEM_REBOOT = 20,
349 };
350
351 static target_ulong pegasos2_rtas(PowerPCCPU *cpu, Pegasos2MachineState *pm,
352 target_ulong args_real)
353 {
354 AddressSpace *as = CPU(cpu)->as;
355 uint32_t token = ldl_be_phys(as, args_real);
356 uint32_t nargs = ldl_be_phys(as, args_real + 4);
357 uint32_t nrets = ldl_be_phys(as, args_real + 8);
358 uint32_t args = args_real + 12;
359 uint32_t rets = args_real + 12 + nargs * 4;
360
361 if (nrets < 1) {
362 qemu_log_mask(LOG_GUEST_ERROR, "Too few return values in RTAS call\n");
363 return H_PARAMETER;
364 }
365 switch (token) {
366 case RTAS_GET_TIME_OF_DAY:
367 {
368 QObject *qo = object_property_get_qobject(qdev_get_machine(),
369 "rtc-time", &error_fatal);
370 QDict *qd = qobject_to(QDict, qo);
371
372 if (nargs != 0 || nrets != 8 || !qd) {
373 stl_be_phys(as, rets, -1);
374 qobject_unref(qo);
375 return H_PARAMETER;
376 }
377
378 stl_be_phys(as, rets, 0);
379 stl_be_phys(as, rets + 4, qdict_get_int(qd, "tm_year") + 1900);
380 stl_be_phys(as, rets + 8, qdict_get_int(qd, "tm_mon") + 1);
381 stl_be_phys(as, rets + 12, qdict_get_int(qd, "tm_mday"));
382 stl_be_phys(as, rets + 16, qdict_get_int(qd, "tm_hour"));
383 stl_be_phys(as, rets + 20, qdict_get_int(qd, "tm_min"));
384 stl_be_phys(as, rets + 24, qdict_get_int(qd, "tm_sec"));
385 stl_be_phys(as, rets + 28, 0);
386 qobject_unref(qo);
387 return H_SUCCESS;
388 }
389 case RTAS_READ_PCI_CONFIG:
390 {
391 uint32_t addr, len, val;
392
393 if (nargs != 2 || nrets != 2) {
394 stl_be_phys(as, rets, -1);
395 return H_PARAMETER;
396 }
397 addr = ldl_be_phys(as, args);
398 len = ldl_be_phys(as, args + 4);
399 val = pegasos2_pci_config_read(pm, !(addr >> 24),
400 addr & 0x0fffffff, len);
401 stl_be_phys(as, rets, 0);
402 stl_be_phys(as, rets + 4, val);
403 return H_SUCCESS;
404 }
405 case RTAS_WRITE_PCI_CONFIG:
406 {
407 uint32_t addr, len, val;
408
409 if (nargs != 3 || nrets != 1) {
410 stl_be_phys(as, rets, -1);
411 return H_PARAMETER;
412 }
413 addr = ldl_be_phys(as, args);
414 len = ldl_be_phys(as, args + 4);
415 val = ldl_be_phys(as, args + 8);
416 pegasos2_pci_config_write(pm, !(addr >> 24),
417 addr & 0x0fffffff, len, val);
418 stl_be_phys(as, rets, 0);
419 return H_SUCCESS;
420 }
421 case RTAS_DISPLAY_CHARACTER:
422 if (nargs != 1 || nrets != 1) {
423 stl_be_phys(as, rets, -1);
424 return H_PARAMETER;
425 }
426 qemu_log_mask(LOG_UNIMP, "%c", ldl_be_phys(as, args));
427 stl_be_phys(as, rets, 0);
428 return H_SUCCESS;
429 case RTAS_POWER_OFF:
430 {
431 if (nargs != 2 || nrets != 1) {
432 stl_be_phys(as, rets, -1);
433 return H_PARAMETER;
434 }
435 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
436 stl_be_phys(as, rets, 0);
437 return H_SUCCESS;
438 }
439 default:
440 qemu_log_mask(LOG_UNIMP, "Unknown RTAS token %u (args=%u, rets=%u)\n",
441 token, nargs, nrets);
442 stl_be_phys(as, rets, 0);
443 return H_SUCCESS;
444 }
445 }
446
447 static bool pegasos2_cpu_in_nested(PowerPCCPU *cpu)
448 {
449 return false;
450 }
451
452 static void pegasos2_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
453 {
454 Pegasos2MachineState *pm = PEGASOS2_MACHINE(vhyp);
455 CPUPPCState *env = &cpu->env;
456
457 /* The TCG path should also be holding the BQL at this point */
458 g_assert(qemu_mutex_iothread_locked());
459
460 if (FIELD_EX64(env->msr, MSR, PR)) {
461 qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=1\n");
462 env->gpr[3] = H_PRIVILEGE;
463 } else if (env->gpr[3] == KVMPPC_H_RTAS) {
464 env->gpr[3] = pegasos2_rtas(cpu, pm, env->gpr[4]);
465 } else if (env->gpr[3] == KVMPPC_H_VOF_CLIENT) {
466 int ret = vof_client_call(MACHINE(pm), pm->vof, pm->fdt_blob,
467 env->gpr[4]);
468 env->gpr[3] = (ret ? H_PARAMETER : H_SUCCESS);
469 } else {
470 qemu_log_mask(LOG_GUEST_ERROR, "Unsupported hypercall " TARGET_FMT_lx
471 "\n", env->gpr[3]);
472 env->gpr[3] = -1;
473 }
474 }
475
476 static void vhyp_nop(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
477 {
478 }
479
480 static target_ulong vhyp_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
481 {
482 return POWERPC_CPU(current_cpu)->env.spr[SPR_SDR1];
483 }
484
485 static bool pegasos2_setprop(MachineState *ms, const char *path,
486 const char *propname, void *val, int vallen)
487 {
488 return true;
489 }
490
491 static void pegasos2_machine_class_init(ObjectClass *oc, void *data)
492 {
493 MachineClass *mc = MACHINE_CLASS(oc);
494 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
495 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc);
496
497 mc->desc = "Genesi/bPlan Pegasos II";
498 mc->init = pegasos2_init;
499 mc->reset = pegasos2_machine_reset;
500 mc->block_default_type = IF_IDE;
501 mc->default_boot_order = "cd";
502 mc->default_display = "std";
503 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9");
504 mc->default_ram_id = "pegasos2.ram";
505 mc->default_ram_size = 512 * MiB;
506
507 vhc->cpu_in_nested = pegasos2_cpu_in_nested;
508 vhc->hypercall = pegasos2_hypercall;
509 vhc->cpu_exec_enter = vhyp_nop;
510 vhc->cpu_exec_exit = vhyp_nop;
511 vhc->encode_hpt_for_kvm_pr = vhyp_encode_hpt_for_kvm_pr;
512
513 vmc->setprop = pegasos2_setprop;
514 }
515
516 static const TypeInfo pegasos2_machine_info = {
517 .name = TYPE_PEGASOS2_MACHINE,
518 .parent = TYPE_MACHINE,
519 .class_init = pegasos2_machine_class_init,
520 .instance_size = sizeof(Pegasos2MachineState),
521 .interfaces = (InterfaceInfo[]) {
522 { TYPE_PPC_VIRTUAL_HYPERVISOR },
523 { TYPE_VOF_MACHINE_IF },
524 { }
525 },
526 };
527
528 static void pegasos2_machine_register_types(void)
529 {
530 type_register_static(&pegasos2_machine_info);
531 }
532
533 type_init(pegasos2_machine_register_types)
534
535 /* FDT creation for passing to firmware */
536
537 typedef struct {
538 void *fdt;
539 const char *path;
540 } FDTInfo;
541
542 /* We do everything in reverse order so it comes out right in the tree */
543
544 static void dt_ide(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
545 {
546 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "spi");
547 }
548
549 static void dt_usb(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
550 {
551 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 0);
552 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 1);
553 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "usb");
554 }
555
556 static void dt_isa(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
557 {
558 GString *name = g_string_sized_new(64);
559 uint32_t cells[3];
560
561 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 1);
562 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 2);
563 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "isa");
564 qemu_fdt_setprop_string(fi->fdt, fi->path, "name", "isa");
565
566 /* additional devices */
567 g_string_printf(name, "%s/lpt@i3bc", fi->path);
568 qemu_fdt_add_subnode(fi->fdt, name->str);
569 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
570 cells[0] = cpu_to_be32(7);
571 cells[1] = 0;
572 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
573 cells, 2 * sizeof(cells[0]));
574 cells[0] = cpu_to_be32(1);
575 cells[1] = cpu_to_be32(0x3bc);
576 cells[2] = cpu_to_be32(8);
577 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
578 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "lpt");
579 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "lpt");
580
581 g_string_printf(name, "%s/fdc@i3f0", fi->path);
582 qemu_fdt_add_subnode(fi->fdt, name->str);
583 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
584 cells[0] = cpu_to_be32(6);
585 cells[1] = 0;
586 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
587 cells, 2 * sizeof(cells[0]));
588 cells[0] = cpu_to_be32(1);
589 cells[1] = cpu_to_be32(0x3f0);
590 cells[2] = cpu_to_be32(8);
591 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
592 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "fdc");
593 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "fdc");
594
595 g_string_printf(name, "%s/timer@i40", fi->path);
596 qemu_fdt_add_subnode(fi->fdt, name->str);
597 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
598 cells[0] = cpu_to_be32(1);
599 cells[1] = cpu_to_be32(0x40);
600 cells[2] = cpu_to_be32(8);
601 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
602 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "timer");
603 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "timer");
604
605 g_string_printf(name, "%s/rtc@i70", fi->path);
606 qemu_fdt_add_subnode(fi->fdt, name->str);
607 qemu_fdt_setprop_string(fi->fdt, name->str, "compatible", "ds1385-rtc");
608 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
609 cells[0] = cpu_to_be32(8);
610 cells[1] = 0;
611 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
612 cells, 2 * sizeof(cells[0]));
613 cells[0] = cpu_to_be32(1);
614 cells[1] = cpu_to_be32(0x70);
615 cells[2] = cpu_to_be32(2);
616 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
617 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "rtc");
618 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "rtc");
619
620 g_string_printf(name, "%s/keyboard@i60", fi->path);
621 qemu_fdt_add_subnode(fi->fdt, name->str);
622 cells[0] = cpu_to_be32(1);
623 cells[1] = 0;
624 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
625 cells, 2 * sizeof(cells[0]));
626 cells[0] = cpu_to_be32(1);
627 cells[1] = cpu_to_be32(0x60);
628 cells[2] = cpu_to_be32(5);
629 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
630 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "keyboard");
631 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "keyboard");
632
633 g_string_printf(name, "%s/8042@i60", fi->path);
634 qemu_fdt_add_subnode(fi->fdt, name->str);
635 qemu_fdt_setprop_cell(fi->fdt, name->str, "#interrupt-cells", 2);
636 qemu_fdt_setprop_cell(fi->fdt, name->str, "#size-cells", 0);
637 qemu_fdt_setprop_cell(fi->fdt, name->str, "#address-cells", 1);
638 qemu_fdt_setprop_string(fi->fdt, name->str, "interrupt-controller", "");
639 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
640 cells[0] = cpu_to_be32(1);
641 cells[1] = cpu_to_be32(0x60);
642 cells[2] = cpu_to_be32(5);
643 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
644 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "");
645 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "8042");
646
647 g_string_printf(name, "%s/serial@i2f8", fi->path);
648 qemu_fdt_add_subnode(fi->fdt, name->str);
649 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
650 cells[0] = cpu_to_be32(3);
651 cells[1] = 0;
652 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
653 cells, 2 * sizeof(cells[0]));
654 cells[0] = cpu_to_be32(1);
655 cells[1] = cpu_to_be32(0x2f8);
656 cells[2] = cpu_to_be32(8);
657 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
658 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "serial");
659 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "serial");
660
661 g_string_free(name, TRUE);
662 }
663
664 static struct {
665 const char *id;
666 const char *name;
667 void (*dtf)(PCIBus *bus, PCIDevice *d, FDTInfo *fi);
668 } device_map[] = {
669 { "pci11ab,6460", "host", NULL },
670 { "pci1106,8231", "isa", dt_isa },
671 { "pci1106,571", "ide", dt_ide },
672 { "pci1106,3044", "firewire", NULL },
673 { "pci1106,3038", "usb", dt_usb },
674 { "pci1106,8235", "other", NULL },
675 { "pci1106,3058", "sound", NULL },
676 { NULL, NULL }
677 };
678
679 static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque)
680 {
681 FDTInfo *fi = opaque;
682 GString *node = g_string_new(NULL);
683 uint32_t cells[(PCI_NUM_REGIONS + 1) * 5];
684 int i, j;
685 const char *name = NULL;
686 g_autofree const gchar *pn = g_strdup_printf("pci%x,%x",
687 pci_get_word(&d->config[PCI_VENDOR_ID]),
688 pci_get_word(&d->config[PCI_DEVICE_ID]));
689
690 for (i = 0; device_map[i].id; i++) {
691 if (!strcmp(pn, device_map[i].id)) {
692 name = device_map[i].name;
693 break;
694 }
695 }
696 g_string_printf(node, "%s/%s@%x", fi->path, (name ?: pn),
697 PCI_SLOT(d->devfn));
698 if (PCI_FUNC(d->devfn)) {
699 g_string_append_printf(node, ",%x", PCI_FUNC(d->devfn));
700 }
701
702 qemu_fdt_add_subnode(fi->fdt, node->str);
703 if (device_map[i].dtf) {
704 FDTInfo cfi = { fi->fdt, node->str };
705 device_map[i].dtf(bus, d, &cfi);
706 }
707 cells[0] = cpu_to_be32(d->devfn << 8);
708 cells[1] = 0;
709 cells[2] = 0;
710 cells[3] = 0;
711 cells[4] = 0;
712 j = 5;
713 for (i = 0; i < PCI_NUM_REGIONS; i++) {
714 if (!d->io_regions[i].size) {
715 continue;
716 }
717 cells[j] = cpu_to_be32(d->devfn << 8 | (PCI_BASE_ADDRESS_0 + i * 4));
718 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
719 cells[j] |= cpu_to_be32(1 << 24);
720 } else {
721 cells[j] |= cpu_to_be32(2 << 24);
722 if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
723 cells[j] |= cpu_to_be32(4 << 28);
724 }
725 }
726 cells[j + 1] = 0;
727 cells[j + 2] = 0;
728 cells[j + 3] = cpu_to_be32(d->io_regions[i].size >> 32);
729 cells[j + 4] = cpu_to_be32(d->io_regions[i].size);
730 j += 5;
731 }
732 qemu_fdt_setprop(fi->fdt, node->str, "reg", cells, j * sizeof(cells[0]));
733 qemu_fdt_setprop_string(fi->fdt, node->str, "name", name ?: pn);
734 if (pci_get_byte(&d->config[PCI_INTERRUPT_PIN])) {
735 qemu_fdt_setprop_cell(fi->fdt, node->str, "interrupts",
736 pci_get_byte(&d->config[PCI_INTERRUPT_PIN]));
737 }
738 /* Pegasos2 firmware has subsystem-id amd subsystem-vendor-id swapped */
739 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-vendor-id",
740 pci_get_word(&d->config[PCI_SUBSYSTEM_ID]));
741 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-id",
742 pci_get_word(&d->config[PCI_SUBSYSTEM_VENDOR_ID]));
743 cells[0] = pci_get_long(&d->config[PCI_CLASS_REVISION]);
744 qemu_fdt_setprop_cell(fi->fdt, node->str, "class-code", cells[0] >> 8);
745 qemu_fdt_setprop_cell(fi->fdt, node->str, "revision-id", cells[0] & 0xff);
746 qemu_fdt_setprop_cell(fi->fdt, node->str, "device-id",
747 pci_get_word(&d->config[PCI_DEVICE_ID]));
748 qemu_fdt_setprop_cell(fi->fdt, node->str, "vendor-id",
749 pci_get_word(&d->config[PCI_VENDOR_ID]));
750
751 g_string_free(node, TRUE);
752 }
753
754 static void *build_fdt(MachineState *machine, int *fdt_size)
755 {
756 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
757 PowerPCCPU *cpu = pm->cpu;
758 PCIBus *pci_bus;
759 FDTInfo fi;
760 uint32_t cells[16];
761 void *fdt = create_device_tree(fdt_size);
762
763 fi.fdt = fdt;
764
765 /* root node */
766 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,description",
767 "Pegasos CHRP PowerPC System");
768 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,board", "Pegasos2");
769 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,vendor", "bplan GmbH");
770 qemu_fdt_setprop_string(fdt, "/", "revision", "2B");
771 qemu_fdt_setprop_string(fdt, "/", "model", "Pegasos2");
772 qemu_fdt_setprop_string(fdt, "/", "device_type", "chrp");
773 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 1);
774 qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos2");
775
776 /* pci@c0000000 */
777 qemu_fdt_add_subnode(fdt, "/pci@c0000000");
778 cells[0] = 0;
779 cells[1] = 0;
780 qemu_fdt_setprop(fdt, "/pci@c0000000", "bus-range",
781 cells, 2 * sizeof(cells[0]));
782 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "pci-bridge-number", 1);
783 cells[0] = cpu_to_be32(PCI0_MEM_BASE);
784 cells[1] = cpu_to_be32(PCI0_MEM_SIZE);
785 qemu_fdt_setprop(fdt, "/pci@c0000000", "reg", cells, 2 * sizeof(cells[0]));
786 cells[0] = cpu_to_be32(0x01000000);
787 cells[1] = 0;
788 cells[2] = 0;
789 cells[3] = cpu_to_be32(PCI0_IO_BASE);
790 cells[4] = 0;
791 cells[5] = cpu_to_be32(PCI0_IO_SIZE);
792 cells[6] = cpu_to_be32(0x02000000);
793 cells[7] = 0;
794 cells[8] = cpu_to_be32(PCI0_MEM_BASE);
795 cells[9] = cpu_to_be32(PCI0_MEM_BASE);
796 cells[10] = 0;
797 cells[11] = cpu_to_be32(PCI0_MEM_SIZE);
798 qemu_fdt_setprop(fdt, "/pci@c0000000", "ranges",
799 cells, 12 * sizeof(cells[0]));
800 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#size-cells", 2);
801 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#address-cells", 3);
802 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "device_type", "pci");
803 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "name", "pci");
804
805 fi.path = "/pci@c0000000";
806 pci_bus = mv64361_get_pci_bus(pm->mv, 0);
807 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
808
809 /* pci@80000000 */
810 qemu_fdt_add_subnode(fdt, "/pci@80000000");
811 cells[0] = 0;
812 cells[1] = 0;
813 qemu_fdt_setprop(fdt, "/pci@80000000", "bus-range",
814 cells, 2 * sizeof(cells[0]));
815 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "pci-bridge-number", 0);
816 cells[0] = cpu_to_be32(PCI1_MEM_BASE);
817 cells[1] = cpu_to_be32(PCI1_MEM_SIZE);
818 qemu_fdt_setprop(fdt, "/pci@80000000", "reg", cells, 2 * sizeof(cells[0]));
819 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "8259-interrupt-acknowledge",
820 0xf1000cb4);
821 cells[0] = cpu_to_be32(0x01000000);
822 cells[1] = 0;
823 cells[2] = 0;
824 cells[3] = cpu_to_be32(PCI1_IO_BASE);
825 cells[4] = 0;
826 cells[5] = cpu_to_be32(PCI1_IO_SIZE);
827 cells[6] = cpu_to_be32(0x02000000);
828 cells[7] = 0;
829 cells[8] = cpu_to_be32(PCI1_MEM_BASE);
830 cells[9] = cpu_to_be32(PCI1_MEM_BASE);
831 cells[10] = 0;
832 cells[11] = cpu_to_be32(PCI1_MEM_SIZE);
833 qemu_fdt_setprop(fdt, "/pci@80000000", "ranges",
834 cells, 12 * sizeof(cells[0]));
835 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#size-cells", 2);
836 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#address-cells", 3);
837 qemu_fdt_setprop_string(fdt, "/pci@80000000", "device_type", "pci");
838 qemu_fdt_setprop_string(fdt, "/pci@80000000", "name", "pci");
839
840 fi.path = "/pci@80000000";
841 pci_bus = mv64361_get_pci_bus(pm->mv, 1);
842 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
843
844 qemu_fdt_add_subnode(fdt, "/failsafe");
845 qemu_fdt_setprop_string(fdt, "/failsafe", "device_type", "serial");
846 qemu_fdt_setprop_string(fdt, "/failsafe", "name", "failsafe");
847
848 qemu_fdt_add_subnode(fdt, "/rtas");
849 qemu_fdt_setprop_cell(fdt, "/rtas", "system-reboot", RTAS_SYSTEM_REBOOT);
850 qemu_fdt_setprop_cell(fdt, "/rtas", "hibernate", RTAS_HIBERNATE);
851 qemu_fdt_setprop_cell(fdt, "/rtas", "suspend", RTAS_SUSPEND);
852 qemu_fdt_setprop_cell(fdt, "/rtas", "power-off", RTAS_POWER_OFF);
853 qemu_fdt_setprop_cell(fdt, "/rtas", "set-indicator", RTAS_SET_INDICATOR);
854 qemu_fdt_setprop_cell(fdt, "/rtas", "display-character",
855 RTAS_DISPLAY_CHARACTER);
856 qemu_fdt_setprop_cell(fdt, "/rtas", "write-pci-config",
857 RTAS_WRITE_PCI_CONFIG);
858 qemu_fdt_setprop_cell(fdt, "/rtas", "read-pci-config",
859 RTAS_READ_PCI_CONFIG);
860 /* Pegasos2 firmware misspells check-exception and guests use that */
861 qemu_fdt_setprop_cell(fdt, "/rtas", "check-execption",
862 RTAS_CHECK_EXCEPTION);
863 qemu_fdt_setprop_cell(fdt, "/rtas", "event-scan", RTAS_EVENT_SCAN);
864 qemu_fdt_setprop_cell(fdt, "/rtas", "set-time-of-day",
865 RTAS_SET_TIME_OF_DAY);
866 qemu_fdt_setprop_cell(fdt, "/rtas", "get-time-of-day",
867 RTAS_GET_TIME_OF_DAY);
868 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-store", RTAS_NVRAM_STORE);
869 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-fetch", RTAS_NVRAM_FETCH);
870 qemu_fdt_setprop_cell(fdt, "/rtas", "restart-rtas", RTAS_RESTART_RTAS);
871 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-error-log-max", 0);
872 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-event-scan-rate", 0);
873 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-display-device", 0);
874 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-size", 20);
875 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-version", 1);
876
877 /* cpus */
878 qemu_fdt_add_subnode(fdt, "/cpus");
879 qemu_fdt_setprop_cell(fdt, "/cpus", "#cpus", 1);
880 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
881 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
882 qemu_fdt_setprop_string(fdt, "/cpus", "name", "cpus");
883
884 /* FIXME Get CPU name from CPU object */
885 const char *cp = "/cpus/PowerPC,G4";
886 qemu_fdt_add_subnode(fdt, cp);
887 qemu_fdt_setprop_cell(fdt, cp, "l2cr", 0);
888 qemu_fdt_setprop_cell(fdt, cp, "d-cache-size", 0x8000);
889 qemu_fdt_setprop_cell(fdt, cp, "d-cache-block-size",
890 cpu->env.dcache_line_size);
891 qemu_fdt_setprop_cell(fdt, cp, "d-cache-line-size",
892 cpu->env.dcache_line_size);
893 qemu_fdt_setprop_cell(fdt, cp, "i-cache-size", 0x8000);
894 qemu_fdt_setprop_cell(fdt, cp, "i-cache-block-size",
895 cpu->env.icache_line_size);
896 qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size",
897 cpu->env.icache_line_size);
898 if (cpu->env.id_tlbs) {
899 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways);
900 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way);
901 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways);
902 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-size", cpu->env.tlb_per_way);
903 qemu_fdt_setprop_string(fdt, cp, "tlb-split", "");
904 }
905 qemu_fdt_setprop_cell(fdt, cp, "tlb-sets", cpu->env.nb_ways);
906 qemu_fdt_setprop_cell(fdt, cp, "tlb-size", cpu->env.nb_tlb);
907 qemu_fdt_setprop_string(fdt, cp, "state", "running");
908 if (cpu->env.insns_flags & PPC_ALTIVEC) {
909 qemu_fdt_setprop_string(fdt, cp, "altivec", "");
910 qemu_fdt_setprop_string(fdt, cp, "data-streams", "");
911 }
912 /*
913 * FIXME What flags do data-streams, external-control and
914 * performance-monitor depend on?
915 */
916 qemu_fdt_setprop_string(fdt, cp, "external-control", "");
917 if (cpu->env.insns_flags & PPC_FLOAT_FSQRT) {
918 qemu_fdt_setprop_string(fdt, cp, "general-purpose", "");
919 }
920 qemu_fdt_setprop_string(fdt, cp, "performance-monitor", "");
921 if (cpu->env.insns_flags & PPC_FLOAT_FRES) {
922 qemu_fdt_setprop_string(fdt, cp, "graphics", "");
923 }
924 qemu_fdt_setprop_cell(fdt, cp, "reservation-granule-size", 4);
925 qemu_fdt_setprop_cell(fdt, cp, "timebase-frequency",
926 cpu->env.tb_env->tb_freq);
927 qemu_fdt_setprop_cell(fdt, cp, "bus-frequency", BUS_FREQ_HZ);
928 qemu_fdt_setprop_cell(fdt, cp, "clock-frequency", BUS_FREQ_HZ * 7.5);
929 qemu_fdt_setprop_cell(fdt, cp, "cpu-version", cpu->env.spr[SPR_PVR]);
930 cells[0] = 0;
931 cells[1] = 0;
932 qemu_fdt_setprop(fdt, cp, "reg", cells, 2 * sizeof(cells[0]));
933 qemu_fdt_setprop_string(fdt, cp, "device_type", "cpu");
934 qemu_fdt_setprop_string(fdt, cp, "name", strrchr(cp, '/') + 1);
935
936 /* memory */
937 qemu_fdt_add_subnode(fdt, "/memory@0");
938 cells[0] = 0;
939 cells[1] = cpu_to_be32(machine->ram_size);
940 qemu_fdt_setprop(fdt, "/memory@0", "reg", cells, 2 * sizeof(cells[0]));
941 qemu_fdt_setprop_string(fdt, "/memory@0", "device_type", "memory");
942 qemu_fdt_setprop_string(fdt, "/memory@0", "name", "memory");
943
944 qemu_fdt_add_subnode(fdt, "/chosen");
945 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
946 machine->kernel_cmdline ?: "");
947 qemu_fdt_setprop_string(fdt, "/chosen", "name", "chosen");
948
949 qemu_fdt_add_subnode(fdt, "/openprom");
950 qemu_fdt_setprop_string(fdt, "/openprom", "model", "Pegasos2,1.1");
951
952 return fdt;
953 }
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