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vhost-vdpa: don't initialize backend_features
[qemu/kevin.git] / hw / pci-host / bonito.c
blobafb3d1f81d5e63661b79b3b16680166799605a33
1 /*
2 * bonito north bridge support
3 *
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
6 *
7 * This code is licensed under the GNU GPL v2.
8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
11 */
12
13 /*
14 * fuloong 2e mini pc has a bonito north bridge.
15 */
16
17 /*
18 * what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
19 *
20 * devfn pci_slot<<3 + funno
21 * one pci bus can have 32 devices and each device can have 8 functions.
22 *
23 * In bonito north bridge, pci slot = IDSEL bit - 12.
24 * For example, PCI_IDSEL_VIA686B = 17,
25 * pci slot = 17-12=5
26 *
27 * so
28 * VT686B_FUN0's devfn = (5<<3)+0
29 * VT686B_FUN1's devfn = (5<<3)+1
30 *
31 * qemu also uses pci address for north bridge to access pci config register.
32 * bus_no [23:16]
33 * dev_no [15:11]
34 * fun_no [10:8]
35 * reg_no [7:2]
36 *
37 * so function bonito_sbridge_pciaddr for the translation from
38 * north bridge address to pci address.
39 */
40
41 #include "qemu/osdep.h"
42 #include "qemu/units.h"
43 #include "qapi/error.h"
44 #include "qemu/error-report.h"
45 #include "hw/pci/pci.h"
46 #include "hw/irq.h"
47 #include "hw/mips/mips.h"
48 #include "hw/pci/pci_host.h"
49 #include "migration/vmstate.h"
50 #include "sysemu/reset.h"
51 #include "sysemu/runstate.h"
52 #include "hw/misc/unimp.h"
53 #include "hw/registerfields.h"
54 #include "qom/object.h"
55
56 /* #define DEBUG_BONITO */
57
58 #ifdef DEBUG_BONITO
59 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)
60 #else
61 #define DPRINTF(fmt, ...)
62 #endif
63
64 /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/
65 #define BONITO_BOOT_BASE 0x1fc00000
66 #define BONITO_BOOT_SIZE 0x00100000
67 #define BONITO_BOOT_TOP (BONITO_BOOT_BASE + BONITO_BOOT_SIZE - 1)
68 #define BONITO_FLASH_BASE 0x1c000000
69 #define BONITO_FLASH_SIZE 0x03000000
70 #define BONITO_FLASH_TOP (BONITO_FLASH_BASE + BONITO_FLASH_SIZE - 1)
71 #define BONITO_SOCKET_BASE 0x1f800000
72 #define BONITO_SOCKET_SIZE 0x00400000
73 #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE + BONITO_SOCKET_SIZE - 1)
74 #define BONITO_REG_BASE 0x1fe00000
75 #define BONITO_REG_SIZE 0x00040000
76 #define BONITO_REG_TOP (BONITO_REG_BASE + BONITO_REG_SIZE - 1)
77 #define BONITO_DEV_BASE 0x1ff00000
78 #define BONITO_DEV_SIZE 0x00100000
79 #define BONITO_DEV_TOP (BONITO_DEV_BASE + BONITO_DEV_SIZE - 1)
80 #define BONITO_PCILO_BASE 0x10000000
81 #define BONITO_PCILO_BASE_VA 0xb0000000
82 #define BONITO_PCILO_SIZE 0x0c000000
83 #define BONITO_PCILO_TOP (BONITO_PCILO_BASE + BONITO_PCILO_SIZE - 1)
84 #define BONITO_PCILO0_BASE 0x10000000
85 #define BONITO_PCILO1_BASE 0x14000000
86 #define BONITO_PCILO2_BASE 0x18000000
87 #define BONITO_PCIHI_BASE 0x20000000
88 #define BONITO_PCIHI_SIZE 0x60000000
89 #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE - 1)
90 #define BONITO_PCIIO_BASE 0x1fd00000
91 #define BONITO_PCIIO_BASE_VA 0xbfd00000
92 #define BONITO_PCIIO_SIZE 0x00010000
93 #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE + BONITO_PCIIO_SIZE - 1)
94 #define BONITO_PCICFG_BASE 0x1fe80000
95 #define BONITO_PCICFG_SIZE 0x00080000
96 #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE + BONITO_PCICFG_SIZE - 1)
97
98
99 #define BONITO_PCICONFIGBASE 0x00
100 #define BONITO_REGBASE 0x100
101
102 #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE + BONITO_REG_BASE)
103 #define BONITO_PCICONFIG_SIZE (0x100)
104
105 #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE + BONITO_REG_BASE)
106 #define BONITO_INTERNAL_REG_SIZE (0x70)
107
108 #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE)
109 #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE)
110
111
112
113 /* 1. Bonito h/w Configuration */
114 /* Power on register */
115
116 #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */
117
118 /* PCI configuration register */
119 #define BONITO_BONGENCFG_OFFSET 0x4
120 #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET >> 2) /*0x104 */
121 REG32(BONGENCFG, 0x104)
122 FIELD(BONGENCFG, DEBUGMODE, 0, 1)
123 FIELD(BONGENCFG, SNOOP, 1, 1)
124 FIELD(BONGENCFG, CPUSELFRESET, 2, 1)
125 FIELD(BONGENCFG, BYTESWAP, 6, 1)
126 FIELD(BONGENCFG, UNCACHED, 7, 1)
127 FIELD(BONGENCFG, PREFETCH, 8, 1)
128 FIELD(BONGENCFG, WRITEBEHIND, 9, 1)
129 FIELD(BONGENCFG, PCIQUEUE, 12, 1)
130
131 /* 2. IO & IDE configuration */
132 #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */
133
134 /* 3. IO & IDE configuration */
135 #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */
136
137 /* 4. PCI address map control */
138 #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */
139 #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */
140 #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */
141
142 /* 5. ICU & GPIO regs */
143 /* GPIO Regs - r/w */
144 #define BONITO_GPIODATA_OFFSET 0x1c
145 #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */
146 #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */
147
148 /* ICU Configuration Regs - r/w */
149 #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */
150 #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */
151 #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */
152
153 /* ICU Enable Regs - IntEn & IntISR are r/o. */
154 #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */
155 #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */
156 #define BONITO_INTEN (0x38 >> 2) /* 0x138 */
157 #define BONITO_INTISR (0x3c >> 2) /* 0x13c */
158
159 /* PCI mail boxes */
160 #define BONITO_PCIMAIL0_OFFSET 0x40
161 #define BONITO_PCIMAIL1_OFFSET 0x44
162 #define BONITO_PCIMAIL2_OFFSET 0x48
163 #define BONITO_PCIMAIL3_OFFSET 0x4c
164 #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */
165 #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */
166 #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */
167 #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */
168
169 /* 6. PCI cache */
170 #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */
171 #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */
172 #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */
173 #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */
174
175 /* 7. other*/
176 #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */
177 #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */
178 #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */
179 #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */
180
181 #define BONITO_REGS (0x70 >> 2)
182
183 /* PCI config for south bridge. type 0 */
184 #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */
185 #define BONITO_PCICONF_IDSEL_OFFSET 11
186 #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */
187 #define BONITO_PCICONF_FUN_OFFSET 8
188 #define BONITO_PCICONF_REG_MASK 0xFC
189 #define BONITO_PCICONF_REG_OFFSET 0
190
191
192 /* idsel BIT = pci slot number +12 */
193 #define PCI_SLOT_BASE 12
194 #define PCI_IDSEL_VIA686B_BIT (17)
195 #define PCI_IDSEL_VIA686B (1 << PCI_IDSEL_VIA686B_BIT)
196
197 #define PCI_ADDR(busno , devno , funno , regno) \
198 ((PCI_BUILD_BDF(busno, PCI_DEVFN(devno , funno)) << 8) + (regno))
199
200 typedef struct BonitoState BonitoState;
201
202 struct PCIBonitoState {
203 PCIDevice dev;
204
205 BonitoState *pcihost;
206 uint32_t regs[BONITO_REGS];
207
208 struct bonldma {
209 uint32_t ldmactrl;
210 uint32_t ldmastat;
211 uint32_t ldmaaddr;
212 uint32_t ldmago;
213 } bonldma;
214
215 /* Based at 1fe00300, bonito Copier */
216 struct boncop {
217 uint32_t copctrl;
218 uint32_t copstat;
219 uint32_t coppaddr;
220 uint32_t copgo;
221 } boncop;
222
223 /* Bonito registers */
224 MemoryRegion iomem;
225 MemoryRegion iomem_ldma;
226 MemoryRegion iomem_cop;
227 MemoryRegion bonito_pciio;
228 MemoryRegion bonito_localio;
229
230 };
231 typedef struct PCIBonitoState PCIBonitoState;
232
233 struct BonitoState {
234 PCIHostState parent_obj;
235 qemu_irq *pic;
236 PCIBonitoState *pci_dev;
237 MemoryRegion pci_mem;
238 };
239
240 #define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost"
241 OBJECT_DECLARE_SIMPLE_TYPE(BonitoState, BONITO_PCI_HOST_BRIDGE)
242
243 #define TYPE_PCI_BONITO "Bonito"
244 OBJECT_DECLARE_SIMPLE_TYPE(PCIBonitoState, PCI_BONITO)
245
246 static void bonito_writel(void *opaque, hwaddr addr,
247 uint64_t val, unsigned size)
248 {
249 PCIBonitoState *s = opaque;
250 uint32_t saddr;
251 int reset = 0;
252
253 saddr = addr >> 2;
254
255 DPRINTF("bonito_writel "TARGET_FMT_plx" val %lx saddr %x\n",
256 addr, val, saddr);
257 switch (saddr) {
258 case BONITO_BONPONCFG:
259 case BONITO_IODEVCFG:
260 case BONITO_SDCFG:
261 case BONITO_PCIMAP:
262 case BONITO_PCIMEMBASECFG:
263 case BONITO_PCIMAP_CFG:
264 case BONITO_GPIODATA:
265 case BONITO_GPIOIE:
266 case BONITO_INTEDGE:
267 case BONITO_INTSTEER:
268 case BONITO_INTPOL:
269 case BONITO_PCIMAIL0:
270 case BONITO_PCIMAIL1:
271 case BONITO_PCIMAIL2:
272 case BONITO_PCIMAIL3:
273 case BONITO_PCICACHECTRL:
274 case BONITO_PCICACHETAG:
275 case BONITO_PCIBADADDR:
276 case BONITO_PCIMSTAT:
277 case BONITO_TIMECFG:
278 case BONITO_CPUCFG:
279 case BONITO_DQCFG:
280 case BONITO_MEMSIZE:
281 s->regs[saddr] = val;
282 break;
283 case BONITO_BONGENCFG:
284 if (!(s->regs[saddr] & 0x04) && (val & 0x04)) {
285 reset = 1; /* bit 2 jump from 0 to 1 cause reset */
286 }
287 s->regs[saddr] = val;
288 if (reset) {
289 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
290 }
291 break;
292 case BONITO_INTENSET:
293 s->regs[BONITO_INTENSET] = val;
294 s->regs[BONITO_INTEN] |= val;
295 break;
296 case BONITO_INTENCLR:
297 s->regs[BONITO_INTENCLR] = val;
298 s->regs[BONITO_INTEN] &= ~val;
299 break;
300 case BONITO_INTEN:
301 case BONITO_INTISR:
302 DPRINTF("write to readonly bonito register %x\n", saddr);
303 break;
304 default:
305 DPRINTF("write to unknown bonito register %x\n", saddr);
306 break;
307 }
308 }
309
310 static uint64_t bonito_readl(void *opaque, hwaddr addr,
311 unsigned size)
312 {
313 PCIBonitoState *s = opaque;
314 uint32_t saddr;
315
316 saddr = addr >> 2;
317
318 DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr);
319 switch (saddr) {
320 case BONITO_INTISR:
321 return s->regs[saddr];
322 default:
323 return s->regs[saddr];
324 }
325 }
326
327 static const MemoryRegionOps bonito_ops = {
328 .read = bonito_readl,
329 .write = bonito_writel,
330 .endianness = DEVICE_NATIVE_ENDIAN,
331 .valid = {
332 .min_access_size = 4,
333 .max_access_size = 4,
334 },
335 };
336
337 static void bonito_pciconf_writel(void *opaque, hwaddr addr,
338 uint64_t val, unsigned size)
339 {
340 PCIBonitoState *s = opaque;
341 PCIDevice *d = PCI_DEVICE(s);
342
343 DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %lx\n", addr, val);
344 d->config_write(d, addr, val, 4);
345 }
346
347 static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr,
348 unsigned size)
349 {
350
351 PCIBonitoState *s = opaque;
352 PCIDevice *d = PCI_DEVICE(s);
353
354 DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr);
355 return d->config_read(d, addr, 4);
356 }
357
358 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */
359
360 static const MemoryRegionOps bonito_pciconf_ops = {
361 .read = bonito_pciconf_readl,
362 .write = bonito_pciconf_writel,
363 .endianness = DEVICE_NATIVE_ENDIAN,
364 .valid = {
365 .min_access_size = 4,
366 .max_access_size = 4,
367 },
368 };
369
370 static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr,
371 unsigned size)
372 {
373 uint32_t val;
374 PCIBonitoState *s = opaque;
375
376 if (addr >= sizeof(s->bonldma)) {
377 return 0;
378 }
379
380 val = ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)];
381
382 return val;
383 }
384
385 static void bonito_ldma_writel(void *opaque, hwaddr addr,
386 uint64_t val, unsigned size)
387 {
388 PCIBonitoState *s = opaque;
389
390 if (addr >= sizeof(s->bonldma)) {
391 return;
392 }
393
394 ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)] = val & 0xffffffff;
395 }
396
397 static const MemoryRegionOps bonito_ldma_ops = {
398 .read = bonito_ldma_readl,
399 .write = bonito_ldma_writel,
400 .endianness = DEVICE_NATIVE_ENDIAN,
401 .valid = {
402 .min_access_size = 4,
403 .max_access_size = 4,
404 },
405 };
406
407 static uint64_t bonito_cop_readl(void *opaque, hwaddr addr,
408 unsigned size)
409 {
410 uint32_t val;
411 PCIBonitoState *s = opaque;
412
413 if (addr >= sizeof(s->boncop)) {
414 return 0;
415 }
416
417 val = ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)];
418
419 return val;
420 }
421
422 static void bonito_cop_writel(void *opaque, hwaddr addr,
423 uint64_t val, unsigned size)
424 {
425 PCIBonitoState *s = opaque;
426
427 if (addr >= sizeof(s->boncop)) {
428 return;
429 }
430
431 ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)] = val & 0xffffffff;
432 }
433
434 static const MemoryRegionOps bonito_cop_ops = {
435 .read = bonito_cop_readl,
436 .write = bonito_cop_writel,
437 .endianness = DEVICE_NATIVE_ENDIAN,
438 .valid = {
439 .min_access_size = 4,
440 .max_access_size = 4,
441 },
442 };
443
444 static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
445 {
446 PCIBonitoState *s = opaque;
447 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
448 uint32_t cfgaddr;
449 uint32_t idsel;
450 uint32_t devno;
451 uint32_t funno;
452 uint32_t regno;
453 uint32_t pciaddr;
454
455 /* support type0 pci config */
456 if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) {
457 return 0xffffffff;
458 }
459
460 cfgaddr = addr & 0xffff;
461 cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16;
462
463 idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >>
464 BONITO_PCICONF_IDSEL_OFFSET;
465 devno = ctz32(idsel);
466 funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET;
467 regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET;
468
469 if (idsel == 0) {
470 error_report("error in bonito pci config address 0x" TARGET_FMT_plx
471 ",pcimap_cfg=0x%x", addr, s->regs[BONITO_PCIMAP_CFG]);
472 exit(1);
473 }
474 pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno);
475 DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
476 cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno);
477
478 return pciaddr;
479 }
480
481 static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val,
482 unsigned size)
483 {
484 PCIBonitoState *s = opaque;
485 PCIDevice *d = PCI_DEVICE(s);
486 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
487 uint32_t pciaddr;
488 uint16_t status;
489
490 DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %lx\n",
491 addr, size, val);
492
493 pciaddr = bonito_sbridge_pciaddr(s, addr);
494
495 if (pciaddr == 0xffffffff) {
496 return;
497 }
498
499 /* set the pci address in s->config_reg */
500 phb->config_reg = (pciaddr) | (1u << 31);
501 pci_data_write(phb->bus, phb->config_reg, val, size);
502
503 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
504 status = pci_get_word(d->config + PCI_STATUS);
505 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
506 pci_set_word(d->config + PCI_STATUS, status);
507 }
508
509 static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size)
510 {
511 PCIBonitoState *s = opaque;
512 PCIDevice *d = PCI_DEVICE(s);
513 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
514 uint32_t pciaddr;
515 uint16_t status;
516
517 DPRINTF("bonito_spciconf_read "TARGET_FMT_plx" size %d\n", addr, size);
518
519 pciaddr = bonito_sbridge_pciaddr(s, addr);
520
521 if (pciaddr == 0xffffffff) {
522 return MAKE_64BIT_MASK(0, size * 8);
523 }
524
525 /* set the pci address in s->config_reg */
526 phb->config_reg = (pciaddr) | (1u << 31);
527
528 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
529 status = pci_get_word(d->config + PCI_STATUS);
530 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
531 pci_set_word(d->config + PCI_STATUS, status);
532
533 return pci_data_read(phb->bus, phb->config_reg, size);
534 }
535
536 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
537 static const MemoryRegionOps bonito_spciconf_ops = {
538 .read = bonito_spciconf_read,
539 .write = bonito_spciconf_write,
540 .valid.min_access_size = 1,
541 .valid.max_access_size = 4,
542 .impl.min_access_size = 1,
543 .impl.max_access_size = 4,
544 .endianness = DEVICE_NATIVE_ENDIAN,
545 };
546
547 #define BONITO_IRQ_BASE 32
548
549 static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
550 {
551 BonitoState *s = opaque;
552 qemu_irq *pic = s->pic;
553 PCIBonitoState *bonito_state = s->pci_dev;
554 int internal_irq = irq_num - BONITO_IRQ_BASE;
555
556 if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) {
557 qemu_irq_pulse(*pic);
558 } else { /* level triggered */
559 if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) {
560 qemu_irq_raise(*pic);
561 } else {
562 qemu_irq_lower(*pic);
563 }
564 }
565 }
566
567 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
568 static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num)
569 {
570 int slot;
571
572 slot = PCI_SLOT(pci_dev->devfn);
573
574 switch (slot) {
575 case 5: /* FULOONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */
576 return irq_num % 4 + BONITO_IRQ_BASE;
577 case 6: /* FULOONG2E_ATI_SLOT, VGA */
578 return 4 + BONITO_IRQ_BASE;
579 case 7: /* FULOONG2E_RTL_SLOT, RTL8139 */
580 return 5 + BONITO_IRQ_BASE;
581 case 8 ... 12: /* PCI slot 1 to 4 */
582 return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE;
583 default: /* Unknown device, don't do any translation */
584 return irq_num;
585 }
586 }
587
588 static void bonito_reset(void *opaque)
589 {
590 PCIBonitoState *s = opaque;
591 uint32_t val = 0;
592
593 /* set the default value of north bridge registers */
594
595 s->regs[BONITO_BONPONCFG] = 0xc40;
596 val = FIELD_DP32(val, BONGENCFG, PCIQUEUE, 1);
597 val = FIELD_DP32(val, BONGENCFG, WRITEBEHIND, 1);
598 val = FIELD_DP32(val, BONGENCFG, PREFETCH, 1);
599 val = FIELD_DP32(val, BONGENCFG, UNCACHED, 1);
600 val = FIELD_DP32(val, BONGENCFG, CPUSELFRESET, 1);
601 s->regs[BONITO_BONGENCFG] = val;
602
603 s->regs[BONITO_IODEVCFG] = 0x2bff8010;
604 s->regs[BONITO_SDCFG] = 0x255e0091;
605
606 s->regs[BONITO_GPIODATA] = 0x1ff;
607 s->regs[BONITO_GPIOIE] = 0x1ff;
608 s->regs[BONITO_DQCFG] = 0x8;
609 s->regs[BONITO_MEMSIZE] = 0x10000000;
610 s->regs[BONITO_PCIMAP] = 0x6140;
611 }
612
613 static const VMStateDescription vmstate_bonito = {
614 .name = "Bonito",
615 .version_id = 1,
616 .minimum_version_id = 1,
617 .fields = (VMStateField[]) {
618 VMSTATE_PCI_DEVICE(dev, PCIBonitoState),
619 VMSTATE_END_OF_LIST()
620 }
621 };
622
623 static void bonito_pcihost_realize(DeviceState *dev, Error **errp)
624 {
625 PCIHostState *phb = PCI_HOST_BRIDGE(dev);
626 BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev);
627 MemoryRegion *pcimem_lo_alias = g_new(MemoryRegion, 3);
628
629 memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCIHI_SIZE);
630 phb->bus = pci_register_root_bus(dev, "pci",
631 pci_bonito_set_irq, pci_bonito_map_irq,
632 dev, &bs->pci_mem, get_system_io(),
633 PCI_DEVFN(5, 0), 32, TYPE_PCI_BUS);
634
635 for (size_t i = 0; i < 3; i++) {
636 char *name = g_strdup_printf("pci.lomem%zu", i);
637
638 memory_region_init_alias(&pcimem_lo_alias[i], NULL, name,
639 &bs->pci_mem, i * 64 * MiB, 64 * MiB);
640 memory_region_add_subregion(get_system_memory(),
641 BONITO_PCILO_BASE + i * 64 * MiB,
642 &pcimem_lo_alias[i]);
643 g_free(name);
644 }
645
646 create_unimplemented_device("pci.io", BONITO_PCIIO_BASE, 1 * MiB);
647 }
648
649 static void bonito_realize(PCIDevice *dev, Error **errp)
650 {
651 PCIBonitoState *s = PCI_BONITO(dev);
652 SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost);
653 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
654 BonitoState *bs = BONITO_PCI_HOST_BRIDGE(s->pcihost);
655 MemoryRegion *pcimem_alias = g_new(MemoryRegion, 1);
656
657 /*
658 * Bonito North Bridge, built on FPGA,
659 * VENDOR_ID/DEVICE_ID are "undefined"
660 */
661 pci_config_set_prog_interface(dev->config, 0x00);
662
663 /* set the north bridge register mapping */
664 memory_region_init_io(&s->iomem, OBJECT(s), &bonito_ops, s,
665 "north-bridge-register", BONITO_INTERNAL_REG_SIZE);
666 sysbus_init_mmio(sysbus, &s->iomem);
667 sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE);
668
669 /* set the north bridge pci configure mapping */
670 memory_region_init_io(&phb->conf_mem, OBJECT(s), &bonito_pciconf_ops, s,
671 "north-bridge-pci-config", BONITO_PCICONFIG_SIZE);
672 sysbus_init_mmio(sysbus, &phb->conf_mem);
673 sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE);
674
675 /* set the south bridge pci configure mapping */
676 memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s,
677 "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE);
678 sysbus_init_mmio(sysbus, &phb->data_mem);
679 sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE);
680
681 create_unimplemented_device("bonito", BONITO_REG_BASE, BONITO_REG_SIZE);
682
683 memory_region_init_io(&s->iomem_ldma, OBJECT(s), &bonito_ldma_ops, s,
684 "ldma", 0x100);
685 sysbus_init_mmio(sysbus, &s->iomem_ldma);
686 sysbus_mmio_map(sysbus, 3, 0x1fe00200);
687
688 /* PCI copier */
689 memory_region_init_io(&s->iomem_cop, OBJECT(s), &bonito_cop_ops, s,
690 "cop", 0x100);
691 sysbus_init_mmio(sysbus, &s->iomem_cop);
692 sysbus_mmio_map(sysbus, 4, 0x1fe00300);
693
694 create_unimplemented_device("ROMCS", BONITO_FLASH_BASE, 60 * MiB);
695
696 /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */
697 memory_region_init_alias(&s->bonito_pciio, OBJECT(s), "isa_mmio",
698 get_system_io(), 0, BONITO_PCIIO_SIZE);
699 sysbus_init_mmio(sysbus, &s->bonito_pciio);
700 sysbus_mmio_map(sysbus, 5, BONITO_PCIIO_BASE);
701
702 /* add pci local io mapping */
703
704 memory_region_init_alias(&s->bonito_localio, OBJECT(s), "IOCS[0]",
705 get_system_io(), 0, 256 * KiB);
706 sysbus_init_mmio(sysbus, &s->bonito_localio);
707 sysbus_mmio_map(sysbus, 6, BONITO_DEV_BASE);
708 create_unimplemented_device("IOCS[1]", BONITO_DEV_BASE + 1 * 256 * KiB,
709 256 * KiB);
710 create_unimplemented_device("IOCS[2]", BONITO_DEV_BASE + 2 * 256 * KiB,
711 256 * KiB);
712 create_unimplemented_device("IOCS[3]", BONITO_DEV_BASE + 3 * 256 * KiB,
713 256 * KiB);
714
715 memory_region_init_alias(pcimem_alias, NULL, "pci.mem.alias",
716 &bs->pci_mem, 0, BONITO_PCIHI_SIZE);
717 memory_region_add_subregion(get_system_memory(),
718 BONITO_PCIHI_BASE, pcimem_alias);
719 create_unimplemented_device("PCI_2",
720 (hwaddr)BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE,
721 2 * GiB);
722
723 /* set the default value of north bridge pci config */
724 pci_set_word(dev->config + PCI_COMMAND, 0x0000);
725 pci_set_word(dev->config + PCI_STATUS, 0x0000);
726 pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000);
727 pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000);
728
729 pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00);
730 pci_config_set_interrupt_pin(dev->config, 0x01); /* interrupt pin A */
731
732 pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c);
733 pci_set_byte(dev->config + PCI_MAX_LAT, 0x00);
734
735 qemu_register_reset(bonito_reset, s);
736 }
737
738 PCIBus *bonito_init(qemu_irq *pic)
739 {
740 DeviceState *dev;
741 BonitoState *pcihost;
742 PCIHostState *phb;
743 PCIBonitoState *s;
744 PCIDevice *d;
745
746 dev = qdev_new(TYPE_BONITO_PCI_HOST_BRIDGE);
747 phb = PCI_HOST_BRIDGE(dev);
748 pcihost = BONITO_PCI_HOST_BRIDGE(dev);
749 pcihost->pic = pic;
750 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
751
752 d = pci_new(PCI_DEVFN(0, 0), TYPE_PCI_BONITO);
753 s = PCI_BONITO(d);
754 s->pcihost = pcihost;
755 pcihost->pci_dev = s;
756 pci_realize_and_unref(d, phb->bus, &error_fatal);
757
758 return phb->bus;
759 }
760
761 static void bonito_class_init(ObjectClass *klass, void *data)
762 {
763 DeviceClass *dc = DEVICE_CLASS(klass);
764 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
765
766 k->realize = bonito_realize;
767 k->vendor_id = 0xdf53;
768 k->device_id = 0x00d5;
769 k->revision = 0x01;
770 k->class_id = PCI_CLASS_BRIDGE_HOST;
771 dc->desc = "Host bridge";
772 dc->vmsd = &vmstate_bonito;
773 /*
774 * PCI-facing part of the host bridge, not usable without the
775 * host-facing part, which can't be device_add'ed, yet.
776 */
777 dc->user_creatable = false;
778 }
779
780 static const TypeInfo bonito_info = {
781 .name = TYPE_PCI_BONITO,
782 .parent = TYPE_PCI_DEVICE,
783 .instance_size = sizeof(PCIBonitoState),
784 .class_init = bonito_class_init,
785 .interfaces = (InterfaceInfo[]) {
786 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
787 { },
788 },
789 };
790
791 static void bonito_pcihost_class_init(ObjectClass *klass, void *data)
792 {
793 DeviceClass *dc = DEVICE_CLASS(klass);
794
795 dc->realize = bonito_pcihost_realize;
796 }
797
798 static const TypeInfo bonito_pcihost_info = {
799 .name = TYPE_BONITO_PCI_HOST_BRIDGE,
800 .parent = TYPE_PCI_HOST_BRIDGE,
801 .instance_size = sizeof(BonitoState),
802 .class_init = bonito_pcihost_class_init,
803 };
804
805 static void bonito_register_types(void)
806 {
807 type_register_static(&bonito_pcihost_info);
808 type_register_static(&bonito_info);
809 }
810
811 type_init(bonito_register_types)
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