4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "internals.h"
25 #include "disas/disas.h"
26 #include "exec/exec-all.h"
29 #include "qemu/bitops.h"
31 #include "exec/semihost.h"
33 #include "exec/helper-proto.h"
34 #include "exec/helper-gen.h"
36 #include "trace-tcg.h"
40 #define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T)
41 #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5)
42 /* currently all emulated v5 cores are also v5TE, so don't bother */
43 #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5)
44 #define ENABLE_ARCH_5J 0
45 #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6)
46 #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K)
47 #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2)
48 #define ENABLE_ARCH_7 arm_dc_feature(s, ARM_FEATURE_V7)
49 #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8)
51 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
53 #include "translate.h"
55 #if defined(CONFIG_USER_ONLY)
58 #define IS_USER(s) (s->user)
62 /* We reuse the same 64-bit temporaries for efficiency. */
63 static TCGv_i64 cpu_V0
, cpu_V1
, cpu_M0
;
64 static TCGv_i32 cpu_R
[16];
65 TCGv_i32 cpu_CF
, cpu_NF
, cpu_VF
, cpu_ZF
;
66 TCGv_i64 cpu_exclusive_addr
;
67 TCGv_i64 cpu_exclusive_val
;
69 /* FIXME: These should be removed. */
70 static TCGv_i32 cpu_F0s
, cpu_F1s
;
71 static TCGv_i64 cpu_F0d
, cpu_F1d
;
73 #include "exec/gen-icount.h"
75 static const char *regnames
[] =
76 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
77 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
79 /* initialize TCG globals. */
80 void arm_translate_init(void)
84 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
85 tcg_ctx
.tcg_env
= cpu_env
;
87 for (i
= 0; i
< 16; i
++) {
88 cpu_R
[i
] = tcg_global_mem_new_i32(cpu_env
,
89 offsetof(CPUARMState
, regs
[i
]),
92 cpu_CF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, CF
), "CF");
93 cpu_NF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, NF
), "NF");
94 cpu_VF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, VF
), "VF");
95 cpu_ZF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, ZF
), "ZF");
97 cpu_exclusive_addr
= tcg_global_mem_new_i64(cpu_env
,
98 offsetof(CPUARMState
, exclusive_addr
), "exclusive_addr");
99 cpu_exclusive_val
= tcg_global_mem_new_i64(cpu_env
,
100 offsetof(CPUARMState
, exclusive_val
), "exclusive_val");
102 a64_translate_init();
105 /* Flags for the disas_set_da_iss info argument:
106 * lower bits hold the Rt register number, higher bits are flags.
108 typedef enum ISSInfo
{
111 ISSInvalid
= (1 << 5),
112 ISSIsAcqRel
= (1 << 6),
113 ISSIsWrite
= (1 << 7),
114 ISSIs16Bit
= (1 << 8),
117 /* Save the syndrome information for a Data Abort */
118 static void disas_set_da_iss(DisasContext
*s
, TCGMemOp memop
, ISSInfo issinfo
)
121 int sas
= memop
& MO_SIZE
;
122 bool sse
= memop
& MO_SIGN
;
123 bool is_acqrel
= issinfo
& ISSIsAcqRel
;
124 bool is_write
= issinfo
& ISSIsWrite
;
125 bool is_16bit
= issinfo
& ISSIs16Bit
;
126 int srt
= issinfo
& ISSRegMask
;
128 if (issinfo
& ISSInvalid
) {
129 /* Some callsites want to conditionally provide ISS info,
130 * eg "only if this was not a writeback"
136 /* For AArch32, insns where the src/dest is R15 never generate
137 * ISS information. Catching that here saves checking at all
143 syn
= syn_data_abort_with_iss(0, sas
, sse
, srt
, 0, is_acqrel
,
144 0, 0, 0, is_write
, 0, is_16bit
);
145 disas_set_insn_syndrome(s
, syn
);
148 static inline ARMMMUIdx
get_a32_user_mem_index(DisasContext
*s
)
150 /* Return the mmu_idx to use for A32/T32 "unprivileged load/store"
152 * if PL2, UNPREDICTABLE (we choose to implement as if PL0)
153 * otherwise, access as if at PL0.
155 switch (s
->mmu_idx
) {
156 case ARMMMUIdx_S1E2
: /* this one is UNPREDICTABLE */
157 case ARMMMUIdx_S12NSE0
:
158 case ARMMMUIdx_S12NSE1
:
159 return ARMMMUIdx_S12NSE0
;
161 case ARMMMUIdx_S1SE0
:
162 case ARMMMUIdx_S1SE1
:
163 return ARMMMUIdx_S1SE0
;
166 g_assert_not_reached();
170 static inline TCGv_i32
load_cpu_offset(int offset
)
172 TCGv_i32 tmp
= tcg_temp_new_i32();
173 tcg_gen_ld_i32(tmp
, cpu_env
, offset
);
177 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
179 static inline void store_cpu_offset(TCGv_i32 var
, int offset
)
181 tcg_gen_st_i32(var
, cpu_env
, offset
);
182 tcg_temp_free_i32(var
);
185 #define store_cpu_field(var, name) \
186 store_cpu_offset(var, offsetof(CPUARMState, name))
188 /* Set a variable to the value of a CPU register. */
189 static void load_reg_var(DisasContext
*s
, TCGv_i32 var
, int reg
)
193 /* normally, since we updated PC, we need only to add one insn */
195 addr
= (long)s
->pc
+ 2;
197 addr
= (long)s
->pc
+ 4;
198 tcg_gen_movi_i32(var
, addr
);
200 tcg_gen_mov_i32(var
, cpu_R
[reg
]);
204 /* Create a new temporary and set it to the value of a CPU register. */
205 static inline TCGv_i32
load_reg(DisasContext
*s
, int reg
)
207 TCGv_i32 tmp
= tcg_temp_new_i32();
208 load_reg_var(s
, tmp
, reg
);
212 /* Set a CPU register. The source must be a temporary and will be
214 static void store_reg(DisasContext
*s
, int reg
, TCGv_i32 var
)
217 /* In Thumb mode, we must ignore bit 0.
218 * In ARM mode, for ARMv4 and ARMv5, it is UNPREDICTABLE if bits [1:0]
219 * are not 0b00, but for ARMv6 and above, we must ignore bits [1:0].
220 * We choose to ignore [1:0] in ARM mode for all architecture versions.
222 tcg_gen_andi_i32(var
, var
, s
->thumb
? ~1 : ~3);
223 s
->is_jmp
= DISAS_JUMP
;
225 tcg_gen_mov_i32(cpu_R
[reg
], var
);
226 tcg_temp_free_i32(var
);
229 /* Value extensions. */
230 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
231 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
232 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
233 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
235 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
236 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
239 static inline void gen_set_cpsr(TCGv_i32 var
, uint32_t mask
)
241 TCGv_i32 tmp_mask
= tcg_const_i32(mask
);
242 gen_helper_cpsr_write(cpu_env
, var
, tmp_mask
);
243 tcg_temp_free_i32(tmp_mask
);
245 /* Set NZCV flags from the high 4 bits of var. */
246 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
248 static void gen_exception_internal(int excp
)
250 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
252 assert(excp_is_internal(excp
));
253 gen_helper_exception_internal(cpu_env
, tcg_excp
);
254 tcg_temp_free_i32(tcg_excp
);
257 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
259 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
260 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
261 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
263 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
266 tcg_temp_free_i32(tcg_el
);
267 tcg_temp_free_i32(tcg_syn
);
268 tcg_temp_free_i32(tcg_excp
);
271 static void gen_ss_advance(DisasContext
*s
)
273 /* If the singlestep state is Active-not-pending, advance to
278 gen_helper_clear_pstate_ss(cpu_env
);
282 static void gen_step_complete_exception(DisasContext
*s
)
284 /* We just completed step of an insn. Move from Active-not-pending
285 * to Active-pending, and then also take the swstep exception.
286 * This corresponds to making the (IMPDEF) choice to prioritize
287 * swstep exceptions over asynchronous exceptions taken to an exception
288 * level where debug is disabled. This choice has the advantage that
289 * we do not need to maintain internal state corresponding to the
290 * ISV/EX syndrome bits between completion of the step and generation
291 * of the exception, and our syndrome information is always correct.
294 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
295 default_exception_el(s
));
296 s
->is_jmp
= DISAS_EXC
;
299 static void gen_smul_dual(TCGv_i32 a
, TCGv_i32 b
)
301 TCGv_i32 tmp1
= tcg_temp_new_i32();
302 TCGv_i32 tmp2
= tcg_temp_new_i32();
303 tcg_gen_ext16s_i32(tmp1
, a
);
304 tcg_gen_ext16s_i32(tmp2
, b
);
305 tcg_gen_mul_i32(tmp1
, tmp1
, tmp2
);
306 tcg_temp_free_i32(tmp2
);
307 tcg_gen_sari_i32(a
, a
, 16);
308 tcg_gen_sari_i32(b
, b
, 16);
309 tcg_gen_mul_i32(b
, b
, a
);
310 tcg_gen_mov_i32(a
, tmp1
);
311 tcg_temp_free_i32(tmp1
);
314 /* Byteswap each halfword. */
315 static void gen_rev16(TCGv_i32 var
)
317 TCGv_i32 tmp
= tcg_temp_new_i32();
318 tcg_gen_shri_i32(tmp
, var
, 8);
319 tcg_gen_andi_i32(tmp
, tmp
, 0x00ff00ff);
320 tcg_gen_shli_i32(var
, var
, 8);
321 tcg_gen_andi_i32(var
, var
, 0xff00ff00);
322 tcg_gen_or_i32(var
, var
, tmp
);
323 tcg_temp_free_i32(tmp
);
326 /* Byteswap low halfword and sign extend. */
327 static void gen_revsh(TCGv_i32 var
)
329 tcg_gen_ext16u_i32(var
, var
);
330 tcg_gen_bswap16_i32(var
, var
);
331 tcg_gen_ext16s_i32(var
, var
);
334 /* Return (b << 32) + a. Mark inputs as dead */
335 static TCGv_i64
gen_addq_msw(TCGv_i64 a
, TCGv_i32 b
)
337 TCGv_i64 tmp64
= tcg_temp_new_i64();
339 tcg_gen_extu_i32_i64(tmp64
, b
);
340 tcg_temp_free_i32(b
);
341 tcg_gen_shli_i64(tmp64
, tmp64
, 32);
342 tcg_gen_add_i64(a
, tmp64
, a
);
344 tcg_temp_free_i64(tmp64
);
348 /* Return (b << 32) - a. Mark inputs as dead. */
349 static TCGv_i64
gen_subq_msw(TCGv_i64 a
, TCGv_i32 b
)
351 TCGv_i64 tmp64
= tcg_temp_new_i64();
353 tcg_gen_extu_i32_i64(tmp64
, b
);
354 tcg_temp_free_i32(b
);
355 tcg_gen_shli_i64(tmp64
, tmp64
, 32);
356 tcg_gen_sub_i64(a
, tmp64
, a
);
358 tcg_temp_free_i64(tmp64
);
362 /* 32x32->64 multiply. Marks inputs as dead. */
363 static TCGv_i64
gen_mulu_i64_i32(TCGv_i32 a
, TCGv_i32 b
)
365 TCGv_i32 lo
= tcg_temp_new_i32();
366 TCGv_i32 hi
= tcg_temp_new_i32();
369 tcg_gen_mulu2_i32(lo
, hi
, a
, b
);
370 tcg_temp_free_i32(a
);
371 tcg_temp_free_i32(b
);
373 ret
= tcg_temp_new_i64();
374 tcg_gen_concat_i32_i64(ret
, lo
, hi
);
375 tcg_temp_free_i32(lo
);
376 tcg_temp_free_i32(hi
);
381 static TCGv_i64
gen_muls_i64_i32(TCGv_i32 a
, TCGv_i32 b
)
383 TCGv_i32 lo
= tcg_temp_new_i32();
384 TCGv_i32 hi
= tcg_temp_new_i32();
387 tcg_gen_muls2_i32(lo
, hi
, a
, b
);
388 tcg_temp_free_i32(a
);
389 tcg_temp_free_i32(b
);
391 ret
= tcg_temp_new_i64();
392 tcg_gen_concat_i32_i64(ret
, lo
, hi
);
393 tcg_temp_free_i32(lo
);
394 tcg_temp_free_i32(hi
);
399 /* Swap low and high halfwords. */
400 static void gen_swap_half(TCGv_i32 var
)
402 TCGv_i32 tmp
= tcg_temp_new_i32();
403 tcg_gen_shri_i32(tmp
, var
, 16);
404 tcg_gen_shli_i32(var
, var
, 16);
405 tcg_gen_or_i32(var
, var
, tmp
);
406 tcg_temp_free_i32(tmp
);
409 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
410 tmp = (t0 ^ t1) & 0x8000;
413 t0 = (t0 + t1) ^ tmp;
416 static void gen_add16(TCGv_i32 t0
, TCGv_i32 t1
)
418 TCGv_i32 tmp
= tcg_temp_new_i32();
419 tcg_gen_xor_i32(tmp
, t0
, t1
);
420 tcg_gen_andi_i32(tmp
, tmp
, 0x8000);
421 tcg_gen_andi_i32(t0
, t0
, ~0x8000);
422 tcg_gen_andi_i32(t1
, t1
, ~0x8000);
423 tcg_gen_add_i32(t0
, t0
, t1
);
424 tcg_gen_xor_i32(t0
, t0
, tmp
);
425 tcg_temp_free_i32(tmp
);
426 tcg_temp_free_i32(t1
);
429 /* Set CF to the top bit of var. */
430 static void gen_set_CF_bit31(TCGv_i32 var
)
432 tcg_gen_shri_i32(cpu_CF
, var
, 31);
435 /* Set N and Z flags from var. */
436 static inline void gen_logic_CC(TCGv_i32 var
)
438 tcg_gen_mov_i32(cpu_NF
, var
);
439 tcg_gen_mov_i32(cpu_ZF
, var
);
443 static void gen_adc(TCGv_i32 t0
, TCGv_i32 t1
)
445 tcg_gen_add_i32(t0
, t0
, t1
);
446 tcg_gen_add_i32(t0
, t0
, cpu_CF
);
449 /* dest = T0 + T1 + CF. */
450 static void gen_add_carry(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
452 tcg_gen_add_i32(dest
, t0
, t1
);
453 tcg_gen_add_i32(dest
, dest
, cpu_CF
);
456 /* dest = T0 - T1 + CF - 1. */
457 static void gen_sub_carry(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
459 tcg_gen_sub_i32(dest
, t0
, t1
);
460 tcg_gen_add_i32(dest
, dest
, cpu_CF
);
461 tcg_gen_subi_i32(dest
, dest
, 1);
464 /* dest = T0 + T1. Compute C, N, V and Z flags */
465 static void gen_add_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
467 TCGv_i32 tmp
= tcg_temp_new_i32();
468 tcg_gen_movi_i32(tmp
, 0);
469 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0
, tmp
, t1
, tmp
);
470 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
471 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0
);
472 tcg_gen_xor_i32(tmp
, t0
, t1
);
473 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
474 tcg_temp_free_i32(tmp
);
475 tcg_gen_mov_i32(dest
, cpu_NF
);
478 /* dest = T0 + T1 + CF. Compute C, N, V and Z flags */
479 static void gen_adc_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
481 TCGv_i32 tmp
= tcg_temp_new_i32();
482 if (TCG_TARGET_HAS_add2_i32
) {
483 tcg_gen_movi_i32(tmp
, 0);
484 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0
, tmp
, cpu_CF
, tmp
);
485 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1
, tmp
);
487 TCGv_i64 q0
= tcg_temp_new_i64();
488 TCGv_i64 q1
= tcg_temp_new_i64();
489 tcg_gen_extu_i32_i64(q0
, t0
);
490 tcg_gen_extu_i32_i64(q1
, t1
);
491 tcg_gen_add_i64(q0
, q0
, q1
);
492 tcg_gen_extu_i32_i64(q1
, cpu_CF
);
493 tcg_gen_add_i64(q0
, q0
, q1
);
494 tcg_gen_extr_i64_i32(cpu_NF
, cpu_CF
, q0
);
495 tcg_temp_free_i64(q0
);
496 tcg_temp_free_i64(q1
);
498 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
499 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0
);
500 tcg_gen_xor_i32(tmp
, t0
, t1
);
501 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
502 tcg_temp_free_i32(tmp
);
503 tcg_gen_mov_i32(dest
, cpu_NF
);
506 /* dest = T0 - T1. Compute C, N, V and Z flags */
507 static void gen_sub_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
510 tcg_gen_sub_i32(cpu_NF
, t0
, t1
);
511 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
512 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0
, t1
);
513 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0
);
514 tmp
= tcg_temp_new_i32();
515 tcg_gen_xor_i32(tmp
, t0
, t1
);
516 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
517 tcg_temp_free_i32(tmp
);
518 tcg_gen_mov_i32(dest
, cpu_NF
);
521 /* dest = T0 + ~T1 + CF. Compute C, N, V and Z flags */
522 static void gen_sbc_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
524 TCGv_i32 tmp
= tcg_temp_new_i32();
525 tcg_gen_not_i32(tmp
, t1
);
526 gen_adc_CC(dest
, t0
, tmp
);
527 tcg_temp_free_i32(tmp
);
530 #define GEN_SHIFT(name) \
531 static void gen_##name(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) \
533 TCGv_i32 tmp1, tmp2, tmp3; \
534 tmp1 = tcg_temp_new_i32(); \
535 tcg_gen_andi_i32(tmp1, t1, 0xff); \
536 tmp2 = tcg_const_i32(0); \
537 tmp3 = tcg_const_i32(0x1f); \
538 tcg_gen_movcond_i32(TCG_COND_GTU, tmp2, tmp1, tmp3, tmp2, t0); \
539 tcg_temp_free_i32(tmp3); \
540 tcg_gen_andi_i32(tmp1, tmp1, 0x1f); \
541 tcg_gen_##name##_i32(dest, tmp2, tmp1); \
542 tcg_temp_free_i32(tmp2); \
543 tcg_temp_free_i32(tmp1); \
549 static void gen_sar(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
552 tmp1
= tcg_temp_new_i32();
553 tcg_gen_andi_i32(tmp1
, t1
, 0xff);
554 tmp2
= tcg_const_i32(0x1f);
555 tcg_gen_movcond_i32(TCG_COND_GTU
, tmp1
, tmp1
, tmp2
, tmp2
, tmp1
);
556 tcg_temp_free_i32(tmp2
);
557 tcg_gen_sar_i32(dest
, t0
, tmp1
);
558 tcg_temp_free_i32(tmp1
);
561 static void tcg_gen_abs_i32(TCGv_i32 dest
, TCGv_i32 src
)
563 TCGv_i32 c0
= tcg_const_i32(0);
564 TCGv_i32 tmp
= tcg_temp_new_i32();
565 tcg_gen_neg_i32(tmp
, src
);
566 tcg_gen_movcond_i32(TCG_COND_GT
, dest
, src
, c0
, src
, tmp
);
567 tcg_temp_free_i32(c0
);
568 tcg_temp_free_i32(tmp
);
571 static void shifter_out_im(TCGv_i32 var
, int shift
)
574 tcg_gen_andi_i32(cpu_CF
, var
, 1);
576 tcg_gen_shri_i32(cpu_CF
, var
, shift
);
578 tcg_gen_andi_i32(cpu_CF
, cpu_CF
, 1);
583 /* Shift by immediate. Includes special handling for shift == 0. */
584 static inline void gen_arm_shift_im(TCGv_i32 var
, int shiftop
,
585 int shift
, int flags
)
591 shifter_out_im(var
, 32 - shift
);
592 tcg_gen_shli_i32(var
, var
, shift
);
598 tcg_gen_shri_i32(cpu_CF
, var
, 31);
600 tcg_gen_movi_i32(var
, 0);
603 shifter_out_im(var
, shift
- 1);
604 tcg_gen_shri_i32(var
, var
, shift
);
611 shifter_out_im(var
, shift
- 1);
614 tcg_gen_sari_i32(var
, var
, shift
);
616 case 3: /* ROR/RRX */
619 shifter_out_im(var
, shift
- 1);
620 tcg_gen_rotri_i32(var
, var
, shift
); break;
622 TCGv_i32 tmp
= tcg_temp_new_i32();
623 tcg_gen_shli_i32(tmp
, cpu_CF
, 31);
625 shifter_out_im(var
, 0);
626 tcg_gen_shri_i32(var
, var
, 1);
627 tcg_gen_or_i32(var
, var
, tmp
);
628 tcg_temp_free_i32(tmp
);
633 static inline void gen_arm_shift_reg(TCGv_i32 var
, int shiftop
,
634 TCGv_i32 shift
, int flags
)
638 case 0: gen_helper_shl_cc(var
, cpu_env
, var
, shift
); break;
639 case 1: gen_helper_shr_cc(var
, cpu_env
, var
, shift
); break;
640 case 2: gen_helper_sar_cc(var
, cpu_env
, var
, shift
); break;
641 case 3: gen_helper_ror_cc(var
, cpu_env
, var
, shift
); break;
646 gen_shl(var
, var
, shift
);
649 gen_shr(var
, var
, shift
);
652 gen_sar(var
, var
, shift
);
654 case 3: tcg_gen_andi_i32(shift
, shift
, 0x1f);
655 tcg_gen_rotr_i32(var
, var
, shift
); break;
658 tcg_temp_free_i32(shift
);
661 #define PAS_OP(pfx) \
663 case 0: gen_pas_helper(glue(pfx,add16)); break; \
664 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
665 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
666 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
667 case 4: gen_pas_helper(glue(pfx,add8)); break; \
668 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
670 static void gen_arm_parallel_addsub(int op1
, int op2
, TCGv_i32 a
, TCGv_i32 b
)
675 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
677 tmp
= tcg_temp_new_ptr();
678 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUARMState
, GE
));
680 tcg_temp_free_ptr(tmp
);
683 tmp
= tcg_temp_new_ptr();
684 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUARMState
, GE
));
686 tcg_temp_free_ptr(tmp
);
688 #undef gen_pas_helper
689 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
702 #undef gen_pas_helper
707 /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
708 #define PAS_OP(pfx) \
710 case 0: gen_pas_helper(glue(pfx,add8)); break; \
711 case 1: gen_pas_helper(glue(pfx,add16)); break; \
712 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
713 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
714 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
715 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
717 static void gen_thumb2_parallel_addsub(int op1
, int op2
, TCGv_i32 a
, TCGv_i32 b
)
722 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
724 tmp
= tcg_temp_new_ptr();
725 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUARMState
, GE
));
727 tcg_temp_free_ptr(tmp
);
730 tmp
= tcg_temp_new_ptr();
731 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUARMState
, GE
));
733 tcg_temp_free_ptr(tmp
);
735 #undef gen_pas_helper
736 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
749 #undef gen_pas_helper
755 * Generate a conditional based on ARM condition code cc.
756 * This is common between ARM and Aarch64 targets.
758 void arm_test_cc(DisasCompare
*cmp
, int cc
)
789 case 8: /* hi: C && !Z */
790 case 9: /* ls: !C || Z -> !(C && !Z) */
792 value
= tcg_temp_new_i32();
794 /* CF is 1 for C, so -CF is an all-bits-set mask for C;
795 ZF is non-zero for !Z; so AND the two subexpressions. */
796 tcg_gen_neg_i32(value
, cpu_CF
);
797 tcg_gen_and_i32(value
, value
, cpu_ZF
);
800 case 10: /* ge: N == V -> N ^ V == 0 */
801 case 11: /* lt: N != V -> N ^ V != 0 */
802 /* Since we're only interested in the sign bit, == 0 is >= 0. */
804 value
= tcg_temp_new_i32();
806 tcg_gen_xor_i32(value
, cpu_VF
, cpu_NF
);
809 case 12: /* gt: !Z && N == V */
810 case 13: /* le: Z || N != V */
812 value
= tcg_temp_new_i32();
814 /* (N == V) is equal to the sign bit of ~(NF ^ VF). Propagate
815 * the sign bit then AND with ZF to yield the result. */
816 tcg_gen_xor_i32(value
, cpu_VF
, cpu_NF
);
817 tcg_gen_sari_i32(value
, value
, 31);
818 tcg_gen_andc_i32(value
, cpu_ZF
, value
);
821 case 14: /* always */
822 case 15: /* always */
823 /* Use the ALWAYS condition, which will fold early.
824 * It doesn't matter what we use for the value. */
825 cond
= TCG_COND_ALWAYS
;
830 fprintf(stderr
, "Bad condition code 0x%x\n", cc
);
835 cond
= tcg_invert_cond(cond
);
841 cmp
->value_global
= global
;
844 void arm_free_cc(DisasCompare
*cmp
)
846 if (!cmp
->value_global
) {
847 tcg_temp_free_i32(cmp
->value
);
851 void arm_jump_cc(DisasCompare
*cmp
, TCGLabel
*label
)
853 tcg_gen_brcondi_i32(cmp
->cond
, cmp
->value
, 0, label
);
856 void arm_gen_test_cc(int cc
, TCGLabel
*label
)
859 arm_test_cc(&cmp
, cc
);
860 arm_jump_cc(&cmp
, label
);
864 static const uint8_t table_logic_cc
[16] = {
883 /* Set PC and Thumb state from an immediate address. */
884 static inline void gen_bx_im(DisasContext
*s
, uint32_t addr
)
888 s
->is_jmp
= DISAS_JUMP
;
889 if (s
->thumb
!= (addr
& 1)) {
890 tmp
= tcg_temp_new_i32();
891 tcg_gen_movi_i32(tmp
, addr
& 1);
892 tcg_gen_st_i32(tmp
, cpu_env
, offsetof(CPUARMState
, thumb
));
893 tcg_temp_free_i32(tmp
);
895 tcg_gen_movi_i32(cpu_R
[15], addr
& ~1);
898 /* Set PC and Thumb state from var. var is marked as dead. */
899 static inline void gen_bx(DisasContext
*s
, TCGv_i32 var
)
901 s
->is_jmp
= DISAS_JUMP
;
902 tcg_gen_andi_i32(cpu_R
[15], var
, ~1);
903 tcg_gen_andi_i32(var
, var
, 1);
904 store_cpu_field(var
, thumb
);
907 /* Variant of store_reg which uses branch&exchange logic when storing
908 to r15 in ARM architecture v7 and above. The source must be a temporary
909 and will be marked as dead. */
910 static inline void store_reg_bx(DisasContext
*s
, int reg
, TCGv_i32 var
)
912 if (reg
== 15 && ENABLE_ARCH_7
) {
915 store_reg(s
, reg
, var
);
919 /* Variant of store_reg which uses branch&exchange logic when storing
920 * to r15 in ARM architecture v5T and above. This is used for storing
921 * the results of a LDR/LDM/POP into r15, and corresponds to the cases
922 * in the ARM ARM which use the LoadWritePC() pseudocode function. */
923 static inline void store_reg_from_load(DisasContext
*s
, int reg
, TCGv_i32 var
)
925 if (reg
== 15 && ENABLE_ARCH_5
) {
928 store_reg(s
, reg
, var
);
932 #ifdef CONFIG_USER_ONLY
933 #define IS_USER_ONLY 1
935 #define IS_USER_ONLY 0
938 /* Abstractions of "generate code to do a guest load/store for
939 * AArch32", where a vaddr is always 32 bits (and is zero
940 * extended if we're a 64 bit core) and data is also
941 * 32 bits unless specifically doing a 64 bit access.
942 * These functions work like tcg_gen_qemu_{ld,st}* except
943 * that the address argument is TCGv_i32 rather than TCGv.
946 static inline TCGv
gen_aa32_addr(DisasContext
*s
, TCGv_i32 a32
, TCGMemOp op
)
948 TCGv addr
= tcg_temp_new();
949 tcg_gen_extu_i32_tl(addr
, a32
);
951 /* Not needed for user-mode BE32, where we use MO_BE instead. */
952 if (!IS_USER_ONLY
&& s
->sctlr_b
&& (op
& MO_SIZE
) < MO_32
) {
953 tcg_gen_xori_tl(addr
, addr
, 4 - (1 << (op
& MO_SIZE
)));
958 static void gen_aa32_ld_i32(DisasContext
*s
, TCGv_i32 val
, TCGv_i32 a32
,
959 int index
, TCGMemOp opc
)
961 TCGv addr
= gen_aa32_addr(s
, a32
, opc
);
962 tcg_gen_qemu_ld_i32(val
, addr
, index
, opc
);
966 static void gen_aa32_st_i32(DisasContext
*s
, TCGv_i32 val
, TCGv_i32 a32
,
967 int index
, TCGMemOp opc
)
969 TCGv addr
= gen_aa32_addr(s
, a32
, opc
);
970 tcg_gen_qemu_st_i32(val
, addr
, index
, opc
);
974 #define DO_GEN_LD(SUFF, OPC) \
975 static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
976 TCGv_i32 a32, int index) \
978 gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \
980 static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s, \
982 TCGv_i32 a32, int index, \
985 gen_aa32_ld##SUFF(s, val, a32, index); \
986 disas_set_da_iss(s, OPC, issinfo); \
989 #define DO_GEN_ST(SUFF, OPC) \
990 static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
991 TCGv_i32 a32, int index) \
993 gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \
995 static inline void gen_aa32_st##SUFF##_iss(DisasContext *s, \
997 TCGv_i32 a32, int index, \
1000 gen_aa32_st##SUFF(s, val, a32, index); \
1001 disas_set_da_iss(s, OPC, issinfo | ISSIsWrite); \
1004 static inline void gen_aa32_frob64(DisasContext
*s
, TCGv_i64 val
)
1006 /* Not needed for user-mode BE32, where we use MO_BE instead. */
1007 if (!IS_USER_ONLY
&& s
->sctlr_b
) {
1008 tcg_gen_rotri_i64(val
, val
, 32);
1012 static void gen_aa32_ld_i64(DisasContext
*s
, TCGv_i64 val
, TCGv_i32 a32
,
1013 int index
, TCGMemOp opc
)
1015 TCGv addr
= gen_aa32_addr(s
, a32
, opc
);
1016 tcg_gen_qemu_ld_i64(val
, addr
, index
, opc
);
1017 gen_aa32_frob64(s
, val
);
1018 tcg_temp_free(addr
);
1021 static inline void gen_aa32_ld64(DisasContext
*s
, TCGv_i64 val
,
1022 TCGv_i32 a32
, int index
)
1024 gen_aa32_ld_i64(s
, val
, a32
, index
, MO_Q
| s
->be_data
);
1027 static void gen_aa32_st_i64(DisasContext
*s
, TCGv_i64 val
, TCGv_i32 a32
,
1028 int index
, TCGMemOp opc
)
1030 TCGv addr
= gen_aa32_addr(s
, a32
, opc
);
1032 /* Not needed for user-mode BE32, where we use MO_BE instead. */
1033 if (!IS_USER_ONLY
&& s
->sctlr_b
) {
1034 TCGv_i64 tmp
= tcg_temp_new_i64();
1035 tcg_gen_rotri_i64(tmp
, val
, 32);
1036 tcg_gen_qemu_st_i64(tmp
, addr
, index
, opc
);
1037 tcg_temp_free_i64(tmp
);
1039 tcg_gen_qemu_st_i64(val
, addr
, index
, opc
);
1041 tcg_temp_free(addr
);
1044 static inline void gen_aa32_st64(DisasContext
*s
, TCGv_i64 val
,
1045 TCGv_i32 a32
, int index
)
1047 gen_aa32_st_i64(s
, val
, a32
, index
, MO_Q
| s
->be_data
);
1050 DO_GEN_LD(8s
, MO_SB
)
1051 DO_GEN_LD(8u, MO_UB
)
1052 DO_GEN_LD(16s
, MO_SW
)
1053 DO_GEN_LD(16u, MO_UW
)
1054 DO_GEN_LD(32u, MO_UL
)
1056 DO_GEN_ST(16, MO_UW
)
1057 DO_GEN_ST(32, MO_UL
)
1059 static inline void gen_set_pc_im(DisasContext
*s
, target_ulong val
)
1061 tcg_gen_movi_i32(cpu_R
[15], val
);
1064 static inline void gen_hvc(DisasContext
*s
, int imm16
)
1066 /* The pre HVC helper handles cases when HVC gets trapped
1067 * as an undefined insn by runtime configuration (ie before
1068 * the insn really executes).
1070 gen_set_pc_im(s
, s
->pc
- 4);
1071 gen_helper_pre_hvc(cpu_env
);
1072 /* Otherwise we will treat this as a real exception which
1073 * happens after execution of the insn. (The distinction matters
1074 * for the PC value reported to the exception handler and also
1075 * for single stepping.)
1078 gen_set_pc_im(s
, s
->pc
);
1079 s
->is_jmp
= DISAS_HVC
;
1082 static inline void gen_smc(DisasContext
*s
)
1084 /* As with HVC, we may take an exception either before or after
1085 * the insn executes.
1089 gen_set_pc_im(s
, s
->pc
- 4);
1090 tmp
= tcg_const_i32(syn_aa32_smc());
1091 gen_helper_pre_smc(cpu_env
, tmp
);
1092 tcg_temp_free_i32(tmp
);
1093 gen_set_pc_im(s
, s
->pc
);
1094 s
->is_jmp
= DISAS_SMC
;
1098 gen_set_condexec (DisasContext
*s
)
1100 if (s
->condexec_mask
) {
1101 uint32_t val
= (s
->condexec_cond
<< 4) | (s
->condexec_mask
>> 1);
1102 TCGv_i32 tmp
= tcg_temp_new_i32();
1103 tcg_gen_movi_i32(tmp
, val
);
1104 store_cpu_field(tmp
, condexec_bits
);
1108 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
1110 gen_set_condexec(s
);
1111 gen_set_pc_im(s
, s
->pc
- offset
);
1112 gen_exception_internal(excp
);
1113 s
->is_jmp
= DISAS_JUMP
;
1116 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
1117 int syn
, uint32_t target_el
)
1119 gen_set_condexec(s
);
1120 gen_set_pc_im(s
, s
->pc
- offset
);
1121 gen_exception(excp
, syn
, target_el
);
1122 s
->is_jmp
= DISAS_JUMP
;
1125 /* Force a TB lookup after an instruction that changes the CPU state. */
1126 static inline void gen_lookup_tb(DisasContext
*s
)
1128 tcg_gen_movi_i32(cpu_R
[15], s
->pc
& ~1);
1129 s
->is_jmp
= DISAS_JUMP
;
1132 static inline void gen_hlt(DisasContext
*s
, int imm
)
1134 /* HLT. This has two purposes.
1135 * Architecturally, it is an external halting debug instruction.
1136 * Since QEMU doesn't implement external debug, we treat this as
1137 * it is required for halting debug disabled: it will UNDEF.
1138 * Secondly, "HLT 0x3C" is a T32 semihosting trap instruction,
1139 * and "HLT 0xF000" is an A32 semihosting syscall. These traps
1140 * must trigger semihosting even for ARMv7 and earlier, where
1141 * HLT was an undefined encoding.
1142 * In system mode, we don't allow userspace access to
1143 * semihosting, to provide some semblance of security
1144 * (and for consistency with our 32-bit semihosting).
1146 if (semihosting_enabled() &&
1147 #ifndef CONFIG_USER_ONLY
1148 s
->current_el
!= 0 &&
1150 (imm
== (s
->thumb
? 0x3c : 0xf000))) {
1151 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1155 gen_exception_insn(s
, s
->thumb
? 2 : 4, EXCP_UDEF
, syn_uncategorized(),
1156 default_exception_el(s
));
1159 static inline void gen_add_data_offset(DisasContext
*s
, unsigned int insn
,
1162 int val
, rm
, shift
, shiftop
;
1165 if (!(insn
& (1 << 25))) {
1168 if (!(insn
& (1 << 23)))
1171 tcg_gen_addi_i32(var
, var
, val
);
1173 /* shift/register */
1175 shift
= (insn
>> 7) & 0x1f;
1176 shiftop
= (insn
>> 5) & 3;
1177 offset
= load_reg(s
, rm
);
1178 gen_arm_shift_im(offset
, shiftop
, shift
, 0);
1179 if (!(insn
& (1 << 23)))
1180 tcg_gen_sub_i32(var
, var
, offset
);
1182 tcg_gen_add_i32(var
, var
, offset
);
1183 tcg_temp_free_i32(offset
);
1187 static inline void gen_add_datah_offset(DisasContext
*s
, unsigned int insn
,
1188 int extra
, TCGv_i32 var
)
1193 if (insn
& (1 << 22)) {
1195 val
= (insn
& 0xf) | ((insn
>> 4) & 0xf0);
1196 if (!(insn
& (1 << 23)))
1200 tcg_gen_addi_i32(var
, var
, val
);
1204 tcg_gen_addi_i32(var
, var
, extra
);
1206 offset
= load_reg(s
, rm
);
1207 if (!(insn
& (1 << 23)))
1208 tcg_gen_sub_i32(var
, var
, offset
);
1210 tcg_gen_add_i32(var
, var
, offset
);
1211 tcg_temp_free_i32(offset
);
1215 static TCGv_ptr
get_fpstatus_ptr(int neon
)
1217 TCGv_ptr statusptr
= tcg_temp_new_ptr();
1220 offset
= offsetof(CPUARMState
, vfp
.standard_fp_status
);
1222 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
1224 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
1228 #define VFP_OP2(name) \
1229 static inline void gen_vfp_##name(int dp) \
1231 TCGv_ptr fpst = get_fpstatus_ptr(0); \
1233 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, fpst); \
1235 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, fpst); \
1237 tcg_temp_free_ptr(fpst); \
1247 static inline void gen_vfp_F1_mul(int dp
)
1249 /* Like gen_vfp_mul() but put result in F1 */
1250 TCGv_ptr fpst
= get_fpstatus_ptr(0);
1252 gen_helper_vfp_muld(cpu_F1d
, cpu_F0d
, cpu_F1d
, fpst
);
1254 gen_helper_vfp_muls(cpu_F1s
, cpu_F0s
, cpu_F1s
, fpst
);
1256 tcg_temp_free_ptr(fpst
);
1259 static inline void gen_vfp_F1_neg(int dp
)
1261 /* Like gen_vfp_neg() but put result in F1 */
1263 gen_helper_vfp_negd(cpu_F1d
, cpu_F0d
);
1265 gen_helper_vfp_negs(cpu_F1s
, cpu_F0s
);
1269 static inline void gen_vfp_abs(int dp
)
1272 gen_helper_vfp_absd(cpu_F0d
, cpu_F0d
);
1274 gen_helper_vfp_abss(cpu_F0s
, cpu_F0s
);
1277 static inline void gen_vfp_neg(int dp
)
1280 gen_helper_vfp_negd(cpu_F0d
, cpu_F0d
);
1282 gen_helper_vfp_negs(cpu_F0s
, cpu_F0s
);
1285 static inline void gen_vfp_sqrt(int dp
)
1288 gen_helper_vfp_sqrtd(cpu_F0d
, cpu_F0d
, cpu_env
);
1290 gen_helper_vfp_sqrts(cpu_F0s
, cpu_F0s
, cpu_env
);
1293 static inline void gen_vfp_cmp(int dp
)
1296 gen_helper_vfp_cmpd(cpu_F0d
, cpu_F1d
, cpu_env
);
1298 gen_helper_vfp_cmps(cpu_F0s
, cpu_F1s
, cpu_env
);
1301 static inline void gen_vfp_cmpe(int dp
)
1304 gen_helper_vfp_cmped(cpu_F0d
, cpu_F1d
, cpu_env
);
1306 gen_helper_vfp_cmpes(cpu_F0s
, cpu_F1s
, cpu_env
);
1309 static inline void gen_vfp_F1_ld0(int dp
)
1312 tcg_gen_movi_i64(cpu_F1d
, 0);
1314 tcg_gen_movi_i32(cpu_F1s
, 0);
1317 #define VFP_GEN_ITOF(name) \
1318 static inline void gen_vfp_##name(int dp, int neon) \
1320 TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
1322 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0s, statusptr); \
1324 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, statusptr); \
1326 tcg_temp_free_ptr(statusptr); \
1333 #define VFP_GEN_FTOI(name) \
1334 static inline void gen_vfp_##name(int dp, int neon) \
1336 TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
1338 gen_helper_vfp_##name##d(cpu_F0s, cpu_F0d, statusptr); \
1340 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, statusptr); \
1342 tcg_temp_free_ptr(statusptr); \
1351 #define VFP_GEN_FIX(name, round) \
1352 static inline void gen_vfp_##name(int dp, int shift, int neon) \
1354 TCGv_i32 tmp_shift = tcg_const_i32(shift); \
1355 TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
1357 gen_helper_vfp_##name##d##round(cpu_F0d, cpu_F0d, tmp_shift, \
1360 gen_helper_vfp_##name##s##round(cpu_F0s, cpu_F0s, tmp_shift, \
1363 tcg_temp_free_i32(tmp_shift); \
1364 tcg_temp_free_ptr(statusptr); \
1366 VFP_GEN_FIX(tosh
, _round_to_zero
)
1367 VFP_GEN_FIX(tosl
, _round_to_zero
)
1368 VFP_GEN_FIX(touh
, _round_to_zero
)
1369 VFP_GEN_FIX(toul
, _round_to_zero
)
1376 static inline void gen_vfp_ld(DisasContext
*s
, int dp
, TCGv_i32 addr
)
1379 gen_aa32_ld64(s
, cpu_F0d
, addr
, get_mem_index(s
));
1381 gen_aa32_ld32u(s
, cpu_F0s
, addr
, get_mem_index(s
));
1385 static inline void gen_vfp_st(DisasContext
*s
, int dp
, TCGv_i32 addr
)
1388 gen_aa32_st64(s
, cpu_F0d
, addr
, get_mem_index(s
));
1390 gen_aa32_st32(s
, cpu_F0s
, addr
, get_mem_index(s
));
1395 vfp_reg_offset (int dp
, int reg
)
1398 return offsetof(CPUARMState
, vfp
.regs
[reg
]);
1400 return offsetof(CPUARMState
, vfp
.regs
[reg
>> 1])
1401 + offsetof(CPU_DoubleU
, l
.upper
);
1403 return offsetof(CPUARMState
, vfp
.regs
[reg
>> 1])
1404 + offsetof(CPU_DoubleU
, l
.lower
);
1408 /* Return the offset of a 32-bit piece of a NEON register.
1409 zero is the least significant end of the register. */
1411 neon_reg_offset (int reg
, int n
)
1415 return vfp_reg_offset(0, sreg
);
1418 static TCGv_i32
neon_load_reg(int reg
, int pass
)
1420 TCGv_i32 tmp
= tcg_temp_new_i32();
1421 tcg_gen_ld_i32(tmp
, cpu_env
, neon_reg_offset(reg
, pass
));
1425 static void neon_store_reg(int reg
, int pass
, TCGv_i32 var
)
1427 tcg_gen_st_i32(var
, cpu_env
, neon_reg_offset(reg
, pass
));
1428 tcg_temp_free_i32(var
);
1431 static inline void neon_load_reg64(TCGv_i64 var
, int reg
)
1433 tcg_gen_ld_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1436 static inline void neon_store_reg64(TCGv_i64 var
, int reg
)
1438 tcg_gen_st_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1441 #define tcg_gen_ld_f32 tcg_gen_ld_i32
1442 #define tcg_gen_ld_f64 tcg_gen_ld_i64
1443 #define tcg_gen_st_f32 tcg_gen_st_i32
1444 #define tcg_gen_st_f64 tcg_gen_st_i64
1446 static inline void gen_mov_F0_vreg(int dp
, int reg
)
1449 tcg_gen_ld_f64(cpu_F0d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1451 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1454 static inline void gen_mov_F1_vreg(int dp
, int reg
)
1457 tcg_gen_ld_f64(cpu_F1d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1459 tcg_gen_ld_f32(cpu_F1s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1462 static inline void gen_mov_vreg_F0(int dp
, int reg
)
1465 tcg_gen_st_f64(cpu_F0d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1467 tcg_gen_st_f32(cpu_F0s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1470 #define ARM_CP_RW_BIT (1 << 20)
1472 static inline void iwmmxt_load_reg(TCGv_i64 var
, int reg
)
1474 tcg_gen_ld_i64(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.regs
[reg
]));
1477 static inline void iwmmxt_store_reg(TCGv_i64 var
, int reg
)
1479 tcg_gen_st_i64(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.regs
[reg
]));
1482 static inline TCGv_i32
iwmmxt_load_creg(int reg
)
1484 TCGv_i32 var
= tcg_temp_new_i32();
1485 tcg_gen_ld_i32(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.cregs
[reg
]));
1489 static inline void iwmmxt_store_creg(int reg
, TCGv_i32 var
)
1491 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.cregs
[reg
]));
1492 tcg_temp_free_i32(var
);
1495 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn
)
1497 iwmmxt_store_reg(cpu_M0
, rn
);
1500 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn
)
1502 iwmmxt_load_reg(cpu_M0
, rn
);
1505 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn
)
1507 iwmmxt_load_reg(cpu_V1
, rn
);
1508 tcg_gen_or_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1511 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn
)
1513 iwmmxt_load_reg(cpu_V1
, rn
);
1514 tcg_gen_and_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1517 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn
)
1519 iwmmxt_load_reg(cpu_V1
, rn
);
1520 tcg_gen_xor_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1523 #define IWMMXT_OP(name) \
1524 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1526 iwmmxt_load_reg(cpu_V1, rn); \
1527 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1530 #define IWMMXT_OP_ENV(name) \
1531 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1533 iwmmxt_load_reg(cpu_V1, rn); \
1534 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1537 #define IWMMXT_OP_ENV_SIZE(name) \
1538 IWMMXT_OP_ENV(name##b) \
1539 IWMMXT_OP_ENV(name##w) \
1540 IWMMXT_OP_ENV(name##l)
1542 #define IWMMXT_OP_ENV1(name) \
1543 static inline void gen_op_iwmmxt_##name##_M0(void) \
1545 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1559 IWMMXT_OP_ENV_SIZE(unpackl
)
1560 IWMMXT_OP_ENV_SIZE(unpackh
)
1562 IWMMXT_OP_ENV1(unpacklub
)
1563 IWMMXT_OP_ENV1(unpackluw
)
1564 IWMMXT_OP_ENV1(unpacklul
)
1565 IWMMXT_OP_ENV1(unpackhub
)
1566 IWMMXT_OP_ENV1(unpackhuw
)
1567 IWMMXT_OP_ENV1(unpackhul
)
1568 IWMMXT_OP_ENV1(unpacklsb
)
1569 IWMMXT_OP_ENV1(unpacklsw
)
1570 IWMMXT_OP_ENV1(unpacklsl
)
1571 IWMMXT_OP_ENV1(unpackhsb
)
1572 IWMMXT_OP_ENV1(unpackhsw
)
1573 IWMMXT_OP_ENV1(unpackhsl
)
1575 IWMMXT_OP_ENV_SIZE(cmpeq
)
1576 IWMMXT_OP_ENV_SIZE(cmpgtu
)
1577 IWMMXT_OP_ENV_SIZE(cmpgts
)
1579 IWMMXT_OP_ENV_SIZE(mins
)
1580 IWMMXT_OP_ENV_SIZE(minu
)
1581 IWMMXT_OP_ENV_SIZE(maxs
)
1582 IWMMXT_OP_ENV_SIZE(maxu
)
1584 IWMMXT_OP_ENV_SIZE(subn
)
1585 IWMMXT_OP_ENV_SIZE(addn
)
1586 IWMMXT_OP_ENV_SIZE(subu
)
1587 IWMMXT_OP_ENV_SIZE(addu
)
1588 IWMMXT_OP_ENV_SIZE(subs
)
1589 IWMMXT_OP_ENV_SIZE(adds
)
1591 IWMMXT_OP_ENV(avgb0
)
1592 IWMMXT_OP_ENV(avgb1
)
1593 IWMMXT_OP_ENV(avgw0
)
1594 IWMMXT_OP_ENV(avgw1
)
1596 IWMMXT_OP_ENV(packuw
)
1597 IWMMXT_OP_ENV(packul
)
1598 IWMMXT_OP_ENV(packuq
)
1599 IWMMXT_OP_ENV(packsw
)
1600 IWMMXT_OP_ENV(packsl
)
1601 IWMMXT_OP_ENV(packsq
)
1603 static void gen_op_iwmmxt_set_mup(void)
1606 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1607 tcg_gen_ori_i32(tmp
, tmp
, 2);
1608 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1611 static void gen_op_iwmmxt_set_cup(void)
1614 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1615 tcg_gen_ori_i32(tmp
, tmp
, 1);
1616 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1619 static void gen_op_iwmmxt_setpsr_nz(void)
1621 TCGv_i32 tmp
= tcg_temp_new_i32();
1622 gen_helper_iwmmxt_setpsr_nz(tmp
, cpu_M0
);
1623 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCASF
]);
1626 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn
)
1628 iwmmxt_load_reg(cpu_V1
, rn
);
1629 tcg_gen_ext32u_i64(cpu_V1
, cpu_V1
);
1630 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1633 static inline int gen_iwmmxt_address(DisasContext
*s
, uint32_t insn
,
1640 rd
= (insn
>> 16) & 0xf;
1641 tmp
= load_reg(s
, rd
);
1643 offset
= (insn
& 0xff) << ((insn
>> 7) & 2);
1644 if (insn
& (1 << 24)) {
1646 if (insn
& (1 << 23))
1647 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1649 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1650 tcg_gen_mov_i32(dest
, tmp
);
1651 if (insn
& (1 << 21))
1652 store_reg(s
, rd
, tmp
);
1654 tcg_temp_free_i32(tmp
);
1655 } else if (insn
& (1 << 21)) {
1657 tcg_gen_mov_i32(dest
, tmp
);
1658 if (insn
& (1 << 23))
1659 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1661 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1662 store_reg(s
, rd
, tmp
);
1663 } else if (!(insn
& (1 << 23)))
1668 static inline int gen_iwmmxt_shift(uint32_t insn
, uint32_t mask
, TCGv_i32 dest
)
1670 int rd
= (insn
>> 0) & 0xf;
1673 if (insn
& (1 << 8)) {
1674 if (rd
< ARM_IWMMXT_wCGR0
|| rd
> ARM_IWMMXT_wCGR3
) {
1677 tmp
= iwmmxt_load_creg(rd
);
1680 tmp
= tcg_temp_new_i32();
1681 iwmmxt_load_reg(cpu_V0
, rd
);
1682 tcg_gen_extrl_i64_i32(tmp
, cpu_V0
);
1684 tcg_gen_andi_i32(tmp
, tmp
, mask
);
1685 tcg_gen_mov_i32(dest
, tmp
);
1686 tcg_temp_free_i32(tmp
);
1690 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occurred
1691 (ie. an undefined instruction). */
1692 static int disas_iwmmxt_insn(DisasContext
*s
, uint32_t insn
)
1695 int rdhi
, rdlo
, rd0
, rd1
, i
;
1697 TCGv_i32 tmp
, tmp2
, tmp3
;
1699 if ((insn
& 0x0e000e00) == 0x0c000000) {
1700 if ((insn
& 0x0fe00ff0) == 0x0c400000) {
1702 rdlo
= (insn
>> 12) & 0xf;
1703 rdhi
= (insn
>> 16) & 0xf;
1704 if (insn
& ARM_CP_RW_BIT
) { /* TMRRC */
1705 iwmmxt_load_reg(cpu_V0
, wrd
);
1706 tcg_gen_extrl_i64_i32(cpu_R
[rdlo
], cpu_V0
);
1707 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
1708 tcg_gen_extrl_i64_i32(cpu_R
[rdhi
], cpu_V0
);
1709 } else { /* TMCRR */
1710 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
1711 iwmmxt_store_reg(cpu_V0
, wrd
);
1712 gen_op_iwmmxt_set_mup();
1717 wrd
= (insn
>> 12) & 0xf;
1718 addr
= tcg_temp_new_i32();
1719 if (gen_iwmmxt_address(s
, insn
, addr
)) {
1720 tcg_temp_free_i32(addr
);
1723 if (insn
& ARM_CP_RW_BIT
) {
1724 if ((insn
>> 28) == 0xf) { /* WLDRW wCx */
1725 tmp
= tcg_temp_new_i32();
1726 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
1727 iwmmxt_store_creg(wrd
, tmp
);
1730 if (insn
& (1 << 8)) {
1731 if (insn
& (1 << 22)) { /* WLDRD */
1732 gen_aa32_ld64(s
, cpu_M0
, addr
, get_mem_index(s
));
1734 } else { /* WLDRW wRd */
1735 tmp
= tcg_temp_new_i32();
1736 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
1739 tmp
= tcg_temp_new_i32();
1740 if (insn
& (1 << 22)) { /* WLDRH */
1741 gen_aa32_ld16u(s
, tmp
, addr
, get_mem_index(s
));
1742 } else { /* WLDRB */
1743 gen_aa32_ld8u(s
, tmp
, addr
, get_mem_index(s
));
1747 tcg_gen_extu_i32_i64(cpu_M0
, tmp
);
1748 tcg_temp_free_i32(tmp
);
1750 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1753 if ((insn
>> 28) == 0xf) { /* WSTRW wCx */
1754 tmp
= iwmmxt_load_creg(wrd
);
1755 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
1757 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1758 tmp
= tcg_temp_new_i32();
1759 if (insn
& (1 << 8)) {
1760 if (insn
& (1 << 22)) { /* WSTRD */
1761 gen_aa32_st64(s
, cpu_M0
, addr
, get_mem_index(s
));
1762 } else { /* WSTRW wRd */
1763 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1764 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
1767 if (insn
& (1 << 22)) { /* WSTRH */
1768 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1769 gen_aa32_st16(s
, tmp
, addr
, get_mem_index(s
));
1770 } else { /* WSTRB */
1771 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1772 gen_aa32_st8(s
, tmp
, addr
, get_mem_index(s
));
1776 tcg_temp_free_i32(tmp
);
1778 tcg_temp_free_i32(addr
);
1782 if ((insn
& 0x0f000000) != 0x0e000000)
1785 switch (((insn
>> 12) & 0xf00) | ((insn
>> 4) & 0xff)) {
1786 case 0x000: /* WOR */
1787 wrd
= (insn
>> 12) & 0xf;
1788 rd0
= (insn
>> 0) & 0xf;
1789 rd1
= (insn
>> 16) & 0xf;
1790 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1791 gen_op_iwmmxt_orq_M0_wRn(rd1
);
1792 gen_op_iwmmxt_setpsr_nz();
1793 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1794 gen_op_iwmmxt_set_mup();
1795 gen_op_iwmmxt_set_cup();
1797 case 0x011: /* TMCR */
1800 rd
= (insn
>> 12) & 0xf;
1801 wrd
= (insn
>> 16) & 0xf;
1803 case ARM_IWMMXT_wCID
:
1804 case ARM_IWMMXT_wCASF
:
1806 case ARM_IWMMXT_wCon
:
1807 gen_op_iwmmxt_set_cup();
1809 case ARM_IWMMXT_wCSSF
:
1810 tmp
= iwmmxt_load_creg(wrd
);
1811 tmp2
= load_reg(s
, rd
);
1812 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
1813 tcg_temp_free_i32(tmp2
);
1814 iwmmxt_store_creg(wrd
, tmp
);
1816 case ARM_IWMMXT_wCGR0
:
1817 case ARM_IWMMXT_wCGR1
:
1818 case ARM_IWMMXT_wCGR2
:
1819 case ARM_IWMMXT_wCGR3
:
1820 gen_op_iwmmxt_set_cup();
1821 tmp
= load_reg(s
, rd
);
1822 iwmmxt_store_creg(wrd
, tmp
);
1828 case 0x100: /* WXOR */
1829 wrd
= (insn
>> 12) & 0xf;
1830 rd0
= (insn
>> 0) & 0xf;
1831 rd1
= (insn
>> 16) & 0xf;
1832 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1833 gen_op_iwmmxt_xorq_M0_wRn(rd1
);
1834 gen_op_iwmmxt_setpsr_nz();
1835 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1836 gen_op_iwmmxt_set_mup();
1837 gen_op_iwmmxt_set_cup();
1839 case 0x111: /* TMRC */
1842 rd
= (insn
>> 12) & 0xf;
1843 wrd
= (insn
>> 16) & 0xf;
1844 tmp
= iwmmxt_load_creg(wrd
);
1845 store_reg(s
, rd
, tmp
);
1847 case 0x300: /* WANDN */
1848 wrd
= (insn
>> 12) & 0xf;
1849 rd0
= (insn
>> 0) & 0xf;
1850 rd1
= (insn
>> 16) & 0xf;
1851 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1852 tcg_gen_neg_i64(cpu_M0
, cpu_M0
);
1853 gen_op_iwmmxt_andq_M0_wRn(rd1
);
1854 gen_op_iwmmxt_setpsr_nz();
1855 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1856 gen_op_iwmmxt_set_mup();
1857 gen_op_iwmmxt_set_cup();
1859 case 0x200: /* WAND */
1860 wrd
= (insn
>> 12) & 0xf;
1861 rd0
= (insn
>> 0) & 0xf;
1862 rd1
= (insn
>> 16) & 0xf;
1863 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1864 gen_op_iwmmxt_andq_M0_wRn(rd1
);
1865 gen_op_iwmmxt_setpsr_nz();
1866 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1867 gen_op_iwmmxt_set_mup();
1868 gen_op_iwmmxt_set_cup();
1870 case 0x810: case 0xa10: /* WMADD */
1871 wrd
= (insn
>> 12) & 0xf;
1872 rd0
= (insn
>> 0) & 0xf;
1873 rd1
= (insn
>> 16) & 0xf;
1874 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1875 if (insn
& (1 << 21))
1876 gen_op_iwmmxt_maddsq_M0_wRn(rd1
);
1878 gen_op_iwmmxt_madduq_M0_wRn(rd1
);
1879 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1880 gen_op_iwmmxt_set_mup();
1882 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1883 wrd
= (insn
>> 12) & 0xf;
1884 rd0
= (insn
>> 16) & 0xf;
1885 rd1
= (insn
>> 0) & 0xf;
1886 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1887 switch ((insn
>> 22) & 3) {
1889 gen_op_iwmmxt_unpacklb_M0_wRn(rd1
);
1892 gen_op_iwmmxt_unpacklw_M0_wRn(rd1
);
1895 gen_op_iwmmxt_unpackll_M0_wRn(rd1
);
1900 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1901 gen_op_iwmmxt_set_mup();
1902 gen_op_iwmmxt_set_cup();
1904 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1905 wrd
= (insn
>> 12) & 0xf;
1906 rd0
= (insn
>> 16) & 0xf;
1907 rd1
= (insn
>> 0) & 0xf;
1908 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1909 switch ((insn
>> 22) & 3) {
1911 gen_op_iwmmxt_unpackhb_M0_wRn(rd1
);
1914 gen_op_iwmmxt_unpackhw_M0_wRn(rd1
);
1917 gen_op_iwmmxt_unpackhl_M0_wRn(rd1
);
1922 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1923 gen_op_iwmmxt_set_mup();
1924 gen_op_iwmmxt_set_cup();
1926 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1927 wrd
= (insn
>> 12) & 0xf;
1928 rd0
= (insn
>> 16) & 0xf;
1929 rd1
= (insn
>> 0) & 0xf;
1930 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1931 if (insn
& (1 << 22))
1932 gen_op_iwmmxt_sadw_M0_wRn(rd1
);
1934 gen_op_iwmmxt_sadb_M0_wRn(rd1
);
1935 if (!(insn
& (1 << 20)))
1936 gen_op_iwmmxt_addl_M0_wRn(wrd
);
1937 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1938 gen_op_iwmmxt_set_mup();
1940 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1941 wrd
= (insn
>> 12) & 0xf;
1942 rd0
= (insn
>> 16) & 0xf;
1943 rd1
= (insn
>> 0) & 0xf;
1944 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1945 if (insn
& (1 << 21)) {
1946 if (insn
& (1 << 20))
1947 gen_op_iwmmxt_mulshw_M0_wRn(rd1
);
1949 gen_op_iwmmxt_mulslw_M0_wRn(rd1
);
1951 if (insn
& (1 << 20))
1952 gen_op_iwmmxt_muluhw_M0_wRn(rd1
);
1954 gen_op_iwmmxt_mululw_M0_wRn(rd1
);
1956 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1957 gen_op_iwmmxt_set_mup();
1959 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1960 wrd
= (insn
>> 12) & 0xf;
1961 rd0
= (insn
>> 16) & 0xf;
1962 rd1
= (insn
>> 0) & 0xf;
1963 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1964 if (insn
& (1 << 21))
1965 gen_op_iwmmxt_macsw_M0_wRn(rd1
);
1967 gen_op_iwmmxt_macuw_M0_wRn(rd1
);
1968 if (!(insn
& (1 << 20))) {
1969 iwmmxt_load_reg(cpu_V1
, wrd
);
1970 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1972 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1973 gen_op_iwmmxt_set_mup();
1975 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1976 wrd
= (insn
>> 12) & 0xf;
1977 rd0
= (insn
>> 16) & 0xf;
1978 rd1
= (insn
>> 0) & 0xf;
1979 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1980 switch ((insn
>> 22) & 3) {
1982 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1
);
1985 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1
);
1988 gen_op_iwmmxt_cmpeql_M0_wRn(rd1
);
1993 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1994 gen_op_iwmmxt_set_mup();
1995 gen_op_iwmmxt_set_cup();
1997 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1998 wrd
= (insn
>> 12) & 0xf;
1999 rd0
= (insn
>> 16) & 0xf;
2000 rd1
= (insn
>> 0) & 0xf;
2001 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2002 if (insn
& (1 << 22)) {
2003 if (insn
& (1 << 20))
2004 gen_op_iwmmxt_avgw1_M0_wRn(rd1
);
2006 gen_op_iwmmxt_avgw0_M0_wRn(rd1
);
2008 if (insn
& (1 << 20))
2009 gen_op_iwmmxt_avgb1_M0_wRn(rd1
);
2011 gen_op_iwmmxt_avgb0_M0_wRn(rd1
);
2013 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2014 gen_op_iwmmxt_set_mup();
2015 gen_op_iwmmxt_set_cup();
2017 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
2018 wrd
= (insn
>> 12) & 0xf;
2019 rd0
= (insn
>> 16) & 0xf;
2020 rd1
= (insn
>> 0) & 0xf;
2021 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2022 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCGR0
+ ((insn
>> 20) & 3));
2023 tcg_gen_andi_i32(tmp
, tmp
, 7);
2024 iwmmxt_load_reg(cpu_V1
, rd1
);
2025 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
2026 tcg_temp_free_i32(tmp
);
2027 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2028 gen_op_iwmmxt_set_mup();
2030 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
2031 if (((insn
>> 6) & 3) == 3)
2033 rd
= (insn
>> 12) & 0xf;
2034 wrd
= (insn
>> 16) & 0xf;
2035 tmp
= load_reg(s
, rd
);
2036 gen_op_iwmmxt_movq_M0_wRn(wrd
);
2037 switch ((insn
>> 6) & 3) {
2039 tmp2
= tcg_const_i32(0xff);
2040 tmp3
= tcg_const_i32((insn
& 7) << 3);
2043 tmp2
= tcg_const_i32(0xffff);
2044 tmp3
= tcg_const_i32((insn
& 3) << 4);
2047 tmp2
= tcg_const_i32(0xffffffff);
2048 tmp3
= tcg_const_i32((insn
& 1) << 5);
2051 TCGV_UNUSED_I32(tmp2
);
2052 TCGV_UNUSED_I32(tmp3
);
2054 gen_helper_iwmmxt_insr(cpu_M0
, cpu_M0
, tmp
, tmp2
, tmp3
);
2055 tcg_temp_free_i32(tmp3
);
2056 tcg_temp_free_i32(tmp2
);
2057 tcg_temp_free_i32(tmp
);
2058 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2059 gen_op_iwmmxt_set_mup();
2061 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
2062 rd
= (insn
>> 12) & 0xf;
2063 wrd
= (insn
>> 16) & 0xf;
2064 if (rd
== 15 || ((insn
>> 22) & 3) == 3)
2066 gen_op_iwmmxt_movq_M0_wRn(wrd
);
2067 tmp
= tcg_temp_new_i32();
2068 switch ((insn
>> 22) & 3) {
2070 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 7) << 3);
2071 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
2073 tcg_gen_ext8s_i32(tmp
, tmp
);
2075 tcg_gen_andi_i32(tmp
, tmp
, 0xff);
2079 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 3) << 4);
2080 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
2082 tcg_gen_ext16s_i32(tmp
, tmp
);
2084 tcg_gen_andi_i32(tmp
, tmp
, 0xffff);
2088 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 1) << 5);
2089 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
2092 store_reg(s
, rd
, tmp
);
2094 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
2095 if ((insn
& 0x000ff008) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
2097 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
2098 switch ((insn
>> 22) & 3) {
2100 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 7) << 2) + 0);
2103 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 3) << 3) + 4);
2106 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 1) << 4) + 12);
2109 tcg_gen_shli_i32(tmp
, tmp
, 28);
2111 tcg_temp_free_i32(tmp
);
2113 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
2114 if (((insn
>> 6) & 3) == 3)
2116 rd
= (insn
>> 12) & 0xf;
2117 wrd
= (insn
>> 16) & 0xf;
2118 tmp
= load_reg(s
, rd
);
2119 switch ((insn
>> 6) & 3) {
2121 gen_helper_iwmmxt_bcstb(cpu_M0
, tmp
);
2124 gen_helper_iwmmxt_bcstw(cpu_M0
, tmp
);
2127 gen_helper_iwmmxt_bcstl(cpu_M0
, tmp
);
2130 tcg_temp_free_i32(tmp
);
2131 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2132 gen_op_iwmmxt_set_mup();
2134 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
2135 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
2137 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
2138 tmp2
= tcg_temp_new_i32();
2139 tcg_gen_mov_i32(tmp2
, tmp
);
2140 switch ((insn
>> 22) & 3) {
2142 for (i
= 0; i
< 7; i
++) {
2143 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
2144 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
2148 for (i
= 0; i
< 3; i
++) {
2149 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
2150 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
2154 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
2155 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
2159 tcg_temp_free_i32(tmp2
);
2160 tcg_temp_free_i32(tmp
);
2162 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
2163 wrd
= (insn
>> 12) & 0xf;
2164 rd0
= (insn
>> 16) & 0xf;
2165 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2166 switch ((insn
>> 22) & 3) {
2168 gen_helper_iwmmxt_addcb(cpu_M0
, cpu_M0
);
2171 gen_helper_iwmmxt_addcw(cpu_M0
, cpu_M0
);
2174 gen_helper_iwmmxt_addcl(cpu_M0
, cpu_M0
);
2179 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2180 gen_op_iwmmxt_set_mup();
2182 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
2183 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
2185 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
2186 tmp2
= tcg_temp_new_i32();
2187 tcg_gen_mov_i32(tmp2
, tmp
);
2188 switch ((insn
>> 22) & 3) {
2190 for (i
= 0; i
< 7; i
++) {
2191 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
2192 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
2196 for (i
= 0; i
< 3; i
++) {
2197 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
2198 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
2202 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
2203 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
2207 tcg_temp_free_i32(tmp2
);
2208 tcg_temp_free_i32(tmp
);
2210 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
2211 rd
= (insn
>> 12) & 0xf;
2212 rd0
= (insn
>> 16) & 0xf;
2213 if ((insn
& 0xf) != 0 || ((insn
>> 22) & 3) == 3)
2215 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2216 tmp
= tcg_temp_new_i32();
2217 switch ((insn
>> 22) & 3) {
2219 gen_helper_iwmmxt_msbb(tmp
, cpu_M0
);
2222 gen_helper_iwmmxt_msbw(tmp
, cpu_M0
);
2225 gen_helper_iwmmxt_msbl(tmp
, cpu_M0
);
2228 store_reg(s
, rd
, tmp
);
2230 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
2231 case 0x906: case 0xb06: case 0xd06: case 0xf06:
2232 wrd
= (insn
>> 12) & 0xf;
2233 rd0
= (insn
>> 16) & 0xf;
2234 rd1
= (insn
>> 0) & 0xf;
2235 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2236 switch ((insn
>> 22) & 3) {
2238 if (insn
& (1 << 21))
2239 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1
);
2241 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1
);
2244 if (insn
& (1 << 21))
2245 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1
);
2247 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1
);
2250 if (insn
& (1 << 21))
2251 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1
);
2253 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1
);
2258 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2259 gen_op_iwmmxt_set_mup();
2260 gen_op_iwmmxt_set_cup();
2262 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
2263 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
2264 wrd
= (insn
>> 12) & 0xf;
2265 rd0
= (insn
>> 16) & 0xf;
2266 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2267 switch ((insn
>> 22) & 3) {
2269 if (insn
& (1 << 21))
2270 gen_op_iwmmxt_unpacklsb_M0();
2272 gen_op_iwmmxt_unpacklub_M0();
2275 if (insn
& (1 << 21))
2276 gen_op_iwmmxt_unpacklsw_M0();
2278 gen_op_iwmmxt_unpackluw_M0();
2281 if (insn
& (1 << 21))
2282 gen_op_iwmmxt_unpacklsl_M0();
2284 gen_op_iwmmxt_unpacklul_M0();
2289 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2290 gen_op_iwmmxt_set_mup();
2291 gen_op_iwmmxt_set_cup();
2293 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
2294 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
2295 wrd
= (insn
>> 12) & 0xf;
2296 rd0
= (insn
>> 16) & 0xf;
2297 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2298 switch ((insn
>> 22) & 3) {
2300 if (insn
& (1 << 21))
2301 gen_op_iwmmxt_unpackhsb_M0();
2303 gen_op_iwmmxt_unpackhub_M0();
2306 if (insn
& (1 << 21))
2307 gen_op_iwmmxt_unpackhsw_M0();
2309 gen_op_iwmmxt_unpackhuw_M0();
2312 if (insn
& (1 << 21))
2313 gen_op_iwmmxt_unpackhsl_M0();
2315 gen_op_iwmmxt_unpackhul_M0();
2320 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2321 gen_op_iwmmxt_set_mup();
2322 gen_op_iwmmxt_set_cup();
2324 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
2325 case 0x214: case 0x614: case 0xa14: case 0xe14:
2326 if (((insn
>> 22) & 3) == 0)
2328 wrd
= (insn
>> 12) & 0xf;
2329 rd0
= (insn
>> 16) & 0xf;
2330 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2331 tmp
= tcg_temp_new_i32();
2332 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2333 tcg_temp_free_i32(tmp
);
2336 switch ((insn
>> 22) & 3) {
2338 gen_helper_iwmmxt_srlw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2341 gen_helper_iwmmxt_srll(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2344 gen_helper_iwmmxt_srlq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2347 tcg_temp_free_i32(tmp
);
2348 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2349 gen_op_iwmmxt_set_mup();
2350 gen_op_iwmmxt_set_cup();
2352 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
2353 case 0x014: case 0x414: case 0x814: case 0xc14:
2354 if (((insn
>> 22) & 3) == 0)
2356 wrd
= (insn
>> 12) & 0xf;
2357 rd0
= (insn
>> 16) & 0xf;
2358 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2359 tmp
= tcg_temp_new_i32();
2360 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2361 tcg_temp_free_i32(tmp
);
2364 switch ((insn
>> 22) & 3) {
2366 gen_helper_iwmmxt_sraw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2369 gen_helper_iwmmxt_sral(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2372 gen_helper_iwmmxt_sraq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2375 tcg_temp_free_i32(tmp
);
2376 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2377 gen_op_iwmmxt_set_mup();
2378 gen_op_iwmmxt_set_cup();
2380 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2381 case 0x114: case 0x514: case 0x914: case 0xd14:
2382 if (((insn
>> 22) & 3) == 0)
2384 wrd
= (insn
>> 12) & 0xf;
2385 rd0
= (insn
>> 16) & 0xf;
2386 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2387 tmp
= tcg_temp_new_i32();
2388 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2389 tcg_temp_free_i32(tmp
);
2392 switch ((insn
>> 22) & 3) {
2394 gen_helper_iwmmxt_sllw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2397 gen_helper_iwmmxt_slll(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2400 gen_helper_iwmmxt_sllq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2403 tcg_temp_free_i32(tmp
);
2404 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2405 gen_op_iwmmxt_set_mup();
2406 gen_op_iwmmxt_set_cup();
2408 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2409 case 0x314: case 0x714: case 0xb14: case 0xf14:
2410 if (((insn
>> 22) & 3) == 0)
2412 wrd
= (insn
>> 12) & 0xf;
2413 rd0
= (insn
>> 16) & 0xf;
2414 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2415 tmp
= tcg_temp_new_i32();
2416 switch ((insn
>> 22) & 3) {
2418 if (gen_iwmmxt_shift(insn
, 0xf, tmp
)) {
2419 tcg_temp_free_i32(tmp
);
2422 gen_helper_iwmmxt_rorw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2425 if (gen_iwmmxt_shift(insn
, 0x1f, tmp
)) {
2426 tcg_temp_free_i32(tmp
);
2429 gen_helper_iwmmxt_rorl(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2432 if (gen_iwmmxt_shift(insn
, 0x3f, tmp
)) {
2433 tcg_temp_free_i32(tmp
);
2436 gen_helper_iwmmxt_rorq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2439 tcg_temp_free_i32(tmp
);
2440 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2441 gen_op_iwmmxt_set_mup();
2442 gen_op_iwmmxt_set_cup();
2444 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2445 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2446 wrd
= (insn
>> 12) & 0xf;
2447 rd0
= (insn
>> 16) & 0xf;
2448 rd1
= (insn
>> 0) & 0xf;
2449 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2450 switch ((insn
>> 22) & 3) {
2452 if (insn
& (1 << 21))
2453 gen_op_iwmmxt_minsb_M0_wRn(rd1
);
2455 gen_op_iwmmxt_minub_M0_wRn(rd1
);
2458 if (insn
& (1 << 21))
2459 gen_op_iwmmxt_minsw_M0_wRn(rd1
);
2461 gen_op_iwmmxt_minuw_M0_wRn(rd1
);
2464 if (insn
& (1 << 21))
2465 gen_op_iwmmxt_minsl_M0_wRn(rd1
);
2467 gen_op_iwmmxt_minul_M0_wRn(rd1
);
2472 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2473 gen_op_iwmmxt_set_mup();
2475 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2476 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2477 wrd
= (insn
>> 12) & 0xf;
2478 rd0
= (insn
>> 16) & 0xf;
2479 rd1
= (insn
>> 0) & 0xf;
2480 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2481 switch ((insn
>> 22) & 3) {
2483 if (insn
& (1 << 21))
2484 gen_op_iwmmxt_maxsb_M0_wRn(rd1
);
2486 gen_op_iwmmxt_maxub_M0_wRn(rd1
);
2489 if (insn
& (1 << 21))
2490 gen_op_iwmmxt_maxsw_M0_wRn(rd1
);
2492 gen_op_iwmmxt_maxuw_M0_wRn(rd1
);
2495 if (insn
& (1 << 21))
2496 gen_op_iwmmxt_maxsl_M0_wRn(rd1
);
2498 gen_op_iwmmxt_maxul_M0_wRn(rd1
);
2503 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2504 gen_op_iwmmxt_set_mup();
2506 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2507 case 0x402: case 0x502: case 0x602: case 0x702:
2508 wrd
= (insn
>> 12) & 0xf;
2509 rd0
= (insn
>> 16) & 0xf;
2510 rd1
= (insn
>> 0) & 0xf;
2511 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2512 tmp
= tcg_const_i32((insn
>> 20) & 3);
2513 iwmmxt_load_reg(cpu_V1
, rd1
);
2514 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
2515 tcg_temp_free_i32(tmp
);
2516 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2517 gen_op_iwmmxt_set_mup();
2519 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2520 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2521 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2522 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2523 wrd
= (insn
>> 12) & 0xf;
2524 rd0
= (insn
>> 16) & 0xf;
2525 rd1
= (insn
>> 0) & 0xf;
2526 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2527 switch ((insn
>> 20) & 0xf) {
2529 gen_op_iwmmxt_subnb_M0_wRn(rd1
);
2532 gen_op_iwmmxt_subub_M0_wRn(rd1
);
2535 gen_op_iwmmxt_subsb_M0_wRn(rd1
);
2538 gen_op_iwmmxt_subnw_M0_wRn(rd1
);
2541 gen_op_iwmmxt_subuw_M0_wRn(rd1
);
2544 gen_op_iwmmxt_subsw_M0_wRn(rd1
);
2547 gen_op_iwmmxt_subnl_M0_wRn(rd1
);
2550 gen_op_iwmmxt_subul_M0_wRn(rd1
);
2553 gen_op_iwmmxt_subsl_M0_wRn(rd1
);
2558 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2559 gen_op_iwmmxt_set_mup();
2560 gen_op_iwmmxt_set_cup();
2562 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2563 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2564 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2565 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2566 wrd
= (insn
>> 12) & 0xf;
2567 rd0
= (insn
>> 16) & 0xf;
2568 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2569 tmp
= tcg_const_i32(((insn
>> 16) & 0xf0) | (insn
& 0x0f));
2570 gen_helper_iwmmxt_shufh(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2571 tcg_temp_free_i32(tmp
);
2572 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2573 gen_op_iwmmxt_set_mup();
2574 gen_op_iwmmxt_set_cup();
2576 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2577 case 0x418: case 0x518: case 0x618: case 0x718:
2578 case 0x818: case 0x918: case 0xa18: case 0xb18:
2579 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2580 wrd
= (insn
>> 12) & 0xf;
2581 rd0
= (insn
>> 16) & 0xf;
2582 rd1
= (insn
>> 0) & 0xf;
2583 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2584 switch ((insn
>> 20) & 0xf) {
2586 gen_op_iwmmxt_addnb_M0_wRn(rd1
);
2589 gen_op_iwmmxt_addub_M0_wRn(rd1
);
2592 gen_op_iwmmxt_addsb_M0_wRn(rd1
);
2595 gen_op_iwmmxt_addnw_M0_wRn(rd1
);
2598 gen_op_iwmmxt_adduw_M0_wRn(rd1
);
2601 gen_op_iwmmxt_addsw_M0_wRn(rd1
);
2604 gen_op_iwmmxt_addnl_M0_wRn(rd1
);
2607 gen_op_iwmmxt_addul_M0_wRn(rd1
);
2610 gen_op_iwmmxt_addsl_M0_wRn(rd1
);
2615 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2616 gen_op_iwmmxt_set_mup();
2617 gen_op_iwmmxt_set_cup();
2619 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2620 case 0x408: case 0x508: case 0x608: case 0x708:
2621 case 0x808: case 0x908: case 0xa08: case 0xb08:
2622 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2623 if (!(insn
& (1 << 20)) || ((insn
>> 22) & 3) == 0)
2625 wrd
= (insn
>> 12) & 0xf;
2626 rd0
= (insn
>> 16) & 0xf;
2627 rd1
= (insn
>> 0) & 0xf;
2628 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2629 switch ((insn
>> 22) & 3) {
2631 if (insn
& (1 << 21))
2632 gen_op_iwmmxt_packsw_M0_wRn(rd1
);
2634 gen_op_iwmmxt_packuw_M0_wRn(rd1
);
2637 if (insn
& (1 << 21))
2638 gen_op_iwmmxt_packsl_M0_wRn(rd1
);
2640 gen_op_iwmmxt_packul_M0_wRn(rd1
);
2643 if (insn
& (1 << 21))
2644 gen_op_iwmmxt_packsq_M0_wRn(rd1
);
2646 gen_op_iwmmxt_packuq_M0_wRn(rd1
);
2649 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2650 gen_op_iwmmxt_set_mup();
2651 gen_op_iwmmxt_set_cup();
2653 case 0x201: case 0x203: case 0x205: case 0x207:
2654 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2655 case 0x211: case 0x213: case 0x215: case 0x217:
2656 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2657 wrd
= (insn
>> 5) & 0xf;
2658 rd0
= (insn
>> 12) & 0xf;
2659 rd1
= (insn
>> 0) & 0xf;
2660 if (rd0
== 0xf || rd1
== 0xf)
2662 gen_op_iwmmxt_movq_M0_wRn(wrd
);
2663 tmp
= load_reg(s
, rd0
);
2664 tmp2
= load_reg(s
, rd1
);
2665 switch ((insn
>> 16) & 0xf) {
2666 case 0x0: /* TMIA */
2667 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2669 case 0x8: /* TMIAPH */
2670 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2672 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2673 if (insn
& (1 << 16))
2674 tcg_gen_shri_i32(tmp
, tmp
, 16);
2675 if (insn
& (1 << 17))
2676 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2677 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2680 tcg_temp_free_i32(tmp2
);
2681 tcg_temp_free_i32(tmp
);
2684 tcg_temp_free_i32(tmp2
);
2685 tcg_temp_free_i32(tmp
);
2686 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2687 gen_op_iwmmxt_set_mup();
2696 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occurred
2697 (ie. an undefined instruction). */
2698 static int disas_dsp_insn(DisasContext
*s
, uint32_t insn
)
2700 int acc
, rd0
, rd1
, rdhi
, rdlo
;
2703 if ((insn
& 0x0ff00f10) == 0x0e200010) {
2704 /* Multiply with Internal Accumulate Format */
2705 rd0
= (insn
>> 12) & 0xf;
2707 acc
= (insn
>> 5) & 7;
2712 tmp
= load_reg(s
, rd0
);
2713 tmp2
= load_reg(s
, rd1
);
2714 switch ((insn
>> 16) & 0xf) {
2716 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2718 case 0x8: /* MIAPH */
2719 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2721 case 0xc: /* MIABB */
2722 case 0xd: /* MIABT */
2723 case 0xe: /* MIATB */
2724 case 0xf: /* MIATT */
2725 if (insn
& (1 << 16))
2726 tcg_gen_shri_i32(tmp
, tmp
, 16);
2727 if (insn
& (1 << 17))
2728 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2729 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2734 tcg_temp_free_i32(tmp2
);
2735 tcg_temp_free_i32(tmp
);
2737 gen_op_iwmmxt_movq_wRn_M0(acc
);
2741 if ((insn
& 0x0fe00ff8) == 0x0c400000) {
2742 /* Internal Accumulator Access Format */
2743 rdhi
= (insn
>> 16) & 0xf;
2744 rdlo
= (insn
>> 12) & 0xf;
2750 if (insn
& ARM_CP_RW_BIT
) { /* MRA */
2751 iwmmxt_load_reg(cpu_V0
, acc
);
2752 tcg_gen_extrl_i64_i32(cpu_R
[rdlo
], cpu_V0
);
2753 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
2754 tcg_gen_extrl_i64_i32(cpu_R
[rdhi
], cpu_V0
);
2755 tcg_gen_andi_i32(cpu_R
[rdhi
], cpu_R
[rdhi
], (1 << (40 - 32)) - 1);
2757 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
2758 iwmmxt_store_reg(cpu_V0
, acc
);
2766 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2767 #define VFP_SREG(insn, bigbit, smallbit) \
2768 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2769 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2770 if (arm_dc_feature(s, ARM_FEATURE_VFP3)) { \
2771 reg = (((insn) >> (bigbit)) & 0x0f) \
2772 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2774 if (insn & (1 << (smallbit))) \
2776 reg = ((insn) >> (bigbit)) & 0x0f; \
2779 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2780 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2781 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2782 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2783 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2784 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2786 /* Move between integer and VFP cores. */
2787 static TCGv_i32
gen_vfp_mrs(void)
2789 TCGv_i32 tmp
= tcg_temp_new_i32();
2790 tcg_gen_mov_i32(tmp
, cpu_F0s
);
2794 static void gen_vfp_msr(TCGv_i32 tmp
)
2796 tcg_gen_mov_i32(cpu_F0s
, tmp
);
2797 tcg_temp_free_i32(tmp
);
2800 static void gen_neon_dup_u8(TCGv_i32 var
, int shift
)
2802 TCGv_i32 tmp
= tcg_temp_new_i32();
2804 tcg_gen_shri_i32(var
, var
, shift
);
2805 tcg_gen_ext8u_i32(var
, var
);
2806 tcg_gen_shli_i32(tmp
, var
, 8);
2807 tcg_gen_or_i32(var
, var
, tmp
);
2808 tcg_gen_shli_i32(tmp
, var
, 16);
2809 tcg_gen_or_i32(var
, var
, tmp
);
2810 tcg_temp_free_i32(tmp
);
2813 static void gen_neon_dup_low16(TCGv_i32 var
)
2815 TCGv_i32 tmp
= tcg_temp_new_i32();
2816 tcg_gen_ext16u_i32(var
, var
);
2817 tcg_gen_shli_i32(tmp
, var
, 16);
2818 tcg_gen_or_i32(var
, var
, tmp
);
2819 tcg_temp_free_i32(tmp
);
2822 static void gen_neon_dup_high16(TCGv_i32 var
)
2824 TCGv_i32 tmp
= tcg_temp_new_i32();
2825 tcg_gen_andi_i32(var
, var
, 0xffff0000);
2826 tcg_gen_shri_i32(tmp
, var
, 16);
2827 tcg_gen_or_i32(var
, var
, tmp
);
2828 tcg_temp_free_i32(tmp
);
2831 static TCGv_i32
gen_load_and_replicate(DisasContext
*s
, TCGv_i32 addr
, int size
)
2833 /* Load a single Neon element and replicate into a 32 bit TCG reg */
2834 TCGv_i32 tmp
= tcg_temp_new_i32();
2837 gen_aa32_ld8u(s
, tmp
, addr
, get_mem_index(s
));
2838 gen_neon_dup_u8(tmp
, 0);
2841 gen_aa32_ld16u(s
, tmp
, addr
, get_mem_index(s
));
2842 gen_neon_dup_low16(tmp
);
2845 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
2847 default: /* Avoid compiler warnings. */
2853 static int handle_vsel(uint32_t insn
, uint32_t rd
, uint32_t rn
, uint32_t rm
,
2856 uint32_t cc
= extract32(insn
, 20, 2);
2859 TCGv_i64 frn
, frm
, dest
;
2860 TCGv_i64 tmp
, zero
, zf
, nf
, vf
;
2862 zero
= tcg_const_i64(0);
2864 frn
= tcg_temp_new_i64();
2865 frm
= tcg_temp_new_i64();
2866 dest
= tcg_temp_new_i64();
2868 zf
= tcg_temp_new_i64();
2869 nf
= tcg_temp_new_i64();
2870 vf
= tcg_temp_new_i64();
2872 tcg_gen_extu_i32_i64(zf
, cpu_ZF
);
2873 tcg_gen_ext_i32_i64(nf
, cpu_NF
);
2874 tcg_gen_ext_i32_i64(vf
, cpu_VF
);
2876 tcg_gen_ld_f64(frn
, cpu_env
, vfp_reg_offset(dp
, rn
));
2877 tcg_gen_ld_f64(frm
, cpu_env
, vfp_reg_offset(dp
, rm
));
2880 tcg_gen_movcond_i64(TCG_COND_EQ
, dest
, zf
, zero
,
2884 tcg_gen_movcond_i64(TCG_COND_LT
, dest
, vf
, zero
,
2887 case 2: /* ge: N == V -> N ^ V == 0 */
2888 tmp
= tcg_temp_new_i64();
2889 tcg_gen_xor_i64(tmp
, vf
, nf
);
2890 tcg_gen_movcond_i64(TCG_COND_GE
, dest
, tmp
, zero
,
2892 tcg_temp_free_i64(tmp
);
2894 case 3: /* gt: !Z && N == V */
2895 tcg_gen_movcond_i64(TCG_COND_NE
, dest
, zf
, zero
,
2897 tmp
= tcg_temp_new_i64();
2898 tcg_gen_xor_i64(tmp
, vf
, nf
);
2899 tcg_gen_movcond_i64(TCG_COND_GE
, dest
, tmp
, zero
,
2901 tcg_temp_free_i64(tmp
);
2904 tcg_gen_st_f64(dest
, cpu_env
, vfp_reg_offset(dp
, rd
));
2905 tcg_temp_free_i64(frn
);
2906 tcg_temp_free_i64(frm
);
2907 tcg_temp_free_i64(dest
);
2909 tcg_temp_free_i64(zf
);
2910 tcg_temp_free_i64(nf
);
2911 tcg_temp_free_i64(vf
);
2913 tcg_temp_free_i64(zero
);
2915 TCGv_i32 frn
, frm
, dest
;
2918 zero
= tcg_const_i32(0);
2920 frn
= tcg_temp_new_i32();
2921 frm
= tcg_temp_new_i32();
2922 dest
= tcg_temp_new_i32();
2923 tcg_gen_ld_f32(frn
, cpu_env
, vfp_reg_offset(dp
, rn
));
2924 tcg_gen_ld_f32(frm
, cpu_env
, vfp_reg_offset(dp
, rm
));
2927 tcg_gen_movcond_i32(TCG_COND_EQ
, dest
, cpu_ZF
, zero
,
2931 tcg_gen_movcond_i32(TCG_COND_LT
, dest
, cpu_VF
, zero
,
2934 case 2: /* ge: N == V -> N ^ V == 0 */
2935 tmp
= tcg_temp_new_i32();
2936 tcg_gen_xor_i32(tmp
, cpu_VF
, cpu_NF
);
2937 tcg_gen_movcond_i32(TCG_COND_GE
, dest
, tmp
, zero
,
2939 tcg_temp_free_i32(tmp
);
2941 case 3: /* gt: !Z && N == V */
2942 tcg_gen_movcond_i32(TCG_COND_NE
, dest
, cpu_ZF
, zero
,
2944 tmp
= tcg_temp_new_i32();
2945 tcg_gen_xor_i32(tmp
, cpu_VF
, cpu_NF
);
2946 tcg_gen_movcond_i32(TCG_COND_GE
, dest
, tmp
, zero
,
2948 tcg_temp_free_i32(tmp
);
2951 tcg_gen_st_f32(dest
, cpu_env
, vfp_reg_offset(dp
, rd
));
2952 tcg_temp_free_i32(frn
);
2953 tcg_temp_free_i32(frm
);
2954 tcg_temp_free_i32(dest
);
2956 tcg_temp_free_i32(zero
);
2962 static int handle_vminmaxnm(uint32_t insn
, uint32_t rd
, uint32_t rn
,
2963 uint32_t rm
, uint32_t dp
)
2965 uint32_t vmin
= extract32(insn
, 6, 1);
2966 TCGv_ptr fpst
= get_fpstatus_ptr(0);
2969 TCGv_i64 frn
, frm
, dest
;
2971 frn
= tcg_temp_new_i64();
2972 frm
= tcg_temp_new_i64();
2973 dest
= tcg_temp_new_i64();
2975 tcg_gen_ld_f64(frn
, cpu_env
, vfp_reg_offset(dp
, rn
));
2976 tcg_gen_ld_f64(frm
, cpu_env
, vfp_reg_offset(dp
, rm
));
2978 gen_helper_vfp_minnumd(dest
, frn
, frm
, fpst
);
2980 gen_helper_vfp_maxnumd(dest
, frn
, frm
, fpst
);
2982 tcg_gen_st_f64(dest
, cpu_env
, vfp_reg_offset(dp
, rd
));
2983 tcg_temp_free_i64(frn
);
2984 tcg_temp_free_i64(frm
);
2985 tcg_temp_free_i64(dest
);
2987 TCGv_i32 frn
, frm
, dest
;
2989 frn
= tcg_temp_new_i32();
2990 frm
= tcg_temp_new_i32();
2991 dest
= tcg_temp_new_i32();
2993 tcg_gen_ld_f32(frn
, cpu_env
, vfp_reg_offset(dp
, rn
));
2994 tcg_gen_ld_f32(frm
, cpu_env
, vfp_reg_offset(dp
, rm
));
2996 gen_helper_vfp_minnums(dest
, frn
, frm
, fpst
);
2998 gen_helper_vfp_maxnums(dest
, frn
, frm
, fpst
);
3000 tcg_gen_st_f32(dest
, cpu_env
, vfp_reg_offset(dp
, rd
));
3001 tcg_temp_free_i32(frn
);
3002 tcg_temp_free_i32(frm
);
3003 tcg_temp_free_i32(dest
);
3006 tcg_temp_free_ptr(fpst
);
3010 static int handle_vrint(uint32_t insn
, uint32_t rd
, uint32_t rm
, uint32_t dp
,
3013 TCGv_ptr fpst
= get_fpstatus_ptr(0);
3016 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rounding
));
3017 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
3022 tcg_op
= tcg_temp_new_i64();
3023 tcg_res
= tcg_temp_new_i64();
3024 tcg_gen_ld_f64(tcg_op
, cpu_env
, vfp_reg_offset(dp
, rm
));
3025 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
3026 tcg_gen_st_f64(tcg_res
, cpu_env
, vfp_reg_offset(dp
, rd
));
3027 tcg_temp_free_i64(tcg_op
);
3028 tcg_temp_free_i64(tcg_res
);
3032 tcg_op
= tcg_temp_new_i32();
3033 tcg_res
= tcg_temp_new_i32();
3034 tcg_gen_ld_f32(tcg_op
, cpu_env
, vfp_reg_offset(dp
, rm
));
3035 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
3036 tcg_gen_st_f32(tcg_res
, cpu_env
, vfp_reg_offset(dp
, rd
));
3037 tcg_temp_free_i32(tcg_op
);
3038 tcg_temp_free_i32(tcg_res
);
3041 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
3042 tcg_temp_free_i32(tcg_rmode
);
3044 tcg_temp_free_ptr(fpst
);
3048 static int handle_vcvt(uint32_t insn
, uint32_t rd
, uint32_t rm
, uint32_t dp
,
3051 bool is_signed
= extract32(insn
, 7, 1);
3052 TCGv_ptr fpst
= get_fpstatus_ptr(0);
3053 TCGv_i32 tcg_rmode
, tcg_shift
;
3055 tcg_shift
= tcg_const_i32(0);
3057 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rounding
));
3058 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
3061 TCGv_i64 tcg_double
, tcg_res
;
3063 /* Rd is encoded as a single precision register even when the source
3064 * is double precision.
3066 rd
= ((rd
<< 1) & 0x1e) | ((rd
>> 4) & 0x1);
3067 tcg_double
= tcg_temp_new_i64();
3068 tcg_res
= tcg_temp_new_i64();
3069 tcg_tmp
= tcg_temp_new_i32();
3070 tcg_gen_ld_f64(tcg_double
, cpu_env
, vfp_reg_offset(1, rm
));
3072 gen_helper_vfp_tosld(tcg_res
, tcg_double
, tcg_shift
, fpst
);
3074 gen_helper_vfp_tould(tcg_res
, tcg_double
, tcg_shift
, fpst
);
3076 tcg_gen_extrl_i64_i32(tcg_tmp
, tcg_res
);
3077 tcg_gen_st_f32(tcg_tmp
, cpu_env
, vfp_reg_offset(0, rd
));
3078 tcg_temp_free_i32(tcg_tmp
);
3079 tcg_temp_free_i64(tcg_res
);
3080 tcg_temp_free_i64(tcg_double
);
3082 TCGv_i32 tcg_single
, tcg_res
;
3083 tcg_single
= tcg_temp_new_i32();
3084 tcg_res
= tcg_temp_new_i32();
3085 tcg_gen_ld_f32(tcg_single
, cpu_env
, vfp_reg_offset(0, rm
));
3087 gen_helper_vfp_tosls(tcg_res
, tcg_single
, tcg_shift
, fpst
);
3089 gen_helper_vfp_touls(tcg_res
, tcg_single
, tcg_shift
, fpst
);
3091 tcg_gen_st_f32(tcg_res
, cpu_env
, vfp_reg_offset(0, rd
));
3092 tcg_temp_free_i32(tcg_res
);
3093 tcg_temp_free_i32(tcg_single
);
3096 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
3097 tcg_temp_free_i32(tcg_rmode
);
3099 tcg_temp_free_i32(tcg_shift
);
3101 tcg_temp_free_ptr(fpst
);
3106 /* Table for converting the most common AArch32 encoding of
3107 * rounding mode to arm_fprounding order (which matches the
3108 * common AArch64 order); see ARM ARM pseudocode FPDecodeRM().
3110 static const uint8_t fp_decode_rm
[] = {
3117 static int disas_vfp_v8_insn(DisasContext
*s
, uint32_t insn
)
3119 uint32_t rd
, rn
, rm
, dp
= extract32(insn
, 8, 1);
3121 if (!arm_dc_feature(s
, ARM_FEATURE_V8
)) {
3126 VFP_DREG_D(rd
, insn
);
3127 VFP_DREG_N(rn
, insn
);
3128 VFP_DREG_M(rm
, insn
);
3130 rd
= VFP_SREG_D(insn
);
3131 rn
= VFP_SREG_N(insn
);
3132 rm
= VFP_SREG_M(insn
);
3135 if ((insn
& 0x0f800e50) == 0x0e000a00) {
3136 return handle_vsel(insn
, rd
, rn
, rm
, dp
);
3137 } else if ((insn
& 0x0fb00e10) == 0x0e800a00) {
3138 return handle_vminmaxnm(insn
, rd
, rn
, rm
, dp
);
3139 } else if ((insn
& 0x0fbc0ed0) == 0x0eb80a40) {
3140 /* VRINTA, VRINTN, VRINTP, VRINTM */
3141 int rounding
= fp_decode_rm
[extract32(insn
, 16, 2)];
3142 return handle_vrint(insn
, rd
, rm
, dp
, rounding
);
3143 } else if ((insn
& 0x0fbc0e50) == 0x0ebc0a40) {
3144 /* VCVTA, VCVTN, VCVTP, VCVTM */
3145 int rounding
= fp_decode_rm
[extract32(insn
, 16, 2)];
3146 return handle_vcvt(insn
, rd
, rm
, dp
, rounding
);
3151 /* Disassemble a VFP instruction. Returns nonzero if an error occurred
3152 (ie. an undefined instruction). */
3153 static int disas_vfp_insn(DisasContext
*s
, uint32_t insn
)
3155 uint32_t rd
, rn
, rm
, op
, i
, n
, offset
, delta_d
, delta_m
, bank_mask
;
3161 if (!arm_dc_feature(s
, ARM_FEATURE_VFP
)) {
3165 /* FIXME: this access check should not take precedence over UNDEF
3166 * for invalid encodings; we will generate incorrect syndrome information
3167 * for attempts to execute invalid vfp/neon encodings with FP disabled.
3169 if (s
->fp_excp_el
) {
3170 gen_exception_insn(s
, 4, EXCP_UDEF
,
3171 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
3175 if (!s
->vfp_enabled
) {
3176 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
3177 if ((insn
& 0x0fe00fff) != 0x0ee00a10)
3179 rn
= (insn
>> 16) & 0xf;
3180 if (rn
!= ARM_VFP_FPSID
&& rn
!= ARM_VFP_FPEXC
&& rn
!= ARM_VFP_MVFR2
3181 && rn
!= ARM_VFP_MVFR1
&& rn
!= ARM_VFP_MVFR0
) {
3186 if (extract32(insn
, 28, 4) == 0xf) {
3187 /* Encodings with T=1 (Thumb) or unconditional (ARM):
3188 * only used in v8 and above.
3190 return disas_vfp_v8_insn(s
, insn
);
3193 dp
= ((insn
& 0xf00) == 0xb00);
3194 switch ((insn
>> 24) & 0xf) {
3196 if (insn
& (1 << 4)) {
3197 /* single register transfer */
3198 rd
= (insn
>> 12) & 0xf;
3203 VFP_DREG_N(rn
, insn
);
3206 if (insn
& 0x00c00060
3207 && !arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
3211 pass
= (insn
>> 21) & 1;
3212 if (insn
& (1 << 22)) {
3214 offset
= ((insn
>> 5) & 3) * 8;
3215 } else if (insn
& (1 << 5)) {
3217 offset
= (insn
& (1 << 6)) ? 16 : 0;
3222 if (insn
& ARM_CP_RW_BIT
) {
3224 tmp
= neon_load_reg(rn
, pass
);
3228 tcg_gen_shri_i32(tmp
, tmp
, offset
);
3229 if (insn
& (1 << 23))
3235 if (insn
& (1 << 23)) {
3237 tcg_gen_shri_i32(tmp
, tmp
, 16);
3243 tcg_gen_sari_i32(tmp
, tmp
, 16);
3252 store_reg(s
, rd
, tmp
);
3255 tmp
= load_reg(s
, rd
);
3256 if (insn
& (1 << 23)) {
3259 gen_neon_dup_u8(tmp
, 0);
3260 } else if (size
== 1) {
3261 gen_neon_dup_low16(tmp
);
3263 for (n
= 0; n
<= pass
* 2; n
++) {
3264 tmp2
= tcg_temp_new_i32();
3265 tcg_gen_mov_i32(tmp2
, tmp
);
3266 neon_store_reg(rn
, n
, tmp2
);
3268 neon_store_reg(rn
, n
, tmp
);
3273 tmp2
= neon_load_reg(rn
, pass
);
3274 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, offset
, 8);
3275 tcg_temp_free_i32(tmp2
);
3278 tmp2
= neon_load_reg(rn
, pass
);
3279 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, offset
, 16);
3280 tcg_temp_free_i32(tmp2
);
3285 neon_store_reg(rn
, pass
, tmp
);
3289 if ((insn
& 0x6f) != 0x00)
3291 rn
= VFP_SREG_N(insn
);
3292 if (insn
& ARM_CP_RW_BIT
) {
3294 if (insn
& (1 << 21)) {
3295 /* system register */
3300 /* VFP2 allows access to FSID from userspace.
3301 VFP3 restricts all id registers to privileged
3304 && arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
3307 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
3312 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
3314 case ARM_VFP_FPINST
:
3315 case ARM_VFP_FPINST2
:
3316 /* Not present in VFP3. */
3318 || arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
3321 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
3325 tmp
= load_cpu_field(vfp
.xregs
[ARM_VFP_FPSCR
]);
3326 tcg_gen_andi_i32(tmp
, tmp
, 0xf0000000);
3328 tmp
= tcg_temp_new_i32();
3329 gen_helper_vfp_get_fpscr(tmp
, cpu_env
);
3333 if (!arm_dc_feature(s
, ARM_FEATURE_V8
)) {
3340 || !arm_dc_feature(s
, ARM_FEATURE_MVFR
)) {
3343 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
3349 gen_mov_F0_vreg(0, rn
);
3350 tmp
= gen_vfp_mrs();
3353 /* Set the 4 flag bits in the CPSR. */
3355 tcg_temp_free_i32(tmp
);
3357 store_reg(s
, rd
, tmp
);
3361 if (insn
& (1 << 21)) {
3363 /* system register */
3368 /* Writes are ignored. */
3371 tmp
= load_reg(s
, rd
);
3372 gen_helper_vfp_set_fpscr(cpu_env
, tmp
);
3373 tcg_temp_free_i32(tmp
);
3379 /* TODO: VFP subarchitecture support.
3380 * For now, keep the EN bit only */
3381 tmp
= load_reg(s
, rd
);
3382 tcg_gen_andi_i32(tmp
, tmp
, 1 << 30);
3383 store_cpu_field(tmp
, vfp
.xregs
[rn
]);
3386 case ARM_VFP_FPINST
:
3387 case ARM_VFP_FPINST2
:
3391 tmp
= load_reg(s
, rd
);
3392 store_cpu_field(tmp
, vfp
.xregs
[rn
]);
3398 tmp
= load_reg(s
, rd
);
3400 gen_mov_vreg_F0(0, rn
);
3405 /* data processing */
3406 /* The opcode is in bits 23, 21, 20 and 6. */
3407 op
= ((insn
>> 20) & 8) | ((insn
>> 19) & 6) | ((insn
>> 6) & 1);
3411 rn
= ((insn
>> 15) & 0x1e) | ((insn
>> 7) & 1);
3413 /* rn is register number */
3414 VFP_DREG_N(rn
, insn
);
3417 if (op
== 15 && (rn
== 15 || ((rn
& 0x1c) == 0x18) ||
3418 ((rn
& 0x1e) == 0x6))) {
3419 /* Integer or single/half precision destination. */
3420 rd
= VFP_SREG_D(insn
);
3422 VFP_DREG_D(rd
, insn
);
3425 (((rn
& 0x1c) == 0x10) || ((rn
& 0x14) == 0x14) ||
3426 ((rn
& 0x1e) == 0x4))) {
3427 /* VCVT from int or half precision is always from S reg
3428 * regardless of dp bit. VCVT with immediate frac_bits
3429 * has same format as SREG_M.
3431 rm
= VFP_SREG_M(insn
);
3433 VFP_DREG_M(rm
, insn
);
3436 rn
= VFP_SREG_N(insn
);
3437 if (op
== 15 && rn
== 15) {
3438 /* Double precision destination. */
3439 VFP_DREG_D(rd
, insn
);
3441 rd
= VFP_SREG_D(insn
);
3443 /* NB that we implicitly rely on the encoding for the frac_bits
3444 * in VCVT of fixed to float being the same as that of an SREG_M
3446 rm
= VFP_SREG_M(insn
);
3449 veclen
= s
->vec_len
;
3450 if (op
== 15 && rn
> 3)
3453 /* Shut up compiler warnings. */
3464 /* Figure out what type of vector operation this is. */
3465 if ((rd
& bank_mask
) == 0) {
3470 delta_d
= (s
->vec_stride
>> 1) + 1;
3472 delta_d
= s
->vec_stride
+ 1;
3474 if ((rm
& bank_mask
) == 0) {
3475 /* mixed scalar/vector */
3484 /* Load the initial operands. */
3489 /* Integer source */
3490 gen_mov_F0_vreg(0, rm
);
3495 gen_mov_F0_vreg(dp
, rd
);
3496 gen_mov_F1_vreg(dp
, rm
);
3500 /* Compare with zero */
3501 gen_mov_F0_vreg(dp
, rd
);
3512 /* Source and destination the same. */
3513 gen_mov_F0_vreg(dp
, rd
);
3519 /* VCVTB, VCVTT: only present with the halfprec extension
3520 * UNPREDICTABLE if bit 8 is set prior to ARMv8
3521 * (we choose to UNDEF)
3523 if ((dp
&& !arm_dc_feature(s
, ARM_FEATURE_V8
)) ||
3524 !arm_dc_feature(s
, ARM_FEATURE_VFP_FP16
)) {
3527 if (!extract32(rn
, 1, 1)) {
3528 /* Half precision source. */
3529 gen_mov_F0_vreg(0, rm
);
3532 /* Otherwise fall through */
3534 /* One source operand. */
3535 gen_mov_F0_vreg(dp
, rm
);
3539 /* Two source operands. */
3540 gen_mov_F0_vreg(dp
, rn
);
3541 gen_mov_F1_vreg(dp
, rm
);
3545 /* Perform the calculation. */
3547 case 0: /* VMLA: fd + (fn * fm) */
3548 /* Note that order of inputs to the add matters for NaNs */
3550 gen_mov_F0_vreg(dp
, rd
);
3553 case 1: /* VMLS: fd + -(fn * fm) */
3556 gen_mov_F0_vreg(dp
, rd
);
3559 case 2: /* VNMLS: -fd + (fn * fm) */
3560 /* Note that it isn't valid to replace (-A + B) with (B - A)
3561 * or similar plausible looking simplifications
3562 * because this will give wrong results for NaNs.
3565 gen_mov_F0_vreg(dp
, rd
);
3569 case 3: /* VNMLA: -fd + -(fn * fm) */
3572 gen_mov_F0_vreg(dp
, rd
);
3576 case 4: /* mul: fn * fm */
3579 case 5: /* nmul: -(fn * fm) */
3583 case 6: /* add: fn + fm */
3586 case 7: /* sub: fn - fm */
3589 case 8: /* div: fn / fm */
3592 case 10: /* VFNMA : fd = muladd(-fd, fn, fm) */
3593 case 11: /* VFNMS : fd = muladd(-fd, -fn, fm) */
3594 case 12: /* VFMA : fd = muladd( fd, fn, fm) */
3595 case 13: /* VFMS : fd = muladd( fd, -fn, fm) */
3596 /* These are fused multiply-add, and must be done as one
3597 * floating point operation with no rounding between the
3598 * multiplication and addition steps.
3599 * NB that doing the negations here as separate steps is
3600 * correct : an input NaN should come out with its sign bit
3601 * flipped if it is a negated-input.
3603 if (!arm_dc_feature(s
, ARM_FEATURE_VFP4
)) {
3611 gen_helper_vfp_negd(cpu_F0d
, cpu_F0d
);
3613 frd
= tcg_temp_new_i64();
3614 tcg_gen_ld_f64(frd
, cpu_env
, vfp_reg_offset(dp
, rd
));
3617 gen_helper_vfp_negd(frd
, frd
);
3619 fpst
= get_fpstatus_ptr(0);
3620 gen_helper_vfp_muladdd(cpu_F0d
, cpu_F0d
,
3621 cpu_F1d
, frd
, fpst
);
3622 tcg_temp_free_ptr(fpst
);
3623 tcg_temp_free_i64(frd
);
3629 gen_helper_vfp_negs(cpu_F0s
, cpu_F0s
);
3631 frd
= tcg_temp_new_i32();
3632 tcg_gen_ld_f32(frd
, cpu_env
, vfp_reg_offset(dp
, rd
));
3634 gen_helper_vfp_negs(frd
, frd
);
3636 fpst
= get_fpstatus_ptr(0);
3637 gen_helper_vfp_muladds(cpu_F0s
, cpu_F0s
,
3638 cpu_F1s
, frd
, fpst
);
3639 tcg_temp_free_ptr(fpst
);
3640 tcg_temp_free_i32(frd
);
3643 case 14: /* fconst */
3644 if (!arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
3648 n
= (insn
<< 12) & 0x80000000;
3649 i
= ((insn
>> 12) & 0x70) | (insn
& 0xf);
3656 tcg_gen_movi_i64(cpu_F0d
, ((uint64_t)n
) << 32);
3663 tcg_gen_movi_i32(cpu_F0s
, n
);
3666 case 15: /* extension space */
3680 case 4: /* vcvtb.f32.f16, vcvtb.f64.f16 */
3681 tmp
= gen_vfp_mrs();
3682 tcg_gen_ext16u_i32(tmp
, tmp
);
3684 gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d
, tmp
,
3687 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s
, tmp
,
3690 tcg_temp_free_i32(tmp
);
3692 case 5: /* vcvtt.f32.f16, vcvtt.f64.f16 */
3693 tmp
= gen_vfp_mrs();
3694 tcg_gen_shri_i32(tmp
, tmp
, 16);
3696 gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d
, tmp
,
3699 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s
, tmp
,
3702 tcg_temp_free_i32(tmp
);
3704 case 6: /* vcvtb.f16.f32, vcvtb.f16.f64 */
3705 tmp
= tcg_temp_new_i32();
3707 gen_helper_vfp_fcvt_f64_to_f16(tmp
, cpu_F0d
,
3710 gen_helper_vfp_fcvt_f32_to_f16(tmp
, cpu_F0s
,
3713 gen_mov_F0_vreg(0, rd
);
3714 tmp2
= gen_vfp_mrs();
3715 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
3716 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
3717 tcg_temp_free_i32(tmp2
);
3720 case 7: /* vcvtt.f16.f32, vcvtt.f16.f64 */
3721 tmp
= tcg_temp_new_i32();
3723 gen_helper_vfp_fcvt_f64_to_f16(tmp
, cpu_F0d
,
3726 gen_helper_vfp_fcvt_f32_to_f16(tmp
, cpu_F0s
,
3729 tcg_gen_shli_i32(tmp
, tmp
, 16);
3730 gen_mov_F0_vreg(0, rd
);
3731 tmp2
= gen_vfp_mrs();
3732 tcg_gen_ext16u_i32(tmp2
, tmp2
);
3733 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
3734 tcg_temp_free_i32(tmp2
);
3746 case 11: /* cmpez */
3750 case 12: /* vrintr */
3752 TCGv_ptr fpst
= get_fpstatus_ptr(0);
3754 gen_helper_rintd(cpu_F0d
, cpu_F0d
, fpst
);
3756 gen_helper_rints(cpu_F0s
, cpu_F0s
, fpst
);
3758 tcg_temp_free_ptr(fpst
);
3761 case 13: /* vrintz */
3763 TCGv_ptr fpst
= get_fpstatus_ptr(0);
3765 tcg_rmode
= tcg_const_i32(float_round_to_zero
);
3766 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
3768 gen_helper_rintd(cpu_F0d
, cpu_F0d
, fpst
);
3770 gen_helper_rints(cpu_F0s
, cpu_F0s
, fpst
);
3772 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
3773 tcg_temp_free_i32(tcg_rmode
);
3774 tcg_temp_free_ptr(fpst
);
3777 case 14: /* vrintx */
3779 TCGv_ptr fpst
= get_fpstatus_ptr(0);
3781 gen_helper_rintd_exact(cpu_F0d
, cpu_F0d
, fpst
);
3783 gen_helper_rints_exact(cpu_F0s
, cpu_F0s
, fpst
);
3785 tcg_temp_free_ptr(fpst
);
3788 case 15: /* single<->double conversion */
3790 gen_helper_vfp_fcvtsd(cpu_F0s
, cpu_F0d
, cpu_env
);
3792 gen_helper_vfp_fcvtds(cpu_F0d
, cpu_F0s
, cpu_env
);
3794 case 16: /* fuito */
3795 gen_vfp_uito(dp
, 0);
3797 case 17: /* fsito */
3798 gen_vfp_sito(dp
, 0);
3800 case 20: /* fshto */
3801 if (!arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
3804 gen_vfp_shto(dp
, 16 - rm
, 0);
3806 case 21: /* fslto */
3807 if (!arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
3810 gen_vfp_slto(dp
, 32 - rm
, 0);
3812 case 22: /* fuhto */
3813 if (!arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
3816 gen_vfp_uhto(dp
, 16 - rm
, 0);
3818 case 23: /* fulto */
3819 if (!arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
3822 gen_vfp_ulto(dp
, 32 - rm
, 0);
3824 case 24: /* ftoui */
3825 gen_vfp_toui(dp
, 0);
3827 case 25: /* ftouiz */
3828 gen_vfp_touiz(dp
, 0);
3830 case 26: /* ftosi */
3831 gen_vfp_tosi(dp
, 0);
3833 case 27: /* ftosiz */
3834 gen_vfp_tosiz(dp
, 0);
3836 case 28: /* ftosh */
3837 if (!arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
3840 gen_vfp_tosh(dp
, 16 - rm
, 0);
3842 case 29: /* ftosl */
3843 if (!arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
3846 gen_vfp_tosl(dp
, 32 - rm
, 0);
3848 case 30: /* ftouh */
3849 if (!arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
3852 gen_vfp_touh(dp
, 16 - rm
, 0);
3854 case 31: /* ftoul */
3855 if (!arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
3858 gen_vfp_toul(dp
, 32 - rm
, 0);
3860 default: /* undefined */
3864 default: /* undefined */
3868 /* Write back the result. */
3869 if (op
== 15 && (rn
>= 8 && rn
<= 11)) {
3870 /* Comparison, do nothing. */
3871 } else if (op
== 15 && dp
&& ((rn
& 0x1c) == 0x18 ||
3872 (rn
& 0x1e) == 0x6)) {
3873 /* VCVT double to int: always integer result.
3874 * VCVT double to half precision is always a single
3877 gen_mov_vreg_F0(0, rd
);
3878 } else if (op
== 15 && rn
== 15) {
3880 gen_mov_vreg_F0(!dp
, rd
);
3882 gen_mov_vreg_F0(dp
, rd
);
3885 /* break out of the loop if we have finished */
3889 if (op
== 15 && delta_m
== 0) {
3890 /* single source one-many */
3892 rd
= ((rd
+ delta_d
) & (bank_mask
- 1))
3894 gen_mov_vreg_F0(dp
, rd
);
3898 /* Setup the next operands. */
3900 rd
= ((rd
+ delta_d
) & (bank_mask
- 1))
3904 /* One source operand. */
3905 rm
= ((rm
+ delta_m
) & (bank_mask
- 1))
3907 gen_mov_F0_vreg(dp
, rm
);
3909 /* Two source operands. */
3910 rn
= ((rn
+ delta_d
) & (bank_mask
- 1))
3912 gen_mov_F0_vreg(dp
, rn
);
3914 rm
= ((rm
+ delta_m
) & (bank_mask
- 1))
3916 gen_mov_F1_vreg(dp
, rm
);
3924 if ((insn
& 0x03e00000) == 0x00400000) {
3925 /* two-register transfer */
3926 rn
= (insn
>> 16) & 0xf;
3927 rd
= (insn
>> 12) & 0xf;
3929 VFP_DREG_M(rm
, insn
);
3931 rm
= VFP_SREG_M(insn
);
3934 if (insn
& ARM_CP_RW_BIT
) {
3937 gen_mov_F0_vreg(0, rm
* 2);
3938 tmp
= gen_vfp_mrs();
3939 store_reg(s
, rd
, tmp
);
3940 gen_mov_F0_vreg(0, rm
* 2 + 1);
3941 tmp
= gen_vfp_mrs();
3942 store_reg(s
, rn
, tmp
);
3944 gen_mov_F0_vreg(0, rm
);
3945 tmp
= gen_vfp_mrs();
3946 store_reg(s
, rd
, tmp
);
3947 gen_mov_F0_vreg(0, rm
+ 1);
3948 tmp
= gen_vfp_mrs();
3949 store_reg(s
, rn
, tmp
);
3954 tmp
= load_reg(s
, rd
);
3956 gen_mov_vreg_F0(0, rm
* 2);
3957 tmp
= load_reg(s
, rn
);
3959 gen_mov_vreg_F0(0, rm
* 2 + 1);
3961 tmp
= load_reg(s
, rd
);
3963 gen_mov_vreg_F0(0, rm
);
3964 tmp
= load_reg(s
, rn
);
3966 gen_mov_vreg_F0(0, rm
+ 1);
3971 rn
= (insn
>> 16) & 0xf;
3973 VFP_DREG_D(rd
, insn
);
3975 rd
= VFP_SREG_D(insn
);
3976 if ((insn
& 0x01200000) == 0x01000000) {
3977 /* Single load/store */
3978 offset
= (insn
& 0xff) << 2;
3979 if ((insn
& (1 << 23)) == 0)
3981 if (s
->thumb
&& rn
== 15) {
3982 /* This is actually UNPREDICTABLE */
3983 addr
= tcg_temp_new_i32();
3984 tcg_gen_movi_i32(addr
, s
->pc
& ~2);
3986 addr
= load_reg(s
, rn
);
3988 tcg_gen_addi_i32(addr
, addr
, offset
);
3989 if (insn
& (1 << 20)) {
3990 gen_vfp_ld(s
, dp
, addr
);
3991 gen_mov_vreg_F0(dp
, rd
);
3993 gen_mov_F0_vreg(dp
, rd
);
3994 gen_vfp_st(s
, dp
, addr
);
3996 tcg_temp_free_i32(addr
);
3998 /* load/store multiple */
3999 int w
= insn
& (1 << 21);
4001 n
= (insn
>> 1) & 0x7f;
4005 if (w
&& !(((insn
>> 23) ^ (insn
>> 24)) & 1)) {
4006 /* P == U , W == 1 => UNDEF */
4009 if (n
== 0 || (rd
+ n
) > 32 || (dp
&& n
> 16)) {
4010 /* UNPREDICTABLE cases for bad immediates: we choose to
4011 * UNDEF to avoid generating huge numbers of TCG ops
4015 if (rn
== 15 && w
) {
4016 /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
4020 if (s
->thumb
&& rn
== 15) {
4021 /* This is actually UNPREDICTABLE */
4022 addr
= tcg_temp_new_i32();
4023 tcg_gen_movi_i32(addr
, s
->pc
& ~2);
4025 addr
= load_reg(s
, rn
);
4027 if (insn
& (1 << 24)) /* pre-decrement */
4028 tcg_gen_addi_i32(addr
, addr
, -((insn
& 0xff) << 2));
4034 for (i
= 0; i
< n
; i
++) {
4035 if (insn
& ARM_CP_RW_BIT
) {
4037 gen_vfp_ld(s
, dp
, addr
);
4038 gen_mov_vreg_F0(dp
, rd
+ i
);
4041 gen_mov_F0_vreg(dp
, rd
+ i
);
4042 gen_vfp_st(s
, dp
, addr
);
4044 tcg_gen_addi_i32(addr
, addr
, offset
);
4048 if (insn
& (1 << 24))
4049 offset
= -offset
* n
;
4050 else if (dp
&& (insn
& 1))
4056 tcg_gen_addi_i32(addr
, addr
, offset
);
4057 store_reg(s
, rn
, addr
);
4059 tcg_temp_free_i32(addr
);
4065 /* Should never happen. */
4071 static inline bool use_goto_tb(DisasContext
*s
, target_ulong dest
)
4073 #ifndef CONFIG_USER_ONLY
4074 return (s
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
4075 ((s
->pc
- 1) & TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
4081 static inline void gen_goto_tb(DisasContext
*s
, int n
, target_ulong dest
)
4083 if (use_goto_tb(s
, dest
)) {
4085 gen_set_pc_im(s
, dest
);
4086 tcg_gen_exit_tb((uintptr_t)s
->tb
+ n
);
4088 gen_set_pc_im(s
, dest
);
4093 static inline void gen_jmp (DisasContext
*s
, uint32_t dest
)
4095 if (unlikely(s
->singlestep_enabled
|| s
->ss_active
)) {
4096 /* An indirect jump so that we still trigger the debug exception. */
4101 gen_goto_tb(s
, 0, dest
);
4102 s
->is_jmp
= DISAS_TB_JUMP
;
4106 static inline void gen_mulxy(TCGv_i32 t0
, TCGv_i32 t1
, int x
, int y
)
4109 tcg_gen_sari_i32(t0
, t0
, 16);
4113 tcg_gen_sari_i32(t1
, t1
, 16);
4116 tcg_gen_mul_i32(t0
, t0
, t1
);
4119 /* Return the mask of PSR bits set by a MSR instruction. */
4120 static uint32_t msr_mask(DisasContext
*s
, int flags
, int spsr
)
4125 if (flags
& (1 << 0))
4127 if (flags
& (1 << 1))
4129 if (flags
& (1 << 2))
4131 if (flags
& (1 << 3))
4134 /* Mask out undefined bits. */
4135 mask
&= ~CPSR_RESERVED
;
4136 if (!arm_dc_feature(s
, ARM_FEATURE_V4T
)) {
4139 if (!arm_dc_feature(s
, ARM_FEATURE_V5
)) {
4140 mask
&= ~CPSR_Q
; /* V5TE in reality*/
4142 if (!arm_dc_feature(s
, ARM_FEATURE_V6
)) {
4143 mask
&= ~(CPSR_E
| CPSR_GE
);
4145 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB2
)) {
4148 /* Mask out execution state and reserved bits. */
4150 mask
&= ~(CPSR_EXEC
| CPSR_RESERVED
);
4152 /* Mask out privileged bits. */
4158 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
4159 static int gen_set_psr(DisasContext
*s
, uint32_t mask
, int spsr
, TCGv_i32 t0
)
4163 /* ??? This is also undefined in system mode. */
4167 tmp
= load_cpu_field(spsr
);
4168 tcg_gen_andi_i32(tmp
, tmp
, ~mask
);
4169 tcg_gen_andi_i32(t0
, t0
, mask
);
4170 tcg_gen_or_i32(tmp
, tmp
, t0
);
4171 store_cpu_field(tmp
, spsr
);
4173 gen_set_cpsr(t0
, mask
);
4175 tcg_temp_free_i32(t0
);
4180 /* Returns nonzero if access to the PSR is not permitted. */
4181 static int gen_set_psr_im(DisasContext
*s
, uint32_t mask
, int spsr
, uint32_t val
)
4184 tmp
= tcg_temp_new_i32();
4185 tcg_gen_movi_i32(tmp
, val
);
4186 return gen_set_psr(s
, mask
, spsr
, tmp
);
4189 static bool msr_banked_access_decode(DisasContext
*s
, int r
, int sysm
, int rn
,
4190 int *tgtmode
, int *regno
)
4192 /* Decode the r and sysm fields of MSR/MRS banked accesses into
4193 * the target mode and register number, and identify the various
4194 * unpredictable cases.
4195 * MSR (banked) and MRS (banked) are CONSTRAINED UNPREDICTABLE if:
4196 * + executed in user mode
4197 * + using R15 as the src/dest register
4198 * + accessing an unimplemented register
4199 * + accessing a register that's inaccessible at current PL/security state*
4200 * + accessing a register that you could access with a different insn
4201 * We choose to UNDEF in all these cases.
4202 * Since we don't know which of the various AArch32 modes we are in
4203 * we have to defer some checks to runtime.
4204 * Accesses to Monitor mode registers from Secure EL1 (which implies
4205 * that EL3 is AArch64) must trap to EL3.
4207 * If the access checks fail this function will emit code to take
4208 * an exception and return false. Otherwise it will return true,
4209 * and set *tgtmode and *regno appropriately.
4211 int exc_target
= default_exception_el(s
);
4213 /* These instructions are present only in ARMv8, or in ARMv7 with the
4214 * Virtualization Extensions.
4216 if (!arm_dc_feature(s
, ARM_FEATURE_V8
) &&
4217 !arm_dc_feature(s
, ARM_FEATURE_EL2
)) {
4221 if (IS_USER(s
) || rn
== 15) {
4225 /* The table in the v8 ARM ARM section F5.2.3 describes the encoding
4226 * of registers into (r, sysm).
4229 /* SPSRs for other modes */
4231 case 0xe: /* SPSR_fiq */
4232 *tgtmode
= ARM_CPU_MODE_FIQ
;
4234 case 0x10: /* SPSR_irq */
4235 *tgtmode
= ARM_CPU_MODE_IRQ
;
4237 case 0x12: /* SPSR_svc */
4238 *tgtmode
= ARM_CPU_MODE_SVC
;
4240 case 0x14: /* SPSR_abt */
4241 *tgtmode
= ARM_CPU_MODE_ABT
;
4243 case 0x16: /* SPSR_und */
4244 *tgtmode
= ARM_CPU_MODE_UND
;
4246 case 0x1c: /* SPSR_mon */
4247 *tgtmode
= ARM_CPU_MODE_MON
;
4249 case 0x1e: /* SPSR_hyp */
4250 *tgtmode
= ARM_CPU_MODE_HYP
;
4252 default: /* unallocated */
4255 /* We arbitrarily assign SPSR a register number of 16. */
4258 /* general purpose registers for other modes */
4260 case 0x0 ... 0x6: /* 0b00xxx : r8_usr ... r14_usr */
4261 *tgtmode
= ARM_CPU_MODE_USR
;
4264 case 0x8 ... 0xe: /* 0b01xxx : r8_fiq ... r14_fiq */
4265 *tgtmode
= ARM_CPU_MODE_FIQ
;
4268 case 0x10 ... 0x11: /* 0b1000x : r14_irq, r13_irq */
4269 *tgtmode
= ARM_CPU_MODE_IRQ
;
4270 *regno
= sysm
& 1 ? 13 : 14;
4272 case 0x12 ... 0x13: /* 0b1001x : r14_svc, r13_svc */
4273 *tgtmode
= ARM_CPU_MODE_SVC
;
4274 *regno
= sysm
& 1 ? 13 : 14;
4276 case 0x14 ... 0x15: /* 0b1010x : r14_abt, r13_abt */
4277 *tgtmode
= ARM_CPU_MODE_ABT
;
4278 *regno
= sysm
& 1 ? 13 : 14;
4280 case 0x16 ... 0x17: /* 0b1011x : r14_und, r13_und */
4281 *tgtmode
= ARM_CPU_MODE_UND
;
4282 *regno
= sysm
& 1 ? 13 : 14;
4284 case 0x1c ... 0x1d: /* 0b1110x : r14_mon, r13_mon */
4285 *tgtmode
= ARM_CPU_MODE_MON
;
4286 *regno
= sysm
& 1 ? 13 : 14;
4288 case 0x1e ... 0x1f: /* 0b1111x : elr_hyp, r13_hyp */
4289 *tgtmode
= ARM_CPU_MODE_HYP
;
4290 /* Arbitrarily pick 17 for ELR_Hyp (which is not a banked LR!) */
4291 *regno
= sysm
& 1 ? 13 : 17;
4293 default: /* unallocated */
4298 /* Catch the 'accessing inaccessible register' cases we can detect
4299 * at translate time.
4302 case ARM_CPU_MODE_MON
:
4303 if (!arm_dc_feature(s
, ARM_FEATURE_EL3
) || s
->ns
) {
4306 if (s
->current_el
== 1) {
4307 /* If we're in Secure EL1 (which implies that EL3 is AArch64)
4308 * then accesses to Mon registers trap to EL3
4314 case ARM_CPU_MODE_HYP
:
4315 /* Note that we can forbid accesses from EL2 here because they
4316 * must be from Hyp mode itself
4318 if (!arm_dc_feature(s
, ARM_FEATURE_EL2
) || s
->current_el
< 3) {
4329 /* If we get here then some access check did not pass */
4330 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(), exc_target
);
4334 static void gen_msr_banked(DisasContext
*s
, int r
, int sysm
, int rn
)
4336 TCGv_i32 tcg_reg
, tcg_tgtmode
, tcg_regno
;
4337 int tgtmode
= 0, regno
= 0;
4339 if (!msr_banked_access_decode(s
, r
, sysm
, rn
, &tgtmode
, ®no
)) {
4343 /* Sync state because msr_banked() can raise exceptions */
4344 gen_set_condexec(s
);
4345 gen_set_pc_im(s
, s
->pc
- 4);
4346 tcg_reg
= load_reg(s
, rn
);
4347 tcg_tgtmode
= tcg_const_i32(tgtmode
);
4348 tcg_regno
= tcg_const_i32(regno
);
4349 gen_helper_msr_banked(cpu_env
, tcg_reg
, tcg_tgtmode
, tcg_regno
);
4350 tcg_temp_free_i32(tcg_tgtmode
);
4351 tcg_temp_free_i32(tcg_regno
);
4352 tcg_temp_free_i32(tcg_reg
);
4353 s
->is_jmp
= DISAS_UPDATE
;
4356 static void gen_mrs_banked(DisasContext
*s
, int r
, int sysm
, int rn
)
4358 TCGv_i32 tcg_reg
, tcg_tgtmode
, tcg_regno
;
4359 int tgtmode
= 0, regno
= 0;
4361 if (!msr_banked_access_decode(s
, r
, sysm
, rn
, &tgtmode
, ®no
)) {
4365 /* Sync state because mrs_banked() can raise exceptions */
4366 gen_set_condexec(s
);
4367 gen_set_pc_im(s
, s
->pc
- 4);
4368 tcg_reg
= tcg_temp_new_i32();
4369 tcg_tgtmode
= tcg_const_i32(tgtmode
);
4370 tcg_regno
= tcg_const_i32(regno
);
4371 gen_helper_mrs_banked(tcg_reg
, cpu_env
, tcg_tgtmode
, tcg_regno
);
4372 tcg_temp_free_i32(tcg_tgtmode
);
4373 tcg_temp_free_i32(tcg_regno
);
4374 store_reg(s
, rn
, tcg_reg
);
4375 s
->is_jmp
= DISAS_UPDATE
;
4378 /* Store value to PC as for an exception return (ie don't
4379 * mask bits). The subsequent call to gen_helper_cpsr_write_eret()
4380 * will do the masking based on the new value of the Thumb bit.
4382 static void store_pc_exc_ret(DisasContext
*s
, TCGv_i32 pc
)
4384 tcg_gen_mov_i32(cpu_R
[15], pc
);
4385 tcg_temp_free_i32(pc
);
4388 /* Generate a v6 exception return. Marks both values as dead. */
4389 static void gen_rfe(DisasContext
*s
, TCGv_i32 pc
, TCGv_i32 cpsr
)
4391 store_pc_exc_ret(s
, pc
);
4392 /* The cpsr_write_eret helper will mask the low bits of PC
4393 * appropriately depending on the new Thumb bit, so it must
4394 * be called after storing the new PC.
4396 gen_helper_cpsr_write_eret(cpu_env
, cpsr
);
4397 tcg_temp_free_i32(cpsr
);
4398 s
->is_jmp
= DISAS_JUMP
;
4401 /* Generate an old-style exception return. Marks pc as dead. */
4402 static void gen_exception_return(DisasContext
*s
, TCGv_i32 pc
)
4404 gen_rfe(s
, pc
, load_cpu_field(spsr
));
4408 * For WFI we will halt the vCPU until an IRQ. For WFE and YIELD we
4409 * only call the helper when running single threaded TCG code to ensure
4410 * the next round-robin scheduled vCPU gets a crack. In MTTCG mode we
4411 * just skip this instruction. Currently the SEV/SEVL instructions
4412 * which are *one* of many ways to wake the CPU from WFE are not
4413 * implemented so we can't sleep like WFI does.
4415 static void gen_nop_hint(DisasContext
*s
, int val
)
4419 if (!parallel_cpus
) {
4420 gen_set_pc_im(s
, s
->pc
);
4421 s
->is_jmp
= DISAS_YIELD
;
4425 gen_set_pc_im(s
, s
->pc
);
4426 s
->is_jmp
= DISAS_WFI
;
4429 if (!parallel_cpus
) {
4430 gen_set_pc_im(s
, s
->pc
);
4431 s
->is_jmp
= DISAS_WFE
;
4436 /* TODO: Implement SEV, SEVL and WFE. May help SMP performance. */
4442 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
4444 static inline void gen_neon_add(int size
, TCGv_i32 t0
, TCGv_i32 t1
)
4447 case 0: gen_helper_neon_add_u8(t0
, t0
, t1
); break;
4448 case 1: gen_helper_neon_add_u16(t0
, t0
, t1
); break;
4449 case 2: tcg_gen_add_i32(t0
, t0
, t1
); break;
4454 static inline void gen_neon_rsb(int size
, TCGv_i32 t0
, TCGv_i32 t1
)
4457 case 0: gen_helper_neon_sub_u8(t0
, t1
, t0
); break;
4458 case 1: gen_helper_neon_sub_u16(t0
, t1
, t0
); break;
4459 case 2: tcg_gen_sub_i32(t0
, t1
, t0
); break;
4464 /* 32-bit pairwise ops end up the same as the elementwise versions. */
4465 #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
4466 #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
4467 #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
4468 #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
4470 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
4471 switch ((size << 1) | u) { \
4473 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
4476 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
4479 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
4482 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
4485 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
4488 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
4490 default: return 1; \
4493 #define GEN_NEON_INTEGER_OP(name) do { \
4494 switch ((size << 1) | u) { \
4496 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
4499 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
4502 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
4505 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
4508 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
4511 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
4513 default: return 1; \
4516 static TCGv_i32
neon_load_scratch(int scratch
)
4518 TCGv_i32 tmp
= tcg_temp_new_i32();
4519 tcg_gen_ld_i32(tmp
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
4523 static void neon_store_scratch(int scratch
, TCGv_i32 var
)
4525 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
4526 tcg_temp_free_i32(var
);
4529 static inline TCGv_i32
neon_get_scalar(int size
, int reg
)
4533 tmp
= neon_load_reg(reg
& 7, reg
>> 4);
4535 gen_neon_dup_high16(tmp
);
4537 gen_neon_dup_low16(tmp
);
4540 tmp
= neon_load_reg(reg
& 15, reg
>> 4);
4545 static int gen_neon_unzip(int rd
, int rm
, int size
, int q
)
4548 if (!q
&& size
== 2) {
4551 tmp
= tcg_const_i32(rd
);
4552 tmp2
= tcg_const_i32(rm
);
4556 gen_helper_neon_qunzip8(cpu_env
, tmp
, tmp2
);
4559 gen_helper_neon_qunzip16(cpu_env
, tmp
, tmp2
);
4562 gen_helper_neon_qunzip32(cpu_env
, tmp
, tmp2
);
4570 gen_helper_neon_unzip8(cpu_env
, tmp
, tmp2
);
4573 gen_helper_neon_unzip16(cpu_env
, tmp
, tmp2
);
4579 tcg_temp_free_i32(tmp
);
4580 tcg_temp_free_i32(tmp2
);
4584 static int gen_neon_zip(int rd
, int rm
, int size
, int q
)
4587 if (!q
&& size
== 2) {
4590 tmp
= tcg_const_i32(rd
);
4591 tmp2
= tcg_const_i32(rm
);
4595 gen_helper_neon_qzip8(cpu_env
, tmp
, tmp2
);
4598 gen_helper_neon_qzip16(cpu_env
, tmp
, tmp2
);
4601 gen_helper_neon_qzip32(cpu_env
, tmp
, tmp2
);
4609 gen_helper_neon_zip8(cpu_env
, tmp
, tmp2
);
4612 gen_helper_neon_zip16(cpu_env
, tmp
, tmp2
);
4618 tcg_temp_free_i32(tmp
);
4619 tcg_temp_free_i32(tmp2
);
4623 static void gen_neon_trn_u8(TCGv_i32 t0
, TCGv_i32 t1
)
4627 rd
= tcg_temp_new_i32();
4628 tmp
= tcg_temp_new_i32();
4630 tcg_gen_shli_i32(rd
, t0
, 8);
4631 tcg_gen_andi_i32(rd
, rd
, 0xff00ff00);
4632 tcg_gen_andi_i32(tmp
, t1
, 0x00ff00ff);
4633 tcg_gen_or_i32(rd
, rd
, tmp
);
4635 tcg_gen_shri_i32(t1
, t1
, 8);
4636 tcg_gen_andi_i32(t1
, t1
, 0x00ff00ff);
4637 tcg_gen_andi_i32(tmp
, t0
, 0xff00ff00);
4638 tcg_gen_or_i32(t1
, t1
, tmp
);
4639 tcg_gen_mov_i32(t0
, rd
);
4641 tcg_temp_free_i32(tmp
);
4642 tcg_temp_free_i32(rd
);
4645 static void gen_neon_trn_u16(TCGv_i32 t0
, TCGv_i32 t1
)
4649 rd
= tcg_temp_new_i32();
4650 tmp
= tcg_temp_new_i32();
4652 tcg_gen_shli_i32(rd
, t0
, 16);
4653 tcg_gen_andi_i32(tmp
, t1
, 0xffff);
4654 tcg_gen_or_i32(rd
, rd
, tmp
);
4655 tcg_gen_shri_i32(t1
, t1
, 16);
4656 tcg_gen_andi_i32(tmp
, t0
, 0xffff0000);
4657 tcg_gen_or_i32(t1
, t1
, tmp
);
4658 tcg_gen_mov_i32(t0
, rd
);
4660 tcg_temp_free_i32(tmp
);
4661 tcg_temp_free_i32(rd
);
4669 } neon_ls_element_type
[11] = {
4683 /* Translate a NEON load/store element instruction. Return nonzero if the
4684 instruction is invalid. */
4685 static int disas_neon_ls_insn(DisasContext
*s
, uint32_t insn
)
4704 /* FIXME: this access check should not take precedence over UNDEF
4705 * for invalid encodings; we will generate incorrect syndrome information
4706 * for attempts to execute invalid vfp/neon encodings with FP disabled.
4708 if (s
->fp_excp_el
) {
4709 gen_exception_insn(s
, 4, EXCP_UDEF
,
4710 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
4714 if (!s
->vfp_enabled
)
4716 VFP_DREG_D(rd
, insn
);
4717 rn
= (insn
>> 16) & 0xf;
4719 load
= (insn
& (1 << 21)) != 0;
4720 if ((insn
& (1 << 23)) == 0) {
4721 /* Load store all elements. */
4722 op
= (insn
>> 8) & 0xf;
4723 size
= (insn
>> 6) & 3;
4726 /* Catch UNDEF cases for bad values of align field */
4729 if (((insn
>> 5) & 1) == 1) {
4734 if (((insn
>> 4) & 3) == 3) {
4741 nregs
= neon_ls_element_type
[op
].nregs
;
4742 interleave
= neon_ls_element_type
[op
].interleave
;
4743 spacing
= neon_ls_element_type
[op
].spacing
;
4744 if (size
== 3 && (interleave
| spacing
) != 1)
4746 addr
= tcg_temp_new_i32();
4747 load_reg_var(s
, addr
, rn
);
4748 stride
= (1 << size
) * interleave
;
4749 for (reg
= 0; reg
< nregs
; reg
++) {
4750 if (interleave
> 2 || (interleave
== 2 && nregs
== 2)) {
4751 load_reg_var(s
, addr
, rn
);
4752 tcg_gen_addi_i32(addr
, addr
, (1 << size
) * reg
);
4753 } else if (interleave
== 2 && nregs
== 4 && reg
== 2) {
4754 load_reg_var(s
, addr
, rn
);
4755 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
4758 tmp64
= tcg_temp_new_i64();
4760 gen_aa32_ld64(s
, tmp64
, addr
, get_mem_index(s
));
4761 neon_store_reg64(tmp64
, rd
);
4763 neon_load_reg64(tmp64
, rd
);
4764 gen_aa32_st64(s
, tmp64
, addr
, get_mem_index(s
));
4766 tcg_temp_free_i64(tmp64
);
4767 tcg_gen_addi_i32(addr
, addr
, stride
);
4769 for (pass
= 0; pass
< 2; pass
++) {
4772 tmp
= tcg_temp_new_i32();
4773 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
4774 neon_store_reg(rd
, pass
, tmp
);
4776 tmp
= neon_load_reg(rd
, pass
);
4777 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
4778 tcg_temp_free_i32(tmp
);
4780 tcg_gen_addi_i32(addr
, addr
, stride
);
4781 } else if (size
== 1) {
4783 tmp
= tcg_temp_new_i32();
4784 gen_aa32_ld16u(s
, tmp
, addr
, get_mem_index(s
));
4785 tcg_gen_addi_i32(addr
, addr
, stride
);
4786 tmp2
= tcg_temp_new_i32();
4787 gen_aa32_ld16u(s
, tmp2
, addr
, get_mem_index(s
));
4788 tcg_gen_addi_i32(addr
, addr
, stride
);
4789 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
4790 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
4791 tcg_temp_free_i32(tmp2
);
4792 neon_store_reg(rd
, pass
, tmp
);
4794 tmp
= neon_load_reg(rd
, pass
);
4795 tmp2
= tcg_temp_new_i32();
4796 tcg_gen_shri_i32(tmp2
, tmp
, 16);
4797 gen_aa32_st16(s
, tmp
, addr
, get_mem_index(s
));
4798 tcg_temp_free_i32(tmp
);
4799 tcg_gen_addi_i32(addr
, addr
, stride
);
4800 gen_aa32_st16(s
, tmp2
, addr
, get_mem_index(s
));
4801 tcg_temp_free_i32(tmp2
);
4802 tcg_gen_addi_i32(addr
, addr
, stride
);
4804 } else /* size == 0 */ {
4806 TCGV_UNUSED_I32(tmp2
);
4807 for (n
= 0; n
< 4; n
++) {
4808 tmp
= tcg_temp_new_i32();
4809 gen_aa32_ld8u(s
, tmp
, addr
, get_mem_index(s
));
4810 tcg_gen_addi_i32(addr
, addr
, stride
);
4814 tcg_gen_shli_i32(tmp
, tmp
, n
* 8);
4815 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
4816 tcg_temp_free_i32(tmp
);
4819 neon_store_reg(rd
, pass
, tmp2
);
4821 tmp2
= neon_load_reg(rd
, pass
);
4822 for (n
= 0; n
< 4; n
++) {
4823 tmp
= tcg_temp_new_i32();
4825 tcg_gen_mov_i32(tmp
, tmp2
);
4827 tcg_gen_shri_i32(tmp
, tmp2
, n
* 8);
4829 gen_aa32_st8(s
, tmp
, addr
, get_mem_index(s
));
4830 tcg_temp_free_i32(tmp
);
4831 tcg_gen_addi_i32(addr
, addr
, stride
);
4833 tcg_temp_free_i32(tmp2
);
4840 tcg_temp_free_i32(addr
);
4843 size
= (insn
>> 10) & 3;
4845 /* Load single element to all lanes. */
4846 int a
= (insn
>> 4) & 1;
4850 size
= (insn
>> 6) & 3;
4851 nregs
= ((insn
>> 8) & 3) + 1;
4854 if (nregs
!= 4 || a
== 0) {
4857 /* For VLD4 size==3 a == 1 means 32 bits at 16 byte alignment */
4860 if (nregs
== 1 && a
== 1 && size
== 0) {
4863 if (nregs
== 3 && a
== 1) {
4866 addr
= tcg_temp_new_i32();
4867 load_reg_var(s
, addr
, rn
);
4869 /* VLD1 to all lanes: bit 5 indicates how many Dregs to write */
4870 tmp
= gen_load_and_replicate(s
, addr
, size
);
4871 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 0));
4872 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 1));
4873 if (insn
& (1 << 5)) {
4874 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
+ 1, 0));
4875 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
+ 1, 1));
4877 tcg_temp_free_i32(tmp
);
4879 /* VLD2/3/4 to all lanes: bit 5 indicates register stride */
4880 stride
= (insn
& (1 << 5)) ? 2 : 1;
4881 for (reg
= 0; reg
< nregs
; reg
++) {
4882 tmp
= gen_load_and_replicate(s
, addr
, size
);
4883 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 0));
4884 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 1));
4885 tcg_temp_free_i32(tmp
);
4886 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
4890 tcg_temp_free_i32(addr
);
4891 stride
= (1 << size
) * nregs
;
4893 /* Single element. */
4894 int idx
= (insn
>> 4) & 0xf;
4895 pass
= (insn
>> 7) & 1;
4898 shift
= ((insn
>> 5) & 3) * 8;
4902 shift
= ((insn
>> 6) & 1) * 16;
4903 stride
= (insn
& (1 << 5)) ? 2 : 1;
4907 stride
= (insn
& (1 << 6)) ? 2 : 1;
4912 nregs
= ((insn
>> 8) & 3) + 1;
4913 /* Catch the UNDEF cases. This is unavoidably a bit messy. */
4916 if (((idx
& (1 << size
)) != 0) ||
4917 (size
== 2 && ((idx
& 3) == 1 || (idx
& 3) == 2))) {
4922 if ((idx
& 1) != 0) {
4927 if (size
== 2 && (idx
& 2) != 0) {
4932 if ((size
== 2) && ((idx
& 3) == 3)) {
4939 if ((rd
+ stride
* (nregs
- 1)) > 31) {
4940 /* Attempts to write off the end of the register file
4941 * are UNPREDICTABLE; we choose to UNDEF because otherwise
4942 * the neon_load_reg() would write off the end of the array.
4946 addr
= tcg_temp_new_i32();
4947 load_reg_var(s
, addr
, rn
);
4948 for (reg
= 0; reg
< nregs
; reg
++) {
4950 tmp
= tcg_temp_new_i32();
4953 gen_aa32_ld8u(s
, tmp
, addr
, get_mem_index(s
));
4956 gen_aa32_ld16u(s
, tmp
, addr
, get_mem_index(s
));
4959 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
4961 default: /* Avoid compiler warnings. */
4965 tmp2
= neon_load_reg(rd
, pass
);
4966 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
,
4967 shift
, size
? 16 : 8);
4968 tcg_temp_free_i32(tmp2
);
4970 neon_store_reg(rd
, pass
, tmp
);
4971 } else { /* Store */
4972 tmp
= neon_load_reg(rd
, pass
);
4974 tcg_gen_shri_i32(tmp
, tmp
, shift
);
4977 gen_aa32_st8(s
, tmp
, addr
, get_mem_index(s
));
4980 gen_aa32_st16(s
, tmp
, addr
, get_mem_index(s
));
4983 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
4986 tcg_temp_free_i32(tmp
);
4989 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
4991 tcg_temp_free_i32(addr
);
4992 stride
= nregs
* (1 << size
);
4998 base
= load_reg(s
, rn
);
5000 tcg_gen_addi_i32(base
, base
, stride
);
5003 index
= load_reg(s
, rm
);
5004 tcg_gen_add_i32(base
, base
, index
);
5005 tcg_temp_free_i32(index
);
5007 store_reg(s
, rn
, base
);
5012 /* Bitwise select. dest = c ? t : f. Clobbers T and F. */
5013 static void gen_neon_bsl(TCGv_i32 dest
, TCGv_i32 t
, TCGv_i32 f
, TCGv_i32 c
)
5015 tcg_gen_and_i32(t
, t
, c
);
5016 tcg_gen_andc_i32(f
, f
, c
);
5017 tcg_gen_or_i32(dest
, t
, f
);
5020 static inline void gen_neon_narrow(int size
, TCGv_i32 dest
, TCGv_i64 src
)
5023 case 0: gen_helper_neon_narrow_u8(dest
, src
); break;
5024 case 1: gen_helper_neon_narrow_u16(dest
, src
); break;
5025 case 2: tcg_gen_extrl_i64_i32(dest
, src
); break;
5030 static inline void gen_neon_narrow_sats(int size
, TCGv_i32 dest
, TCGv_i64 src
)
5033 case 0: gen_helper_neon_narrow_sat_s8(dest
, cpu_env
, src
); break;
5034 case 1: gen_helper_neon_narrow_sat_s16(dest
, cpu_env
, src
); break;
5035 case 2: gen_helper_neon_narrow_sat_s32(dest
, cpu_env
, src
); break;
5040 static inline void gen_neon_narrow_satu(int size
, TCGv_i32 dest
, TCGv_i64 src
)
5043 case 0: gen_helper_neon_narrow_sat_u8(dest
, cpu_env
, src
); break;
5044 case 1: gen_helper_neon_narrow_sat_u16(dest
, cpu_env
, src
); break;
5045 case 2: gen_helper_neon_narrow_sat_u32(dest
, cpu_env
, src
); break;
5050 static inline void gen_neon_unarrow_sats(int size
, TCGv_i32 dest
, TCGv_i64 src
)
5053 case 0: gen_helper_neon_unarrow_sat8(dest
, cpu_env
, src
); break;
5054 case 1: gen_helper_neon_unarrow_sat16(dest
, cpu_env
, src
); break;
5055 case 2: gen_helper_neon_unarrow_sat32(dest
, cpu_env
, src
); break;
5060 static inline void gen_neon_shift_narrow(int size
, TCGv_i32 var
, TCGv_i32 shift
,
5066 case 1: gen_helper_neon_rshl_u16(var
, var
, shift
); break;
5067 case 2: gen_helper_neon_rshl_u32(var
, var
, shift
); break;
5072 case 1: gen_helper_neon_rshl_s16(var
, var
, shift
); break;
5073 case 2: gen_helper_neon_rshl_s32(var
, var
, shift
); break;
5080 case 1: gen_helper_neon_shl_u16(var
, var
, shift
); break;
5081 case 2: gen_helper_neon_shl_u32(var
, var
, shift
); break;
5086 case 1: gen_helper_neon_shl_s16(var
, var
, shift
); break;
5087 case 2: gen_helper_neon_shl_s32(var
, var
, shift
); break;
5094 static inline void gen_neon_widen(TCGv_i64 dest
, TCGv_i32 src
, int size
, int u
)
5098 case 0: gen_helper_neon_widen_u8(dest
, src
); break;
5099 case 1: gen_helper_neon_widen_u16(dest
, src
); break;
5100 case 2: tcg_gen_extu_i32_i64(dest
, src
); break;
5105 case 0: gen_helper_neon_widen_s8(dest
, src
); break;
5106 case 1: gen_helper_neon_widen_s16(dest
, src
); break;
5107 case 2: tcg_gen_ext_i32_i64(dest
, src
); break;
5111 tcg_temp_free_i32(src
);
5114 static inline void gen_neon_addl(int size
)
5117 case 0: gen_helper_neon_addl_u16(CPU_V001
); break;
5118 case 1: gen_helper_neon_addl_u32(CPU_V001
); break;
5119 case 2: tcg_gen_add_i64(CPU_V001
); break;
5124 static inline void gen_neon_subl(int size
)
5127 case 0: gen_helper_neon_subl_u16(CPU_V001
); break;
5128 case 1: gen_helper_neon_subl_u32(CPU_V001
); break;
5129 case 2: tcg_gen_sub_i64(CPU_V001
); break;
5134 static inline void gen_neon_negl(TCGv_i64 var
, int size
)
5137 case 0: gen_helper_neon_negl_u16(var
, var
); break;
5138 case 1: gen_helper_neon_negl_u32(var
, var
); break;
5140 tcg_gen_neg_i64(var
, var
);
5146 static inline void gen_neon_addl_saturate(TCGv_i64 op0
, TCGv_i64 op1
, int size
)
5149 case 1: gen_helper_neon_addl_saturate_s32(op0
, cpu_env
, op0
, op1
); break;
5150 case 2: gen_helper_neon_addl_saturate_s64(op0
, cpu_env
, op0
, op1
); break;
5155 static inline void gen_neon_mull(TCGv_i64 dest
, TCGv_i32 a
, TCGv_i32 b
,
5160 switch ((size
<< 1) | u
) {
5161 case 0: gen_helper_neon_mull_s8(dest
, a
, b
); break;
5162 case 1: gen_helper_neon_mull_u8(dest
, a
, b
); break;
5163 case 2: gen_helper_neon_mull_s16(dest
, a
, b
); break;
5164 case 3: gen_helper_neon_mull_u16(dest
, a
, b
); break;
5166 tmp
= gen_muls_i64_i32(a
, b
);
5167 tcg_gen_mov_i64(dest
, tmp
);
5168 tcg_temp_free_i64(tmp
);
5171 tmp
= gen_mulu_i64_i32(a
, b
);
5172 tcg_gen_mov_i64(dest
, tmp
);
5173 tcg_temp_free_i64(tmp
);
5178 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
5179 Don't forget to clean them now. */
5181 tcg_temp_free_i32(a
);
5182 tcg_temp_free_i32(b
);
5186 static void gen_neon_narrow_op(int op
, int u
, int size
,
5187 TCGv_i32 dest
, TCGv_i64 src
)
5191 gen_neon_unarrow_sats(size
, dest
, src
);
5193 gen_neon_narrow(size
, dest
, src
);
5197 gen_neon_narrow_satu(size
, dest
, src
);
5199 gen_neon_narrow_sats(size
, dest
, src
);
5204 /* Symbolic constants for op fields for Neon 3-register same-length.
5205 * The values correspond to bits [11:8,4]; see the ARM ARM DDI0406B
5208 #define NEON_3R_VHADD 0
5209 #define NEON_3R_VQADD 1
5210 #define NEON_3R_VRHADD 2
5211 #define NEON_3R_LOGIC 3 /* VAND,VBIC,VORR,VMOV,VORN,VEOR,VBIF,VBIT,VBSL */
5212 #define NEON_3R_VHSUB 4
5213 #define NEON_3R_VQSUB 5
5214 #define NEON_3R_VCGT 6
5215 #define NEON_3R_VCGE 7
5216 #define NEON_3R_VSHL 8
5217 #define NEON_3R_VQSHL 9
5218 #define NEON_3R_VRSHL 10
5219 #define NEON_3R_VQRSHL 11
5220 #define NEON_3R_VMAX 12
5221 #define NEON_3R_VMIN 13
5222 #define NEON_3R_VABD 14
5223 #define NEON_3R_VABA 15
5224 #define NEON_3R_VADD_VSUB 16
5225 #define NEON_3R_VTST_VCEQ 17
5226 #define NEON_3R_VML 18 /* VMLA, VMLAL, VMLS, VMLSL */
5227 #define NEON_3R_VMUL 19
5228 #define NEON_3R_VPMAX 20
5229 #define NEON_3R_VPMIN 21
5230 #define NEON_3R_VQDMULH_VQRDMULH 22
5231 #define NEON_3R_VPADD 23
5232 #define NEON_3R_SHA 24 /* SHA1C,SHA1P,SHA1M,SHA1SU0,SHA256H{2},SHA256SU1 */
5233 #define NEON_3R_VFM 25 /* VFMA, VFMS : float fused multiply-add */
5234 #define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */
5235 #define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */
5236 #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */
5237 #define NEON_3R_FLOAT_ACMP 29 /* float VACGE, VACGT, VACLE, VACLT */
5238 #define NEON_3R_FLOAT_MINMAX 30 /* float VMIN, VMAX */
5239 #define NEON_3R_FLOAT_MISC 31 /* float VRECPS, VRSQRTS, VMAXNM/MINNM */
5241 static const uint8_t neon_3r_sizes
[] = {
5242 [NEON_3R_VHADD
] = 0x7,
5243 [NEON_3R_VQADD
] = 0xf,
5244 [NEON_3R_VRHADD
] = 0x7,
5245 [NEON_3R_LOGIC
] = 0xf, /* size field encodes op type */
5246 [NEON_3R_VHSUB
] = 0x7,
5247 [NEON_3R_VQSUB
] = 0xf,
5248 [NEON_3R_VCGT
] = 0x7,
5249 [NEON_3R_VCGE
] = 0x7,
5250 [NEON_3R_VSHL
] = 0xf,
5251 [NEON_3R_VQSHL
] = 0xf,
5252 [NEON_3R_VRSHL
] = 0xf,
5253 [NEON_3R_VQRSHL
] = 0xf,
5254 [NEON_3R_VMAX
] = 0x7,
5255 [NEON_3R_VMIN
] = 0x7,
5256 [NEON_3R_VABD
] = 0x7,
5257 [NEON_3R_VABA
] = 0x7,
5258 [NEON_3R_VADD_VSUB
] = 0xf,
5259 [NEON_3R_VTST_VCEQ
] = 0x7,
5260 [NEON_3R_VML
] = 0x7,
5261 [NEON_3R_VMUL
] = 0x7,
5262 [NEON_3R_VPMAX
] = 0x7,
5263 [NEON_3R_VPMIN
] = 0x7,
5264 [NEON_3R_VQDMULH_VQRDMULH
] = 0x6,
5265 [NEON_3R_VPADD
] = 0x7,
5266 [NEON_3R_SHA
] = 0xf, /* size field encodes op type */
5267 [NEON_3R_VFM
] = 0x5, /* size bit 1 encodes op */
5268 [NEON_3R_FLOAT_ARITH
] = 0x5, /* size bit 1 encodes op */
5269 [NEON_3R_FLOAT_MULTIPLY
] = 0x5, /* size bit 1 encodes op */
5270 [NEON_3R_FLOAT_CMP
] = 0x5, /* size bit 1 encodes op */
5271 [NEON_3R_FLOAT_ACMP
] = 0x5, /* size bit 1 encodes op */
5272 [NEON_3R_FLOAT_MINMAX
] = 0x5, /* size bit 1 encodes op */
5273 [NEON_3R_FLOAT_MISC
] = 0x5, /* size bit 1 encodes op */
5276 /* Symbolic constants for op fields for Neon 2-register miscellaneous.
5277 * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B
5280 #define NEON_2RM_VREV64 0
5281 #define NEON_2RM_VREV32 1
5282 #define NEON_2RM_VREV16 2
5283 #define NEON_2RM_VPADDL 4
5284 #define NEON_2RM_VPADDL_U 5
5285 #define NEON_2RM_AESE 6 /* Includes AESD */
5286 #define NEON_2RM_AESMC 7 /* Includes AESIMC */
5287 #define NEON_2RM_VCLS 8
5288 #define NEON_2RM_VCLZ 9
5289 #define NEON_2RM_VCNT 10
5290 #define NEON_2RM_VMVN 11
5291 #define NEON_2RM_VPADAL 12
5292 #define NEON_2RM_VPADAL_U 13
5293 #define NEON_2RM_VQABS 14
5294 #define NEON_2RM_VQNEG 15
5295 #define NEON_2RM_VCGT0 16
5296 #define NEON_2RM_VCGE0 17
5297 #define NEON_2RM_VCEQ0 18
5298 #define NEON_2RM_VCLE0 19
5299 #define NEON_2RM_VCLT0 20
5300 #define NEON_2RM_SHA1H 21
5301 #define NEON_2RM_VABS 22
5302 #define NEON_2RM_VNEG 23
5303 #define NEON_2RM_VCGT0_F 24
5304 #define NEON_2RM_VCGE0_F 25
5305 #define NEON_2RM_VCEQ0_F 26
5306 #define NEON_2RM_VCLE0_F 27
5307 #define NEON_2RM_VCLT0_F 28
5308 #define NEON_2RM_VABS_F 30
5309 #define NEON_2RM_VNEG_F 31
5310 #define NEON_2RM_VSWP 32
5311 #define NEON_2RM_VTRN 33
5312 #define NEON_2RM_VUZP 34
5313 #define NEON_2RM_VZIP 35
5314 #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
5315 #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
5316 #define NEON_2RM_VSHLL 38
5317 #define NEON_2RM_SHA1SU1 39 /* Includes SHA256SU0 */
5318 #define NEON_2RM_VRINTN 40
5319 #define NEON_2RM_VRINTX 41
5320 #define NEON_2RM_VRINTA 42
5321 #define NEON_2RM_VRINTZ 43
5322 #define NEON_2RM_VCVT_F16_F32 44
5323 #define NEON_2RM_VRINTM 45
5324 #define NEON_2RM_VCVT_F32_F16 46
5325 #define NEON_2RM_VRINTP 47
5326 #define NEON_2RM_VCVTAU 48
5327 #define NEON_2RM_VCVTAS 49
5328 #define NEON_2RM_VCVTNU 50
5329 #define NEON_2RM_VCVTNS 51
5330 #define NEON_2RM_VCVTPU 52
5331 #define NEON_2RM_VCVTPS 53
5332 #define NEON_2RM_VCVTMU 54
5333 #define NEON_2RM_VCVTMS 55
5334 #define NEON_2RM_VRECPE 56
5335 #define NEON_2RM_VRSQRTE 57
5336 #define NEON_2RM_VRECPE_F 58
5337 #define NEON_2RM_VRSQRTE_F 59
5338 #define NEON_2RM_VCVT_FS 60
5339 #define NEON_2RM_VCVT_FU 61
5340 #define NEON_2RM_VCVT_SF 62
5341 #define NEON_2RM_VCVT_UF 63
5343 static int neon_2rm_is_float_op(int op
)
5345 /* Return true if this neon 2reg-misc op is float-to-float */
5346 return (op
== NEON_2RM_VABS_F
|| op
== NEON_2RM_VNEG_F
||
5347 (op
>= NEON_2RM_VRINTN
&& op
<= NEON_2RM_VRINTZ
) ||
5348 op
== NEON_2RM_VRINTM
||
5349 (op
>= NEON_2RM_VRINTP
&& op
<= NEON_2RM_VCVTMS
) ||
5350 op
>= NEON_2RM_VRECPE_F
);
5353 static bool neon_2rm_is_v8_op(int op
)
5355 /* Return true if this neon 2reg-misc op is ARMv8 and up */
5357 case NEON_2RM_VRINTN
:
5358 case NEON_2RM_VRINTA
:
5359 case NEON_2RM_VRINTM
:
5360 case NEON_2RM_VRINTP
:
5361 case NEON_2RM_VRINTZ
:
5362 case NEON_2RM_VRINTX
:
5363 case NEON_2RM_VCVTAU
:
5364 case NEON_2RM_VCVTAS
:
5365 case NEON_2RM_VCVTNU
:
5366 case NEON_2RM_VCVTNS
:
5367 case NEON_2RM_VCVTPU
:
5368 case NEON_2RM_VCVTPS
:
5369 case NEON_2RM_VCVTMU
:
5370 case NEON_2RM_VCVTMS
:
5377 /* Each entry in this array has bit n set if the insn allows
5378 * size value n (otherwise it will UNDEF). Since unallocated
5379 * op values will have no bits set they always UNDEF.
5381 static const uint8_t neon_2rm_sizes
[] = {
5382 [NEON_2RM_VREV64
] = 0x7,
5383 [NEON_2RM_VREV32
] = 0x3,
5384 [NEON_2RM_VREV16
] = 0x1,
5385 [NEON_2RM_VPADDL
] = 0x7,
5386 [NEON_2RM_VPADDL_U
] = 0x7,
5387 [NEON_2RM_AESE
] = 0x1,
5388 [NEON_2RM_AESMC
] = 0x1,
5389 [NEON_2RM_VCLS
] = 0x7,
5390 [NEON_2RM_VCLZ
] = 0x7,
5391 [NEON_2RM_VCNT
] = 0x1,
5392 [NEON_2RM_VMVN
] = 0x1,
5393 [NEON_2RM_VPADAL
] = 0x7,
5394 [NEON_2RM_VPADAL_U
] = 0x7,
5395 [NEON_2RM_VQABS
] = 0x7,
5396 [NEON_2RM_VQNEG
] = 0x7,
5397 [NEON_2RM_VCGT0
] = 0x7,
5398 [NEON_2RM_VCGE0
] = 0x7,
5399 [NEON_2RM_VCEQ0
] = 0x7,
5400 [NEON_2RM_VCLE0
] = 0x7,
5401 [NEON_2RM_VCLT0
] = 0x7,
5402 [NEON_2RM_SHA1H
] = 0x4,
5403 [NEON_2RM_VABS
] = 0x7,
5404 [NEON_2RM_VNEG
] = 0x7,
5405 [NEON_2RM_VCGT0_F
] = 0x4,
5406 [NEON_2RM_VCGE0_F
] = 0x4,
5407 [NEON_2RM_VCEQ0_F
] = 0x4,
5408 [NEON_2RM_VCLE0_F
] = 0x4,
5409 [NEON_2RM_VCLT0_F
] = 0x4,
5410 [NEON_2RM_VABS_F
] = 0x4,
5411 [NEON_2RM_VNEG_F
] = 0x4,
5412 [NEON_2RM_VSWP
] = 0x1,
5413 [NEON_2RM_VTRN
] = 0x7,
5414 [NEON_2RM_VUZP
] = 0x7,
5415 [NEON_2RM_VZIP
] = 0x7,
5416 [NEON_2RM_VMOVN
] = 0x7,
5417 [NEON_2RM_VQMOVN
] = 0x7,
5418 [NEON_2RM_VSHLL
] = 0x7,
5419 [NEON_2RM_SHA1SU1
] = 0x4,
5420 [NEON_2RM_VRINTN
] = 0x4,
5421 [NEON_2RM_VRINTX
] = 0x4,
5422 [NEON_2RM_VRINTA
] = 0x4,
5423 [NEON_2RM_VRINTZ
] = 0x4,
5424 [NEON_2RM_VCVT_F16_F32
] = 0x2,
5425 [NEON_2RM_VRINTM
] = 0x4,
5426 [NEON_2RM_VCVT_F32_F16
] = 0x2,
5427 [NEON_2RM_VRINTP
] = 0x4,
5428 [NEON_2RM_VCVTAU
] = 0x4,
5429 [NEON_2RM_VCVTAS
] = 0x4,
5430 [NEON_2RM_VCVTNU
] = 0x4,
5431 [NEON_2RM_VCVTNS
] = 0x4,
5432 [NEON_2RM_VCVTPU
] = 0x4,
5433 [NEON_2RM_VCVTPS
] = 0x4,
5434 [NEON_2RM_VCVTMU
] = 0x4,
5435 [NEON_2RM_VCVTMS
] = 0x4,
5436 [NEON_2RM_VRECPE
] = 0x4,
5437 [NEON_2RM_VRSQRTE
] = 0x4,
5438 [NEON_2RM_VRECPE_F
] = 0x4,
5439 [NEON_2RM_VRSQRTE_F
] = 0x4,
5440 [NEON_2RM_VCVT_FS
] = 0x4,
5441 [NEON_2RM_VCVT_FU
] = 0x4,
5442 [NEON_2RM_VCVT_SF
] = 0x4,
5443 [NEON_2RM_VCVT_UF
] = 0x4,
5446 /* Translate a NEON data processing instruction. Return nonzero if the
5447 instruction is invalid.
5448 We process data in a mixture of 32-bit and 64-bit chunks.
5449 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
5451 static int disas_neon_data_insn(DisasContext
*s
, uint32_t insn
)
5463 TCGv_i32 tmp
, tmp2
, tmp3
, tmp4
, tmp5
;
5466 /* FIXME: this access check should not take precedence over UNDEF
5467 * for invalid encodings; we will generate incorrect syndrome information
5468 * for attempts to execute invalid vfp/neon encodings with FP disabled.
5470 if (s
->fp_excp_el
) {
5471 gen_exception_insn(s
, 4, EXCP_UDEF
,
5472 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
5476 if (!s
->vfp_enabled
)
5478 q
= (insn
& (1 << 6)) != 0;
5479 u
= (insn
>> 24) & 1;
5480 VFP_DREG_D(rd
, insn
);
5481 VFP_DREG_N(rn
, insn
);
5482 VFP_DREG_M(rm
, insn
);
5483 size
= (insn
>> 20) & 3;
5484 if ((insn
& (1 << 23)) == 0) {
5485 /* Three register same length. */
5486 op
= ((insn
>> 7) & 0x1e) | ((insn
>> 4) & 1);
5487 /* Catch invalid op and bad size combinations: UNDEF */
5488 if ((neon_3r_sizes
[op
] & (1 << size
)) == 0) {
5491 /* All insns of this form UNDEF for either this condition or the
5492 * superset of cases "Q==1"; we catch the latter later.
5494 if (q
&& ((rd
| rn
| rm
) & 1)) {
5498 * The SHA-1/SHA-256 3-register instructions require special treatment
5499 * here, as their size field is overloaded as an op type selector, and
5500 * they all consume their input in a single pass.
5502 if (op
== NEON_3R_SHA
) {
5506 if (!u
) { /* SHA-1 */
5507 if (!arm_dc_feature(s
, ARM_FEATURE_V8_SHA1
)) {
5510 tmp
= tcg_const_i32(rd
);
5511 tmp2
= tcg_const_i32(rn
);
5512 tmp3
= tcg_const_i32(rm
);
5513 tmp4
= tcg_const_i32(size
);
5514 gen_helper_crypto_sha1_3reg(cpu_env
, tmp
, tmp2
, tmp3
, tmp4
);
5515 tcg_temp_free_i32(tmp4
);
5516 } else { /* SHA-256 */
5517 if (!arm_dc_feature(s
, ARM_FEATURE_V8_SHA256
) || size
== 3) {
5520 tmp
= tcg_const_i32(rd
);
5521 tmp2
= tcg_const_i32(rn
);
5522 tmp3
= tcg_const_i32(rm
);
5525 gen_helper_crypto_sha256h(cpu_env
, tmp
, tmp2
, tmp3
);
5528 gen_helper_crypto_sha256h2(cpu_env
, tmp
, tmp2
, tmp3
);
5531 gen_helper_crypto_sha256su1(cpu_env
, tmp
, tmp2
, tmp3
);
5535 tcg_temp_free_i32(tmp
);
5536 tcg_temp_free_i32(tmp2
);
5537 tcg_temp_free_i32(tmp3
);
5540 if (size
== 3 && op
!= NEON_3R_LOGIC
) {
5541 /* 64-bit element instructions. */
5542 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
5543 neon_load_reg64(cpu_V0
, rn
+ pass
);
5544 neon_load_reg64(cpu_V1
, rm
+ pass
);
5548 gen_helper_neon_qadd_u64(cpu_V0
, cpu_env
,
5551 gen_helper_neon_qadd_s64(cpu_V0
, cpu_env
,
5557 gen_helper_neon_qsub_u64(cpu_V0
, cpu_env
,
5560 gen_helper_neon_qsub_s64(cpu_V0
, cpu_env
,
5566 gen_helper_neon_shl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
5568 gen_helper_neon_shl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
5573 gen_helper_neon_qshl_u64(cpu_V0
, cpu_env
,
5576 gen_helper_neon_qshl_s64(cpu_V0
, cpu_env
,
5582 gen_helper_neon_rshl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
5584 gen_helper_neon_rshl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
5587 case NEON_3R_VQRSHL
:
5589 gen_helper_neon_qrshl_u64(cpu_V0
, cpu_env
,
5592 gen_helper_neon_qrshl_s64(cpu_V0
, cpu_env
,
5596 case NEON_3R_VADD_VSUB
:
5598 tcg_gen_sub_i64(CPU_V001
);
5600 tcg_gen_add_i64(CPU_V001
);
5606 neon_store_reg64(cpu_V0
, rd
+ pass
);
5615 case NEON_3R_VQRSHL
:
5618 /* Shift instruction operands are reversed. */
5633 case NEON_3R_FLOAT_ARITH
:
5634 pairwise
= (u
&& size
< 2); /* if VPADD (float) */
5636 case NEON_3R_FLOAT_MINMAX
:
5637 pairwise
= u
; /* if VPMIN/VPMAX (float) */
5639 case NEON_3R_FLOAT_CMP
:
5641 /* no encoding for U=0 C=1x */
5645 case NEON_3R_FLOAT_ACMP
:
5650 case NEON_3R_FLOAT_MISC
:
5651 /* VMAXNM/VMINNM in ARMv8 */
5652 if (u
&& !arm_dc_feature(s
, ARM_FEATURE_V8
)) {
5657 if (u
&& (size
!= 0)) {
5658 /* UNDEF on invalid size for polynomial subcase */
5663 if (!arm_dc_feature(s
, ARM_FEATURE_VFP4
) || u
) {
5671 if (pairwise
&& q
) {
5672 /* All the pairwise insns UNDEF if Q is set */
5676 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5681 tmp
= neon_load_reg(rn
, 0);
5682 tmp2
= neon_load_reg(rn
, 1);
5684 tmp
= neon_load_reg(rm
, 0);
5685 tmp2
= neon_load_reg(rm
, 1);
5689 tmp
= neon_load_reg(rn
, pass
);
5690 tmp2
= neon_load_reg(rm
, pass
);
5694 GEN_NEON_INTEGER_OP(hadd
);
5697 GEN_NEON_INTEGER_OP_ENV(qadd
);
5699 case NEON_3R_VRHADD
:
5700 GEN_NEON_INTEGER_OP(rhadd
);
5702 case NEON_3R_LOGIC
: /* Logic ops. */
5703 switch ((u
<< 2) | size
) {
5705 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
5708 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
5711 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
5714 tcg_gen_orc_i32(tmp
, tmp
, tmp2
);
5717 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
5720 tmp3
= neon_load_reg(rd
, pass
);
5721 gen_neon_bsl(tmp
, tmp
, tmp2
, tmp3
);
5722 tcg_temp_free_i32(tmp3
);
5725 tmp3
= neon_load_reg(rd
, pass
);
5726 gen_neon_bsl(tmp
, tmp
, tmp3
, tmp2
);
5727 tcg_temp_free_i32(tmp3
);
5730 tmp3
= neon_load_reg(rd
, pass
);
5731 gen_neon_bsl(tmp
, tmp3
, tmp
, tmp2
);
5732 tcg_temp_free_i32(tmp3
);
5737 GEN_NEON_INTEGER_OP(hsub
);
5740 GEN_NEON_INTEGER_OP_ENV(qsub
);
5743 GEN_NEON_INTEGER_OP(cgt
);
5746 GEN_NEON_INTEGER_OP(cge
);
5749 GEN_NEON_INTEGER_OP(shl
);
5752 GEN_NEON_INTEGER_OP_ENV(qshl
);
5755 GEN_NEON_INTEGER_OP(rshl
);
5757 case NEON_3R_VQRSHL
:
5758 GEN_NEON_INTEGER_OP_ENV(qrshl
);
5761 GEN_NEON_INTEGER_OP(max
);
5764 GEN_NEON_INTEGER_OP(min
);
5767 GEN_NEON_INTEGER_OP(abd
);
5770 GEN_NEON_INTEGER_OP(abd
);
5771 tcg_temp_free_i32(tmp2
);
5772 tmp2
= neon_load_reg(rd
, pass
);
5773 gen_neon_add(size
, tmp
, tmp2
);
5775 case NEON_3R_VADD_VSUB
:
5776 if (!u
) { /* VADD */
5777 gen_neon_add(size
, tmp
, tmp2
);
5780 case 0: gen_helper_neon_sub_u8(tmp
, tmp
, tmp2
); break;
5781 case 1: gen_helper_neon_sub_u16(tmp
, tmp
, tmp2
); break;
5782 case 2: tcg_gen_sub_i32(tmp
, tmp
, tmp2
); break;
5787 case NEON_3R_VTST_VCEQ
:
5788 if (!u
) { /* VTST */
5790 case 0: gen_helper_neon_tst_u8(tmp
, tmp
, tmp2
); break;
5791 case 1: gen_helper_neon_tst_u16(tmp
, tmp
, tmp2
); break;
5792 case 2: gen_helper_neon_tst_u32(tmp
, tmp
, tmp2
); break;
5797 case 0: gen_helper_neon_ceq_u8(tmp
, tmp
, tmp2
); break;
5798 case 1: gen_helper_neon_ceq_u16(tmp
, tmp
, tmp2
); break;
5799 case 2: gen_helper_neon_ceq_u32(tmp
, tmp
, tmp2
); break;
5804 case NEON_3R_VML
: /* VMLA, VMLAL, VMLS,VMLSL */
5806 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
5807 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
5808 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
5811 tcg_temp_free_i32(tmp2
);
5812 tmp2
= neon_load_reg(rd
, pass
);
5814 gen_neon_rsb(size
, tmp
, tmp2
);
5816 gen_neon_add(size
, tmp
, tmp2
);
5820 if (u
) { /* polynomial */
5821 gen_helper_neon_mul_p8(tmp
, tmp
, tmp2
);
5822 } else { /* Integer */
5824 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
5825 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
5826 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
5832 GEN_NEON_INTEGER_OP(pmax
);
5835 GEN_NEON_INTEGER_OP(pmin
);
5837 case NEON_3R_VQDMULH_VQRDMULH
: /* Multiply high. */
5838 if (!u
) { /* VQDMULH */
5841 gen_helper_neon_qdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
5844 gen_helper_neon_qdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
5848 } else { /* VQRDMULH */
5851 gen_helper_neon_qrdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
5854 gen_helper_neon_qrdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
5862 case 0: gen_helper_neon_padd_u8(tmp
, tmp
, tmp2
); break;
5863 case 1: gen_helper_neon_padd_u16(tmp
, tmp
, tmp2
); break;
5864 case 2: tcg_gen_add_i32(tmp
, tmp
, tmp2
); break;
5868 case NEON_3R_FLOAT_ARITH
: /* Floating point arithmetic. */
5870 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5871 switch ((u
<< 2) | size
) {
5874 gen_helper_vfp_adds(tmp
, tmp
, tmp2
, fpstatus
);
5877 gen_helper_vfp_subs(tmp
, tmp
, tmp2
, fpstatus
);
5880 gen_helper_neon_abd_f32(tmp
, tmp
, tmp2
, fpstatus
);
5885 tcg_temp_free_ptr(fpstatus
);
5888 case NEON_3R_FLOAT_MULTIPLY
:
5890 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5891 gen_helper_vfp_muls(tmp
, tmp
, tmp2
, fpstatus
);
5893 tcg_temp_free_i32(tmp2
);
5894 tmp2
= neon_load_reg(rd
, pass
);
5896 gen_helper_vfp_adds(tmp
, tmp
, tmp2
, fpstatus
);
5898 gen_helper_vfp_subs(tmp
, tmp2
, tmp
, fpstatus
);
5901 tcg_temp_free_ptr(fpstatus
);
5904 case NEON_3R_FLOAT_CMP
:
5906 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5908 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
, fpstatus
);
5911 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
, fpstatus
);
5913 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
, fpstatus
);
5916 tcg_temp_free_ptr(fpstatus
);
5919 case NEON_3R_FLOAT_ACMP
:
5921 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5923 gen_helper_neon_acge_f32(tmp
, tmp
, tmp2
, fpstatus
);
5925 gen_helper_neon_acgt_f32(tmp
, tmp
, tmp2
, fpstatus
);
5927 tcg_temp_free_ptr(fpstatus
);
5930 case NEON_3R_FLOAT_MINMAX
:
5932 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5934 gen_helper_vfp_maxs(tmp
, tmp
, tmp2
, fpstatus
);
5936 gen_helper_vfp_mins(tmp
, tmp
, tmp2
, fpstatus
);
5938 tcg_temp_free_ptr(fpstatus
);
5941 case NEON_3R_FLOAT_MISC
:
5944 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5946 gen_helper_vfp_maxnums(tmp
, tmp
, tmp2
, fpstatus
);
5948 gen_helper_vfp_minnums(tmp
, tmp
, tmp2
, fpstatus
);
5950 tcg_temp_free_ptr(fpstatus
);
5953 gen_helper_recps_f32(tmp
, tmp
, tmp2
, cpu_env
);
5955 gen_helper_rsqrts_f32(tmp
, tmp
, tmp2
, cpu_env
);
5961 /* VFMA, VFMS: fused multiply-add */
5962 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5963 TCGv_i32 tmp3
= neon_load_reg(rd
, pass
);
5966 gen_helper_vfp_negs(tmp
, tmp
);
5968 gen_helper_vfp_muladds(tmp
, tmp
, tmp2
, tmp3
, fpstatus
);
5969 tcg_temp_free_i32(tmp3
);
5970 tcg_temp_free_ptr(fpstatus
);
5976 tcg_temp_free_i32(tmp2
);
5978 /* Save the result. For elementwise operations we can put it
5979 straight into the destination register. For pairwise operations
5980 we have to be careful to avoid clobbering the source operands. */
5981 if (pairwise
&& rd
== rm
) {
5982 neon_store_scratch(pass
, tmp
);
5984 neon_store_reg(rd
, pass
, tmp
);
5988 if (pairwise
&& rd
== rm
) {
5989 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5990 tmp
= neon_load_scratch(pass
);
5991 neon_store_reg(rd
, pass
, tmp
);
5994 /* End of 3 register same size operations. */
5995 } else if (insn
& (1 << 4)) {
5996 if ((insn
& 0x00380080) != 0) {
5997 /* Two registers and shift. */
5998 op
= (insn
>> 8) & 0xf;
5999 if (insn
& (1 << 7)) {
6007 while ((insn
& (1 << (size
+ 19))) == 0)
6010 shift
= (insn
>> 16) & ((1 << (3 + size
)) - 1);
6011 /* To avoid excessive duplication of ops we implement shift
6012 by immediate using the variable shift operations. */
6014 /* Shift by immediate:
6015 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
6016 if (q
&& ((rd
| rm
) & 1)) {
6019 if (!u
&& (op
== 4 || op
== 6)) {
6022 /* Right shifts are encoded as N - shift, where N is the
6023 element size in bits. */
6025 shift
= shift
- (1 << (size
+ 3));
6033 imm
= (uint8_t) shift
;
6038 imm
= (uint16_t) shift
;
6049 for (pass
= 0; pass
< count
; pass
++) {
6051 neon_load_reg64(cpu_V0
, rm
+ pass
);
6052 tcg_gen_movi_i64(cpu_V1
, imm
);
6057 gen_helper_neon_shl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
6059 gen_helper_neon_shl_s64(cpu_V0
, cpu_V0
, cpu_V1
);
6064 gen_helper_neon_rshl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
6066 gen_helper_neon_rshl_s64(cpu_V0
, cpu_V0
, cpu_V1
);
6069 case 5: /* VSHL, VSLI */
6070 gen_helper_neon_shl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
6072 case 6: /* VQSHLU */
6073 gen_helper_neon_qshlu_s64(cpu_V0
, cpu_env
,
6078 gen_helper_neon_qshl_u64(cpu_V0
, cpu_env
,
6081 gen_helper_neon_qshl_s64(cpu_V0
, cpu_env
,
6086 if (op
== 1 || op
== 3) {
6088 neon_load_reg64(cpu_V1
, rd
+ pass
);
6089 tcg_gen_add_i64(cpu_V0
, cpu_V0
, cpu_V1
);
6090 } else if (op
== 4 || (op
== 5 && u
)) {
6092 neon_load_reg64(cpu_V1
, rd
+ pass
);
6094 if (shift
< -63 || shift
> 63) {
6098 mask
= 0xffffffffffffffffull
>> -shift
;
6100 mask
= 0xffffffffffffffffull
<< shift
;
6103 tcg_gen_andi_i64(cpu_V1
, cpu_V1
, ~mask
);
6104 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
6106 neon_store_reg64(cpu_V0
, rd
+ pass
);
6107 } else { /* size < 3 */
6108 /* Operands in T0 and T1. */
6109 tmp
= neon_load_reg(rm
, pass
);
6110 tmp2
= tcg_temp_new_i32();
6111 tcg_gen_movi_i32(tmp2
, imm
);
6115 GEN_NEON_INTEGER_OP(shl
);
6119 GEN_NEON_INTEGER_OP(rshl
);
6122 case 5: /* VSHL, VSLI */
6124 case 0: gen_helper_neon_shl_u8(tmp
, tmp
, tmp2
); break;
6125 case 1: gen_helper_neon_shl_u16(tmp
, tmp
, tmp2
); break;
6126 case 2: gen_helper_neon_shl_u32(tmp
, tmp
, tmp2
); break;
6130 case 6: /* VQSHLU */
6133 gen_helper_neon_qshlu_s8(tmp
, cpu_env
,
6137 gen_helper_neon_qshlu_s16(tmp
, cpu_env
,
6141 gen_helper_neon_qshlu_s32(tmp
, cpu_env
,
6149 GEN_NEON_INTEGER_OP_ENV(qshl
);
6152 tcg_temp_free_i32(tmp2
);
6154 if (op
== 1 || op
== 3) {
6156 tmp2
= neon_load_reg(rd
, pass
);
6157 gen_neon_add(size
, tmp
, tmp2
);
6158 tcg_temp_free_i32(tmp2
);
6159 } else if (op
== 4 || (op
== 5 && u
)) {
6164 mask
= 0xff >> -shift
;
6166 mask
= (uint8_t)(0xff << shift
);
6172 mask
= 0xffff >> -shift
;
6174 mask
= (uint16_t)(0xffff << shift
);
6178 if (shift
< -31 || shift
> 31) {
6182 mask
= 0xffffffffu
>> -shift
;
6184 mask
= 0xffffffffu
<< shift
;
6190 tmp2
= neon_load_reg(rd
, pass
);
6191 tcg_gen_andi_i32(tmp
, tmp
, mask
);
6192 tcg_gen_andi_i32(tmp2
, tmp2
, ~mask
);
6193 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
6194 tcg_temp_free_i32(tmp2
);
6196 neon_store_reg(rd
, pass
, tmp
);
6199 } else if (op
< 10) {
6200 /* Shift by immediate and narrow:
6201 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
6202 int input_unsigned
= (op
== 8) ? !u
: u
;
6206 shift
= shift
- (1 << (size
+ 3));
6209 tmp64
= tcg_const_i64(shift
);
6210 neon_load_reg64(cpu_V0
, rm
);
6211 neon_load_reg64(cpu_V1
, rm
+ 1);
6212 for (pass
= 0; pass
< 2; pass
++) {
6220 if (input_unsigned
) {
6221 gen_helper_neon_rshl_u64(cpu_V0
, in
, tmp64
);
6223 gen_helper_neon_rshl_s64(cpu_V0
, in
, tmp64
);
6226 if (input_unsigned
) {
6227 gen_helper_neon_shl_u64(cpu_V0
, in
, tmp64
);
6229 gen_helper_neon_shl_s64(cpu_V0
, in
, tmp64
);
6232 tmp
= tcg_temp_new_i32();
6233 gen_neon_narrow_op(op
== 8, u
, size
- 1, tmp
, cpu_V0
);
6234 neon_store_reg(rd
, pass
, tmp
);
6236 tcg_temp_free_i64(tmp64
);
6239 imm
= (uint16_t)shift
;
6243 imm
= (uint32_t)shift
;
6245 tmp2
= tcg_const_i32(imm
);
6246 tmp4
= neon_load_reg(rm
+ 1, 0);
6247 tmp5
= neon_load_reg(rm
+ 1, 1);
6248 for (pass
= 0; pass
< 2; pass
++) {
6250 tmp
= neon_load_reg(rm
, 0);
6254 gen_neon_shift_narrow(size
, tmp
, tmp2
, q
,
6257 tmp3
= neon_load_reg(rm
, 1);
6261 gen_neon_shift_narrow(size
, tmp3
, tmp2
, q
,
6263 tcg_gen_concat_i32_i64(cpu_V0
, tmp
, tmp3
);
6264 tcg_temp_free_i32(tmp
);
6265 tcg_temp_free_i32(tmp3
);
6266 tmp
= tcg_temp_new_i32();
6267 gen_neon_narrow_op(op
== 8, u
, size
- 1, tmp
, cpu_V0
);
6268 neon_store_reg(rd
, pass
, tmp
);
6270 tcg_temp_free_i32(tmp2
);
6272 } else if (op
== 10) {
6274 if (q
|| (rd
& 1)) {
6277 tmp
= neon_load_reg(rm
, 0);
6278 tmp2
= neon_load_reg(rm
, 1);
6279 for (pass
= 0; pass
< 2; pass
++) {
6283 gen_neon_widen(cpu_V0
, tmp
, size
, u
);
6286 /* The shift is less than the width of the source
6287 type, so we can just shift the whole register. */
6288 tcg_gen_shli_i64(cpu_V0
, cpu_V0
, shift
);
6289 /* Widen the result of shift: we need to clear
6290 * the potential overflow bits resulting from
6291 * left bits of the narrow input appearing as
6292 * right bits of left the neighbour narrow
6294 if (size
< 2 || !u
) {
6297 imm
= (0xffu
>> (8 - shift
));
6299 } else if (size
== 1) {
6300 imm
= 0xffff >> (16 - shift
);
6303 imm
= 0xffffffff >> (32 - shift
);
6306 imm64
= imm
| (((uint64_t)imm
) << 32);
6310 tcg_gen_andi_i64(cpu_V0
, cpu_V0
, ~imm64
);
6313 neon_store_reg64(cpu_V0
, rd
+ pass
);
6315 } else if (op
>= 14) {
6316 /* VCVT fixed-point. */
6317 if (!(insn
& (1 << 21)) || (q
&& ((rd
| rm
) & 1))) {
6320 /* We have already masked out the must-be-1 top bit of imm6,
6321 * hence this 32-shift where the ARM ARM has 64-imm6.
6324 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
6325 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, pass
));
6328 gen_vfp_ulto(0, shift
, 1);
6330 gen_vfp_slto(0, shift
, 1);
6333 gen_vfp_toul(0, shift
, 1);
6335 gen_vfp_tosl(0, shift
, 1);
6337 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, pass
));
6342 } else { /* (insn & 0x00380080) == 0 */
6344 if (q
&& (rd
& 1)) {
6348 op
= (insn
>> 8) & 0xf;
6349 /* One register and immediate. */
6350 imm
= (u
<< 7) | ((insn
>> 12) & 0x70) | (insn
& 0xf);
6351 invert
= (insn
& (1 << 5)) != 0;
6352 /* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
6353 * We choose to not special-case this and will behave as if a
6354 * valid constant encoding of 0 had been given.
6373 imm
= (imm
<< 8) | (imm
<< 24);
6376 imm
= (imm
<< 8) | 0xff;
6379 imm
= (imm
<< 16) | 0xffff;
6382 imm
|= (imm
<< 8) | (imm
<< 16) | (imm
<< 24);
6390 imm
= ((imm
& 0x80) << 24) | ((imm
& 0x3f) << 19)
6391 | ((imm
& 0x40) ? (0x1f << 25) : (1 << 30));
6397 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
6398 if (op
& 1 && op
< 12) {
6399 tmp
= neon_load_reg(rd
, pass
);
6401 /* The immediate value has already been inverted, so
6403 tcg_gen_andi_i32(tmp
, tmp
, imm
);
6405 tcg_gen_ori_i32(tmp
, tmp
, imm
);
6409 tmp
= tcg_temp_new_i32();
6410 if (op
== 14 && invert
) {
6414 for (n
= 0; n
< 4; n
++) {
6415 if (imm
& (1 << (n
+ (pass
& 1) * 4)))
6416 val
|= 0xff << (n
* 8);
6418 tcg_gen_movi_i32(tmp
, val
);
6420 tcg_gen_movi_i32(tmp
, imm
);
6423 neon_store_reg(rd
, pass
, tmp
);
6426 } else { /* (insn & 0x00800010 == 0x00800000) */
6428 op
= (insn
>> 8) & 0xf;
6429 if ((insn
& (1 << 6)) == 0) {
6430 /* Three registers of different lengths. */
6434 /* undefreq: bit 0 : UNDEF if size == 0
6435 * bit 1 : UNDEF if size == 1
6436 * bit 2 : UNDEF if size == 2
6437 * bit 3 : UNDEF if U == 1
6438 * Note that [2:0] set implies 'always UNDEF'
6441 /* prewiden, src1_wide, src2_wide, undefreq */
6442 static const int neon_3reg_wide
[16][4] = {
6443 {1, 0, 0, 0}, /* VADDL */
6444 {1, 1, 0, 0}, /* VADDW */
6445 {1, 0, 0, 0}, /* VSUBL */
6446 {1, 1, 0, 0}, /* VSUBW */
6447 {0, 1, 1, 0}, /* VADDHN */
6448 {0, 0, 0, 0}, /* VABAL */
6449 {0, 1, 1, 0}, /* VSUBHN */
6450 {0, 0, 0, 0}, /* VABDL */
6451 {0, 0, 0, 0}, /* VMLAL */
6452 {0, 0, 0, 9}, /* VQDMLAL */
6453 {0, 0, 0, 0}, /* VMLSL */
6454 {0, 0, 0, 9}, /* VQDMLSL */
6455 {0, 0, 0, 0}, /* Integer VMULL */
6456 {0, 0, 0, 1}, /* VQDMULL */
6457 {0, 0, 0, 0xa}, /* Polynomial VMULL */
6458 {0, 0, 0, 7}, /* Reserved: always UNDEF */
6461 prewiden
= neon_3reg_wide
[op
][0];
6462 src1_wide
= neon_3reg_wide
[op
][1];
6463 src2_wide
= neon_3reg_wide
[op
][2];
6464 undefreq
= neon_3reg_wide
[op
][3];
6466 if ((undefreq
& (1 << size
)) ||
6467 ((undefreq
& 8) && u
)) {
6470 if ((src1_wide
&& (rn
& 1)) ||
6471 (src2_wide
&& (rm
& 1)) ||
6472 (!src2_wide
&& (rd
& 1))) {
6476 /* Handle VMULL.P64 (Polynomial 64x64 to 128 bit multiply)
6477 * outside the loop below as it only performs a single pass.
6479 if (op
== 14 && size
== 2) {
6480 TCGv_i64 tcg_rn
, tcg_rm
, tcg_rd
;
6482 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
6485 tcg_rn
= tcg_temp_new_i64();
6486 tcg_rm
= tcg_temp_new_i64();
6487 tcg_rd
= tcg_temp_new_i64();
6488 neon_load_reg64(tcg_rn
, rn
);
6489 neon_load_reg64(tcg_rm
, rm
);
6490 gen_helper_neon_pmull_64_lo(tcg_rd
, tcg_rn
, tcg_rm
);
6491 neon_store_reg64(tcg_rd
, rd
);
6492 gen_helper_neon_pmull_64_hi(tcg_rd
, tcg_rn
, tcg_rm
);
6493 neon_store_reg64(tcg_rd
, rd
+ 1);
6494 tcg_temp_free_i64(tcg_rn
);
6495 tcg_temp_free_i64(tcg_rm
);
6496 tcg_temp_free_i64(tcg_rd
);
6500 /* Avoid overlapping operands. Wide source operands are
6501 always aligned so will never overlap with wide
6502 destinations in problematic ways. */
6503 if (rd
== rm
&& !src2_wide
) {
6504 tmp
= neon_load_reg(rm
, 1);
6505 neon_store_scratch(2, tmp
);
6506 } else if (rd
== rn
&& !src1_wide
) {
6507 tmp
= neon_load_reg(rn
, 1);
6508 neon_store_scratch(2, tmp
);
6510 TCGV_UNUSED_I32(tmp3
);
6511 for (pass
= 0; pass
< 2; pass
++) {
6513 neon_load_reg64(cpu_V0
, rn
+ pass
);
6514 TCGV_UNUSED_I32(tmp
);
6516 if (pass
== 1 && rd
== rn
) {
6517 tmp
= neon_load_scratch(2);
6519 tmp
= neon_load_reg(rn
, pass
);
6522 gen_neon_widen(cpu_V0
, tmp
, size
, u
);
6526 neon_load_reg64(cpu_V1
, rm
+ pass
);
6527 TCGV_UNUSED_I32(tmp2
);
6529 if (pass
== 1 && rd
== rm
) {
6530 tmp2
= neon_load_scratch(2);
6532 tmp2
= neon_load_reg(rm
, pass
);
6535 gen_neon_widen(cpu_V1
, tmp2
, size
, u
);
6539 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
6540 gen_neon_addl(size
);
6542 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
6543 gen_neon_subl(size
);
6545 case 5: case 7: /* VABAL, VABDL */
6546 switch ((size
<< 1) | u
) {
6548 gen_helper_neon_abdl_s16(cpu_V0
, tmp
, tmp2
);
6551 gen_helper_neon_abdl_u16(cpu_V0
, tmp
, tmp2
);
6554 gen_helper_neon_abdl_s32(cpu_V0
, tmp
, tmp2
);
6557 gen_helper_neon_abdl_u32(cpu_V0
, tmp
, tmp2
);
6560 gen_helper_neon_abdl_s64(cpu_V0
, tmp
, tmp2
);
6563 gen_helper_neon_abdl_u64(cpu_V0
, tmp
, tmp2
);
6567 tcg_temp_free_i32(tmp2
);
6568 tcg_temp_free_i32(tmp
);
6570 case 8: case 9: case 10: case 11: case 12: case 13:
6571 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
6572 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
6574 case 14: /* Polynomial VMULL */
6575 gen_helper_neon_mull_p8(cpu_V0
, tmp
, tmp2
);
6576 tcg_temp_free_i32(tmp2
);
6577 tcg_temp_free_i32(tmp
);
6579 default: /* 15 is RESERVED: caught earlier */
6584 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
6585 neon_store_reg64(cpu_V0
, rd
+ pass
);
6586 } else if (op
== 5 || (op
>= 8 && op
<= 11)) {
6588 neon_load_reg64(cpu_V1
, rd
+ pass
);
6590 case 10: /* VMLSL */
6591 gen_neon_negl(cpu_V0
, size
);
6593 case 5: case 8: /* VABAL, VMLAL */
6594 gen_neon_addl(size
);
6596 case 9: case 11: /* VQDMLAL, VQDMLSL */
6597 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
6599 gen_neon_negl(cpu_V0
, size
);
6601 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
6606 neon_store_reg64(cpu_V0
, rd
+ pass
);
6607 } else if (op
== 4 || op
== 6) {
6608 /* Narrowing operation. */
6609 tmp
= tcg_temp_new_i32();
6613 gen_helper_neon_narrow_high_u8(tmp
, cpu_V0
);
6616 gen_helper_neon_narrow_high_u16(tmp
, cpu_V0
);
6619 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
6620 tcg_gen_extrl_i64_i32(tmp
, cpu_V0
);
6627 gen_helper_neon_narrow_round_high_u8(tmp
, cpu_V0
);
6630 gen_helper_neon_narrow_round_high_u16(tmp
, cpu_V0
);
6633 tcg_gen_addi_i64(cpu_V0
, cpu_V0
, 1u << 31);
6634 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
6635 tcg_gen_extrl_i64_i32(tmp
, cpu_V0
);
6643 neon_store_reg(rd
, 0, tmp3
);
6644 neon_store_reg(rd
, 1, tmp
);
6647 /* Write back the result. */
6648 neon_store_reg64(cpu_V0
, rd
+ pass
);
6652 /* Two registers and a scalar. NB that for ops of this form
6653 * the ARM ARM labels bit 24 as Q, but it is in our variable
6660 case 1: /* Float VMLA scalar */
6661 case 5: /* Floating point VMLS scalar */
6662 case 9: /* Floating point VMUL scalar */
6667 case 0: /* Integer VMLA scalar */
6668 case 4: /* Integer VMLS scalar */
6669 case 8: /* Integer VMUL scalar */
6670 case 12: /* VQDMULH scalar */
6671 case 13: /* VQRDMULH scalar */
6672 if (u
&& ((rd
| rn
) & 1)) {
6675 tmp
= neon_get_scalar(size
, rm
);
6676 neon_store_scratch(0, tmp
);
6677 for (pass
= 0; pass
< (u
? 4 : 2); pass
++) {
6678 tmp
= neon_load_scratch(0);
6679 tmp2
= neon_load_reg(rn
, pass
);
6682 gen_helper_neon_qdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
6684 gen_helper_neon_qdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
6686 } else if (op
== 13) {
6688 gen_helper_neon_qrdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
6690 gen_helper_neon_qrdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
6692 } else if (op
& 1) {
6693 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6694 gen_helper_vfp_muls(tmp
, tmp
, tmp2
, fpstatus
);
6695 tcg_temp_free_ptr(fpstatus
);
6698 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
6699 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
6700 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
6704 tcg_temp_free_i32(tmp2
);
6707 tmp2
= neon_load_reg(rd
, pass
);
6710 gen_neon_add(size
, tmp
, tmp2
);
6714 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6715 gen_helper_vfp_adds(tmp
, tmp
, tmp2
, fpstatus
);
6716 tcg_temp_free_ptr(fpstatus
);
6720 gen_neon_rsb(size
, tmp
, tmp2
);
6724 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6725 gen_helper_vfp_subs(tmp
, tmp2
, tmp
, fpstatus
);
6726 tcg_temp_free_ptr(fpstatus
);
6732 tcg_temp_free_i32(tmp2
);
6734 neon_store_reg(rd
, pass
, tmp
);
6737 case 3: /* VQDMLAL scalar */
6738 case 7: /* VQDMLSL scalar */
6739 case 11: /* VQDMULL scalar */
6744 case 2: /* VMLAL sclar */
6745 case 6: /* VMLSL scalar */
6746 case 10: /* VMULL scalar */
6750 tmp2
= neon_get_scalar(size
, rm
);
6751 /* We need a copy of tmp2 because gen_neon_mull
6752 * deletes it during pass 0. */
6753 tmp4
= tcg_temp_new_i32();
6754 tcg_gen_mov_i32(tmp4
, tmp2
);
6755 tmp3
= neon_load_reg(rn
, 1);
6757 for (pass
= 0; pass
< 2; pass
++) {
6759 tmp
= neon_load_reg(rn
, 0);
6764 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
6766 neon_load_reg64(cpu_V1
, rd
+ pass
);
6770 gen_neon_negl(cpu_V0
, size
);
6773 gen_neon_addl(size
);
6776 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
6778 gen_neon_negl(cpu_V0
, size
);
6780 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
6786 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
6791 neon_store_reg64(cpu_V0
, rd
+ pass
);
6796 default: /* 14 and 15 are RESERVED */
6800 } else { /* size == 3 */
6803 imm
= (insn
>> 8) & 0xf;
6808 if (q
&& ((rd
| rn
| rm
) & 1)) {
6813 neon_load_reg64(cpu_V0
, rn
);
6815 neon_load_reg64(cpu_V1
, rn
+ 1);
6817 } else if (imm
== 8) {
6818 neon_load_reg64(cpu_V0
, rn
+ 1);
6820 neon_load_reg64(cpu_V1
, rm
);
6823 tmp64
= tcg_temp_new_i64();
6825 neon_load_reg64(cpu_V0
, rn
);
6826 neon_load_reg64(tmp64
, rn
+ 1);
6828 neon_load_reg64(cpu_V0
, rn
+ 1);
6829 neon_load_reg64(tmp64
, rm
);
6831 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, (imm
& 7) * 8);
6832 tcg_gen_shli_i64(cpu_V1
, tmp64
, 64 - ((imm
& 7) * 8));
6833 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
6835 neon_load_reg64(cpu_V1
, rm
);
6837 neon_load_reg64(cpu_V1
, rm
+ 1);
6840 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
6841 tcg_gen_shri_i64(tmp64
, tmp64
, imm
* 8);
6842 tcg_gen_or_i64(cpu_V1
, cpu_V1
, tmp64
);
6843 tcg_temp_free_i64(tmp64
);
6846 neon_load_reg64(cpu_V0
, rn
);
6847 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, imm
* 8);
6848 neon_load_reg64(cpu_V1
, rm
);
6849 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
6850 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
6852 neon_store_reg64(cpu_V0
, rd
);
6854 neon_store_reg64(cpu_V1
, rd
+ 1);
6856 } else if ((insn
& (1 << 11)) == 0) {
6857 /* Two register misc. */
6858 op
= ((insn
>> 12) & 0x30) | ((insn
>> 7) & 0xf);
6859 size
= (insn
>> 18) & 3;
6860 /* UNDEF for unknown op values and bad op-size combinations */
6861 if ((neon_2rm_sizes
[op
] & (1 << size
)) == 0) {
6864 if (neon_2rm_is_v8_op(op
) &&
6865 !arm_dc_feature(s
, ARM_FEATURE_V8
)) {
6868 if ((op
!= NEON_2RM_VMOVN
&& op
!= NEON_2RM_VQMOVN
) &&
6869 q
&& ((rm
| rd
) & 1)) {
6873 case NEON_2RM_VREV64
:
6874 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
6875 tmp
= neon_load_reg(rm
, pass
* 2);
6876 tmp2
= neon_load_reg(rm
, pass
* 2 + 1);
6878 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
6879 case 1: gen_swap_half(tmp
); break;
6880 case 2: /* no-op */ break;
6883 neon_store_reg(rd
, pass
* 2 + 1, tmp
);
6885 neon_store_reg(rd
, pass
* 2, tmp2
);
6888 case 0: tcg_gen_bswap32_i32(tmp2
, tmp2
); break;
6889 case 1: gen_swap_half(tmp2
); break;
6892 neon_store_reg(rd
, pass
* 2, tmp2
);
6896 case NEON_2RM_VPADDL
: case NEON_2RM_VPADDL_U
:
6897 case NEON_2RM_VPADAL
: case NEON_2RM_VPADAL_U
:
6898 for (pass
= 0; pass
< q
+ 1; pass
++) {
6899 tmp
= neon_load_reg(rm
, pass
* 2);
6900 gen_neon_widen(cpu_V0
, tmp
, size
, op
& 1);
6901 tmp
= neon_load_reg(rm
, pass
* 2 + 1);
6902 gen_neon_widen(cpu_V1
, tmp
, size
, op
& 1);
6904 case 0: gen_helper_neon_paddl_u16(CPU_V001
); break;
6905 case 1: gen_helper_neon_paddl_u32(CPU_V001
); break;
6906 case 2: tcg_gen_add_i64(CPU_V001
); break;
6909 if (op
>= NEON_2RM_VPADAL
) {
6911 neon_load_reg64(cpu_V1
, rd
+ pass
);
6912 gen_neon_addl(size
);
6914 neon_store_reg64(cpu_V0
, rd
+ pass
);
6920 for (n
= 0; n
< (q
? 4 : 2); n
+= 2) {
6921 tmp
= neon_load_reg(rm
, n
);
6922 tmp2
= neon_load_reg(rd
, n
+ 1);
6923 neon_store_reg(rm
, n
, tmp2
);
6924 neon_store_reg(rd
, n
+ 1, tmp
);
6931 if (gen_neon_unzip(rd
, rm
, size
, q
)) {
6936 if (gen_neon_zip(rd
, rm
, size
, q
)) {
6940 case NEON_2RM_VMOVN
: case NEON_2RM_VQMOVN
:
6941 /* also VQMOVUN; op field and mnemonics don't line up */
6945 TCGV_UNUSED_I32(tmp2
);
6946 for (pass
= 0; pass
< 2; pass
++) {
6947 neon_load_reg64(cpu_V0
, rm
+ pass
);
6948 tmp
= tcg_temp_new_i32();
6949 gen_neon_narrow_op(op
== NEON_2RM_VMOVN
, q
, size
,
6954 neon_store_reg(rd
, 0, tmp2
);
6955 neon_store_reg(rd
, 1, tmp
);
6959 case NEON_2RM_VSHLL
:
6960 if (q
|| (rd
& 1)) {
6963 tmp
= neon_load_reg(rm
, 0);
6964 tmp2
= neon_load_reg(rm
, 1);
6965 for (pass
= 0; pass
< 2; pass
++) {
6968 gen_neon_widen(cpu_V0
, tmp
, size
, 1);
6969 tcg_gen_shli_i64(cpu_V0
, cpu_V0
, 8 << size
);
6970 neon_store_reg64(cpu_V0
, rd
+ pass
);
6973 case NEON_2RM_VCVT_F16_F32
:
6974 if (!arm_dc_feature(s
, ARM_FEATURE_VFP_FP16
) ||
6978 tmp
= tcg_temp_new_i32();
6979 tmp2
= tcg_temp_new_i32();
6980 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 0));
6981 gen_helper_neon_fcvt_f32_to_f16(tmp
, cpu_F0s
, cpu_env
);
6982 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 1));
6983 gen_helper_neon_fcvt_f32_to_f16(tmp2
, cpu_F0s
, cpu_env
);
6984 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
6985 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
6986 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 2));
6987 gen_helper_neon_fcvt_f32_to_f16(tmp
, cpu_F0s
, cpu_env
);
6988 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 3));
6989 neon_store_reg(rd
, 0, tmp2
);
6990 tmp2
= tcg_temp_new_i32();
6991 gen_helper_neon_fcvt_f32_to_f16(tmp2
, cpu_F0s
, cpu_env
);
6992 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
6993 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
6994 neon_store_reg(rd
, 1, tmp2
);
6995 tcg_temp_free_i32(tmp
);
6997 case NEON_2RM_VCVT_F32_F16
:
6998 if (!arm_dc_feature(s
, ARM_FEATURE_VFP_FP16
) ||
7002 tmp3
= tcg_temp_new_i32();
7003 tmp
= neon_load_reg(rm
, 0);
7004 tmp2
= neon_load_reg(rm
, 1);
7005 tcg_gen_ext16u_i32(tmp3
, tmp
);
7006 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
7007 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 0));
7008 tcg_gen_shri_i32(tmp3
, tmp
, 16);
7009 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
7010 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 1));
7011 tcg_temp_free_i32(tmp
);
7012 tcg_gen_ext16u_i32(tmp3
, tmp2
);
7013 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
7014 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 2));
7015 tcg_gen_shri_i32(tmp3
, tmp2
, 16);
7016 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
7017 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 3));
7018 tcg_temp_free_i32(tmp2
);
7019 tcg_temp_free_i32(tmp3
);
7021 case NEON_2RM_AESE
: case NEON_2RM_AESMC
:
7022 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
7023 || ((rm
| rd
) & 1)) {
7026 tmp
= tcg_const_i32(rd
);
7027 tmp2
= tcg_const_i32(rm
);
7029 /* Bit 6 is the lowest opcode bit; it distinguishes between
7030 * encryption (AESE/AESMC) and decryption (AESD/AESIMC)
7032 tmp3
= tcg_const_i32(extract32(insn
, 6, 1));
7034 if (op
== NEON_2RM_AESE
) {
7035 gen_helper_crypto_aese(cpu_env
, tmp
, tmp2
, tmp3
);
7037 gen_helper_crypto_aesmc(cpu_env
, tmp
, tmp2
, tmp3
);
7039 tcg_temp_free_i32(tmp
);
7040 tcg_temp_free_i32(tmp2
);
7041 tcg_temp_free_i32(tmp3
);
7043 case NEON_2RM_SHA1H
:
7044 if (!arm_dc_feature(s
, ARM_FEATURE_V8_SHA1
)
7045 || ((rm
| rd
) & 1)) {
7048 tmp
= tcg_const_i32(rd
);
7049 tmp2
= tcg_const_i32(rm
);
7051 gen_helper_crypto_sha1h(cpu_env
, tmp
, tmp2
);
7053 tcg_temp_free_i32(tmp
);
7054 tcg_temp_free_i32(tmp2
);
7056 case NEON_2RM_SHA1SU1
:
7057 if ((rm
| rd
) & 1) {
7060 /* bit 6 (q): set -> SHA256SU0, cleared -> SHA1SU1 */
7062 if (!arm_dc_feature(s
, ARM_FEATURE_V8_SHA256
)) {
7065 } else if (!arm_dc_feature(s
, ARM_FEATURE_V8_SHA1
)) {
7068 tmp
= tcg_const_i32(rd
);
7069 tmp2
= tcg_const_i32(rm
);
7071 gen_helper_crypto_sha256su0(cpu_env
, tmp
, tmp2
);
7073 gen_helper_crypto_sha1su1(cpu_env
, tmp
, tmp2
);
7075 tcg_temp_free_i32(tmp
);
7076 tcg_temp_free_i32(tmp2
);
7080 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
7081 if (neon_2rm_is_float_op(op
)) {
7082 tcg_gen_ld_f32(cpu_F0s
, cpu_env
,
7083 neon_reg_offset(rm
, pass
));
7084 TCGV_UNUSED_I32(tmp
);
7086 tmp
= neon_load_reg(rm
, pass
);
7089 case NEON_2RM_VREV32
:
7091 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
7092 case 1: gen_swap_half(tmp
); break;
7096 case NEON_2RM_VREV16
:
7101 case 0: gen_helper_neon_cls_s8(tmp
, tmp
); break;
7102 case 1: gen_helper_neon_cls_s16(tmp
, tmp
); break;
7103 case 2: gen_helper_neon_cls_s32(tmp
, tmp
); break;
7109 case 0: gen_helper_neon_clz_u8(tmp
, tmp
); break;
7110 case 1: gen_helper_neon_clz_u16(tmp
, tmp
); break;
7111 case 2: tcg_gen_clzi_i32(tmp
, tmp
, 32); break;
7116 gen_helper_neon_cnt_u8(tmp
, tmp
);
7119 tcg_gen_not_i32(tmp
, tmp
);
7121 case NEON_2RM_VQABS
:
7124 gen_helper_neon_qabs_s8(tmp
, cpu_env
, tmp
);
7127 gen_helper_neon_qabs_s16(tmp
, cpu_env
, tmp
);
7130 gen_helper_neon_qabs_s32(tmp
, cpu_env
, tmp
);
7135 case NEON_2RM_VQNEG
:
7138 gen_helper_neon_qneg_s8(tmp
, cpu_env
, tmp
);
7141 gen_helper_neon_qneg_s16(tmp
, cpu_env
, tmp
);
7144 gen_helper_neon_qneg_s32(tmp
, cpu_env
, tmp
);
7149 case NEON_2RM_VCGT0
: case NEON_2RM_VCLE0
:
7150 tmp2
= tcg_const_i32(0);
7152 case 0: gen_helper_neon_cgt_s8(tmp
, tmp
, tmp2
); break;
7153 case 1: gen_helper_neon_cgt_s16(tmp
, tmp
, tmp2
); break;
7154 case 2: gen_helper_neon_cgt_s32(tmp
, tmp
, tmp2
); break;
7157 tcg_temp_free_i32(tmp2
);
7158 if (op
== NEON_2RM_VCLE0
) {
7159 tcg_gen_not_i32(tmp
, tmp
);
7162 case NEON_2RM_VCGE0
: case NEON_2RM_VCLT0
:
7163 tmp2
= tcg_const_i32(0);
7165 case 0: gen_helper_neon_cge_s8(tmp
, tmp
, tmp2
); break;
7166 case 1: gen_helper_neon_cge_s16(tmp
, tmp
, tmp2
); break;
7167 case 2: gen_helper_neon_cge_s32(tmp
, tmp
, tmp2
); break;
7170 tcg_temp_free_i32(tmp2
);
7171 if (op
== NEON_2RM_VCLT0
) {
7172 tcg_gen_not_i32(tmp
, tmp
);
7175 case NEON_2RM_VCEQ0
:
7176 tmp2
= tcg_const_i32(0);
7178 case 0: gen_helper_neon_ceq_u8(tmp
, tmp
, tmp2
); break;
7179 case 1: gen_helper_neon_ceq_u16(tmp
, tmp
, tmp2
); break;
7180 case 2: gen_helper_neon_ceq_u32(tmp
, tmp
, tmp2
); break;
7183 tcg_temp_free_i32(tmp2
);
7187 case 0: gen_helper_neon_abs_s8(tmp
, tmp
); break;
7188 case 1: gen_helper_neon_abs_s16(tmp
, tmp
); break;
7189 case 2: tcg_gen_abs_i32(tmp
, tmp
); break;
7194 tmp2
= tcg_const_i32(0);
7195 gen_neon_rsb(size
, tmp
, tmp2
);
7196 tcg_temp_free_i32(tmp2
);
7198 case NEON_2RM_VCGT0_F
:
7200 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7201 tmp2
= tcg_const_i32(0);
7202 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
, fpstatus
);
7203 tcg_temp_free_i32(tmp2
);
7204 tcg_temp_free_ptr(fpstatus
);
7207 case NEON_2RM_VCGE0_F
:
7209 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7210 tmp2
= tcg_const_i32(0);
7211 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
, fpstatus
);
7212 tcg_temp_free_i32(tmp2
);
7213 tcg_temp_free_ptr(fpstatus
);
7216 case NEON_2RM_VCEQ0_F
:
7218 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7219 tmp2
= tcg_const_i32(0);
7220 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
, fpstatus
);
7221 tcg_temp_free_i32(tmp2
);
7222 tcg_temp_free_ptr(fpstatus
);
7225 case NEON_2RM_VCLE0_F
:
7227 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7228 tmp2
= tcg_const_i32(0);
7229 gen_helper_neon_cge_f32(tmp
, tmp2
, tmp
, fpstatus
);
7230 tcg_temp_free_i32(tmp2
);
7231 tcg_temp_free_ptr(fpstatus
);
7234 case NEON_2RM_VCLT0_F
:
7236 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7237 tmp2
= tcg_const_i32(0);
7238 gen_helper_neon_cgt_f32(tmp
, tmp2
, tmp
, fpstatus
);
7239 tcg_temp_free_i32(tmp2
);
7240 tcg_temp_free_ptr(fpstatus
);
7243 case NEON_2RM_VABS_F
:
7246 case NEON_2RM_VNEG_F
:
7250 tmp2
= neon_load_reg(rd
, pass
);
7251 neon_store_reg(rm
, pass
, tmp2
);
7254 tmp2
= neon_load_reg(rd
, pass
);
7256 case 0: gen_neon_trn_u8(tmp
, tmp2
); break;
7257 case 1: gen_neon_trn_u16(tmp
, tmp2
); break;
7260 neon_store_reg(rm
, pass
, tmp2
);
7262 case NEON_2RM_VRINTN
:
7263 case NEON_2RM_VRINTA
:
7264 case NEON_2RM_VRINTM
:
7265 case NEON_2RM_VRINTP
:
7266 case NEON_2RM_VRINTZ
:
7269 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7272 if (op
== NEON_2RM_VRINTZ
) {
7273 rmode
= FPROUNDING_ZERO
;
7275 rmode
= fp_decode_rm
[((op
& 0x6) >> 1) ^ 1];
7278 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
7279 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
7281 gen_helper_rints(cpu_F0s
, cpu_F0s
, fpstatus
);
7282 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
7284 tcg_temp_free_ptr(fpstatus
);
7285 tcg_temp_free_i32(tcg_rmode
);
7288 case NEON_2RM_VRINTX
:
7290 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7291 gen_helper_rints_exact(cpu_F0s
, cpu_F0s
, fpstatus
);
7292 tcg_temp_free_ptr(fpstatus
);
7295 case NEON_2RM_VCVTAU
:
7296 case NEON_2RM_VCVTAS
:
7297 case NEON_2RM_VCVTNU
:
7298 case NEON_2RM_VCVTNS
:
7299 case NEON_2RM_VCVTPU
:
7300 case NEON_2RM_VCVTPS
:
7301 case NEON_2RM_VCVTMU
:
7302 case NEON_2RM_VCVTMS
:
7304 bool is_signed
= !extract32(insn
, 7, 1);
7305 TCGv_ptr fpst
= get_fpstatus_ptr(1);
7306 TCGv_i32 tcg_rmode
, tcg_shift
;
7307 int rmode
= fp_decode_rm
[extract32(insn
, 8, 2)];
7309 tcg_shift
= tcg_const_i32(0);
7310 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
7311 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
7315 gen_helper_vfp_tosls(cpu_F0s
, cpu_F0s
,
7318 gen_helper_vfp_touls(cpu_F0s
, cpu_F0s
,
7322 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
7324 tcg_temp_free_i32(tcg_rmode
);
7325 tcg_temp_free_i32(tcg_shift
);
7326 tcg_temp_free_ptr(fpst
);
7329 case NEON_2RM_VRECPE
:
7331 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7332 gen_helper_recpe_u32(tmp
, tmp
, fpstatus
);
7333 tcg_temp_free_ptr(fpstatus
);
7336 case NEON_2RM_VRSQRTE
:
7338 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7339 gen_helper_rsqrte_u32(tmp
, tmp
, fpstatus
);
7340 tcg_temp_free_ptr(fpstatus
);
7343 case NEON_2RM_VRECPE_F
:
7345 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7346 gen_helper_recpe_f32(cpu_F0s
, cpu_F0s
, fpstatus
);
7347 tcg_temp_free_ptr(fpstatus
);
7350 case NEON_2RM_VRSQRTE_F
:
7352 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7353 gen_helper_rsqrte_f32(cpu_F0s
, cpu_F0s
, fpstatus
);
7354 tcg_temp_free_ptr(fpstatus
);
7357 case NEON_2RM_VCVT_FS
: /* VCVT.F32.S32 */
7360 case NEON_2RM_VCVT_FU
: /* VCVT.F32.U32 */
7363 case NEON_2RM_VCVT_SF
: /* VCVT.S32.F32 */
7364 gen_vfp_tosiz(0, 1);
7366 case NEON_2RM_VCVT_UF
: /* VCVT.U32.F32 */
7367 gen_vfp_touiz(0, 1);
7370 /* Reserved op values were caught by the
7371 * neon_2rm_sizes[] check earlier.
7375 if (neon_2rm_is_float_op(op
)) {
7376 tcg_gen_st_f32(cpu_F0s
, cpu_env
,
7377 neon_reg_offset(rd
, pass
));
7379 neon_store_reg(rd
, pass
, tmp
);
7384 } else if ((insn
& (1 << 10)) == 0) {
7386 int n
= ((insn
>> 8) & 3) + 1;
7387 if ((rn
+ n
) > 32) {
7388 /* This is UNPREDICTABLE; we choose to UNDEF to avoid the
7389 * helper function running off the end of the register file.
7394 if (insn
& (1 << 6)) {
7395 tmp
= neon_load_reg(rd
, 0);
7397 tmp
= tcg_temp_new_i32();
7398 tcg_gen_movi_i32(tmp
, 0);
7400 tmp2
= neon_load_reg(rm
, 0);
7401 tmp4
= tcg_const_i32(rn
);
7402 tmp5
= tcg_const_i32(n
);
7403 gen_helper_neon_tbl(tmp2
, cpu_env
, tmp2
, tmp
, tmp4
, tmp5
);
7404 tcg_temp_free_i32(tmp
);
7405 if (insn
& (1 << 6)) {
7406 tmp
= neon_load_reg(rd
, 1);
7408 tmp
= tcg_temp_new_i32();
7409 tcg_gen_movi_i32(tmp
, 0);
7411 tmp3
= neon_load_reg(rm
, 1);
7412 gen_helper_neon_tbl(tmp3
, cpu_env
, tmp3
, tmp
, tmp4
, tmp5
);
7413 tcg_temp_free_i32(tmp5
);
7414 tcg_temp_free_i32(tmp4
);
7415 neon_store_reg(rd
, 0, tmp2
);
7416 neon_store_reg(rd
, 1, tmp3
);
7417 tcg_temp_free_i32(tmp
);
7418 } else if ((insn
& 0x380) == 0) {
7420 if ((insn
& (7 << 16)) == 0 || (q
&& (rd
& 1))) {
7423 if (insn
& (1 << 19)) {
7424 tmp
= neon_load_reg(rm
, 1);
7426 tmp
= neon_load_reg(rm
, 0);
7428 if (insn
& (1 << 16)) {
7429 gen_neon_dup_u8(tmp
, ((insn
>> 17) & 3) * 8);
7430 } else if (insn
& (1 << 17)) {
7431 if ((insn
>> 18) & 1)
7432 gen_neon_dup_high16(tmp
);
7434 gen_neon_dup_low16(tmp
);
7436 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
7437 tmp2
= tcg_temp_new_i32();
7438 tcg_gen_mov_i32(tmp2
, tmp
);
7439 neon_store_reg(rd
, pass
, tmp2
);
7441 tcg_temp_free_i32(tmp
);
7450 static int disas_coproc_insn(DisasContext
*s
, uint32_t insn
)
7452 int cpnum
, is64
, crn
, crm
, opc1
, opc2
, isread
, rt
, rt2
;
7453 const ARMCPRegInfo
*ri
;
7455 cpnum
= (insn
>> 8) & 0xf;
7457 /* First check for coprocessor space used for XScale/iwMMXt insns */
7458 if (arm_dc_feature(s
, ARM_FEATURE_XSCALE
) && (cpnum
< 2)) {
7459 if (extract32(s
->c15_cpar
, cpnum
, 1) == 0) {
7462 if (arm_dc_feature(s
, ARM_FEATURE_IWMMXT
)) {
7463 return disas_iwmmxt_insn(s
, insn
);
7464 } else if (arm_dc_feature(s
, ARM_FEATURE_XSCALE
)) {
7465 return disas_dsp_insn(s
, insn
);
7470 /* Otherwise treat as a generic register access */
7471 is64
= (insn
& (1 << 25)) == 0;
7472 if (!is64
&& ((insn
& (1 << 4)) == 0)) {
7480 opc1
= (insn
>> 4) & 0xf;
7482 rt2
= (insn
>> 16) & 0xf;
7484 crn
= (insn
>> 16) & 0xf;
7485 opc1
= (insn
>> 21) & 7;
7486 opc2
= (insn
>> 5) & 7;
7489 isread
= (insn
>> 20) & 1;
7490 rt
= (insn
>> 12) & 0xf;
7492 ri
= get_arm_cp_reginfo(s
->cp_regs
,
7493 ENCODE_CP_REG(cpnum
, is64
, s
->ns
, crn
, crm
, opc1
, opc2
));
7495 /* Check access permissions */
7496 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
7501 (arm_dc_feature(s
, ARM_FEATURE_XSCALE
) && cpnum
< 14)) {
7502 /* Emit code to perform further access permissions checks at
7503 * runtime; this may result in an exception.
7504 * Note that on XScale all cp0..c13 registers do an access check
7505 * call in order to handle c15_cpar.
7508 TCGv_i32 tcg_syn
, tcg_isread
;
7511 /* Note that since we are an implementation which takes an
7512 * exception on a trapped conditional instruction only if the
7513 * instruction passes its condition code check, we can take
7514 * advantage of the clause in the ARM ARM that allows us to set
7515 * the COND field in the instruction to 0xE in all cases.
7516 * We could fish the actual condition out of the insn (ARM)
7517 * or the condexec bits (Thumb) but it isn't necessary.
7522 syndrome
= syn_cp14_rrt_trap(1, 0xe, opc1
, crm
, rt
, rt2
,
7525 syndrome
= syn_cp14_rt_trap(1, 0xe, opc1
, opc2
, crn
, crm
,
7531 syndrome
= syn_cp15_rrt_trap(1, 0xe, opc1
, crm
, rt
, rt2
,
7534 syndrome
= syn_cp15_rt_trap(1, 0xe, opc1
, opc2
, crn
, crm
,
7539 /* ARMv8 defines that only coprocessors 14 and 15 exist,
7540 * so this can only happen if this is an ARMv7 or earlier CPU,
7541 * in which case the syndrome information won't actually be
7544 assert(!arm_dc_feature(s
, ARM_FEATURE_V8
));
7545 syndrome
= syn_uncategorized();
7549 gen_set_condexec(s
);
7550 gen_set_pc_im(s
, s
->pc
- 4);
7551 tmpptr
= tcg_const_ptr(ri
);
7552 tcg_syn
= tcg_const_i32(syndrome
);
7553 tcg_isread
= tcg_const_i32(isread
);
7554 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
,
7556 tcg_temp_free_ptr(tmpptr
);
7557 tcg_temp_free_i32(tcg_syn
);
7558 tcg_temp_free_i32(tcg_isread
);
7561 /* Handle special cases first */
7562 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
7569 gen_set_pc_im(s
, s
->pc
);
7570 s
->is_jmp
= DISAS_WFI
;
7576 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
7585 if (ri
->type
& ARM_CP_CONST
) {
7586 tmp64
= tcg_const_i64(ri
->resetvalue
);
7587 } else if (ri
->readfn
) {
7589 tmp64
= tcg_temp_new_i64();
7590 tmpptr
= tcg_const_ptr(ri
);
7591 gen_helper_get_cp_reg64(tmp64
, cpu_env
, tmpptr
);
7592 tcg_temp_free_ptr(tmpptr
);
7594 tmp64
= tcg_temp_new_i64();
7595 tcg_gen_ld_i64(tmp64
, cpu_env
, ri
->fieldoffset
);
7597 tmp
= tcg_temp_new_i32();
7598 tcg_gen_extrl_i64_i32(tmp
, tmp64
);
7599 store_reg(s
, rt
, tmp
);
7600 tcg_gen_shri_i64(tmp64
, tmp64
, 32);
7601 tmp
= tcg_temp_new_i32();
7602 tcg_gen_extrl_i64_i32(tmp
, tmp64
);
7603 tcg_temp_free_i64(tmp64
);
7604 store_reg(s
, rt2
, tmp
);
7607 if (ri
->type
& ARM_CP_CONST
) {
7608 tmp
= tcg_const_i32(ri
->resetvalue
);
7609 } else if (ri
->readfn
) {
7611 tmp
= tcg_temp_new_i32();
7612 tmpptr
= tcg_const_ptr(ri
);
7613 gen_helper_get_cp_reg(tmp
, cpu_env
, tmpptr
);
7614 tcg_temp_free_ptr(tmpptr
);
7616 tmp
= load_cpu_offset(ri
->fieldoffset
);
7619 /* Destination register of r15 for 32 bit loads sets
7620 * the condition codes from the high 4 bits of the value
7623 tcg_temp_free_i32(tmp
);
7625 store_reg(s
, rt
, tmp
);
7630 if (ri
->type
& ARM_CP_CONST
) {
7631 /* If not forbidden by access permissions, treat as WI */
7636 TCGv_i32 tmplo
, tmphi
;
7637 TCGv_i64 tmp64
= tcg_temp_new_i64();
7638 tmplo
= load_reg(s
, rt
);
7639 tmphi
= load_reg(s
, rt2
);
7640 tcg_gen_concat_i32_i64(tmp64
, tmplo
, tmphi
);
7641 tcg_temp_free_i32(tmplo
);
7642 tcg_temp_free_i32(tmphi
);
7644 TCGv_ptr tmpptr
= tcg_const_ptr(ri
);
7645 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tmp64
);
7646 tcg_temp_free_ptr(tmpptr
);
7648 tcg_gen_st_i64(tmp64
, cpu_env
, ri
->fieldoffset
);
7650 tcg_temp_free_i64(tmp64
);
7655 tmp
= load_reg(s
, rt
);
7656 tmpptr
= tcg_const_ptr(ri
);
7657 gen_helper_set_cp_reg(cpu_env
, tmpptr
, tmp
);
7658 tcg_temp_free_ptr(tmpptr
);
7659 tcg_temp_free_i32(tmp
);
7661 TCGv_i32 tmp
= load_reg(s
, rt
);
7662 store_cpu_offset(tmp
, ri
->fieldoffset
);
7667 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
7668 /* I/O operations must end the TB here (whether read or write) */
7671 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
7672 /* We default to ending the TB on a coprocessor register write,
7673 * but allow this to be suppressed by the register definition
7674 * (usually only necessary to work around guest bugs).
7682 /* Unknown register; this might be a guest error or a QEMU
7683 * unimplemented feature.
7686 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch32 "
7687 "64 bit system register cp:%d opc1: %d crm:%d "
7689 isread
? "read" : "write", cpnum
, opc1
, crm
,
7690 s
->ns
? "non-secure" : "secure");
7692 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch32 "
7693 "system register cp:%d opc1:%d crn:%d crm:%d opc2:%d "
7695 isread
? "read" : "write", cpnum
, opc1
, crn
, crm
, opc2
,
7696 s
->ns
? "non-secure" : "secure");
7703 /* Store a 64-bit value to a register pair. Clobbers val. */
7704 static void gen_storeq_reg(DisasContext
*s
, int rlow
, int rhigh
, TCGv_i64 val
)
7707 tmp
= tcg_temp_new_i32();
7708 tcg_gen_extrl_i64_i32(tmp
, val
);
7709 store_reg(s
, rlow
, tmp
);
7710 tmp
= tcg_temp_new_i32();
7711 tcg_gen_shri_i64(val
, val
, 32);
7712 tcg_gen_extrl_i64_i32(tmp
, val
);
7713 store_reg(s
, rhigh
, tmp
);
7716 /* load a 32-bit value from a register and perform a 64-bit accumulate. */
7717 static void gen_addq_lo(DisasContext
*s
, TCGv_i64 val
, int rlow
)
7722 /* Load value and extend to 64 bits. */
7723 tmp
= tcg_temp_new_i64();
7724 tmp2
= load_reg(s
, rlow
);
7725 tcg_gen_extu_i32_i64(tmp
, tmp2
);
7726 tcg_temp_free_i32(tmp2
);
7727 tcg_gen_add_i64(val
, val
, tmp
);
7728 tcg_temp_free_i64(tmp
);
7731 /* load and add a 64-bit value from a register pair. */
7732 static void gen_addq(DisasContext
*s
, TCGv_i64 val
, int rlow
, int rhigh
)
7738 /* Load 64-bit value rd:rn. */
7739 tmpl
= load_reg(s
, rlow
);
7740 tmph
= load_reg(s
, rhigh
);
7741 tmp
= tcg_temp_new_i64();
7742 tcg_gen_concat_i32_i64(tmp
, tmpl
, tmph
);
7743 tcg_temp_free_i32(tmpl
);
7744 tcg_temp_free_i32(tmph
);
7745 tcg_gen_add_i64(val
, val
, tmp
);
7746 tcg_temp_free_i64(tmp
);
7749 /* Set N and Z flags from hi|lo. */
7750 static void gen_logicq_cc(TCGv_i32 lo
, TCGv_i32 hi
)
7752 tcg_gen_mov_i32(cpu_NF
, hi
);
7753 tcg_gen_or_i32(cpu_ZF
, lo
, hi
);
7756 /* Load/Store exclusive instructions are implemented by remembering
7757 the value/address loaded, and seeing if these are the same
7758 when the store is performed. This should be sufficient to implement
7759 the architecturally mandated semantics, and avoids having to monitor
7760 regular stores. The compare vs the remembered value is done during
7761 the cmpxchg operation, but we must compare the addresses manually. */
7762 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
7763 TCGv_i32 addr
, int size
)
7765 TCGv_i32 tmp
= tcg_temp_new_i32();
7766 TCGMemOp opc
= size
| MO_ALIGN
| s
->be_data
;
7771 TCGv_i32 tmp2
= tcg_temp_new_i32();
7772 TCGv_i64 t64
= tcg_temp_new_i64();
7774 gen_aa32_ld_i64(s
, t64
, addr
, get_mem_index(s
), opc
);
7775 tcg_gen_mov_i64(cpu_exclusive_val
, t64
);
7776 tcg_gen_extr_i64_i32(tmp
, tmp2
, t64
);
7777 tcg_temp_free_i64(t64
);
7779 store_reg(s
, rt2
, tmp2
);
7781 gen_aa32_ld_i32(s
, tmp
, addr
, get_mem_index(s
), opc
);
7782 tcg_gen_extu_i32_i64(cpu_exclusive_val
, tmp
);
7785 store_reg(s
, rt
, tmp
);
7786 tcg_gen_extu_i32_i64(cpu_exclusive_addr
, addr
);
7789 static void gen_clrex(DisasContext
*s
)
7791 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
7794 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
7795 TCGv_i32 addr
, int size
)
7797 TCGv_i32 t0
, t1
, t2
;
7800 TCGLabel
*done_label
;
7801 TCGLabel
*fail_label
;
7802 TCGMemOp opc
= size
| MO_ALIGN
| s
->be_data
;
7804 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
7810 fail_label
= gen_new_label();
7811 done_label
= gen_new_label();
7812 extaddr
= tcg_temp_new_i64();
7813 tcg_gen_extu_i32_i64(extaddr
, addr
);
7814 tcg_gen_brcond_i64(TCG_COND_NE
, extaddr
, cpu_exclusive_addr
, fail_label
);
7815 tcg_temp_free_i64(extaddr
);
7817 taddr
= gen_aa32_addr(s
, addr
, opc
);
7818 t0
= tcg_temp_new_i32();
7819 t1
= load_reg(s
, rt
);
7821 TCGv_i64 o64
= tcg_temp_new_i64();
7822 TCGv_i64 n64
= tcg_temp_new_i64();
7824 t2
= load_reg(s
, rt2
);
7825 tcg_gen_concat_i32_i64(n64
, t1
, t2
);
7826 tcg_temp_free_i32(t2
);
7827 gen_aa32_frob64(s
, n64
);
7829 tcg_gen_atomic_cmpxchg_i64(o64
, taddr
, cpu_exclusive_val
, n64
,
7830 get_mem_index(s
), opc
);
7831 tcg_temp_free_i64(n64
);
7833 gen_aa32_frob64(s
, o64
);
7834 tcg_gen_setcond_i64(TCG_COND_NE
, o64
, o64
, cpu_exclusive_val
);
7835 tcg_gen_extrl_i64_i32(t0
, o64
);
7837 tcg_temp_free_i64(o64
);
7839 t2
= tcg_temp_new_i32();
7840 tcg_gen_extrl_i64_i32(t2
, cpu_exclusive_val
);
7841 tcg_gen_atomic_cmpxchg_i32(t0
, taddr
, t2
, t1
, get_mem_index(s
), opc
);
7842 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t2
);
7843 tcg_temp_free_i32(t2
);
7845 tcg_temp_free_i32(t1
);
7846 tcg_temp_free(taddr
);
7847 tcg_gen_mov_i32(cpu_R
[rd
], t0
);
7848 tcg_temp_free_i32(t0
);
7849 tcg_gen_br(done_label
);
7851 gen_set_label(fail_label
);
7852 tcg_gen_movi_i32(cpu_R
[rd
], 1);
7853 gen_set_label(done_label
);
7854 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
7860 * @mode: mode field from insn (which stack to store to)
7861 * @amode: addressing mode (DA/IA/DB/IB), encoded as per P,U bits in ARM insn
7862 * @writeback: true if writeback bit set
7864 * Generate code for the SRS (Store Return State) insn.
7866 static void gen_srs(DisasContext
*s
,
7867 uint32_t mode
, uint32_t amode
, bool writeback
)
7874 * - trapped to EL3 if EL3 is AArch64 and we are at Secure EL1
7875 * and specified mode is monitor mode
7876 * - UNDEFINED in Hyp mode
7877 * - UNPREDICTABLE in User or System mode
7878 * - UNPREDICTABLE if the specified mode is:
7879 * -- not implemented
7880 * -- not a valid mode number
7881 * -- a mode that's at a higher exception level
7882 * -- Monitor, if we are Non-secure
7883 * For the UNPREDICTABLE cases we choose to UNDEF.
7885 if (s
->current_el
== 1 && !s
->ns
&& mode
== ARM_CPU_MODE_MON
) {
7886 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(), 3);
7890 if (s
->current_el
== 0 || s
->current_el
== 2) {
7895 case ARM_CPU_MODE_USR
:
7896 case ARM_CPU_MODE_FIQ
:
7897 case ARM_CPU_MODE_IRQ
:
7898 case ARM_CPU_MODE_SVC
:
7899 case ARM_CPU_MODE_ABT
:
7900 case ARM_CPU_MODE_UND
:
7901 case ARM_CPU_MODE_SYS
:
7903 case ARM_CPU_MODE_HYP
:
7904 if (s
->current_el
== 1 || !arm_dc_feature(s
, ARM_FEATURE_EL2
)) {
7908 case ARM_CPU_MODE_MON
:
7909 /* No need to check specifically for "are we non-secure" because
7910 * we've already made EL0 UNDEF and handled the trap for S-EL1;
7911 * so if this isn't EL3 then we must be non-secure.
7913 if (s
->current_el
!= 3) {
7922 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
7923 default_exception_el(s
));
7927 addr
= tcg_temp_new_i32();
7928 tmp
= tcg_const_i32(mode
);
7929 /* get_r13_banked() will raise an exception if called from System mode */
7930 gen_set_condexec(s
);
7931 gen_set_pc_im(s
, s
->pc
- 4);
7932 gen_helper_get_r13_banked(addr
, cpu_env
, tmp
);
7933 tcg_temp_free_i32(tmp
);
7950 tcg_gen_addi_i32(addr
, addr
, offset
);
7951 tmp
= load_reg(s
, 14);
7952 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
7953 tcg_temp_free_i32(tmp
);
7954 tmp
= load_cpu_field(spsr
);
7955 tcg_gen_addi_i32(addr
, addr
, 4);
7956 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
7957 tcg_temp_free_i32(tmp
);
7975 tcg_gen_addi_i32(addr
, addr
, offset
);
7976 tmp
= tcg_const_i32(mode
);
7977 gen_helper_set_r13_banked(cpu_env
, tmp
, addr
);
7978 tcg_temp_free_i32(tmp
);
7980 tcg_temp_free_i32(addr
);
7981 s
->is_jmp
= DISAS_UPDATE
;
7984 static void disas_arm_insn(DisasContext
*s
, unsigned int insn
)
7986 unsigned int cond
, val
, op1
, i
, shift
, rm
, rs
, rn
, rd
, sh
;
7993 /* M variants do not implement ARM mode. */
7994 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
7999 /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
8000 * choose to UNDEF. In ARMv5 and above the space is used
8001 * for miscellaneous unconditional instructions.
8005 /* Unconditional instructions. */
8006 if (((insn
>> 25) & 7) == 1) {
8007 /* NEON Data processing. */
8008 if (!arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
8012 if (disas_neon_data_insn(s
, insn
)) {
8017 if ((insn
& 0x0f100000) == 0x04000000) {
8018 /* NEON load/store. */
8019 if (!arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
8023 if (disas_neon_ls_insn(s
, insn
)) {
8028 if ((insn
& 0x0f000e10) == 0x0e000a00) {
8030 if (disas_vfp_insn(s
, insn
)) {
8035 if (((insn
& 0x0f30f000) == 0x0510f000) ||
8036 ((insn
& 0x0f30f010) == 0x0710f000)) {
8037 if ((insn
& (1 << 22)) == 0) {
8039 if (!arm_dc_feature(s
, ARM_FEATURE_V7MP
)) {
8043 /* Otherwise PLD; v5TE+ */
8047 if (((insn
& 0x0f70f000) == 0x0450f000) ||
8048 ((insn
& 0x0f70f010) == 0x0650f000)) {
8050 return; /* PLI; V7 */
8052 if (((insn
& 0x0f700000) == 0x04100000) ||
8053 ((insn
& 0x0f700010) == 0x06100000)) {
8054 if (!arm_dc_feature(s
, ARM_FEATURE_V7MP
)) {
8057 return; /* v7MP: Unallocated memory hint: must NOP */
8060 if ((insn
& 0x0ffffdff) == 0x01010000) {
8063 if (((insn
>> 9) & 1) != !!(s
->be_data
== MO_BE
)) {
8064 gen_helper_setend(cpu_env
);
8065 s
->is_jmp
= DISAS_UPDATE
;
8068 } else if ((insn
& 0x0fffff00) == 0x057ff000) {
8069 switch ((insn
>> 4) & 0xf) {
8077 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
8080 /* We need to break the TB after this insn to execute
8081 * self-modifying code correctly and also to take
8082 * any pending interrupts immediately.
8089 } else if ((insn
& 0x0e5fffe0) == 0x084d0500) {
8092 gen_srs(s
, (insn
& 0x1f), (insn
>> 23) & 3, insn
& (1 << 21));
8094 } else if ((insn
& 0x0e50ffe0) == 0x08100a00) {
8100 rn
= (insn
>> 16) & 0xf;
8101 addr
= load_reg(s
, rn
);
8102 i
= (insn
>> 23) & 3;
8104 case 0: offset
= -4; break; /* DA */
8105 case 1: offset
= 0; break; /* IA */
8106 case 2: offset
= -8; break; /* DB */
8107 case 3: offset
= 4; break; /* IB */
8111 tcg_gen_addi_i32(addr
, addr
, offset
);
8112 /* Load PC into tmp and CPSR into tmp2. */
8113 tmp
= tcg_temp_new_i32();
8114 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
8115 tcg_gen_addi_i32(addr
, addr
, 4);
8116 tmp2
= tcg_temp_new_i32();
8117 gen_aa32_ld32u(s
, tmp2
, addr
, get_mem_index(s
));
8118 if (insn
& (1 << 21)) {
8119 /* Base writeback. */
8121 case 0: offset
= -8; break;
8122 case 1: offset
= 4; break;
8123 case 2: offset
= -4; break;
8124 case 3: offset
= 0; break;
8128 tcg_gen_addi_i32(addr
, addr
, offset
);
8129 store_reg(s
, rn
, addr
);
8131 tcg_temp_free_i32(addr
);
8133 gen_rfe(s
, tmp
, tmp2
);
8135 } else if ((insn
& 0x0e000000) == 0x0a000000) {
8136 /* branch link and change to thumb (blx <offset>) */
8139 val
= (uint32_t)s
->pc
;
8140 tmp
= tcg_temp_new_i32();
8141 tcg_gen_movi_i32(tmp
, val
);
8142 store_reg(s
, 14, tmp
);
8143 /* Sign-extend the 24-bit offset */
8144 offset
= (((int32_t)insn
) << 8) >> 8;
8145 /* offset * 4 + bit24 * 2 + (thumb bit) */
8146 val
+= (offset
<< 2) | ((insn
>> 23) & 2) | 1;
8147 /* pipeline offset */
8149 /* protected by ARCH(5); above, near the start of uncond block */
8152 } else if ((insn
& 0x0e000f00) == 0x0c000100) {
8153 if (arm_dc_feature(s
, ARM_FEATURE_IWMMXT
)) {
8154 /* iWMMXt register transfer. */
8155 if (extract32(s
->c15_cpar
, 1, 1)) {
8156 if (!disas_iwmmxt_insn(s
, insn
)) {
8161 } else if ((insn
& 0x0fe00000) == 0x0c400000) {
8162 /* Coprocessor double register transfer. */
8164 } else if ((insn
& 0x0f000010) == 0x0e000010) {
8165 /* Additional coprocessor register transfer. */
8166 } else if ((insn
& 0x0ff10020) == 0x01000000) {
8169 /* cps (privileged) */
8173 if (insn
& (1 << 19)) {
8174 if (insn
& (1 << 8))
8176 if (insn
& (1 << 7))
8178 if (insn
& (1 << 6))
8180 if (insn
& (1 << 18))
8183 if (insn
& (1 << 17)) {
8185 val
|= (insn
& 0x1f);
8188 gen_set_psr_im(s
, mask
, 0, val
);
8195 /* if not always execute, we generate a conditional jump to
8197 s
->condlabel
= gen_new_label();
8198 arm_gen_test_cc(cond
^ 1, s
->condlabel
);
8201 if ((insn
& 0x0f900000) == 0x03000000) {
8202 if ((insn
& (1 << 21)) == 0) {
8204 rd
= (insn
>> 12) & 0xf;
8205 val
= ((insn
>> 4) & 0xf000) | (insn
& 0xfff);
8206 if ((insn
& (1 << 22)) == 0) {
8208 tmp
= tcg_temp_new_i32();
8209 tcg_gen_movi_i32(tmp
, val
);
8212 tmp
= load_reg(s
, rd
);
8213 tcg_gen_ext16u_i32(tmp
, tmp
);
8214 tcg_gen_ori_i32(tmp
, tmp
, val
<< 16);
8216 store_reg(s
, rd
, tmp
);
8218 if (((insn
>> 12) & 0xf) != 0xf)
8220 if (((insn
>> 16) & 0xf) == 0) {
8221 gen_nop_hint(s
, insn
& 0xff);
8223 /* CPSR = immediate */
8225 shift
= ((insn
>> 8) & 0xf) * 2;
8227 val
= (val
>> shift
) | (val
<< (32 - shift
));
8228 i
= ((insn
& (1 << 22)) != 0);
8229 if (gen_set_psr_im(s
, msr_mask(s
, (insn
>> 16) & 0xf, i
),
8235 } else if ((insn
& 0x0f900000) == 0x01000000
8236 && (insn
& 0x00000090) != 0x00000090) {
8237 /* miscellaneous instructions */
8238 op1
= (insn
>> 21) & 3;
8239 sh
= (insn
>> 4) & 0xf;
8242 case 0x0: /* MSR, MRS */
8243 if (insn
& (1 << 9)) {
8244 /* MSR (banked) and MRS (banked) */
8245 int sysm
= extract32(insn
, 16, 4) |
8246 (extract32(insn
, 8, 1) << 4);
8247 int r
= extract32(insn
, 22, 1);
8251 gen_msr_banked(s
, r
, sysm
, rm
);
8254 int rd
= extract32(insn
, 12, 4);
8256 gen_mrs_banked(s
, r
, sysm
, rd
);
8261 /* MSR, MRS (for PSRs) */
8264 tmp
= load_reg(s
, rm
);
8265 i
= ((op1
& 2) != 0);
8266 if (gen_set_psr(s
, msr_mask(s
, (insn
>> 16) & 0xf, i
), i
, tmp
))
8270 rd
= (insn
>> 12) & 0xf;
8274 tmp
= load_cpu_field(spsr
);
8276 tmp
= tcg_temp_new_i32();
8277 gen_helper_cpsr_read(tmp
, cpu_env
);
8279 store_reg(s
, rd
, tmp
);
8284 /* branch/exchange thumb (bx). */
8286 tmp
= load_reg(s
, rm
);
8288 } else if (op1
== 3) {
8291 rd
= (insn
>> 12) & 0xf;
8292 tmp
= load_reg(s
, rm
);
8293 tcg_gen_clzi_i32(tmp
, tmp
, 32);
8294 store_reg(s
, rd
, tmp
);
8302 /* Trivial implementation equivalent to bx. */
8303 tmp
= load_reg(s
, rm
);
8314 /* branch link/exchange thumb (blx) */
8315 tmp
= load_reg(s
, rm
);
8316 tmp2
= tcg_temp_new_i32();
8317 tcg_gen_movi_i32(tmp2
, s
->pc
);
8318 store_reg(s
, 14, tmp2
);
8324 uint32_t c
= extract32(insn
, 8, 4);
8326 /* Check this CPU supports ARMv8 CRC instructions.
8327 * op1 == 3 is UNPREDICTABLE but handle as UNDEFINED.
8328 * Bits 8, 10 and 11 should be zero.
8330 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
) || op1
== 0x3 ||
8335 rn
= extract32(insn
, 16, 4);
8336 rd
= extract32(insn
, 12, 4);
8338 tmp
= load_reg(s
, rn
);
8339 tmp2
= load_reg(s
, rm
);
8341 tcg_gen_andi_i32(tmp2
, tmp2
, 0xff);
8342 } else if (op1
== 1) {
8343 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff);
8345 tmp3
= tcg_const_i32(1 << op1
);
8347 gen_helper_crc32c(tmp
, tmp
, tmp2
, tmp3
);
8349 gen_helper_crc32(tmp
, tmp
, tmp2
, tmp3
);
8351 tcg_temp_free_i32(tmp2
);
8352 tcg_temp_free_i32(tmp3
);
8353 store_reg(s
, rd
, tmp
);
8356 case 0x5: /* saturating add/subtract */
8358 rd
= (insn
>> 12) & 0xf;
8359 rn
= (insn
>> 16) & 0xf;
8360 tmp
= load_reg(s
, rm
);
8361 tmp2
= load_reg(s
, rn
);
8363 gen_helper_double_saturate(tmp2
, cpu_env
, tmp2
);
8365 gen_helper_sub_saturate(tmp
, cpu_env
, tmp
, tmp2
);
8367 gen_helper_add_saturate(tmp
, cpu_env
, tmp
, tmp2
);
8368 tcg_temp_free_i32(tmp2
);
8369 store_reg(s
, rd
, tmp
);
8373 int imm16
= extract32(insn
, 0, 4) | (extract32(insn
, 8, 12) << 4);
8382 gen_exception_insn(s
, 4, EXCP_BKPT
,
8383 syn_aa32_bkpt(imm16
, false),
8384 default_exception_el(s
));
8387 /* Hypervisor call (v7) */
8395 /* Secure monitor call (v6+) */
8403 g_assert_not_reached();
8407 case 0x8: /* signed multiply */
8412 rs
= (insn
>> 8) & 0xf;
8413 rn
= (insn
>> 12) & 0xf;
8414 rd
= (insn
>> 16) & 0xf;
8416 /* (32 * 16) >> 16 */
8417 tmp
= load_reg(s
, rm
);
8418 tmp2
= load_reg(s
, rs
);
8420 tcg_gen_sari_i32(tmp2
, tmp2
, 16);
8423 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
8424 tcg_gen_shri_i64(tmp64
, tmp64
, 16);
8425 tmp
= tcg_temp_new_i32();
8426 tcg_gen_extrl_i64_i32(tmp
, tmp64
);
8427 tcg_temp_free_i64(tmp64
);
8428 if ((sh
& 2) == 0) {
8429 tmp2
= load_reg(s
, rn
);
8430 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
8431 tcg_temp_free_i32(tmp2
);
8433 store_reg(s
, rd
, tmp
);
8436 tmp
= load_reg(s
, rm
);
8437 tmp2
= load_reg(s
, rs
);
8438 gen_mulxy(tmp
, tmp2
, sh
& 2, sh
& 4);
8439 tcg_temp_free_i32(tmp2
);
8441 tmp64
= tcg_temp_new_i64();
8442 tcg_gen_ext_i32_i64(tmp64
, tmp
);
8443 tcg_temp_free_i32(tmp
);
8444 gen_addq(s
, tmp64
, rn
, rd
);
8445 gen_storeq_reg(s
, rn
, rd
, tmp64
);
8446 tcg_temp_free_i64(tmp64
);
8449 tmp2
= load_reg(s
, rn
);
8450 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
8451 tcg_temp_free_i32(tmp2
);
8453 store_reg(s
, rd
, tmp
);
8460 } else if (((insn
& 0x0e000000) == 0 &&
8461 (insn
& 0x00000090) != 0x90) ||
8462 ((insn
& 0x0e000000) == (1 << 25))) {
8463 int set_cc
, logic_cc
, shiftop
;
8465 op1
= (insn
>> 21) & 0xf;
8466 set_cc
= (insn
>> 20) & 1;
8467 logic_cc
= table_logic_cc
[op1
] & set_cc
;
8469 /* data processing instruction */
8470 if (insn
& (1 << 25)) {
8471 /* immediate operand */
8473 shift
= ((insn
>> 8) & 0xf) * 2;
8475 val
= (val
>> shift
) | (val
<< (32 - shift
));
8477 tmp2
= tcg_temp_new_i32();
8478 tcg_gen_movi_i32(tmp2
, val
);
8479 if (logic_cc
&& shift
) {
8480 gen_set_CF_bit31(tmp2
);
8485 tmp2
= load_reg(s
, rm
);
8486 shiftop
= (insn
>> 5) & 3;
8487 if (!(insn
& (1 << 4))) {
8488 shift
= (insn
>> 7) & 0x1f;
8489 gen_arm_shift_im(tmp2
, shiftop
, shift
, logic_cc
);
8491 rs
= (insn
>> 8) & 0xf;
8492 tmp
= load_reg(s
, rs
);
8493 gen_arm_shift_reg(tmp2
, shiftop
, tmp
, logic_cc
);
8496 if (op1
!= 0x0f && op1
!= 0x0d) {
8497 rn
= (insn
>> 16) & 0xf;
8498 tmp
= load_reg(s
, rn
);
8500 TCGV_UNUSED_I32(tmp
);
8502 rd
= (insn
>> 12) & 0xf;
8505 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
8509 store_reg_bx(s
, rd
, tmp
);
8512 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
8516 store_reg_bx(s
, rd
, tmp
);
8519 if (set_cc
&& rd
== 15) {
8520 /* SUBS r15, ... is used for exception return. */
8524 gen_sub_CC(tmp
, tmp
, tmp2
);
8525 gen_exception_return(s
, tmp
);
8528 gen_sub_CC(tmp
, tmp
, tmp2
);
8530 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
8532 store_reg_bx(s
, rd
, tmp
);
8537 gen_sub_CC(tmp
, tmp2
, tmp
);
8539 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
8541 store_reg_bx(s
, rd
, tmp
);
8545 gen_add_CC(tmp
, tmp
, tmp2
);
8547 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8549 store_reg_bx(s
, rd
, tmp
);
8553 gen_adc_CC(tmp
, tmp
, tmp2
);
8555 gen_add_carry(tmp
, tmp
, tmp2
);
8557 store_reg_bx(s
, rd
, tmp
);
8561 gen_sbc_CC(tmp
, tmp
, tmp2
);
8563 gen_sub_carry(tmp
, tmp
, tmp2
);
8565 store_reg_bx(s
, rd
, tmp
);
8569 gen_sbc_CC(tmp
, tmp2
, tmp
);
8571 gen_sub_carry(tmp
, tmp2
, tmp
);
8573 store_reg_bx(s
, rd
, tmp
);
8577 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
8580 tcg_temp_free_i32(tmp
);
8584 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
8587 tcg_temp_free_i32(tmp
);
8591 gen_sub_CC(tmp
, tmp
, tmp2
);
8593 tcg_temp_free_i32(tmp
);
8597 gen_add_CC(tmp
, tmp
, tmp2
);
8599 tcg_temp_free_i32(tmp
);
8602 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
8606 store_reg_bx(s
, rd
, tmp
);
8609 if (logic_cc
&& rd
== 15) {
8610 /* MOVS r15, ... is used for exception return. */
8614 gen_exception_return(s
, tmp2
);
8619 store_reg_bx(s
, rd
, tmp2
);
8623 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
8627 store_reg_bx(s
, rd
, tmp
);
8631 tcg_gen_not_i32(tmp2
, tmp2
);
8635 store_reg_bx(s
, rd
, tmp2
);
8638 if (op1
!= 0x0f && op1
!= 0x0d) {
8639 tcg_temp_free_i32(tmp2
);
8642 /* other instructions */
8643 op1
= (insn
>> 24) & 0xf;
8647 /* multiplies, extra load/stores */
8648 sh
= (insn
>> 5) & 3;
8651 rd
= (insn
>> 16) & 0xf;
8652 rn
= (insn
>> 12) & 0xf;
8653 rs
= (insn
>> 8) & 0xf;
8655 op1
= (insn
>> 20) & 0xf;
8657 case 0: case 1: case 2: case 3: case 6:
8659 tmp
= load_reg(s
, rs
);
8660 tmp2
= load_reg(s
, rm
);
8661 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
8662 tcg_temp_free_i32(tmp2
);
8663 if (insn
& (1 << 22)) {
8664 /* Subtract (mls) */
8666 tmp2
= load_reg(s
, rn
);
8667 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
8668 tcg_temp_free_i32(tmp2
);
8669 } else if (insn
& (1 << 21)) {
8671 tmp2
= load_reg(s
, rn
);
8672 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8673 tcg_temp_free_i32(tmp2
);
8675 if (insn
& (1 << 20))
8677 store_reg(s
, rd
, tmp
);
8680 /* 64 bit mul double accumulate (UMAAL) */
8682 tmp
= load_reg(s
, rs
);
8683 tmp2
= load_reg(s
, rm
);
8684 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
8685 gen_addq_lo(s
, tmp64
, rn
);
8686 gen_addq_lo(s
, tmp64
, rd
);
8687 gen_storeq_reg(s
, rn
, rd
, tmp64
);
8688 tcg_temp_free_i64(tmp64
);
8690 case 8: case 9: case 10: case 11:
8691 case 12: case 13: case 14: case 15:
8692 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
8693 tmp
= load_reg(s
, rs
);
8694 tmp2
= load_reg(s
, rm
);
8695 if (insn
& (1 << 22)) {
8696 tcg_gen_muls2_i32(tmp
, tmp2
, tmp
, tmp2
);
8698 tcg_gen_mulu2_i32(tmp
, tmp2
, tmp
, tmp2
);
8700 if (insn
& (1 << 21)) { /* mult accumulate */
8701 TCGv_i32 al
= load_reg(s
, rn
);
8702 TCGv_i32 ah
= load_reg(s
, rd
);
8703 tcg_gen_add2_i32(tmp
, tmp2
, tmp
, tmp2
, al
, ah
);
8704 tcg_temp_free_i32(al
);
8705 tcg_temp_free_i32(ah
);
8707 if (insn
& (1 << 20)) {
8708 gen_logicq_cc(tmp
, tmp2
);
8710 store_reg(s
, rn
, tmp
);
8711 store_reg(s
, rd
, tmp2
);
8717 rn
= (insn
>> 16) & 0xf;
8718 rd
= (insn
>> 12) & 0xf;
8719 if (insn
& (1 << 23)) {
8720 /* load/store exclusive */
8721 int op2
= (insn
>> 8) & 3;
8722 op1
= (insn
>> 21) & 0x3;
8725 case 0: /* lda/stl */
8731 case 1: /* reserved */
8733 case 2: /* ldaex/stlex */
8736 case 3: /* ldrex/strex */
8745 addr
= tcg_temp_local_new_i32();
8746 load_reg_var(s
, addr
, rn
);
8748 /* Since the emulation does not have barriers,
8749 the acquire/release semantics need no special
8752 if (insn
& (1 << 20)) {
8753 tmp
= tcg_temp_new_i32();
8756 gen_aa32_ld32u_iss(s
, tmp
, addr
,
8761 gen_aa32_ld8u_iss(s
, tmp
, addr
,
8766 gen_aa32_ld16u_iss(s
, tmp
, addr
,
8773 store_reg(s
, rd
, tmp
);
8776 tmp
= load_reg(s
, rm
);
8779 gen_aa32_st32_iss(s
, tmp
, addr
,
8784 gen_aa32_st8_iss(s
, tmp
, addr
,
8789 gen_aa32_st16_iss(s
, tmp
, addr
,
8796 tcg_temp_free_i32(tmp
);
8798 } else if (insn
& (1 << 20)) {
8801 gen_load_exclusive(s
, rd
, 15, addr
, 2);
8803 case 1: /* ldrexd */
8804 gen_load_exclusive(s
, rd
, rd
+ 1, addr
, 3);
8806 case 2: /* ldrexb */
8807 gen_load_exclusive(s
, rd
, 15, addr
, 0);
8809 case 3: /* ldrexh */
8810 gen_load_exclusive(s
, rd
, 15, addr
, 1);
8819 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 2);
8821 case 1: /* strexd */
8822 gen_store_exclusive(s
, rd
, rm
, rm
+ 1, addr
, 3);
8824 case 2: /* strexb */
8825 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 0);
8827 case 3: /* strexh */
8828 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 1);
8834 tcg_temp_free_i32(addr
);
8837 TCGMemOp opc
= s
->be_data
;
8839 /* SWP instruction */
8842 if (insn
& (1 << 22)) {
8845 opc
|= MO_UL
| MO_ALIGN
;
8848 addr
= load_reg(s
, rn
);
8849 taddr
= gen_aa32_addr(s
, addr
, opc
);
8850 tcg_temp_free_i32(addr
);
8852 tmp
= load_reg(s
, rm
);
8853 tcg_gen_atomic_xchg_i32(tmp
, taddr
, tmp
,
8854 get_mem_index(s
), opc
);
8855 tcg_temp_free(taddr
);
8856 store_reg(s
, rd
, tmp
);
8861 bool load
= insn
& (1 << 20);
8862 bool wbit
= insn
& (1 << 21);
8863 bool pbit
= insn
& (1 << 24);
8864 bool doubleword
= false;
8867 /* Misc load/store */
8868 rn
= (insn
>> 16) & 0xf;
8869 rd
= (insn
>> 12) & 0xf;
8871 /* ISS not valid if writeback */
8872 issinfo
= (pbit
& !wbit
) ? rd
: ISSInvalid
;
8874 if (!load
&& (sh
& 2)) {
8878 /* UNPREDICTABLE; we choose to UNDEF */
8881 load
= (sh
& 1) == 0;
8885 addr
= load_reg(s
, rn
);
8887 gen_add_datah_offset(s
, insn
, 0, addr
);
8894 tmp
= load_reg(s
, rd
);
8895 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
8896 tcg_temp_free_i32(tmp
);
8897 tcg_gen_addi_i32(addr
, addr
, 4);
8898 tmp
= load_reg(s
, rd
+ 1);
8899 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
8900 tcg_temp_free_i32(tmp
);
8903 tmp
= tcg_temp_new_i32();
8904 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
8905 store_reg(s
, rd
, tmp
);
8906 tcg_gen_addi_i32(addr
, addr
, 4);
8907 tmp
= tcg_temp_new_i32();
8908 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
8911 address_offset
= -4;
8914 tmp
= tcg_temp_new_i32();
8917 gen_aa32_ld16u_iss(s
, tmp
, addr
, get_mem_index(s
),
8921 gen_aa32_ld8s_iss(s
, tmp
, addr
, get_mem_index(s
),
8926 gen_aa32_ld16s_iss(s
, tmp
, addr
, get_mem_index(s
),
8932 tmp
= load_reg(s
, rd
);
8933 gen_aa32_st16_iss(s
, tmp
, addr
, get_mem_index(s
), issinfo
);
8934 tcg_temp_free_i32(tmp
);
8936 /* Perform base writeback before the loaded value to
8937 ensure correct behavior with overlapping index registers.
8938 ldrd with base writeback is undefined if the
8939 destination and index registers overlap. */
8941 gen_add_datah_offset(s
, insn
, address_offset
, addr
);
8942 store_reg(s
, rn
, addr
);
8945 tcg_gen_addi_i32(addr
, addr
, address_offset
);
8946 store_reg(s
, rn
, addr
);
8948 tcg_temp_free_i32(addr
);
8951 /* Complete the load. */
8952 store_reg(s
, rd
, tmp
);
8961 if (insn
& (1 << 4)) {
8963 /* Armv6 Media instructions. */
8965 rn
= (insn
>> 16) & 0xf;
8966 rd
= (insn
>> 12) & 0xf;
8967 rs
= (insn
>> 8) & 0xf;
8968 switch ((insn
>> 23) & 3) {
8969 case 0: /* Parallel add/subtract. */
8970 op1
= (insn
>> 20) & 7;
8971 tmp
= load_reg(s
, rn
);
8972 tmp2
= load_reg(s
, rm
);
8973 sh
= (insn
>> 5) & 7;
8974 if ((op1
& 3) == 0 || sh
== 5 || sh
== 6)
8976 gen_arm_parallel_addsub(op1
, sh
, tmp
, tmp2
);
8977 tcg_temp_free_i32(tmp2
);
8978 store_reg(s
, rd
, tmp
);
8981 if ((insn
& 0x00700020) == 0) {
8982 /* Halfword pack. */
8983 tmp
= load_reg(s
, rn
);
8984 tmp2
= load_reg(s
, rm
);
8985 shift
= (insn
>> 7) & 0x1f;
8986 if (insn
& (1 << 6)) {
8990 tcg_gen_sari_i32(tmp2
, tmp2
, shift
);
8991 tcg_gen_andi_i32(tmp
, tmp
, 0xffff0000);
8992 tcg_gen_ext16u_i32(tmp2
, tmp2
);
8996 tcg_gen_shli_i32(tmp2
, tmp2
, shift
);
8997 tcg_gen_ext16u_i32(tmp
, tmp
);
8998 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
9000 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
9001 tcg_temp_free_i32(tmp2
);
9002 store_reg(s
, rd
, tmp
);
9003 } else if ((insn
& 0x00200020) == 0x00200000) {
9005 tmp
= load_reg(s
, rm
);
9006 shift
= (insn
>> 7) & 0x1f;
9007 if (insn
& (1 << 6)) {
9010 tcg_gen_sari_i32(tmp
, tmp
, shift
);
9012 tcg_gen_shli_i32(tmp
, tmp
, shift
);
9014 sh
= (insn
>> 16) & 0x1f;
9015 tmp2
= tcg_const_i32(sh
);
9016 if (insn
& (1 << 22))
9017 gen_helper_usat(tmp
, cpu_env
, tmp
, tmp2
);
9019 gen_helper_ssat(tmp
, cpu_env
, tmp
, tmp2
);
9020 tcg_temp_free_i32(tmp2
);
9021 store_reg(s
, rd
, tmp
);
9022 } else if ((insn
& 0x00300fe0) == 0x00200f20) {
9024 tmp
= load_reg(s
, rm
);
9025 sh
= (insn
>> 16) & 0x1f;
9026 tmp2
= tcg_const_i32(sh
);
9027 if (insn
& (1 << 22))
9028 gen_helper_usat16(tmp
, cpu_env
, tmp
, tmp2
);
9030 gen_helper_ssat16(tmp
, cpu_env
, tmp
, tmp2
);
9031 tcg_temp_free_i32(tmp2
);
9032 store_reg(s
, rd
, tmp
);
9033 } else if ((insn
& 0x00700fe0) == 0x00000fa0) {
9035 tmp
= load_reg(s
, rn
);
9036 tmp2
= load_reg(s
, rm
);
9037 tmp3
= tcg_temp_new_i32();
9038 tcg_gen_ld_i32(tmp3
, cpu_env
, offsetof(CPUARMState
, GE
));
9039 gen_helper_sel_flags(tmp
, tmp3
, tmp
, tmp2
);
9040 tcg_temp_free_i32(tmp3
);
9041 tcg_temp_free_i32(tmp2
);
9042 store_reg(s
, rd
, tmp
);
9043 } else if ((insn
& 0x000003e0) == 0x00000060) {
9044 tmp
= load_reg(s
, rm
);
9045 shift
= (insn
>> 10) & 3;
9046 /* ??? In many cases it's not necessary to do a
9047 rotate, a shift is sufficient. */
9049 tcg_gen_rotri_i32(tmp
, tmp
, shift
* 8);
9050 op1
= (insn
>> 20) & 7;
9052 case 0: gen_sxtb16(tmp
); break;
9053 case 2: gen_sxtb(tmp
); break;
9054 case 3: gen_sxth(tmp
); break;
9055 case 4: gen_uxtb16(tmp
); break;
9056 case 6: gen_uxtb(tmp
); break;
9057 case 7: gen_uxth(tmp
); break;
9058 default: goto illegal_op
;
9061 tmp2
= load_reg(s
, rn
);
9062 if ((op1
& 3) == 0) {
9063 gen_add16(tmp
, tmp2
);
9065 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
9066 tcg_temp_free_i32(tmp2
);
9069 store_reg(s
, rd
, tmp
);
9070 } else if ((insn
& 0x003f0f60) == 0x003f0f20) {
9072 tmp
= load_reg(s
, rm
);
9073 if (insn
& (1 << 22)) {
9074 if (insn
& (1 << 7)) {
9078 gen_helper_rbit(tmp
, tmp
);
9081 if (insn
& (1 << 7))
9084 tcg_gen_bswap32_i32(tmp
, tmp
);
9086 store_reg(s
, rd
, tmp
);
9091 case 2: /* Multiplies (Type 3). */
9092 switch ((insn
>> 20) & 0x7) {
9094 if (((insn
>> 6) ^ (insn
>> 7)) & 1) {
9095 /* op2 not 00x or 11x : UNDEF */
9098 /* Signed multiply most significant [accumulate].
9099 (SMMUL, SMMLA, SMMLS) */
9100 tmp
= load_reg(s
, rm
);
9101 tmp2
= load_reg(s
, rs
);
9102 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
9105 tmp
= load_reg(s
, rd
);
9106 if (insn
& (1 << 6)) {
9107 tmp64
= gen_subq_msw(tmp64
, tmp
);
9109 tmp64
= gen_addq_msw(tmp64
, tmp
);
9112 if (insn
& (1 << 5)) {
9113 tcg_gen_addi_i64(tmp64
, tmp64
, 0x80000000u
);
9115 tcg_gen_shri_i64(tmp64
, tmp64
, 32);
9116 tmp
= tcg_temp_new_i32();
9117 tcg_gen_extrl_i64_i32(tmp
, tmp64
);
9118 tcg_temp_free_i64(tmp64
);
9119 store_reg(s
, rn
, tmp
);
9123 /* SMLAD, SMUAD, SMLSD, SMUSD, SMLALD, SMLSLD */
9124 if (insn
& (1 << 7)) {
9127 tmp
= load_reg(s
, rm
);
9128 tmp2
= load_reg(s
, rs
);
9129 if (insn
& (1 << 5))
9130 gen_swap_half(tmp2
);
9131 gen_smul_dual(tmp
, tmp2
);
9132 if (insn
& (1 << 22)) {
9133 /* smlald, smlsld */
9136 tmp64
= tcg_temp_new_i64();
9137 tmp64_2
= tcg_temp_new_i64();
9138 tcg_gen_ext_i32_i64(tmp64
, tmp
);
9139 tcg_gen_ext_i32_i64(tmp64_2
, tmp2
);
9140 tcg_temp_free_i32(tmp
);
9141 tcg_temp_free_i32(tmp2
);
9142 if (insn
& (1 << 6)) {
9143 tcg_gen_sub_i64(tmp64
, tmp64
, tmp64_2
);
9145 tcg_gen_add_i64(tmp64
, tmp64
, tmp64_2
);
9147 tcg_temp_free_i64(tmp64_2
);
9148 gen_addq(s
, tmp64
, rd
, rn
);
9149 gen_storeq_reg(s
, rd
, rn
, tmp64
);
9150 tcg_temp_free_i64(tmp64
);
9152 /* smuad, smusd, smlad, smlsd */
9153 if (insn
& (1 << 6)) {
9154 /* This subtraction cannot overflow. */
9155 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
9157 /* This addition cannot overflow 32 bits;
9158 * however it may overflow considered as a
9159 * signed operation, in which case we must set
9162 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
9164 tcg_temp_free_i32(tmp2
);
9167 tmp2
= load_reg(s
, rd
);
9168 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
9169 tcg_temp_free_i32(tmp2
);
9171 store_reg(s
, rn
, tmp
);
9177 if (!arm_dc_feature(s
, ARM_FEATURE_ARM_DIV
)) {
9180 if (((insn
>> 5) & 7) || (rd
!= 15)) {
9183 tmp
= load_reg(s
, rm
);
9184 tmp2
= load_reg(s
, rs
);
9185 if (insn
& (1 << 21)) {
9186 gen_helper_udiv(tmp
, tmp
, tmp2
);
9188 gen_helper_sdiv(tmp
, tmp
, tmp2
);
9190 tcg_temp_free_i32(tmp2
);
9191 store_reg(s
, rn
, tmp
);
9198 op1
= ((insn
>> 17) & 0x38) | ((insn
>> 5) & 7);
9200 case 0: /* Unsigned sum of absolute differences. */
9202 tmp
= load_reg(s
, rm
);
9203 tmp2
= load_reg(s
, rs
);
9204 gen_helper_usad8(tmp
, tmp
, tmp2
);
9205 tcg_temp_free_i32(tmp2
);
9207 tmp2
= load_reg(s
, rd
);
9208 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
9209 tcg_temp_free_i32(tmp2
);
9211 store_reg(s
, rn
, tmp
);
9213 case 0x20: case 0x24: case 0x28: case 0x2c:
9214 /* Bitfield insert/clear. */
9216 shift
= (insn
>> 7) & 0x1f;
9217 i
= (insn
>> 16) & 0x1f;
9219 /* UNPREDICTABLE; we choose to UNDEF */
9224 tmp
= tcg_temp_new_i32();
9225 tcg_gen_movi_i32(tmp
, 0);
9227 tmp
= load_reg(s
, rm
);
9230 tmp2
= load_reg(s
, rd
);
9231 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, shift
, i
);
9232 tcg_temp_free_i32(tmp2
);
9234 store_reg(s
, rd
, tmp
);
9236 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
9237 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
9239 tmp
= load_reg(s
, rm
);
9240 shift
= (insn
>> 7) & 0x1f;
9241 i
= ((insn
>> 16) & 0x1f) + 1;
9246 tcg_gen_extract_i32(tmp
, tmp
, shift
, i
);
9248 tcg_gen_sextract_i32(tmp
, tmp
, shift
, i
);
9251 store_reg(s
, rd
, tmp
);
9261 /* Check for undefined extension instructions
9262 * per the ARM Bible IE:
9263 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
9265 sh
= (0xf << 20) | (0xf << 4);
9266 if (op1
== 0x7 && ((insn
& sh
) == sh
))
9270 /* load/store byte/word */
9271 rn
= (insn
>> 16) & 0xf;
9272 rd
= (insn
>> 12) & 0xf;
9273 tmp2
= load_reg(s
, rn
);
9274 if ((insn
& 0x01200000) == 0x00200000) {
9276 i
= get_a32_user_mem_index(s
);
9278 i
= get_mem_index(s
);
9280 if (insn
& (1 << 24))
9281 gen_add_data_offset(s
, insn
, tmp2
);
9282 if (insn
& (1 << 20)) {
9284 tmp
= tcg_temp_new_i32();
9285 if (insn
& (1 << 22)) {
9286 gen_aa32_ld8u_iss(s
, tmp
, tmp2
, i
, rd
);
9288 gen_aa32_ld32u_iss(s
, tmp
, tmp2
, i
, rd
);
9292 tmp
= load_reg(s
, rd
);
9293 if (insn
& (1 << 22)) {
9294 gen_aa32_st8_iss(s
, tmp
, tmp2
, i
, rd
);
9296 gen_aa32_st32_iss(s
, tmp
, tmp2
, i
, rd
);
9298 tcg_temp_free_i32(tmp
);
9300 if (!(insn
& (1 << 24))) {
9301 gen_add_data_offset(s
, insn
, tmp2
);
9302 store_reg(s
, rn
, tmp2
);
9303 } else if (insn
& (1 << 21)) {
9304 store_reg(s
, rn
, tmp2
);
9306 tcg_temp_free_i32(tmp2
);
9308 if (insn
& (1 << 20)) {
9309 /* Complete the load. */
9310 store_reg_from_load(s
, rd
, tmp
);
9316 int j
, n
, loaded_base
;
9317 bool exc_return
= false;
9318 bool is_load
= extract32(insn
, 20, 1);
9320 TCGv_i32 loaded_var
;
9321 /* load/store multiple words */
9322 /* XXX: store correct base if write back */
9323 if (insn
& (1 << 22)) {
9324 /* LDM (user), LDM (exception return) and STM (user) */
9326 goto illegal_op
; /* only usable in supervisor mode */
9328 if (is_load
&& extract32(insn
, 15, 1)) {
9334 rn
= (insn
>> 16) & 0xf;
9335 addr
= load_reg(s
, rn
);
9337 /* compute total size */
9339 TCGV_UNUSED_I32(loaded_var
);
9342 if (insn
& (1 << i
))
9345 /* XXX: test invalid n == 0 case ? */
9346 if (insn
& (1 << 23)) {
9347 if (insn
& (1 << 24)) {
9349 tcg_gen_addi_i32(addr
, addr
, 4);
9351 /* post increment */
9354 if (insn
& (1 << 24)) {
9356 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
9358 /* post decrement */
9360 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
9365 if (insn
& (1 << i
)) {
9368 tmp
= tcg_temp_new_i32();
9369 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
9371 tmp2
= tcg_const_i32(i
);
9372 gen_helper_set_user_reg(cpu_env
, tmp2
, tmp
);
9373 tcg_temp_free_i32(tmp2
);
9374 tcg_temp_free_i32(tmp
);
9375 } else if (i
== rn
) {
9378 } else if (rn
== 15 && exc_return
) {
9379 store_pc_exc_ret(s
, tmp
);
9381 store_reg_from_load(s
, i
, tmp
);
9386 /* special case: r15 = PC + 8 */
9387 val
= (long)s
->pc
+ 4;
9388 tmp
= tcg_temp_new_i32();
9389 tcg_gen_movi_i32(tmp
, val
);
9391 tmp
= tcg_temp_new_i32();
9392 tmp2
= tcg_const_i32(i
);
9393 gen_helper_get_user_reg(tmp
, cpu_env
, tmp2
);
9394 tcg_temp_free_i32(tmp2
);
9396 tmp
= load_reg(s
, i
);
9398 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
9399 tcg_temp_free_i32(tmp
);
9402 /* no need to add after the last transfer */
9404 tcg_gen_addi_i32(addr
, addr
, 4);
9407 if (insn
& (1 << 21)) {
9409 if (insn
& (1 << 23)) {
9410 if (insn
& (1 << 24)) {
9413 /* post increment */
9414 tcg_gen_addi_i32(addr
, addr
, 4);
9417 if (insn
& (1 << 24)) {
9420 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
9422 /* post decrement */
9423 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
9426 store_reg(s
, rn
, addr
);
9428 tcg_temp_free_i32(addr
);
9431 store_reg(s
, rn
, loaded_var
);
9434 /* Restore CPSR from SPSR. */
9435 tmp
= load_cpu_field(spsr
);
9436 gen_helper_cpsr_write_eret(cpu_env
, tmp
);
9437 tcg_temp_free_i32(tmp
);
9438 s
->is_jmp
= DISAS_JUMP
;
9447 /* branch (and link) */
9448 val
= (int32_t)s
->pc
;
9449 if (insn
& (1 << 24)) {
9450 tmp
= tcg_temp_new_i32();
9451 tcg_gen_movi_i32(tmp
, val
);
9452 store_reg(s
, 14, tmp
);
9454 offset
= sextract32(insn
<< 2, 0, 26);
9462 if (((insn
>> 8) & 0xe) == 10) {
9464 if (disas_vfp_insn(s
, insn
)) {
9467 } else if (disas_coproc_insn(s
, insn
)) {
9474 gen_set_pc_im(s
, s
->pc
);
9475 s
->svc_imm
= extract32(insn
, 0, 24);
9476 s
->is_jmp
= DISAS_SWI
;
9480 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
9481 default_exception_el(s
));
9487 /* Return true if this is a Thumb-2 logical op. */
9489 thumb2_logic_op(int op
)
9494 /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
9495 then set condition code flags based on the result of the operation.
9496 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
9497 to the high bit of T1.
9498 Returns zero if the opcode is valid. */
9501 gen_thumb2_data_op(DisasContext
*s
, int op
, int conds
, uint32_t shifter_out
,
9502 TCGv_i32 t0
, TCGv_i32 t1
)
9509 tcg_gen_and_i32(t0
, t0
, t1
);
9513 tcg_gen_andc_i32(t0
, t0
, t1
);
9517 tcg_gen_or_i32(t0
, t0
, t1
);
9521 tcg_gen_orc_i32(t0
, t0
, t1
);
9525 tcg_gen_xor_i32(t0
, t0
, t1
);
9530 gen_add_CC(t0
, t0
, t1
);
9532 tcg_gen_add_i32(t0
, t0
, t1
);
9536 gen_adc_CC(t0
, t0
, t1
);
9542 gen_sbc_CC(t0
, t0
, t1
);
9544 gen_sub_carry(t0
, t0
, t1
);
9549 gen_sub_CC(t0
, t0
, t1
);
9551 tcg_gen_sub_i32(t0
, t0
, t1
);
9555 gen_sub_CC(t0
, t1
, t0
);
9557 tcg_gen_sub_i32(t0
, t1
, t0
);
9559 default: /* 5, 6, 7, 9, 12, 15. */
9565 gen_set_CF_bit31(t1
);
9570 /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
9572 static int disas_thumb2_insn(CPUARMState
*env
, DisasContext
*s
, uint16_t insn_hw1
)
9574 uint32_t insn
, imm
, shift
, offset
;
9575 uint32_t rd
, rn
, rm
, rs
;
9586 if (!(arm_dc_feature(s
, ARM_FEATURE_THUMB2
)
9587 || arm_dc_feature(s
, ARM_FEATURE_M
))) {
9588 /* Thumb-1 cores may need to treat bl and blx as a pair of
9589 16-bit instructions to get correct prefetch abort behavior. */
9591 if ((insn
& (1 << 12)) == 0) {
9593 /* Second half of blx. */
9594 offset
= ((insn
& 0x7ff) << 1);
9595 tmp
= load_reg(s
, 14);
9596 tcg_gen_addi_i32(tmp
, tmp
, offset
);
9597 tcg_gen_andi_i32(tmp
, tmp
, 0xfffffffc);
9599 tmp2
= tcg_temp_new_i32();
9600 tcg_gen_movi_i32(tmp2
, s
->pc
| 1);
9601 store_reg(s
, 14, tmp2
);
9605 if (insn
& (1 << 11)) {
9606 /* Second half of bl. */
9607 offset
= ((insn
& 0x7ff) << 1) | 1;
9608 tmp
= load_reg(s
, 14);
9609 tcg_gen_addi_i32(tmp
, tmp
, offset
);
9611 tmp2
= tcg_temp_new_i32();
9612 tcg_gen_movi_i32(tmp2
, s
->pc
| 1);
9613 store_reg(s
, 14, tmp2
);
9617 if ((s
->pc
& ~TARGET_PAGE_MASK
) == 0) {
9618 /* Instruction spans a page boundary. Implement it as two
9619 16-bit instructions in case the second half causes an
9621 offset
= ((int32_t)insn
<< 21) >> 9;
9622 tcg_gen_movi_i32(cpu_R
[14], s
->pc
+ 2 + offset
);
9625 /* Fall through to 32-bit decode. */
9628 insn
= arm_lduw_code(env
, s
->pc
, s
->sctlr_b
);
9630 insn
|= (uint32_t)insn_hw1
<< 16;
9632 if ((insn
& 0xf800e800) != 0xf000e800) {
9636 rn
= (insn
>> 16) & 0xf;
9637 rs
= (insn
>> 12) & 0xf;
9638 rd
= (insn
>> 8) & 0xf;
9640 switch ((insn
>> 25) & 0xf) {
9641 case 0: case 1: case 2: case 3:
9642 /* 16-bit instructions. Should never happen. */
9645 if (insn
& (1 << 22)) {
9646 /* Other load/store, table branch. */
9647 if (insn
& 0x01200000) {
9648 /* Load/store doubleword. */
9650 addr
= tcg_temp_new_i32();
9651 tcg_gen_movi_i32(addr
, s
->pc
& ~3);
9653 addr
= load_reg(s
, rn
);
9655 offset
= (insn
& 0xff) * 4;
9656 if ((insn
& (1 << 23)) == 0)
9658 if (insn
& (1 << 24)) {
9659 tcg_gen_addi_i32(addr
, addr
, offset
);
9662 if (insn
& (1 << 20)) {
9664 tmp
= tcg_temp_new_i32();
9665 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
9666 store_reg(s
, rs
, tmp
);
9667 tcg_gen_addi_i32(addr
, addr
, 4);
9668 tmp
= tcg_temp_new_i32();
9669 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
9670 store_reg(s
, rd
, tmp
);
9673 tmp
= load_reg(s
, rs
);
9674 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
9675 tcg_temp_free_i32(tmp
);
9676 tcg_gen_addi_i32(addr
, addr
, 4);
9677 tmp
= load_reg(s
, rd
);
9678 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
9679 tcg_temp_free_i32(tmp
);
9681 if (insn
& (1 << 21)) {
9682 /* Base writeback. */
9685 tcg_gen_addi_i32(addr
, addr
, offset
- 4);
9686 store_reg(s
, rn
, addr
);
9688 tcg_temp_free_i32(addr
);
9690 } else if ((insn
& (1 << 23)) == 0) {
9691 /* Load/store exclusive word. */
9692 addr
= tcg_temp_local_new_i32();
9693 load_reg_var(s
, addr
, rn
);
9694 tcg_gen_addi_i32(addr
, addr
, (insn
& 0xff) << 2);
9695 if (insn
& (1 << 20)) {
9696 gen_load_exclusive(s
, rs
, 15, addr
, 2);
9698 gen_store_exclusive(s
, rd
, rs
, 15, addr
, 2);
9700 tcg_temp_free_i32(addr
);
9701 } else if ((insn
& (7 << 5)) == 0) {
9704 addr
= tcg_temp_new_i32();
9705 tcg_gen_movi_i32(addr
, s
->pc
);
9707 addr
= load_reg(s
, rn
);
9709 tmp
= load_reg(s
, rm
);
9710 tcg_gen_add_i32(addr
, addr
, tmp
);
9711 if (insn
& (1 << 4)) {
9713 tcg_gen_add_i32(addr
, addr
, tmp
);
9714 tcg_temp_free_i32(tmp
);
9715 tmp
= tcg_temp_new_i32();
9716 gen_aa32_ld16u(s
, tmp
, addr
, get_mem_index(s
));
9718 tcg_temp_free_i32(tmp
);
9719 tmp
= tcg_temp_new_i32();
9720 gen_aa32_ld8u(s
, tmp
, addr
, get_mem_index(s
));
9722 tcg_temp_free_i32(addr
);
9723 tcg_gen_shli_i32(tmp
, tmp
, 1);
9724 tcg_gen_addi_i32(tmp
, tmp
, s
->pc
);
9725 store_reg(s
, 15, tmp
);
9727 int op2
= (insn
>> 6) & 0x3;
9728 op
= (insn
>> 4) & 0x3;
9733 /* Load/store exclusive byte/halfword/doubleword */
9740 /* Load-acquire/store-release */
9746 /* Load-acquire/store-release exclusive */
9750 addr
= tcg_temp_local_new_i32();
9751 load_reg_var(s
, addr
, rn
);
9753 if (insn
& (1 << 20)) {
9754 tmp
= tcg_temp_new_i32();
9757 gen_aa32_ld8u_iss(s
, tmp
, addr
, get_mem_index(s
),
9761 gen_aa32_ld16u_iss(s
, tmp
, addr
, get_mem_index(s
),
9765 gen_aa32_ld32u_iss(s
, tmp
, addr
, get_mem_index(s
),
9771 store_reg(s
, rs
, tmp
);
9773 tmp
= load_reg(s
, rs
);
9776 gen_aa32_st8_iss(s
, tmp
, addr
, get_mem_index(s
),
9780 gen_aa32_st16_iss(s
, tmp
, addr
, get_mem_index(s
),
9784 gen_aa32_st32_iss(s
, tmp
, addr
, get_mem_index(s
),
9790 tcg_temp_free_i32(tmp
);
9792 } else if (insn
& (1 << 20)) {
9793 gen_load_exclusive(s
, rs
, rd
, addr
, op
);
9795 gen_store_exclusive(s
, rm
, rs
, rd
, addr
, op
);
9797 tcg_temp_free_i32(addr
);
9800 /* Load/store multiple, RFE, SRS. */
9801 if (((insn
>> 23) & 1) == ((insn
>> 24) & 1)) {
9802 /* RFE, SRS: not available in user mode or on M profile */
9803 if (IS_USER(s
) || arm_dc_feature(s
, ARM_FEATURE_M
)) {
9806 if (insn
& (1 << 20)) {
9808 addr
= load_reg(s
, rn
);
9809 if ((insn
& (1 << 24)) == 0)
9810 tcg_gen_addi_i32(addr
, addr
, -8);
9811 /* Load PC into tmp and CPSR into tmp2. */
9812 tmp
= tcg_temp_new_i32();
9813 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
9814 tcg_gen_addi_i32(addr
, addr
, 4);
9815 tmp2
= tcg_temp_new_i32();
9816 gen_aa32_ld32u(s
, tmp2
, addr
, get_mem_index(s
));
9817 if (insn
& (1 << 21)) {
9818 /* Base writeback. */
9819 if (insn
& (1 << 24)) {
9820 tcg_gen_addi_i32(addr
, addr
, 4);
9822 tcg_gen_addi_i32(addr
, addr
, -4);
9824 store_reg(s
, rn
, addr
);
9826 tcg_temp_free_i32(addr
);
9828 gen_rfe(s
, tmp
, tmp2
);
9831 gen_srs(s
, (insn
& 0x1f), (insn
& (1 << 24)) ? 1 : 2,
9835 int i
, loaded_base
= 0;
9836 TCGv_i32 loaded_var
;
9837 /* Load/store multiple. */
9838 addr
= load_reg(s
, rn
);
9840 for (i
= 0; i
< 16; i
++) {
9841 if (insn
& (1 << i
))
9844 if (insn
& (1 << 24)) {
9845 tcg_gen_addi_i32(addr
, addr
, -offset
);
9848 TCGV_UNUSED_I32(loaded_var
);
9849 for (i
= 0; i
< 16; i
++) {
9850 if ((insn
& (1 << i
)) == 0)
9852 if (insn
& (1 << 20)) {
9854 tmp
= tcg_temp_new_i32();
9855 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
9858 } else if (i
== rn
) {
9862 store_reg(s
, i
, tmp
);
9866 tmp
= load_reg(s
, i
);
9867 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
9868 tcg_temp_free_i32(tmp
);
9870 tcg_gen_addi_i32(addr
, addr
, 4);
9873 store_reg(s
, rn
, loaded_var
);
9875 if (insn
& (1 << 21)) {
9876 /* Base register writeback. */
9877 if (insn
& (1 << 24)) {
9878 tcg_gen_addi_i32(addr
, addr
, -offset
);
9880 /* Fault if writeback register is in register list. */
9881 if (insn
& (1 << rn
))
9883 store_reg(s
, rn
, addr
);
9885 tcg_temp_free_i32(addr
);
9892 op
= (insn
>> 21) & 0xf;
9894 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
9897 /* Halfword pack. */
9898 tmp
= load_reg(s
, rn
);
9899 tmp2
= load_reg(s
, rm
);
9900 shift
= ((insn
>> 10) & 0x1c) | ((insn
>> 6) & 0x3);
9901 if (insn
& (1 << 5)) {
9905 tcg_gen_sari_i32(tmp2
, tmp2
, shift
);
9906 tcg_gen_andi_i32(tmp
, tmp
, 0xffff0000);
9907 tcg_gen_ext16u_i32(tmp2
, tmp2
);
9911 tcg_gen_shli_i32(tmp2
, tmp2
, shift
);
9912 tcg_gen_ext16u_i32(tmp
, tmp
);
9913 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
9915 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
9916 tcg_temp_free_i32(tmp2
);
9917 store_reg(s
, rd
, tmp
);
9919 /* Data processing register constant shift. */
9921 tmp
= tcg_temp_new_i32();
9922 tcg_gen_movi_i32(tmp
, 0);
9924 tmp
= load_reg(s
, rn
);
9926 tmp2
= load_reg(s
, rm
);
9928 shiftop
= (insn
>> 4) & 3;
9929 shift
= ((insn
>> 6) & 3) | ((insn
>> 10) & 0x1c);
9930 conds
= (insn
& (1 << 20)) != 0;
9931 logic_cc
= (conds
&& thumb2_logic_op(op
));
9932 gen_arm_shift_im(tmp2
, shiftop
, shift
, logic_cc
);
9933 if (gen_thumb2_data_op(s
, op
, conds
, 0, tmp
, tmp2
))
9935 tcg_temp_free_i32(tmp2
);
9937 store_reg(s
, rd
, tmp
);
9939 tcg_temp_free_i32(tmp
);
9943 case 13: /* Misc data processing. */
9944 op
= ((insn
>> 22) & 6) | ((insn
>> 7) & 1);
9945 if (op
< 4 && (insn
& 0xf000) != 0xf000)
9948 case 0: /* Register controlled shift. */
9949 tmp
= load_reg(s
, rn
);
9950 tmp2
= load_reg(s
, rm
);
9951 if ((insn
& 0x70) != 0)
9953 op
= (insn
>> 21) & 3;
9954 logic_cc
= (insn
& (1 << 20)) != 0;
9955 gen_arm_shift_reg(tmp
, op
, tmp2
, logic_cc
);
9958 store_reg_bx(s
, rd
, tmp
);
9960 case 1: /* Sign/zero extend. */
9961 op
= (insn
>> 20) & 7;
9963 case 0: /* SXTAH, SXTH */
9964 case 1: /* UXTAH, UXTH */
9965 case 4: /* SXTAB, SXTB */
9966 case 5: /* UXTAB, UXTB */
9968 case 2: /* SXTAB16, SXTB16 */
9969 case 3: /* UXTAB16, UXTB16 */
9970 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
9978 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
9982 tmp
= load_reg(s
, rm
);
9983 shift
= (insn
>> 4) & 3;
9984 /* ??? In many cases it's not necessary to do a
9985 rotate, a shift is sufficient. */
9987 tcg_gen_rotri_i32(tmp
, tmp
, shift
* 8);
9988 op
= (insn
>> 20) & 7;
9990 case 0: gen_sxth(tmp
); break;
9991 case 1: gen_uxth(tmp
); break;
9992 case 2: gen_sxtb16(tmp
); break;
9993 case 3: gen_uxtb16(tmp
); break;
9994 case 4: gen_sxtb(tmp
); break;
9995 case 5: gen_uxtb(tmp
); break;
9997 g_assert_not_reached();
10000 tmp2
= load_reg(s
, rn
);
10001 if ((op
>> 1) == 1) {
10002 gen_add16(tmp
, tmp2
);
10004 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
10005 tcg_temp_free_i32(tmp2
);
10008 store_reg(s
, rd
, tmp
);
10010 case 2: /* SIMD add/subtract. */
10011 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
10014 op
= (insn
>> 20) & 7;
10015 shift
= (insn
>> 4) & 7;
10016 if ((op
& 3) == 3 || (shift
& 3) == 3)
10018 tmp
= load_reg(s
, rn
);
10019 tmp2
= load_reg(s
, rm
);
10020 gen_thumb2_parallel_addsub(op
, shift
, tmp
, tmp2
);
10021 tcg_temp_free_i32(tmp2
);
10022 store_reg(s
, rd
, tmp
);
10024 case 3: /* Other data processing. */
10025 op
= ((insn
>> 17) & 0x38) | ((insn
>> 4) & 7);
10027 /* Saturating add/subtract. */
10028 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
10031 tmp
= load_reg(s
, rn
);
10032 tmp2
= load_reg(s
, rm
);
10034 gen_helper_double_saturate(tmp
, cpu_env
, tmp
);
10036 gen_helper_sub_saturate(tmp
, cpu_env
, tmp2
, tmp
);
10038 gen_helper_add_saturate(tmp
, cpu_env
, tmp
, tmp2
);
10039 tcg_temp_free_i32(tmp2
);
10042 case 0x0a: /* rbit */
10043 case 0x08: /* rev */
10044 case 0x09: /* rev16 */
10045 case 0x0b: /* revsh */
10046 case 0x18: /* clz */
10048 case 0x10: /* sel */
10049 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
10053 case 0x20: /* crc32/crc32c */
10059 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)) {
10066 tmp
= load_reg(s
, rn
);
10068 case 0x0a: /* rbit */
10069 gen_helper_rbit(tmp
, tmp
);
10071 case 0x08: /* rev */
10072 tcg_gen_bswap32_i32(tmp
, tmp
);
10074 case 0x09: /* rev16 */
10077 case 0x0b: /* revsh */
10080 case 0x10: /* sel */
10081 tmp2
= load_reg(s
, rm
);
10082 tmp3
= tcg_temp_new_i32();
10083 tcg_gen_ld_i32(tmp3
, cpu_env
, offsetof(CPUARMState
, GE
));
10084 gen_helper_sel_flags(tmp
, tmp3
, tmp
, tmp2
);
10085 tcg_temp_free_i32(tmp3
);
10086 tcg_temp_free_i32(tmp2
);
10088 case 0x18: /* clz */
10089 tcg_gen_clzi_i32(tmp
, tmp
, 32);
10099 uint32_t sz
= op
& 0x3;
10100 uint32_t c
= op
& 0x8;
10102 tmp2
= load_reg(s
, rm
);
10104 tcg_gen_andi_i32(tmp2
, tmp2
, 0xff);
10105 } else if (sz
== 1) {
10106 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff);
10108 tmp3
= tcg_const_i32(1 << sz
);
10110 gen_helper_crc32c(tmp
, tmp
, tmp2
, tmp3
);
10112 gen_helper_crc32(tmp
, tmp
, tmp2
, tmp3
);
10114 tcg_temp_free_i32(tmp2
);
10115 tcg_temp_free_i32(tmp3
);
10119 g_assert_not_reached();
10122 store_reg(s
, rd
, tmp
);
10124 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
10125 switch ((insn
>> 20) & 7) {
10126 case 0: /* 32 x 32 -> 32 */
10127 case 7: /* Unsigned sum of absolute differences. */
10129 case 1: /* 16 x 16 -> 32 */
10130 case 2: /* Dual multiply add. */
10131 case 3: /* 32 * 16 -> 32msb */
10132 case 4: /* Dual multiply subtract. */
10133 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
10134 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
10139 op
= (insn
>> 4) & 0xf;
10140 tmp
= load_reg(s
, rn
);
10141 tmp2
= load_reg(s
, rm
);
10142 switch ((insn
>> 20) & 7) {
10143 case 0: /* 32 x 32 -> 32 */
10144 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
10145 tcg_temp_free_i32(tmp2
);
10147 tmp2
= load_reg(s
, rs
);
10149 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
10151 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
10152 tcg_temp_free_i32(tmp2
);
10155 case 1: /* 16 x 16 -> 32 */
10156 gen_mulxy(tmp
, tmp2
, op
& 2, op
& 1);
10157 tcg_temp_free_i32(tmp2
);
10159 tmp2
= load_reg(s
, rs
);
10160 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
10161 tcg_temp_free_i32(tmp2
);
10164 case 2: /* Dual multiply add. */
10165 case 4: /* Dual multiply subtract. */
10167 gen_swap_half(tmp2
);
10168 gen_smul_dual(tmp
, tmp2
);
10169 if (insn
& (1 << 22)) {
10170 /* This subtraction cannot overflow. */
10171 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
10173 /* This addition cannot overflow 32 bits;
10174 * however it may overflow considered as a signed
10175 * operation, in which case we must set the Q flag.
10177 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
10179 tcg_temp_free_i32(tmp2
);
10182 tmp2
= load_reg(s
, rs
);
10183 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
10184 tcg_temp_free_i32(tmp2
);
10187 case 3: /* 32 * 16 -> 32msb */
10189 tcg_gen_sari_i32(tmp2
, tmp2
, 16);
10192 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
10193 tcg_gen_shri_i64(tmp64
, tmp64
, 16);
10194 tmp
= tcg_temp_new_i32();
10195 tcg_gen_extrl_i64_i32(tmp
, tmp64
);
10196 tcg_temp_free_i64(tmp64
);
10199 tmp2
= load_reg(s
, rs
);
10200 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
10201 tcg_temp_free_i32(tmp2
);
10204 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
10205 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
10207 tmp
= load_reg(s
, rs
);
10208 if (insn
& (1 << 20)) {
10209 tmp64
= gen_addq_msw(tmp64
, tmp
);
10211 tmp64
= gen_subq_msw(tmp64
, tmp
);
10214 if (insn
& (1 << 4)) {
10215 tcg_gen_addi_i64(tmp64
, tmp64
, 0x80000000u
);
10217 tcg_gen_shri_i64(tmp64
, tmp64
, 32);
10218 tmp
= tcg_temp_new_i32();
10219 tcg_gen_extrl_i64_i32(tmp
, tmp64
);
10220 tcg_temp_free_i64(tmp64
);
10222 case 7: /* Unsigned sum of absolute differences. */
10223 gen_helper_usad8(tmp
, tmp
, tmp2
);
10224 tcg_temp_free_i32(tmp2
);
10226 tmp2
= load_reg(s
, rs
);
10227 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
10228 tcg_temp_free_i32(tmp2
);
10232 store_reg(s
, rd
, tmp
);
10234 case 6: case 7: /* 64-bit multiply, Divide. */
10235 op
= ((insn
>> 4) & 0xf) | ((insn
>> 16) & 0x70);
10236 tmp
= load_reg(s
, rn
);
10237 tmp2
= load_reg(s
, rm
);
10238 if ((op
& 0x50) == 0x10) {
10240 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DIV
)) {
10244 gen_helper_udiv(tmp
, tmp
, tmp2
);
10246 gen_helper_sdiv(tmp
, tmp
, tmp2
);
10247 tcg_temp_free_i32(tmp2
);
10248 store_reg(s
, rd
, tmp
);
10249 } else if ((op
& 0xe) == 0xc) {
10250 /* Dual multiply accumulate long. */
10251 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
10252 tcg_temp_free_i32(tmp
);
10253 tcg_temp_free_i32(tmp2
);
10257 gen_swap_half(tmp2
);
10258 gen_smul_dual(tmp
, tmp2
);
10260 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
10262 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
10264 tcg_temp_free_i32(tmp2
);
10266 tmp64
= tcg_temp_new_i64();
10267 tcg_gen_ext_i32_i64(tmp64
, tmp
);
10268 tcg_temp_free_i32(tmp
);
10269 gen_addq(s
, tmp64
, rs
, rd
);
10270 gen_storeq_reg(s
, rs
, rd
, tmp64
);
10271 tcg_temp_free_i64(tmp64
);
10274 /* Unsigned 64-bit multiply */
10275 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
10279 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
10280 tcg_temp_free_i32(tmp2
);
10281 tcg_temp_free_i32(tmp
);
10284 gen_mulxy(tmp
, tmp2
, op
& 2, op
& 1);
10285 tcg_temp_free_i32(tmp2
);
10286 tmp64
= tcg_temp_new_i64();
10287 tcg_gen_ext_i32_i64(tmp64
, tmp
);
10288 tcg_temp_free_i32(tmp
);
10290 /* Signed 64-bit multiply */
10291 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
10296 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
10297 tcg_temp_free_i64(tmp64
);
10300 gen_addq_lo(s
, tmp64
, rs
);
10301 gen_addq_lo(s
, tmp64
, rd
);
10302 } else if (op
& 0x40) {
10303 /* 64-bit accumulate. */
10304 gen_addq(s
, tmp64
, rs
, rd
);
10306 gen_storeq_reg(s
, rs
, rd
, tmp64
);
10307 tcg_temp_free_i64(tmp64
);
10312 case 6: case 7: case 14: case 15:
10314 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
10315 /* We don't currently implement M profile FP support,
10316 * so this entire space should give a NOCP fault.
10318 gen_exception_insn(s
, 4, EXCP_NOCP
, syn_uncategorized(),
10319 default_exception_el(s
));
10322 if (((insn
>> 24) & 3) == 3) {
10323 /* Translate into the equivalent ARM encoding. */
10324 insn
= (insn
& 0xe2ffffff) | ((insn
& (1 << 28)) >> 4) | (1 << 28);
10325 if (disas_neon_data_insn(s
, insn
)) {
10328 } else if (((insn
>> 8) & 0xe) == 10) {
10329 if (disas_vfp_insn(s
, insn
)) {
10333 if (insn
& (1 << 28))
10335 if (disas_coproc_insn(s
, insn
)) {
10340 case 8: case 9: case 10: case 11:
10341 if (insn
& (1 << 15)) {
10342 /* Branches, misc control. */
10343 if (insn
& 0x5000) {
10344 /* Unconditional branch. */
10345 /* signextend(hw1[10:0]) -> offset[:12]. */
10346 offset
= ((int32_t)insn
<< 5) >> 9 & ~(int32_t)0xfff;
10347 /* hw1[10:0] -> offset[11:1]. */
10348 offset
|= (insn
& 0x7ff) << 1;
10349 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
10350 offset[24:22] already have the same value because of the
10351 sign extension above. */
10352 offset
^= ((~insn
) & (1 << 13)) << 10;
10353 offset
^= ((~insn
) & (1 << 11)) << 11;
10355 if (insn
& (1 << 14)) {
10356 /* Branch and link. */
10357 tcg_gen_movi_i32(cpu_R
[14], s
->pc
| 1);
10361 if (insn
& (1 << 12)) {
10363 gen_jmp(s
, offset
);
10366 offset
&= ~(uint32_t)2;
10367 /* thumb2 bx, no need to check */
10368 gen_bx_im(s
, offset
);
10370 } else if (((insn
>> 23) & 7) == 7) {
10372 if (insn
& (1 << 13))
10375 if (insn
& (1 << 26)) {
10376 if (!(insn
& (1 << 20))) {
10377 /* Hypervisor call (v7) */
10378 int imm16
= extract32(insn
, 16, 4) << 12
10379 | extract32(insn
, 0, 12);
10386 /* Secure monitor call (v6+) */
10394 op
= (insn
>> 20) & 7;
10396 case 0: /* msr cpsr. */
10397 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
10398 tmp
= load_reg(s
, rn
);
10399 addr
= tcg_const_i32(insn
& 0xff);
10400 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
10401 tcg_temp_free_i32(addr
);
10402 tcg_temp_free_i32(tmp
);
10407 case 1: /* msr spsr. */
10408 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
10412 if (extract32(insn
, 5, 1)) {
10414 int sysm
= extract32(insn
, 8, 4) |
10415 (extract32(insn
, 4, 1) << 4);
10418 gen_msr_banked(s
, r
, sysm
, rm
);
10422 /* MSR (for PSRs) */
10423 tmp
= load_reg(s
, rn
);
10425 msr_mask(s
, (insn
>> 8) & 0xf, op
== 1),
10429 case 2: /* cps, nop-hint. */
10430 if (((insn
>> 8) & 7) == 0) {
10431 gen_nop_hint(s
, insn
& 0xff);
10433 /* Implemented as NOP in user mode. */
10438 if (insn
& (1 << 10)) {
10439 if (insn
& (1 << 7))
10441 if (insn
& (1 << 6))
10443 if (insn
& (1 << 5))
10445 if (insn
& (1 << 9))
10446 imm
= CPSR_A
| CPSR_I
| CPSR_F
;
10448 if (insn
& (1 << 8)) {
10450 imm
|= (insn
& 0x1f);
10453 gen_set_psr_im(s
, offset
, 0, imm
);
10456 case 3: /* Special control operations. */
10458 op
= (insn
>> 4) & 0xf;
10460 case 2: /* clrex */
10465 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
10468 /* We need to break the TB after this insn
10469 * to execute self-modifying code correctly
10470 * and also to take any pending interrupts
10480 /* Trivial implementation equivalent to bx. */
10481 tmp
= load_reg(s
, rn
);
10484 case 5: /* Exception return. */
10488 if (rn
!= 14 || rd
!= 15) {
10491 tmp
= load_reg(s
, rn
);
10492 tcg_gen_subi_i32(tmp
, tmp
, insn
& 0xff);
10493 gen_exception_return(s
, tmp
);
10496 if (extract32(insn
, 5, 1)) {
10498 int sysm
= extract32(insn
, 16, 4) |
10499 (extract32(insn
, 4, 1) << 4);
10501 gen_mrs_banked(s
, 0, sysm
, rd
);
10506 tmp
= tcg_temp_new_i32();
10507 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
10508 addr
= tcg_const_i32(insn
& 0xff);
10509 gen_helper_v7m_mrs(tmp
, cpu_env
, addr
);
10510 tcg_temp_free_i32(addr
);
10512 gen_helper_cpsr_read(tmp
, cpu_env
);
10514 store_reg(s
, rd
, tmp
);
10517 if (extract32(insn
, 5, 1)) {
10519 int sysm
= extract32(insn
, 16, 4) |
10520 (extract32(insn
, 4, 1) << 4);
10522 gen_mrs_banked(s
, 1, sysm
, rd
);
10527 /* Not accessible in user mode. */
10528 if (IS_USER(s
) || arm_dc_feature(s
, ARM_FEATURE_M
)) {
10531 tmp
= load_cpu_field(spsr
);
10532 store_reg(s
, rd
, tmp
);
10537 /* Conditional branch. */
10538 op
= (insn
>> 22) & 0xf;
10539 /* Generate a conditional jump to next instruction. */
10540 s
->condlabel
= gen_new_label();
10541 arm_gen_test_cc(op
^ 1, s
->condlabel
);
10544 /* offset[11:1] = insn[10:0] */
10545 offset
= (insn
& 0x7ff) << 1;
10546 /* offset[17:12] = insn[21:16]. */
10547 offset
|= (insn
& 0x003f0000) >> 4;
10548 /* offset[31:20] = insn[26]. */
10549 offset
|= ((int32_t)((insn
<< 5) & 0x80000000)) >> 11;
10550 /* offset[18] = insn[13]. */
10551 offset
|= (insn
& (1 << 13)) << 5;
10552 /* offset[19] = insn[11]. */
10553 offset
|= (insn
& (1 << 11)) << 8;
10555 /* jump to the offset */
10556 gen_jmp(s
, s
->pc
+ offset
);
10559 /* Data processing immediate. */
10560 if (insn
& (1 << 25)) {
10561 if (insn
& (1 << 24)) {
10562 if (insn
& (1 << 20))
10564 /* Bitfield/Saturate. */
10565 op
= (insn
>> 21) & 7;
10567 shift
= ((insn
>> 6) & 3) | ((insn
>> 10) & 0x1c);
10569 tmp
= tcg_temp_new_i32();
10570 tcg_gen_movi_i32(tmp
, 0);
10572 tmp
= load_reg(s
, rn
);
10575 case 2: /* Signed bitfield extract. */
10577 if (shift
+ imm
> 32)
10580 tcg_gen_sextract_i32(tmp
, tmp
, shift
, imm
);
10583 case 6: /* Unsigned bitfield extract. */
10585 if (shift
+ imm
> 32)
10588 tcg_gen_extract_i32(tmp
, tmp
, shift
, imm
);
10591 case 3: /* Bitfield insert/clear. */
10594 imm
= imm
+ 1 - shift
;
10596 tmp2
= load_reg(s
, rd
);
10597 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, shift
, imm
);
10598 tcg_temp_free_i32(tmp2
);
10603 default: /* Saturate. */
10606 tcg_gen_sari_i32(tmp
, tmp
, shift
);
10608 tcg_gen_shli_i32(tmp
, tmp
, shift
);
10610 tmp2
= tcg_const_i32(imm
);
10613 if ((op
& 1) && shift
== 0) {
10614 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
10615 tcg_temp_free_i32(tmp
);
10616 tcg_temp_free_i32(tmp2
);
10619 gen_helper_usat16(tmp
, cpu_env
, tmp
, tmp2
);
10621 gen_helper_usat(tmp
, cpu_env
, tmp
, tmp2
);
10625 if ((op
& 1) && shift
== 0) {
10626 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
10627 tcg_temp_free_i32(tmp
);
10628 tcg_temp_free_i32(tmp2
);
10631 gen_helper_ssat16(tmp
, cpu_env
, tmp
, tmp2
);
10633 gen_helper_ssat(tmp
, cpu_env
, tmp
, tmp2
);
10636 tcg_temp_free_i32(tmp2
);
10639 store_reg(s
, rd
, tmp
);
10641 imm
= ((insn
& 0x04000000) >> 15)
10642 | ((insn
& 0x7000) >> 4) | (insn
& 0xff);
10643 if (insn
& (1 << 22)) {
10644 /* 16-bit immediate. */
10645 imm
|= (insn
>> 4) & 0xf000;
10646 if (insn
& (1 << 23)) {
10648 tmp
= load_reg(s
, rd
);
10649 tcg_gen_ext16u_i32(tmp
, tmp
);
10650 tcg_gen_ori_i32(tmp
, tmp
, imm
<< 16);
10653 tmp
= tcg_temp_new_i32();
10654 tcg_gen_movi_i32(tmp
, imm
);
10657 /* Add/sub 12-bit immediate. */
10659 offset
= s
->pc
& ~(uint32_t)3;
10660 if (insn
& (1 << 23))
10664 tmp
= tcg_temp_new_i32();
10665 tcg_gen_movi_i32(tmp
, offset
);
10667 tmp
= load_reg(s
, rn
);
10668 if (insn
& (1 << 23))
10669 tcg_gen_subi_i32(tmp
, tmp
, imm
);
10671 tcg_gen_addi_i32(tmp
, tmp
, imm
);
10674 store_reg(s
, rd
, tmp
);
10677 int shifter_out
= 0;
10678 /* modified 12-bit immediate. */
10679 shift
= ((insn
& 0x04000000) >> 23) | ((insn
& 0x7000) >> 12);
10680 imm
= (insn
& 0xff);
10683 /* Nothing to do. */
10685 case 1: /* 00XY00XY */
10688 case 2: /* XY00XY00 */
10692 case 3: /* XYXYXYXY */
10696 default: /* Rotated constant. */
10697 shift
= (shift
<< 1) | (imm
>> 7);
10699 imm
= imm
<< (32 - shift
);
10703 tmp2
= tcg_temp_new_i32();
10704 tcg_gen_movi_i32(tmp2
, imm
);
10705 rn
= (insn
>> 16) & 0xf;
10707 tmp
= tcg_temp_new_i32();
10708 tcg_gen_movi_i32(tmp
, 0);
10710 tmp
= load_reg(s
, rn
);
10712 op
= (insn
>> 21) & 0xf;
10713 if (gen_thumb2_data_op(s
, op
, (insn
& (1 << 20)) != 0,
10714 shifter_out
, tmp
, tmp2
))
10716 tcg_temp_free_i32(tmp2
);
10717 rd
= (insn
>> 8) & 0xf;
10719 store_reg(s
, rd
, tmp
);
10721 tcg_temp_free_i32(tmp
);
10726 case 12: /* Load/store single data item. */
10733 if ((insn
& 0x01100000) == 0x01000000) {
10734 if (disas_neon_ls_insn(s
, insn
)) {
10739 op
= ((insn
>> 21) & 3) | ((insn
>> 22) & 4);
10741 if (!(insn
& (1 << 20))) {
10745 /* Byte or halfword load space with dest == r15 : memory hints.
10746 * Catch them early so we don't emit pointless addressing code.
10747 * This space is a mix of:
10748 * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
10749 * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
10751 * unallocated hints, which must be treated as NOPs
10752 * UNPREDICTABLE space, which we NOP or UNDEF depending on
10753 * which is easiest for the decoding logic
10754 * Some space which must UNDEF
10756 int op1
= (insn
>> 23) & 3;
10757 int op2
= (insn
>> 6) & 0x3f;
10762 /* UNPREDICTABLE, unallocated hint or
10763 * PLD/PLDW/PLI (literal)
10768 return 0; /* PLD/PLDW/PLI or unallocated hint */
10770 if ((op2
== 0) || ((op2
& 0x3c) == 0x30)) {
10771 return 0; /* PLD/PLDW/PLI or unallocated hint */
10773 /* UNDEF space, or an UNPREDICTABLE */
10777 memidx
= get_mem_index(s
);
10779 addr
= tcg_temp_new_i32();
10781 /* s->pc has already been incremented by 4. */
10782 imm
= s
->pc
& 0xfffffffc;
10783 if (insn
& (1 << 23))
10784 imm
+= insn
& 0xfff;
10786 imm
-= insn
& 0xfff;
10787 tcg_gen_movi_i32(addr
, imm
);
10789 addr
= load_reg(s
, rn
);
10790 if (insn
& (1 << 23)) {
10791 /* Positive offset. */
10792 imm
= insn
& 0xfff;
10793 tcg_gen_addi_i32(addr
, addr
, imm
);
10796 switch ((insn
>> 8) & 0xf) {
10797 case 0x0: /* Shifted Register. */
10798 shift
= (insn
>> 4) & 0xf;
10800 tcg_temp_free_i32(addr
);
10803 tmp
= load_reg(s
, rm
);
10805 tcg_gen_shli_i32(tmp
, tmp
, shift
);
10806 tcg_gen_add_i32(addr
, addr
, tmp
);
10807 tcg_temp_free_i32(tmp
);
10809 case 0xc: /* Negative offset. */
10810 tcg_gen_addi_i32(addr
, addr
, -imm
);
10812 case 0xe: /* User privilege. */
10813 tcg_gen_addi_i32(addr
, addr
, imm
);
10814 memidx
= get_a32_user_mem_index(s
);
10816 case 0x9: /* Post-decrement. */
10818 /* Fall through. */
10819 case 0xb: /* Post-increment. */
10823 case 0xd: /* Pre-decrement. */
10825 /* Fall through. */
10826 case 0xf: /* Pre-increment. */
10827 tcg_gen_addi_i32(addr
, addr
, imm
);
10831 tcg_temp_free_i32(addr
);
10837 issinfo
= writeback
? ISSInvalid
: rs
;
10839 if (insn
& (1 << 20)) {
10841 tmp
= tcg_temp_new_i32();
10844 gen_aa32_ld8u_iss(s
, tmp
, addr
, memidx
, issinfo
);
10847 gen_aa32_ld8s_iss(s
, tmp
, addr
, memidx
, issinfo
);
10850 gen_aa32_ld16u_iss(s
, tmp
, addr
, memidx
, issinfo
);
10853 gen_aa32_ld16s_iss(s
, tmp
, addr
, memidx
, issinfo
);
10856 gen_aa32_ld32u_iss(s
, tmp
, addr
, memidx
, issinfo
);
10859 tcg_temp_free_i32(tmp
);
10860 tcg_temp_free_i32(addr
);
10866 store_reg(s
, rs
, tmp
);
10870 tmp
= load_reg(s
, rs
);
10873 gen_aa32_st8_iss(s
, tmp
, addr
, memidx
, issinfo
);
10876 gen_aa32_st16_iss(s
, tmp
, addr
, memidx
, issinfo
);
10879 gen_aa32_st32_iss(s
, tmp
, addr
, memidx
, issinfo
);
10882 tcg_temp_free_i32(tmp
);
10883 tcg_temp_free_i32(addr
);
10886 tcg_temp_free_i32(tmp
);
10889 tcg_gen_addi_i32(addr
, addr
, imm
);
10891 store_reg(s
, rn
, addr
);
10893 tcg_temp_free_i32(addr
);
10905 static void disas_thumb_insn(CPUARMState
*env
, DisasContext
*s
)
10907 uint32_t val
, insn
, op
, rm
, rn
, rd
, shift
, cond
;
10914 if (s
->condexec_mask
) {
10915 cond
= s
->condexec_cond
;
10916 if (cond
!= 0x0e) { /* Skip conditional when condition is AL. */
10917 s
->condlabel
= gen_new_label();
10918 arm_gen_test_cc(cond
^ 1, s
->condlabel
);
10923 insn
= arm_lduw_code(env
, s
->pc
, s
->sctlr_b
);
10926 switch (insn
>> 12) {
10930 op
= (insn
>> 11) & 3;
10933 rn
= (insn
>> 3) & 7;
10934 tmp
= load_reg(s
, rn
);
10935 if (insn
& (1 << 10)) {
10937 tmp2
= tcg_temp_new_i32();
10938 tcg_gen_movi_i32(tmp2
, (insn
>> 6) & 7);
10941 rm
= (insn
>> 6) & 7;
10942 tmp2
= load_reg(s
, rm
);
10944 if (insn
& (1 << 9)) {
10945 if (s
->condexec_mask
)
10946 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
10948 gen_sub_CC(tmp
, tmp
, tmp2
);
10950 if (s
->condexec_mask
)
10951 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
10953 gen_add_CC(tmp
, tmp
, tmp2
);
10955 tcg_temp_free_i32(tmp2
);
10956 store_reg(s
, rd
, tmp
);
10958 /* shift immediate */
10959 rm
= (insn
>> 3) & 7;
10960 shift
= (insn
>> 6) & 0x1f;
10961 tmp
= load_reg(s
, rm
);
10962 gen_arm_shift_im(tmp
, op
, shift
, s
->condexec_mask
== 0);
10963 if (!s
->condexec_mask
)
10965 store_reg(s
, rd
, tmp
);
10969 /* arithmetic large immediate */
10970 op
= (insn
>> 11) & 3;
10971 rd
= (insn
>> 8) & 0x7;
10972 if (op
== 0) { /* mov */
10973 tmp
= tcg_temp_new_i32();
10974 tcg_gen_movi_i32(tmp
, insn
& 0xff);
10975 if (!s
->condexec_mask
)
10977 store_reg(s
, rd
, tmp
);
10979 tmp
= load_reg(s
, rd
);
10980 tmp2
= tcg_temp_new_i32();
10981 tcg_gen_movi_i32(tmp2
, insn
& 0xff);
10984 gen_sub_CC(tmp
, tmp
, tmp2
);
10985 tcg_temp_free_i32(tmp
);
10986 tcg_temp_free_i32(tmp2
);
10989 if (s
->condexec_mask
)
10990 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
10992 gen_add_CC(tmp
, tmp
, tmp2
);
10993 tcg_temp_free_i32(tmp2
);
10994 store_reg(s
, rd
, tmp
);
10997 if (s
->condexec_mask
)
10998 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
11000 gen_sub_CC(tmp
, tmp
, tmp2
);
11001 tcg_temp_free_i32(tmp2
);
11002 store_reg(s
, rd
, tmp
);
11008 if (insn
& (1 << 11)) {
11009 rd
= (insn
>> 8) & 7;
11010 /* load pc-relative. Bit 1 of PC is ignored. */
11011 val
= s
->pc
+ 2 + ((insn
& 0xff) * 4);
11012 val
&= ~(uint32_t)2;
11013 addr
= tcg_temp_new_i32();
11014 tcg_gen_movi_i32(addr
, val
);
11015 tmp
= tcg_temp_new_i32();
11016 gen_aa32_ld32u_iss(s
, tmp
, addr
, get_mem_index(s
),
11018 tcg_temp_free_i32(addr
);
11019 store_reg(s
, rd
, tmp
);
11022 if (insn
& (1 << 10)) {
11023 /* data processing extended or blx */
11024 rd
= (insn
& 7) | ((insn
>> 4) & 8);
11025 rm
= (insn
>> 3) & 0xf;
11026 op
= (insn
>> 8) & 3;
11029 tmp
= load_reg(s
, rd
);
11030 tmp2
= load_reg(s
, rm
);
11031 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
11032 tcg_temp_free_i32(tmp2
);
11033 store_reg(s
, rd
, tmp
);
11036 tmp
= load_reg(s
, rd
);
11037 tmp2
= load_reg(s
, rm
);
11038 gen_sub_CC(tmp
, tmp
, tmp2
);
11039 tcg_temp_free_i32(tmp2
);
11040 tcg_temp_free_i32(tmp
);
11042 case 2: /* mov/cpy */
11043 tmp
= load_reg(s
, rm
);
11044 store_reg(s
, rd
, tmp
);
11046 case 3:/* branch [and link] exchange thumb register */
11047 tmp
= load_reg(s
, rm
);
11048 if (insn
& (1 << 7)) {
11050 val
= (uint32_t)s
->pc
| 1;
11051 tmp2
= tcg_temp_new_i32();
11052 tcg_gen_movi_i32(tmp2
, val
);
11053 store_reg(s
, 14, tmp2
);
11055 /* already thumb, no need to check */
11062 /* data processing register */
11064 rm
= (insn
>> 3) & 7;
11065 op
= (insn
>> 6) & 0xf;
11066 if (op
== 2 || op
== 3 || op
== 4 || op
== 7) {
11067 /* the shift/rotate ops want the operands backwards */
11076 if (op
== 9) { /* neg */
11077 tmp
= tcg_temp_new_i32();
11078 tcg_gen_movi_i32(tmp
, 0);
11079 } else if (op
!= 0xf) { /* mvn doesn't read its first operand */
11080 tmp
= load_reg(s
, rd
);
11082 TCGV_UNUSED_I32(tmp
);
11085 tmp2
= load_reg(s
, rm
);
11087 case 0x0: /* and */
11088 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
11089 if (!s
->condexec_mask
)
11092 case 0x1: /* eor */
11093 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
11094 if (!s
->condexec_mask
)
11097 case 0x2: /* lsl */
11098 if (s
->condexec_mask
) {
11099 gen_shl(tmp2
, tmp2
, tmp
);
11101 gen_helper_shl_cc(tmp2
, cpu_env
, tmp2
, tmp
);
11102 gen_logic_CC(tmp2
);
11105 case 0x3: /* lsr */
11106 if (s
->condexec_mask
) {
11107 gen_shr(tmp2
, tmp2
, tmp
);
11109 gen_helper_shr_cc(tmp2
, cpu_env
, tmp2
, tmp
);
11110 gen_logic_CC(tmp2
);
11113 case 0x4: /* asr */
11114 if (s
->condexec_mask
) {
11115 gen_sar(tmp2
, tmp2
, tmp
);
11117 gen_helper_sar_cc(tmp2
, cpu_env
, tmp2
, tmp
);
11118 gen_logic_CC(tmp2
);
11121 case 0x5: /* adc */
11122 if (s
->condexec_mask
) {
11123 gen_adc(tmp
, tmp2
);
11125 gen_adc_CC(tmp
, tmp
, tmp2
);
11128 case 0x6: /* sbc */
11129 if (s
->condexec_mask
) {
11130 gen_sub_carry(tmp
, tmp
, tmp2
);
11132 gen_sbc_CC(tmp
, tmp
, tmp2
);
11135 case 0x7: /* ror */
11136 if (s
->condexec_mask
) {
11137 tcg_gen_andi_i32(tmp
, tmp
, 0x1f);
11138 tcg_gen_rotr_i32(tmp2
, tmp2
, tmp
);
11140 gen_helper_ror_cc(tmp2
, cpu_env
, tmp2
, tmp
);
11141 gen_logic_CC(tmp2
);
11144 case 0x8: /* tst */
11145 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
11149 case 0x9: /* neg */
11150 if (s
->condexec_mask
)
11151 tcg_gen_neg_i32(tmp
, tmp2
);
11153 gen_sub_CC(tmp
, tmp
, tmp2
);
11155 case 0xa: /* cmp */
11156 gen_sub_CC(tmp
, tmp
, tmp2
);
11159 case 0xb: /* cmn */
11160 gen_add_CC(tmp
, tmp
, tmp2
);
11163 case 0xc: /* orr */
11164 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
11165 if (!s
->condexec_mask
)
11168 case 0xd: /* mul */
11169 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
11170 if (!s
->condexec_mask
)
11173 case 0xe: /* bic */
11174 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
11175 if (!s
->condexec_mask
)
11178 case 0xf: /* mvn */
11179 tcg_gen_not_i32(tmp2
, tmp2
);
11180 if (!s
->condexec_mask
)
11181 gen_logic_CC(tmp2
);
11188 store_reg(s
, rm
, tmp2
);
11190 tcg_temp_free_i32(tmp
);
11192 store_reg(s
, rd
, tmp
);
11193 tcg_temp_free_i32(tmp2
);
11196 tcg_temp_free_i32(tmp
);
11197 tcg_temp_free_i32(tmp2
);
11202 /* load/store register offset. */
11204 rn
= (insn
>> 3) & 7;
11205 rm
= (insn
>> 6) & 7;
11206 op
= (insn
>> 9) & 7;
11207 addr
= load_reg(s
, rn
);
11208 tmp
= load_reg(s
, rm
);
11209 tcg_gen_add_i32(addr
, addr
, tmp
);
11210 tcg_temp_free_i32(tmp
);
11212 if (op
< 3) { /* store */
11213 tmp
= load_reg(s
, rd
);
11215 tmp
= tcg_temp_new_i32();
11220 gen_aa32_st32_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11223 gen_aa32_st16_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11226 gen_aa32_st8_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11228 case 3: /* ldrsb */
11229 gen_aa32_ld8s_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11232 gen_aa32_ld32u_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11235 gen_aa32_ld16u_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11238 gen_aa32_ld8u_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11240 case 7: /* ldrsh */
11241 gen_aa32_ld16s_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11244 if (op
>= 3) { /* load */
11245 store_reg(s
, rd
, tmp
);
11247 tcg_temp_free_i32(tmp
);
11249 tcg_temp_free_i32(addr
);
11253 /* load/store word immediate offset */
11255 rn
= (insn
>> 3) & 7;
11256 addr
= load_reg(s
, rn
);
11257 val
= (insn
>> 4) & 0x7c;
11258 tcg_gen_addi_i32(addr
, addr
, val
);
11260 if (insn
& (1 << 11)) {
11262 tmp
= tcg_temp_new_i32();
11263 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
11264 store_reg(s
, rd
, tmp
);
11267 tmp
= load_reg(s
, rd
);
11268 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
11269 tcg_temp_free_i32(tmp
);
11271 tcg_temp_free_i32(addr
);
11275 /* load/store byte immediate offset */
11277 rn
= (insn
>> 3) & 7;
11278 addr
= load_reg(s
, rn
);
11279 val
= (insn
>> 6) & 0x1f;
11280 tcg_gen_addi_i32(addr
, addr
, val
);
11282 if (insn
& (1 << 11)) {
11284 tmp
= tcg_temp_new_i32();
11285 gen_aa32_ld8u_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11286 store_reg(s
, rd
, tmp
);
11289 tmp
= load_reg(s
, rd
);
11290 gen_aa32_st8_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11291 tcg_temp_free_i32(tmp
);
11293 tcg_temp_free_i32(addr
);
11297 /* load/store halfword immediate offset */
11299 rn
= (insn
>> 3) & 7;
11300 addr
= load_reg(s
, rn
);
11301 val
= (insn
>> 5) & 0x3e;
11302 tcg_gen_addi_i32(addr
, addr
, val
);
11304 if (insn
& (1 << 11)) {
11306 tmp
= tcg_temp_new_i32();
11307 gen_aa32_ld16u_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11308 store_reg(s
, rd
, tmp
);
11311 tmp
= load_reg(s
, rd
);
11312 gen_aa32_st16_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11313 tcg_temp_free_i32(tmp
);
11315 tcg_temp_free_i32(addr
);
11319 /* load/store from stack */
11320 rd
= (insn
>> 8) & 7;
11321 addr
= load_reg(s
, 13);
11322 val
= (insn
& 0xff) * 4;
11323 tcg_gen_addi_i32(addr
, addr
, val
);
11325 if (insn
& (1 << 11)) {
11327 tmp
= tcg_temp_new_i32();
11328 gen_aa32_ld32u_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11329 store_reg(s
, rd
, tmp
);
11332 tmp
= load_reg(s
, rd
);
11333 gen_aa32_st32_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11334 tcg_temp_free_i32(tmp
);
11336 tcg_temp_free_i32(addr
);
11340 /* add to high reg */
11341 rd
= (insn
>> 8) & 7;
11342 if (insn
& (1 << 11)) {
11344 tmp
= load_reg(s
, 13);
11346 /* PC. bit 1 is ignored. */
11347 tmp
= tcg_temp_new_i32();
11348 tcg_gen_movi_i32(tmp
, (s
->pc
+ 2) & ~(uint32_t)2);
11350 val
= (insn
& 0xff) * 4;
11351 tcg_gen_addi_i32(tmp
, tmp
, val
);
11352 store_reg(s
, rd
, tmp
);
11357 op
= (insn
>> 8) & 0xf;
11360 /* adjust stack pointer */
11361 tmp
= load_reg(s
, 13);
11362 val
= (insn
& 0x7f) * 4;
11363 if (insn
& (1 << 7))
11364 val
= -(int32_t)val
;
11365 tcg_gen_addi_i32(tmp
, tmp
, val
);
11366 store_reg(s
, 13, tmp
);
11369 case 2: /* sign/zero extend. */
11372 rm
= (insn
>> 3) & 7;
11373 tmp
= load_reg(s
, rm
);
11374 switch ((insn
>> 6) & 3) {
11375 case 0: gen_sxth(tmp
); break;
11376 case 1: gen_sxtb(tmp
); break;
11377 case 2: gen_uxth(tmp
); break;
11378 case 3: gen_uxtb(tmp
); break;
11380 store_reg(s
, rd
, tmp
);
11382 case 4: case 5: case 0xc: case 0xd:
11384 addr
= load_reg(s
, 13);
11385 if (insn
& (1 << 8))
11389 for (i
= 0; i
< 8; i
++) {
11390 if (insn
& (1 << i
))
11393 if ((insn
& (1 << 11)) == 0) {
11394 tcg_gen_addi_i32(addr
, addr
, -offset
);
11396 for (i
= 0; i
< 8; i
++) {
11397 if (insn
& (1 << i
)) {
11398 if (insn
& (1 << 11)) {
11400 tmp
= tcg_temp_new_i32();
11401 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
11402 store_reg(s
, i
, tmp
);
11405 tmp
= load_reg(s
, i
);
11406 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
11407 tcg_temp_free_i32(tmp
);
11409 /* advance to the next address. */
11410 tcg_gen_addi_i32(addr
, addr
, 4);
11413 TCGV_UNUSED_I32(tmp
);
11414 if (insn
& (1 << 8)) {
11415 if (insn
& (1 << 11)) {
11417 tmp
= tcg_temp_new_i32();
11418 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
11419 /* don't set the pc until the rest of the instruction
11423 tmp
= load_reg(s
, 14);
11424 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
11425 tcg_temp_free_i32(tmp
);
11427 tcg_gen_addi_i32(addr
, addr
, 4);
11429 if ((insn
& (1 << 11)) == 0) {
11430 tcg_gen_addi_i32(addr
, addr
, -offset
);
11432 /* write back the new stack pointer */
11433 store_reg(s
, 13, addr
);
11434 /* set the new PC value */
11435 if ((insn
& 0x0900) == 0x0900) {
11436 store_reg_from_load(s
, 15, tmp
);
11440 case 1: case 3: case 9: case 11: /* czb */
11442 tmp
= load_reg(s
, rm
);
11443 s
->condlabel
= gen_new_label();
11445 if (insn
& (1 << 11))
11446 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, s
->condlabel
);
11448 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, s
->condlabel
);
11449 tcg_temp_free_i32(tmp
);
11450 offset
= ((insn
& 0xf8) >> 2) | (insn
& 0x200) >> 3;
11451 val
= (uint32_t)s
->pc
+ 2;
11456 case 15: /* IT, nop-hint. */
11457 if ((insn
& 0xf) == 0) {
11458 gen_nop_hint(s
, (insn
>> 4) & 0xf);
11462 s
->condexec_cond
= (insn
>> 4) & 0xe;
11463 s
->condexec_mask
= insn
& 0x1f;
11464 /* No actual code generated for this insn, just setup state. */
11467 case 0xe: /* bkpt */
11469 int imm8
= extract32(insn
, 0, 8);
11471 gen_exception_insn(s
, 2, EXCP_BKPT
, syn_aa32_bkpt(imm8
, true),
11472 default_exception_el(s
));
11476 case 0xa: /* rev, and hlt */
11478 int op1
= extract32(insn
, 6, 2);
11482 int imm6
= extract32(insn
, 0, 6);
11488 /* Otherwise this is rev */
11490 rn
= (insn
>> 3) & 0x7;
11492 tmp
= load_reg(s
, rn
);
11494 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
11495 case 1: gen_rev16(tmp
); break;
11496 case 3: gen_revsh(tmp
); break;
11498 g_assert_not_reached();
11500 store_reg(s
, rd
, tmp
);
11505 switch ((insn
>> 5) & 7) {
11509 if (((insn
>> 3) & 1) != !!(s
->be_data
== MO_BE
)) {
11510 gen_helper_setend(cpu_env
);
11511 s
->is_jmp
= DISAS_UPDATE
;
11520 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
11521 tmp
= tcg_const_i32((insn
& (1 << 4)) != 0);
11524 addr
= tcg_const_i32(19);
11525 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
11526 tcg_temp_free_i32(addr
);
11530 addr
= tcg_const_i32(16);
11531 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
11532 tcg_temp_free_i32(addr
);
11534 tcg_temp_free_i32(tmp
);
11537 if (insn
& (1 << 4)) {
11538 shift
= CPSR_A
| CPSR_I
| CPSR_F
;
11542 gen_set_psr_im(s
, ((insn
& 7) << 6), 0, shift
);
11557 /* load/store multiple */
11558 TCGv_i32 loaded_var
;
11559 TCGV_UNUSED_I32(loaded_var
);
11560 rn
= (insn
>> 8) & 0x7;
11561 addr
= load_reg(s
, rn
);
11562 for (i
= 0; i
< 8; i
++) {
11563 if (insn
& (1 << i
)) {
11564 if (insn
& (1 << 11)) {
11566 tmp
= tcg_temp_new_i32();
11567 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
11571 store_reg(s
, i
, tmp
);
11575 tmp
= load_reg(s
, i
);
11576 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
11577 tcg_temp_free_i32(tmp
);
11579 /* advance to the next address */
11580 tcg_gen_addi_i32(addr
, addr
, 4);
11583 if ((insn
& (1 << rn
)) == 0) {
11584 /* base reg not in list: base register writeback */
11585 store_reg(s
, rn
, addr
);
11587 /* base reg in list: if load, complete it now */
11588 if (insn
& (1 << 11)) {
11589 store_reg(s
, rn
, loaded_var
);
11591 tcg_temp_free_i32(addr
);
11596 /* conditional branch or swi */
11597 cond
= (insn
>> 8) & 0xf;
11603 gen_set_pc_im(s
, s
->pc
);
11604 s
->svc_imm
= extract32(insn
, 0, 8);
11605 s
->is_jmp
= DISAS_SWI
;
11608 /* generate a conditional jump to next instruction */
11609 s
->condlabel
= gen_new_label();
11610 arm_gen_test_cc(cond
^ 1, s
->condlabel
);
11613 /* jump to the offset */
11614 val
= (uint32_t)s
->pc
+ 2;
11615 offset
= ((int32_t)insn
<< 24) >> 24;
11616 val
+= offset
<< 1;
11621 if (insn
& (1 << 11)) {
11622 if (disas_thumb2_insn(env
, s
, insn
))
11626 /* unconditional branch */
11627 val
= (uint32_t)s
->pc
;
11628 offset
= ((int32_t)insn
<< 21) >> 21;
11629 val
+= (offset
<< 1) + 2;
11634 if (disas_thumb2_insn(env
, s
, insn
))
11640 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
11641 default_exception_el(s
));
11645 gen_exception_insn(s
, 2, EXCP_UDEF
, syn_uncategorized(),
11646 default_exception_el(s
));
11649 static bool insn_crosses_page(CPUARMState
*env
, DisasContext
*s
)
11651 /* Return true if the insn at dc->pc might cross a page boundary.
11652 * (False positives are OK, false negatives are not.)
11656 if ((s
->pc
& 3) == 0) {
11657 /* At a 4-aligned address we can't be crossing a page */
11661 /* This must be a Thumb insn */
11662 insn
= arm_lduw_code(env
, s
->pc
, s
->sctlr_b
);
11664 if ((insn
>> 11) >= 0x1d) {
11665 /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the
11666 * First half of a 32-bit Thumb insn. Thumb-1 cores might
11667 * end up actually treating this as two 16-bit insns (see the
11668 * code at the start of disas_thumb2_insn()) but we don't bother
11669 * to check for that as it is unlikely, and false positives here
11674 /* Definitely a 16-bit insn, can't be crossing a page. */
11678 /* generate intermediate code for basic block 'tb'. */
11679 void gen_intermediate_code(CPUARMState
*env
, TranslationBlock
*tb
)
11681 ARMCPU
*cpu
= arm_env_get_cpu(env
);
11682 CPUState
*cs
= CPU(cpu
);
11683 DisasContext dc1
, *dc
= &dc1
;
11684 target_ulong pc_start
;
11685 target_ulong next_page_start
;
11690 /* generate intermediate code */
11692 /* The A64 decoder has its own top level loop, because it doesn't need
11693 * the A32/T32 complexity to do with conditional execution/IT blocks/etc.
11695 if (ARM_TBFLAG_AARCH64_STATE(tb
->flags
)) {
11696 gen_intermediate_code_a64(cpu
, tb
);
11704 dc
->is_jmp
= DISAS_NEXT
;
11706 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
11710 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
11711 * there is no secure EL1, so we route exceptions to EL3.
11713 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
11714 !arm_el_is_aa64(env
, 3);
11715 dc
->thumb
= ARM_TBFLAG_THUMB(tb
->flags
);
11716 dc
->sctlr_b
= ARM_TBFLAG_SCTLR_B(tb
->flags
);
11717 dc
->be_data
= ARM_TBFLAG_BE_DATA(tb
->flags
) ? MO_BE
: MO_LE
;
11718 dc
->condexec_mask
= (ARM_TBFLAG_CONDEXEC(tb
->flags
) & 0xf) << 1;
11719 dc
->condexec_cond
= ARM_TBFLAG_CONDEXEC(tb
->flags
) >> 4;
11720 dc
->mmu_idx
= ARM_TBFLAG_MMUIDX(tb
->flags
);
11721 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
11722 #if !defined(CONFIG_USER_ONLY)
11723 dc
->user
= (dc
->current_el
== 0);
11725 dc
->ns
= ARM_TBFLAG_NS(tb
->flags
);
11726 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(tb
->flags
);
11727 dc
->vfp_enabled
= ARM_TBFLAG_VFPEN(tb
->flags
);
11728 dc
->vec_len
= ARM_TBFLAG_VECLEN(tb
->flags
);
11729 dc
->vec_stride
= ARM_TBFLAG_VECSTRIDE(tb
->flags
);
11730 dc
->c15_cpar
= ARM_TBFLAG_XSCALE_CPAR(tb
->flags
);
11731 dc
->cp_regs
= cpu
->cp_regs
;
11732 dc
->features
= env
->features
;
11734 /* Single step state. The code-generation logic here is:
11736 * generate code with no special handling for single-stepping (except
11737 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
11738 * this happens anyway because those changes are all system register or
11740 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
11741 * emit code for one insn
11742 * emit code to clear PSTATE.SS
11743 * emit code to generate software step exception for completed step
11744 * end TB (as usual for having generated an exception)
11745 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
11746 * emit code to generate a software step exception
11749 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(tb
->flags
);
11750 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(tb
->flags
);
11751 dc
->is_ldex
= false;
11752 dc
->ss_same_el
= false; /* Can't be true since EL_d must be AArch64 */
11754 cpu_F0s
= tcg_temp_new_i32();
11755 cpu_F1s
= tcg_temp_new_i32();
11756 cpu_F0d
= tcg_temp_new_i64();
11757 cpu_F1d
= tcg_temp_new_i64();
11760 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
11761 cpu_M0
= tcg_temp_new_i64();
11762 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
11764 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
11765 if (max_insns
== 0) {
11766 max_insns
= CF_COUNT_MASK
;
11768 if (max_insns
> TCG_MAX_INSNS
) {
11769 max_insns
= TCG_MAX_INSNS
;
11774 tcg_clear_temp_count();
11776 /* A note on handling of the condexec (IT) bits:
11778 * We want to avoid the overhead of having to write the updated condexec
11779 * bits back to the CPUARMState for every instruction in an IT block. So:
11780 * (1) if the condexec bits are not already zero then we write
11781 * zero back into the CPUARMState now. This avoids complications trying
11782 * to do it at the end of the block. (For example if we don't do this
11783 * it's hard to identify whether we can safely skip writing condexec
11784 * at the end of the TB, which we definitely want to do for the case
11785 * where a TB doesn't do anything with the IT state at all.)
11786 * (2) if we are going to leave the TB then we call gen_set_condexec()
11787 * which will write the correct value into CPUARMState if zero is wrong.
11788 * This is done both for leaving the TB at the end, and for leaving
11789 * it because of an exception we know will happen, which is done in
11790 * gen_exception_insn(). The latter is necessary because we need to
11791 * leave the TB with the PC/IT state just prior to execution of the
11792 * instruction which caused the exception.
11793 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
11794 * then the CPUARMState will be wrong and we need to reset it.
11795 * This is handled in the same way as restoration of the
11796 * PC in these situations; we save the value of the condexec bits
11797 * for each PC via tcg_gen_insn_start(), and restore_state_to_opc()
11798 * then uses this to restore them after an exception.
11800 * Note that there are no instructions which can read the condexec
11801 * bits, and none which can write non-static values to them, so
11802 * we don't need to care about whether CPUARMState is correct in the
11806 /* Reset the conditional execution bits immediately. This avoids
11807 complications trying to do it at the end of the block. */
11808 if (dc
->condexec_mask
|| dc
->condexec_cond
)
11810 TCGv_i32 tmp
= tcg_temp_new_i32();
11811 tcg_gen_movi_i32(tmp
, 0);
11812 store_cpu_field(tmp
, condexec_bits
);
11815 dc
->insn_start_idx
= tcg_op_buf_count();
11816 tcg_gen_insn_start(dc
->pc
,
11817 (dc
->condexec_cond
<< 4) | (dc
->condexec_mask
>> 1),
11821 #ifdef CONFIG_USER_ONLY
11822 /* Intercept jump to the magic kernel page. */
11823 if (dc
->pc
>= 0xffff0000) {
11824 /* We always get here via a jump, so know we are not in a
11825 conditional execution block. */
11826 gen_exception_internal(EXCP_KERNEL_TRAP
);
11827 dc
->is_jmp
= DISAS_EXC
;
11831 if (arm_dc_feature(dc
, ARM_FEATURE_M
)) {
11832 /* Branches to the magic exception-return addresses should
11833 * already have been caught via the arm_v7m_unassigned_access hook,
11834 * and never get here.
11836 assert(dc
->pc
< 0xfffffff0);
11840 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
11842 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
11843 if (bp
->pc
== dc
->pc
) {
11844 if (bp
->flags
& BP_CPU
) {
11845 gen_set_condexec(dc
);
11846 gen_set_pc_im(dc
, dc
->pc
);
11847 gen_helper_check_breakpoints(cpu_env
);
11848 /* End the TB early; it's likely not going to be executed */
11849 dc
->is_jmp
= DISAS_UPDATE
;
11851 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
11852 /* The address covered by the breakpoint must be
11853 included in [tb->pc, tb->pc + tb->size) in order
11854 to for it to be properly cleared -- thus we
11855 increment the PC here so that the logic setting
11856 tb->size below does the right thing. */
11857 /* TODO: Advance PC by correct instruction length to
11858 * avoid disassembler error messages */
11860 goto done_generating
;
11867 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
11871 if (dc
->ss_active
&& !dc
->pstate_ss
) {
11872 /* Singlestep state is Active-pending.
11873 * If we're in this state at the start of a TB then either
11874 * a) we just took an exception to an EL which is being debugged
11875 * and this is the first insn in the exception handler
11876 * b) debug exceptions were masked and we just unmasked them
11877 * without changing EL (eg by clearing PSTATE.D)
11878 * In either case we're going to take a swstep exception in the
11879 * "did not step an insn" case, and so the syndrome ISV and EX
11880 * bits should be zero.
11882 assert(num_insns
== 1);
11883 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
11884 default_exception_el(dc
));
11885 goto done_generating
;
11889 disas_thumb_insn(env
, dc
);
11890 if (dc
->condexec_mask
) {
11891 dc
->condexec_cond
= (dc
->condexec_cond
& 0xe)
11892 | ((dc
->condexec_mask
>> 4) & 1);
11893 dc
->condexec_mask
= (dc
->condexec_mask
<< 1) & 0x1f;
11894 if (dc
->condexec_mask
== 0) {
11895 dc
->condexec_cond
= 0;
11899 unsigned int insn
= arm_ldl_code(env
, dc
->pc
, dc
->sctlr_b
);
11901 disas_arm_insn(dc
, insn
);
11904 if (dc
->condjmp
&& !dc
->is_jmp
) {
11905 gen_set_label(dc
->condlabel
);
11909 if (tcg_check_temp_count()) {
11910 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
11914 /* Translation stops when a conditional branch is encountered.
11915 * Otherwise the subsequent code could get translated several times.
11916 * Also stop translation when a page boundary is reached. This
11917 * ensures prefetch aborts occur at the right place. */
11919 /* We want to stop the TB if the next insn starts in a new page,
11920 * or if it spans between this page and the next. This means that
11921 * if we're looking at the last halfword in the page we need to
11922 * see if it's a 16-bit Thumb insn (which will fit in this TB)
11923 * or a 32-bit Thumb insn (which won't).
11924 * This is to avoid generating a silly TB with a single 16-bit insn
11925 * in it at the end of this page (which would execute correctly
11926 * but isn't very efficient).
11928 end_of_page
= (dc
->pc
>= next_page_start
) ||
11929 ((dc
->pc
>= next_page_start
- 3) && insn_crosses_page(env
, dc
));
11931 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
11932 !cs
->singlestep_enabled
&&
11936 num_insns
< max_insns
);
11938 if (tb
->cflags
& CF_LAST_IO
) {
11940 /* FIXME: This can theoretically happen with self-modifying
11942 cpu_abort(cs
, "IO on conditional branch instruction");
11947 /* At this stage dc->condjmp will only be set when the skipped
11948 instruction was a conditional branch or trap, and the PC has
11949 already been written. */
11950 if (unlikely(cs
->singlestep_enabled
|| dc
->ss_active
)) {
11951 /* Unconditional and "condition passed" instruction codepath. */
11952 gen_set_condexec(dc
);
11953 switch (dc
->is_jmp
) {
11955 gen_ss_advance(dc
);
11956 gen_exception(EXCP_SWI
, syn_aa32_svc(dc
->svc_imm
, dc
->thumb
),
11957 default_exception_el(dc
));
11960 gen_ss_advance(dc
);
11961 gen_exception(EXCP_HVC
, syn_aa32_hvc(dc
->svc_imm
), 2);
11964 gen_ss_advance(dc
);
11965 gen_exception(EXCP_SMC
, syn_aa32_smc(), 3);
11969 gen_set_pc_im(dc
, dc
->pc
);
11972 if (dc
->ss_active
) {
11973 gen_step_complete_exception(dc
);
11975 /* FIXME: Single stepping a WFI insn will not halt
11977 gen_exception_internal(EXCP_DEBUG
);
11981 /* "Condition failed" instruction codepath. */
11982 gen_set_label(dc
->condlabel
);
11983 gen_set_condexec(dc
);
11984 gen_set_pc_im(dc
, dc
->pc
);
11985 if (dc
->ss_active
) {
11986 gen_step_complete_exception(dc
);
11988 gen_exception_internal(EXCP_DEBUG
);
11992 /* While branches must always occur at the end of an IT block,
11993 there are a few other things that can cause us to terminate
11994 the TB in the middle of an IT block:
11995 - Exception generating instructions (bkpt, swi, undefined).
11997 - Hardware watchpoints.
11998 Hardware breakpoints have already been handled and skip this code.
12000 gen_set_condexec(dc
);
12001 switch(dc
->is_jmp
) {
12003 gen_goto_tb(dc
, 1, dc
->pc
);
12006 gen_set_pc_im(dc
, dc
->pc
);
12010 /* indicate that the hash table must be used to find the next TB */
12011 tcg_gen_exit_tb(0);
12013 case DISAS_TB_JUMP
:
12014 /* nothing more to generate */
12017 gen_helper_wfi(cpu_env
);
12018 /* The helper doesn't necessarily throw an exception, but we
12019 * must go back to the main loop to check for interrupts anyway.
12021 tcg_gen_exit_tb(0);
12024 gen_helper_wfe(cpu_env
);
12027 gen_helper_yield(cpu_env
);
12030 gen_exception(EXCP_SWI
, syn_aa32_svc(dc
->svc_imm
, dc
->thumb
),
12031 default_exception_el(dc
));
12034 gen_exception(EXCP_HVC
, syn_aa32_hvc(dc
->svc_imm
), 2);
12037 gen_exception(EXCP_SMC
, syn_aa32_smc(), 3);
12041 gen_set_label(dc
->condlabel
);
12042 gen_set_condexec(dc
);
12043 gen_goto_tb(dc
, 1, dc
->pc
);
12049 gen_tb_end(tb
, num_insns
);
12052 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
) &&
12053 qemu_log_in_addr_range(pc_start
)) {
12055 qemu_log("----------------\n");
12056 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
12057 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
,
12058 dc
->thumb
| (dc
->sctlr_b
<< 1));
12063 tb
->size
= dc
->pc
- pc_start
;
12064 tb
->icount
= num_insns
;
12067 static const char *cpu_mode_names
[16] = {
12068 "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
12069 "???", "???", "hyp", "und", "???", "???", "???", "sys"
12072 void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
12075 ARMCPU
*cpu
= ARM_CPU(cs
);
12076 CPUARMState
*env
= &cpu
->env
;
12079 const char *ns_status
;
12082 aarch64_cpu_dump_state(cs
, f
, cpu_fprintf
, flags
);
12086 for(i
=0;i
<16;i
++) {
12087 cpu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
12089 cpu_fprintf(f
, "\n");
12091 cpu_fprintf(f
, " ");
12093 psr
= cpsr_read(env
);
12095 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
12096 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
12097 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
12102 cpu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
12104 psr
& (1 << 31) ? 'N' : '-',
12105 psr
& (1 << 30) ? 'Z' : '-',
12106 psr
& (1 << 29) ? 'C' : '-',
12107 psr
& (1 << 28) ? 'V' : '-',
12108 psr
& CPSR_T
? 'T' : 'A',
12110 cpu_mode_names
[psr
& 0xf], (psr
& 0x10) ? 32 : 26);
12112 if (flags
& CPU_DUMP_FPU
) {
12113 int numvfpregs
= 0;
12114 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
12117 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
12120 for (i
= 0; i
< numvfpregs
; i
++) {
12121 uint64_t v
= float64_val(env
->vfp
.regs
[i
]);
12122 cpu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
12123 i
* 2, (uint32_t)v
,
12124 i
* 2 + 1, (uint32_t)(v
>> 32),
12127 cpu_fprintf(f
, "FPSCR: %08x\n", (int)env
->vfp
.xregs
[ARM_VFP_FPSCR
]);
12131 void restore_state_to_opc(CPUARMState
*env
, TranslationBlock
*tb
,
12132 target_ulong
*data
)
12136 env
->condexec_bits
= 0;
12137 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;
12139 env
->regs
[15] = data
[0];
12140 env
->condexec_bits
= data
[1];
12141 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;