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s390x/css: clear IO irqs when generating IPI CRW
[qemu/kevin.git] / hw / scsi / megasas.c
bloba9ffc326826e5d4964733b26238e556fd56bd6d6
1 /*
2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
3 * Based on the linux driver code at drivers/scsi/megaraid
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "hw/hw.h"
23 #include "hw/pci/pci.h"
24 #include "sysemu/dma.h"
25 #include "sysemu/block-backend.h"
26 #include "hw/pci/msi.h"
27 #include "hw/pci/msix.h"
28 #include "qemu/iov.h"
29 #include "hw/scsi/scsi.h"
30 #include "block/scsi.h"
31 #include "trace.h"
32
33 #include "mfi.h"
34
35 #define MEGASAS_VERSION_GEN1 "1.70"
36 #define MEGASAS_VERSION_GEN2 "1.80"
37 #define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
38 #define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */
39 #define MEGASAS_GEN2_DEFAULT_FRAMES 1008 /* Windows requires this */
40 #define MEGASAS_MAX_SGE 128 /* Firmware limit */
41 #define MEGASAS_DEFAULT_SGE 80
42 #define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */
43 #define MEGASAS_MAX_ARRAYS 128
44
45 #define MEGASAS_HBA_SERIAL "QEMU123456"
46 #define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
47 #define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
48
49 #define MEGASAS_FLAG_USE_JBOD 0
50 #define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD)
51 #define MEGASAS_FLAG_USE_MSI 1
52 #define MEGASAS_MASK_USE_MSI (1 << MEGASAS_FLAG_USE_MSI)
53 #define MEGASAS_FLAG_USE_MSIX 2
54 #define MEGASAS_MASK_USE_MSIX (1 << MEGASAS_FLAG_USE_MSIX)
55 #define MEGASAS_FLAG_USE_QUEUE64 3
56 #define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64)
57
58 static const char *mfi_frame_desc[] = {
59 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
60 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"};
61
62 typedef struct MegasasCmd {
63 uint32_t index;
64 uint16_t flags;
65 uint16_t count;
66 uint64_t context;
67
68 hwaddr pa;
69 hwaddr pa_size;
70 union mfi_frame *frame;
71 SCSIRequest *req;
72 QEMUSGList qsg;
73 void *iov_buf;
74 size_t iov_size;
75 size_t iov_offset;
76 struct MegasasState *state;
77 } MegasasCmd;
78
79 typedef struct MegasasState {
80 /*< private >*/
81 PCIDevice parent_obj;
82 /*< public >*/
83
84 MemoryRegion mmio_io;
85 MemoryRegion port_io;
86 MemoryRegion queue_io;
87 uint32_t frame_hi;
88
89 int fw_state;
90 uint32_t fw_sge;
91 uint32_t fw_cmds;
92 uint32_t flags;
93 int fw_luns;
94 int intr_mask;
95 int doorbell;
96 int busy;
97 int diag;
98 int adp_reset;
99
100 MegasasCmd *event_cmd;
101 int event_locale;
102 int event_class;
103 int event_count;
104 int shutdown_event;
105 int boot_event;
106
107 uint64_t sas_addr;
108 char *hba_serial;
109
110 uint64_t reply_queue_pa;
111 void *reply_queue;
112 int reply_queue_len;
113 int reply_queue_head;
114 int reply_queue_tail;
115 uint64_t consumer_pa;
116 uint64_t producer_pa;
117
118 MegasasCmd frames[MEGASAS_MAX_FRAMES];
119 DECLARE_BITMAP(frame_map, MEGASAS_MAX_FRAMES);
120 SCSIBus bus;
121 } MegasasState;
122
123 typedef struct MegasasBaseClass {
124 PCIDeviceClass parent_class;
125 const char *product_name;
126 const char *product_version;
127 int mmio_bar;
128 int ioport_bar;
129 int osts;
130 } MegasasBaseClass;
131
132 #define TYPE_MEGASAS_BASE "megasas-base"
133 #define TYPE_MEGASAS_GEN1 "megasas"
134 #define TYPE_MEGASAS_GEN2 "megasas-gen2"
135
136 #define MEGASAS(obj) \
137 OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS_BASE)
138
139 #define MEGASAS_DEVICE_CLASS(oc) \
140 OBJECT_CLASS_CHECK(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
141 #define MEGASAS_DEVICE_GET_CLASS(oc) \
142 OBJECT_GET_CLASS(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
143
144 #define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
145
146 static bool megasas_intr_enabled(MegasasState *s)
147 {
148 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
149 MEGASAS_INTR_DISABLED_MASK) {
150 return true;
151 }
152 return false;
153 }
154
155 static bool megasas_use_queue64(MegasasState *s)
156 {
157 return s->flags & MEGASAS_MASK_USE_QUEUE64;
158 }
159
160 static bool megasas_use_msi(MegasasState *s)
161 {
162 return s->flags & MEGASAS_MASK_USE_MSI;
163 }
164
165 static bool megasas_use_msix(MegasasState *s)
166 {
167 return s->flags & MEGASAS_MASK_USE_MSIX;
168 }
169
170 static bool megasas_is_jbod(MegasasState *s)
171 {
172 return s->flags & MEGASAS_MASK_USE_JBOD;
173 }
174
175 static void megasas_frame_set_cmd_status(MegasasState *s,
176 unsigned long frame, uint8_t v)
177 {
178 PCIDevice *pci = &s->parent_obj;
179 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, cmd_status), v);
180 }
181
182 static void megasas_frame_set_scsi_status(MegasasState *s,
183 unsigned long frame, uint8_t v)
184 {
185 PCIDevice *pci = &s->parent_obj;
186 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, scsi_status), v);
187 }
188
189 /*
190 * Context is considered opaque, but the HBA firmware is running
191 * in little endian mode. So convert it to little endian, too.
192 */
193 static uint64_t megasas_frame_get_context(MegasasState *s,
194 unsigned long frame)
195 {
196 PCIDevice *pci = &s->parent_obj;
197 return ldq_le_pci_dma(pci, frame + offsetof(struct mfi_frame_header, context));
198 }
199
200 static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
201 {
202 return cmd->flags & MFI_FRAME_IEEE_SGL;
203 }
204
205 static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
206 {
207 return cmd->flags & MFI_FRAME_SGL64;
208 }
209
210 static bool megasas_frame_is_sense64(MegasasCmd *cmd)
211 {
212 return cmd->flags & MFI_FRAME_SENSE64;
213 }
214
215 static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
216 union mfi_sgl *sgl)
217 {
218 uint64_t addr;
219
220 if (megasas_frame_is_ieee_sgl(cmd)) {
221 addr = le64_to_cpu(sgl->sg_skinny->addr);
222 } else if (megasas_frame_is_sgl64(cmd)) {
223 addr = le64_to_cpu(sgl->sg64->addr);
224 } else {
225 addr = le32_to_cpu(sgl->sg32->addr);
226 }
227 return addr;
228 }
229
230 static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
231 union mfi_sgl *sgl)
232 {
233 uint32_t len;
234
235 if (megasas_frame_is_ieee_sgl(cmd)) {
236 len = le32_to_cpu(sgl->sg_skinny->len);
237 } else if (megasas_frame_is_sgl64(cmd)) {
238 len = le32_to_cpu(sgl->sg64->len);
239 } else {
240 len = le32_to_cpu(sgl->sg32->len);
241 }
242 return len;
243 }
244
245 static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
246 union mfi_sgl *sgl)
247 {
248 uint8_t *next = (uint8_t *)sgl;
249
250 if (megasas_frame_is_ieee_sgl(cmd)) {
251 next += sizeof(struct mfi_sg_skinny);
252 } else if (megasas_frame_is_sgl64(cmd)) {
253 next += sizeof(struct mfi_sg64);
254 } else {
255 next += sizeof(struct mfi_sg32);
256 }
257
258 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
259 return NULL;
260 }
261 return (union mfi_sgl *)next;
262 }
263
264 static void megasas_soft_reset(MegasasState *s);
265
266 static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
267 {
268 int i;
269 int iov_count = 0;
270 size_t iov_size = 0;
271
272 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
273 iov_count = cmd->frame->header.sge_count;
274 if (iov_count > MEGASAS_MAX_SGE) {
275 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
276 MEGASAS_MAX_SGE);
277 return iov_count;
278 }
279 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
280 for (i = 0; i < iov_count; i++) {
281 dma_addr_t iov_pa, iov_size_p;
282
283 if (!sgl) {
284 trace_megasas_iovec_sgl_underflow(cmd->index, i);
285 goto unmap;
286 }
287 iov_pa = megasas_sgl_get_addr(cmd, sgl);
288 iov_size_p = megasas_sgl_get_len(cmd, sgl);
289 if (!iov_pa || !iov_size_p) {
290 trace_megasas_iovec_sgl_invalid(cmd->index, i,
291 iov_pa, iov_size_p);
292 goto unmap;
293 }
294 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
295 sgl = megasas_sgl_next(cmd, sgl);
296 iov_size += (size_t)iov_size_p;
297 }
298 if (cmd->iov_size > iov_size) {
299 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
300 } else if (cmd->iov_size < iov_size) {
301 trace_megasas_iovec_underflow(cmd->iov_size, iov_size, cmd->iov_size);
302 }
303 cmd->iov_offset = 0;
304 return 0;
305 unmap:
306 qemu_sglist_destroy(&cmd->qsg);
307 return iov_count - i;
308 }
309
310 static void megasas_unmap_sgl(MegasasCmd *cmd)
311 {
312 qemu_sglist_destroy(&cmd->qsg);
313 cmd->iov_offset = 0;
314 }
315
316 /*
317 * passthrough sense and io sense are at the same offset
318 */
319 static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
320 uint8_t sense_len)
321 {
322 PCIDevice *pcid = PCI_DEVICE(cmd->state);
323 uint32_t pa_hi = 0, pa_lo;
324 hwaddr pa;
325
326 if (sense_len > cmd->frame->header.sense_len) {
327 sense_len = cmd->frame->header.sense_len;
328 }
329 if (sense_len) {
330 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
331 if (megasas_frame_is_sense64(cmd)) {
332 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
333 }
334 pa = ((uint64_t) pa_hi << 32) | pa_lo;
335 pci_dma_write(pcid, pa, sense_ptr, sense_len);
336 cmd->frame->header.sense_len = sense_len;
337 }
338 return sense_len;
339 }
340
341 static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
342 {
343 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
344 uint8_t sense_len = 18;
345
346 memset(sense_buf, 0, sense_len);
347 sense_buf[0] = 0xf0;
348 sense_buf[2] = sense.key;
349 sense_buf[7] = 10;
350 sense_buf[12] = sense.asc;
351 sense_buf[13] = sense.ascq;
352 megasas_build_sense(cmd, sense_buf, sense_len);
353 }
354
355 static void megasas_copy_sense(MegasasCmd *cmd)
356 {
357 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
358 uint8_t sense_len;
359
360 sense_len = scsi_req_get_sense(cmd->req, sense_buf,
361 SCSI_SENSE_BUF_SIZE);
362 megasas_build_sense(cmd, sense_buf, sense_len);
363 }
364
365 /*
366 * Format an INQUIRY CDB
367 */
368 static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
369 {
370 memset(cdb, 0, 6);
371 cdb[0] = INQUIRY;
372 if (pg > 0) {
373 cdb[1] = 0x1;
374 cdb[2] = pg;
375 }
376 cdb[3] = (len >> 8) & 0xff;
377 cdb[4] = (len & 0xff);
378 return len;
379 }
380
381 /*
382 * Encode lba and len into a READ_16/WRITE_16 CDB
383 */
384 static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
385 uint32_t len, bool is_write)
386 {
387 memset(cdb, 0x0, 16);
388 if (is_write) {
389 cdb[0] = WRITE_16;
390 } else {
391 cdb[0] = READ_16;
392 }
393 cdb[2] = (lba >> 56) & 0xff;
394 cdb[3] = (lba >> 48) & 0xff;
395 cdb[4] = (lba >> 40) & 0xff;
396 cdb[5] = (lba >> 32) & 0xff;
397 cdb[6] = (lba >> 24) & 0xff;
398 cdb[7] = (lba >> 16) & 0xff;
399 cdb[8] = (lba >> 8) & 0xff;
400 cdb[9] = (lba) & 0xff;
401 cdb[10] = (len >> 24) & 0xff;
402 cdb[11] = (len >> 16) & 0xff;
403 cdb[12] = (len >> 8) & 0xff;
404 cdb[13] = (len) & 0xff;
405 }
406
407 /*
408 * Utility functions
409 */
410 static uint64_t megasas_fw_time(void)
411 {
412 struct tm curtime;
413 uint64_t bcd_time;
414
415 qemu_get_timedate(&curtime, 0);
416 bcd_time = ((uint64_t)curtime.tm_sec & 0xff) << 48 |
417 ((uint64_t)curtime.tm_min & 0xff) << 40 |
418 ((uint64_t)curtime.tm_hour & 0xff) << 32 |
419 ((uint64_t)curtime.tm_mday & 0xff) << 24 |
420 ((uint64_t)curtime.tm_mon & 0xff) << 16 |
421 ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
422
423 return bcd_time;
424 }
425
426 /*
427 * Default disk sata address
428 * 0x1221 is the magic number as
429 * present in real hardware,
430 * so use it here, too.
431 */
432 static uint64_t megasas_get_sata_addr(uint16_t id)
433 {
434 uint64_t addr = (0x1221ULL << 48);
435 return addr | ((uint64_t)id << 24);
436 }
437
438 /*
439 * Frame handling
440 */
441 static int megasas_next_index(MegasasState *s, int index, int limit)
442 {
443 index++;
444 if (index == limit) {
445 index = 0;
446 }
447 return index;
448 }
449
450 static MegasasCmd *megasas_lookup_frame(MegasasState *s,
451 hwaddr frame)
452 {
453 MegasasCmd *cmd = NULL;
454 int num = 0, index;
455
456 index = s->reply_queue_head;
457
458 while (num < s->fw_cmds) {
459 if (s->frames[index].pa && s->frames[index].pa == frame) {
460 cmd = &s->frames[index];
461 break;
462 }
463 index = megasas_next_index(s, index, s->fw_cmds);
464 num++;
465 }
466
467 return cmd;
468 }
469
470 static void megasas_unmap_frame(MegasasState *s, MegasasCmd *cmd)
471 {
472 PCIDevice *p = PCI_DEVICE(s);
473
474 pci_dma_unmap(p, cmd->frame, cmd->pa_size, 0, 0);
475 cmd->frame = NULL;
476 cmd->pa = 0;
477 clear_bit(cmd->index, s->frame_map);
478 }
479
480 /*
481 * This absolutely needs to be locked if
482 * qemu ever goes multithreaded.
483 */
484 static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
485 hwaddr frame, uint64_t context, int count)
486 {
487 PCIDevice *pcid = PCI_DEVICE(s);
488 MegasasCmd *cmd = NULL;
489 int frame_size = MFI_FRAME_SIZE * 16;
490 hwaddr frame_size_p = frame_size;
491 unsigned long index;
492
493 index = 0;
494 while (index < s->fw_cmds) {
495 index = find_next_zero_bit(s->frame_map, s->fw_cmds, index);
496 if (!s->frames[index].pa)
497 break;
498 /* Busy frame found */
499 trace_megasas_qf_mapped(index);
500 }
501 if (index >= s->fw_cmds) {
502 /* All frames busy */
503 trace_megasas_qf_busy(frame);
504 return NULL;
505 }
506 cmd = &s->frames[index];
507 set_bit(index, s->frame_map);
508 trace_megasas_qf_new(index, frame);
509
510 cmd->pa = frame;
511 /* Map all possible frames */
512 cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0);
513 if (frame_size_p != frame_size) {
514 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
515 if (cmd->frame) {
516 megasas_unmap_frame(s, cmd);
517 }
518 s->event_count++;
519 return NULL;
520 }
521 cmd->pa_size = frame_size_p;
522 cmd->context = context;
523 if (!megasas_use_queue64(s)) {
524 cmd->context &= (uint64_t)0xFFFFFFFF;
525 }
526 cmd->count = count;
527 s->busy++;
528
529 if (s->consumer_pa) {
530 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
531 }
532 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
533 s->reply_queue_head, s->reply_queue_tail, s->busy);
534
535 return cmd;
536 }
537
538 static void megasas_complete_frame(MegasasState *s, uint64_t context)
539 {
540 PCIDevice *pci_dev = PCI_DEVICE(s);
541 int tail, queue_offset;
542
543 /* Decrement busy count */
544 s->busy--;
545 if (s->reply_queue_pa) {
546 /*
547 * Put command on the reply queue.
548 * Context is opaque, but emulation is running in
549 * little endian. So convert it.
550 */
551 if (megasas_use_queue64(s)) {
552 queue_offset = s->reply_queue_head * sizeof(uint64_t);
553 stq_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
554 } else {
555 queue_offset = s->reply_queue_head * sizeof(uint32_t);
556 stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
557 }
558 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
559 trace_megasas_qf_complete(context, s->reply_queue_head,
560 s->reply_queue_tail, s->busy);
561 }
562
563 if (megasas_intr_enabled(s)) {
564 /* Update reply queue pointer */
565 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
566 tail = s->reply_queue_head;
567 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
568 trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail,
569 s->busy);
570 stl_le_pci_dma(pci_dev, s->producer_pa, s->reply_queue_head);
571 /* Notify HBA */
572 if (msix_enabled(pci_dev)) {
573 trace_megasas_msix_raise(0);
574 msix_notify(pci_dev, 0);
575 } else if (msi_enabled(pci_dev)) {
576 trace_megasas_msi_raise(0);
577 msi_notify(pci_dev, 0);
578 } else {
579 s->doorbell++;
580 if (s->doorbell == 1) {
581 trace_megasas_irq_raise();
582 pci_irq_assert(pci_dev);
583 }
584 }
585 } else {
586 trace_megasas_qf_complete_noirq(context);
587 }
588 }
589
590 static void megasas_reset_frames(MegasasState *s)
591 {
592 int i;
593 MegasasCmd *cmd;
594
595 for (i = 0; i < s->fw_cmds; i++) {
596 cmd = &s->frames[i];
597 if (cmd->pa) {
598 megasas_unmap_frame(s, cmd);
599 }
600 }
601 bitmap_zero(s->frame_map, MEGASAS_MAX_FRAMES);
602 }
603
604 static void megasas_abort_command(MegasasCmd *cmd)
605 {
606 if (cmd->req) {
607 scsi_req_cancel(cmd->req);
608 cmd->req = NULL;
609 }
610 }
611
612 static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
613 {
614 PCIDevice *pcid = PCI_DEVICE(s);
615 uint32_t pa_hi, pa_lo;
616 hwaddr iq_pa, initq_size = sizeof(struct mfi_init_qinfo);
617 struct mfi_init_qinfo *initq = NULL;
618 uint32_t flags;
619 int ret = MFI_STAT_OK;
620
621 if (s->reply_queue_pa) {
622 trace_megasas_initq_mapped(s->reply_queue_pa);
623 goto out;
624 }
625 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
626 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
627 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
628 trace_megasas_init_firmware((uint64_t)iq_pa);
629 initq = pci_dma_map(pcid, iq_pa, &initq_size, 0);
630 if (!initq || initq_size != sizeof(*initq)) {
631 trace_megasas_initq_map_failed(cmd->index);
632 s->event_count++;
633 ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
634 goto out;
635 }
636 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
637 if (s->reply_queue_len > s->fw_cmds) {
638 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
639 s->event_count++;
640 ret = MFI_STAT_INVALID_PARAMETER;
641 goto out;
642 }
643 pa_lo = le32_to_cpu(initq->rq_addr_lo);
644 pa_hi = le32_to_cpu(initq->rq_addr_hi);
645 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
646 pa_lo = le32_to_cpu(initq->ci_addr_lo);
647 pa_hi = le32_to_cpu(initq->ci_addr_hi);
648 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
649 pa_lo = le32_to_cpu(initq->pi_addr_lo);
650 pa_hi = le32_to_cpu(initq->pi_addr_hi);
651 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
652 s->reply_queue_head = ldl_le_pci_dma(pcid, s->producer_pa);
653 s->reply_queue_head %= MEGASAS_MAX_FRAMES;
654 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
655 s->reply_queue_tail %= MEGASAS_MAX_FRAMES;
656 flags = le32_to_cpu(initq->flags);
657 if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
658 s->flags |= MEGASAS_MASK_USE_QUEUE64;
659 }
660 trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
661 s->reply_queue_len, s->reply_queue_head,
662 s->reply_queue_tail, flags);
663 megasas_reset_frames(s);
664 s->fw_state = MFI_FWSTATE_OPERATIONAL;
665 out:
666 if (initq) {
667 pci_dma_unmap(pcid, initq, initq_size, 0, 0);
668 }
669 return ret;
670 }
671
672 static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
673 {
674 dma_addr_t iov_pa, iov_size;
675
676 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
677 if (!cmd->frame->header.sge_count) {
678 trace_megasas_dcmd_zero_sge(cmd->index);
679 cmd->iov_size = 0;
680 return 0;
681 } else if (cmd->frame->header.sge_count > 1) {
682 trace_megasas_dcmd_invalid_sge(cmd->index,
683 cmd->frame->header.sge_count);
684 cmd->iov_size = 0;
685 return -1;
686 }
687 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
688 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
689 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
690 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
691 cmd->iov_size = iov_size;
692 return cmd->iov_size;
693 }
694
695 static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
696 {
697 trace_megasas_finish_dcmd(cmd->index, iov_size);
698
699 if (cmd->frame->header.sge_count) {
700 qemu_sglist_destroy(&cmd->qsg);
701 }
702 if (iov_size > cmd->iov_size) {
703 if (megasas_frame_is_ieee_sgl(cmd)) {
704 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
705 } else if (megasas_frame_is_sgl64(cmd)) {
706 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
707 } else {
708 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
709 }
710 }
711 cmd->iov_size = 0;
712 }
713
714 static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
715 {
716 PCIDevice *pci_dev = PCI_DEVICE(s);
717 PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev);
718 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
719 struct mfi_ctrl_info info;
720 size_t dcmd_size = sizeof(info);
721 BusChild *kid;
722 int num_pd_disks = 0;
723
724 memset(&info, 0x0, dcmd_size);
725 if (cmd->iov_size < dcmd_size) {
726 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
727 dcmd_size);
728 return MFI_STAT_INVALID_PARAMETER;
729 }
730
731 info.pci.vendor = cpu_to_le16(pci_class->vendor_id);
732 info.pci.device = cpu_to_le16(pci_class->device_id);
733 info.pci.subvendor = cpu_to_le16(pci_class->subsystem_vendor_id);
734 info.pci.subdevice = cpu_to_le16(pci_class->subsystem_id);
735
736 /*
737 * For some reason the firmware supports
738 * only up to 8 device ports.
739 * Despite supporting a far larger number
740 * of devices for the physical devices.
741 * So just display the first 8 devices
742 * in the device port list, independent
743 * of how many logical devices are actually
744 * present.
745 */
746 info.host.type = MFI_INFO_HOST_PCIE;
747 info.device.type = MFI_INFO_DEV_SAS3G;
748 info.device.port_count = 8;
749 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
750 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
751 uint16_t pd_id;
752
753 if (num_pd_disks < 8) {
754 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
755 info.device.port_addr[num_pd_disks] =
756 cpu_to_le64(megasas_get_sata_addr(pd_id));
757 }
758 num_pd_disks++;
759 }
760
761 memcpy(info.product_name, base_class->product_name, 24);
762 snprintf(info.serial_number, 32, "%s", s->hba_serial);
763 snprintf(info.package_version, 0x60, "%s-QEMU", qemu_hw_version());
764 memcpy(info.image_component[0].name, "APP", 3);
765 snprintf(info.image_component[0].version, 10, "%s-QEMU",
766 base_class->product_version);
767 memcpy(info.image_component[0].build_date, "Apr 1 2014", 11);
768 memcpy(info.image_component[0].build_time, "12:34:56", 8);
769 info.image_component_count = 1;
770 if (pci_dev->has_rom) {
771 uint8_t biosver[32];
772 uint8_t *ptr;
773
774 ptr = memory_region_get_ram_ptr(&pci_dev->rom);
775 memcpy(biosver, ptr + 0x41, 31);
776 biosver[31] = 0;
777 memcpy(info.image_component[1].name, "BIOS", 4);
778 memcpy(info.image_component[1].version, biosver,
779 strlen((const char *)biosver));
780 info.image_component_count++;
781 }
782 info.current_fw_time = cpu_to_le32(megasas_fw_time());
783 info.max_arms = 32;
784 info.max_spans = 8;
785 info.max_arrays = MEGASAS_MAX_ARRAYS;
786 info.max_lds = MFI_MAX_LD;
787 info.max_cmds = cpu_to_le16(s->fw_cmds);
788 info.max_sg_elements = cpu_to_le16(s->fw_sge);
789 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
790 if (!megasas_is_jbod(s))
791 info.lds_present = cpu_to_le16(num_pd_disks);
792 info.pd_present = cpu_to_le16(num_pd_disks);
793 info.pd_disks_present = cpu_to_le16(num_pd_disks);
794 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
795 MFI_INFO_HW_MEM |
796 MFI_INFO_HW_FLASH);
797 info.memory_size = cpu_to_le16(512);
798 info.nvram_size = cpu_to_le16(32);
799 info.flash_size = cpu_to_le16(16);
800 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
801 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
802 MFI_INFO_AOPS_SELF_DIAGNOSTIC |
803 MFI_INFO_AOPS_MIXED_ARRAY);
804 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
805 MFI_INFO_LDOPS_ACCESS_POLICY |
806 MFI_INFO_LDOPS_IO_POLICY |
807 MFI_INFO_LDOPS_WRITE_POLICY |
808 MFI_INFO_LDOPS_READ_POLICY);
809 info.max_strips_per_io = cpu_to_le16(s->fw_sge);
810 info.stripe_sz_ops.min = 3;
811 info.stripe_sz_ops.max = ctz32(MEGASAS_MAX_SECTORS + 1);
812 info.properties.pred_fail_poll_interval = cpu_to_le16(300);
813 info.properties.intr_throttle_cnt = cpu_to_le16(16);
814 info.properties.intr_throttle_timeout = cpu_to_le16(50);
815 info.properties.rebuild_rate = 30;
816 info.properties.patrol_read_rate = 30;
817 info.properties.bgi_rate = 30;
818 info.properties.cc_rate = 30;
819 info.properties.recon_rate = 30;
820 info.properties.cache_flush_interval = 4;
821 info.properties.spinup_drv_cnt = 2;
822 info.properties.spinup_delay = 6;
823 info.properties.ecc_bucket_size = 15;
824 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
825 info.properties.expose_encl_devices = 1;
826 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
827 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
828 MFI_INFO_PDOPS_FORCE_OFFLINE);
829 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
830 MFI_INFO_PDMIX_SATA |
831 MFI_INFO_PDMIX_LD);
832
833 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
834 return MFI_STAT_OK;
835 }
836
837 static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
838 {
839 struct mfi_defaults info;
840 size_t dcmd_size = sizeof(struct mfi_defaults);
841
842 memset(&info, 0x0, dcmd_size);
843 if (cmd->iov_size < dcmd_size) {
844 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
845 dcmd_size);
846 return MFI_STAT_INVALID_PARAMETER;
847 }
848
849 info.sas_addr = cpu_to_le64(s->sas_addr);
850 info.stripe_size = 3;
851 info.flush_time = 4;
852 info.background_rate = 30;
853 info.allow_mix_in_enclosure = 1;
854 info.allow_mix_in_ld = 1;
855 info.direct_pd_mapping = 1;
856 /* Enable for BIOS support */
857 info.bios_enumerate_lds = 1;
858 info.disable_ctrl_r = 1;
859 info.expose_enclosure_devices = 1;
860 info.disable_preboot_cli = 1;
861 info.cluster_disable = 1;
862
863 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
864 return MFI_STAT_OK;
865 }
866
867 static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
868 {
869 struct mfi_bios_data info;
870 size_t dcmd_size = sizeof(info);
871
872 memset(&info, 0x0, dcmd_size);
873 if (cmd->iov_size < dcmd_size) {
874 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
875 dcmd_size);
876 return MFI_STAT_INVALID_PARAMETER;
877 }
878 info.continue_on_error = 1;
879 info.verbose = 1;
880 if (megasas_is_jbod(s)) {
881 info.expose_all_drives = 1;
882 }
883
884 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
885 return MFI_STAT_OK;
886 }
887
888 static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
889 {
890 uint64_t fw_time;
891 size_t dcmd_size = sizeof(fw_time);
892
893 fw_time = cpu_to_le64(megasas_fw_time());
894
895 cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg);
896 return MFI_STAT_OK;
897 }
898
899 static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
900 {
901 uint64_t fw_time;
902
903 /* This is a dummy; setting of firmware time is not allowed */
904 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
905
906 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
907 fw_time = cpu_to_le64(megasas_fw_time());
908 return MFI_STAT_OK;
909 }
910
911 static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
912 {
913 struct mfi_evt_log_state info;
914 size_t dcmd_size = sizeof(info);
915
916 memset(&info, 0, dcmd_size);
917
918 info.newest_seq_num = cpu_to_le32(s->event_count);
919 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
920 info.boot_seq_num = cpu_to_le32(s->boot_event);
921
922 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
923 return MFI_STAT_OK;
924 }
925
926 static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
927 {
928 union mfi_evt event;
929
930 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
931 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
932 sizeof(struct mfi_evt_detail));
933 return MFI_STAT_INVALID_PARAMETER;
934 }
935 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
936 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
937 s->event_locale = event.members.locale;
938 s->event_class = event.members.class;
939 s->event_cmd = cmd;
940 /* Decrease busy count; event frame doesn't count here */
941 s->busy--;
942 cmd->iov_size = sizeof(struct mfi_evt_detail);
943 return MFI_STAT_INVALID_STATUS;
944 }
945
946 static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
947 {
948 struct mfi_pd_list info;
949 size_t dcmd_size = sizeof(info);
950 BusChild *kid;
951 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
952
953 memset(&info, 0, dcmd_size);
954 offset = 8;
955 dcmd_limit = offset + sizeof(struct mfi_pd_address);
956 if (cmd->iov_size < dcmd_limit) {
957 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
958 dcmd_limit);
959 return MFI_STAT_INVALID_PARAMETER;
960 }
961
962 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
963 if (max_pd_disks > MFI_MAX_SYS_PDS) {
964 max_pd_disks = MFI_MAX_SYS_PDS;
965 }
966 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
967 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
968 uint16_t pd_id;
969
970 if (num_pd_disks >= max_pd_disks)
971 break;
972
973 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
974 info.addr[num_pd_disks].device_id = cpu_to_le16(pd_id);
975 info.addr[num_pd_disks].encl_device_id = 0xFFFF;
976 info.addr[num_pd_disks].encl_index = 0;
977 info.addr[num_pd_disks].slot_number = sdev->id & 0xFF;
978 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
979 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
980 info.addr[num_pd_disks].sas_addr[0] =
981 cpu_to_le64(megasas_get_sata_addr(pd_id));
982 num_pd_disks++;
983 offset += sizeof(struct mfi_pd_address);
984 }
985 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
986 max_pd_disks, offset);
987
988 info.size = cpu_to_le32(offset);
989 info.count = cpu_to_le32(num_pd_disks);
990
991 cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg);
992 return MFI_STAT_OK;
993 }
994
995 static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
996 {
997 uint16_t flags;
998
999 /* mbox0 contains flags */
1000 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1001 trace_megasas_dcmd_pd_list_query(cmd->index, flags);
1002 if (flags == MR_PD_QUERY_TYPE_ALL ||
1003 megasas_is_jbod(s)) {
1004 return megasas_dcmd_pd_get_list(s, cmd);
1005 }
1006
1007 return MFI_STAT_OK;
1008 }
1009
1010 static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
1011 MegasasCmd *cmd)
1012 {
1013 struct mfi_pd_info *info = cmd->iov_buf;
1014 size_t dcmd_size = sizeof(struct mfi_pd_info);
1015 uint64_t pd_size;
1016 uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
1017 uint8_t cmdbuf[6];
1018 SCSIRequest *req;
1019 size_t len, resid;
1020
1021 if (!cmd->iov_buf) {
1022 cmd->iov_buf = g_malloc0(dcmd_size);
1023 info = cmd->iov_buf;
1024 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
1025 info->vpd_page83[0] = 0x7f;
1026 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
1027 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1028 if (!req) {
1029 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1030 "PD get info std inquiry");
1031 g_free(cmd->iov_buf);
1032 cmd->iov_buf = NULL;
1033 return MFI_STAT_FLASH_ALLOC_FAIL;
1034 }
1035 trace_megasas_dcmd_internal_submit(cmd->index,
1036 "PD get info std inquiry", lun);
1037 len = scsi_req_enqueue(req);
1038 if (len > 0) {
1039 cmd->iov_size = len;
1040 scsi_req_continue(req);
1041 }
1042 return MFI_STAT_INVALID_STATUS;
1043 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1044 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
1045 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1046 if (!req) {
1047 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1048 "PD get info vpd inquiry");
1049 return MFI_STAT_FLASH_ALLOC_FAIL;
1050 }
1051 trace_megasas_dcmd_internal_submit(cmd->index,
1052 "PD get info vpd inquiry", lun);
1053 len = scsi_req_enqueue(req);
1054 if (len > 0) {
1055 cmd->iov_size = len;
1056 scsi_req_continue(req);
1057 }
1058 return MFI_STAT_INVALID_STATUS;
1059 }
1060 /* Finished, set FW state */
1061 if ((info->inquiry_data[0] >> 5) == 0) {
1062 if (megasas_is_jbod(cmd->state)) {
1063 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1064 } else {
1065 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1066 }
1067 } else {
1068 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1069 }
1070
1071 info->ref.v.device_id = cpu_to_le16(pd_id);
1072 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1073 MFI_PD_DDF_TYPE_INTF_SAS);
1074 blk_get_geometry(sdev->conf.blk, &pd_size);
1075 info->raw_size = cpu_to_le64(pd_size);
1076 info->non_coerced_size = cpu_to_le64(pd_size);
1077 info->coerced_size = cpu_to_le64(pd_size);
1078 info->encl_device_id = 0xFFFF;
1079 info->slot_number = (sdev->id & 0xFF);
1080 info->path_info.count = 1;
1081 info->path_info.sas_addr[0] =
1082 cpu_to_le64(megasas_get_sata_addr(pd_id));
1083 info->connected_port_bitmap = 0x1;
1084 info->device_speed = 1;
1085 info->link_speed = 1;
1086 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1087 g_free(cmd->iov_buf);
1088 cmd->iov_size = dcmd_size - resid;
1089 cmd->iov_buf = NULL;
1090 return MFI_STAT_OK;
1091 }
1092
1093 static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1094 {
1095 size_t dcmd_size = sizeof(struct mfi_pd_info);
1096 uint16_t pd_id;
1097 uint8_t target_id, lun_id;
1098 SCSIDevice *sdev = NULL;
1099 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1100
1101 if (cmd->iov_size < dcmd_size) {
1102 return MFI_STAT_INVALID_PARAMETER;
1103 }
1104
1105 /* mbox0 has the ID */
1106 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1107 target_id = (pd_id >> 8) & 0xFF;
1108 lun_id = pd_id & 0xFF;
1109 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1110 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1111
1112 if (sdev) {
1113 /* Submit inquiry */
1114 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1115 }
1116
1117 return retval;
1118 }
1119
1120 static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1121 {
1122 struct mfi_ld_list info;
1123 size_t dcmd_size = sizeof(info), resid;
1124 uint32_t num_ld_disks = 0, max_ld_disks;
1125 uint64_t ld_size;
1126 BusChild *kid;
1127
1128 memset(&info, 0, dcmd_size);
1129 if (cmd->iov_size > dcmd_size) {
1130 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1131 dcmd_size);
1132 return MFI_STAT_INVALID_PARAMETER;
1133 }
1134
1135 max_ld_disks = (cmd->iov_size - 8) / 16;
1136 if (megasas_is_jbod(s)) {
1137 max_ld_disks = 0;
1138 }
1139 if (max_ld_disks > MFI_MAX_LD) {
1140 max_ld_disks = MFI_MAX_LD;
1141 }
1142 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1143 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1144
1145 if (num_ld_disks >= max_ld_disks) {
1146 break;
1147 }
1148 /* Logical device size is in blocks */
1149 blk_get_geometry(sdev->conf.blk, &ld_size);
1150 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
1151 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1152 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1153 num_ld_disks++;
1154 }
1155 info.ld_count = cpu_to_le32(num_ld_disks);
1156 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1157
1158 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1159 cmd->iov_size = dcmd_size - resid;
1160 return MFI_STAT_OK;
1161 }
1162
1163 static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1164 {
1165 uint16_t flags;
1166 struct mfi_ld_targetid_list info;
1167 size_t dcmd_size = sizeof(info), resid;
1168 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1169 BusChild *kid;
1170
1171 /* mbox0 contains flags */
1172 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1173 trace_megasas_dcmd_ld_list_query(cmd->index, flags);
1174 if (flags != MR_LD_QUERY_TYPE_ALL &&
1175 flags != MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1176 max_ld_disks = 0;
1177 }
1178
1179 memset(&info, 0, dcmd_size);
1180 if (cmd->iov_size < 12) {
1181 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1182 dcmd_size);
1183 return MFI_STAT_INVALID_PARAMETER;
1184 }
1185 dcmd_size = sizeof(uint32_t) * 2 + 3;
1186 max_ld_disks = cmd->iov_size - dcmd_size;
1187 if (megasas_is_jbod(s)) {
1188 max_ld_disks = 0;
1189 }
1190 if (max_ld_disks > MFI_MAX_LD) {
1191 max_ld_disks = MFI_MAX_LD;
1192 }
1193 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1194 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1195
1196 if (num_ld_disks >= max_ld_disks) {
1197 break;
1198 }
1199 info.targetid[num_ld_disks] = sdev->lun;
1200 num_ld_disks++;
1201 dcmd_size++;
1202 }
1203 info.ld_count = cpu_to_le32(num_ld_disks);
1204 info.size = dcmd_size;
1205 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1206
1207 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1208 cmd->iov_size = dcmd_size - resid;
1209 return MFI_STAT_OK;
1210 }
1211
1212 static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1213 MegasasCmd *cmd)
1214 {
1215 struct mfi_ld_info *info = cmd->iov_buf;
1216 size_t dcmd_size = sizeof(struct mfi_ld_info);
1217 uint8_t cdb[6];
1218 SCSIRequest *req;
1219 ssize_t len, resid;
1220 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
1221 uint64_t ld_size;
1222
1223 if (!cmd->iov_buf) {
1224 cmd->iov_buf = g_malloc0(dcmd_size);
1225 info = cmd->iov_buf;
1226 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
1227 req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd);
1228 if (!req) {
1229 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1230 "LD get info vpd inquiry");
1231 g_free(cmd->iov_buf);
1232 cmd->iov_buf = NULL;
1233 return MFI_STAT_FLASH_ALLOC_FAIL;
1234 }
1235 trace_megasas_dcmd_internal_submit(cmd->index,
1236 "LD get info vpd inquiry", lun);
1237 len = scsi_req_enqueue(req);
1238 if (len > 0) {
1239 cmd->iov_size = len;
1240 scsi_req_continue(req);
1241 }
1242 return MFI_STAT_INVALID_STATUS;
1243 }
1244
1245 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1246 info->ld_config.properties.ld.v.target_id = lun;
1247 info->ld_config.params.stripe_size = 3;
1248 info->ld_config.params.num_drives = 1;
1249 info->ld_config.params.is_consistent = 1;
1250 /* Logical device size is in blocks */
1251 blk_get_geometry(sdev->conf.blk, &ld_size);
1252 info->size = cpu_to_le64(ld_size);
1253 memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1254 info->ld_config.span[0].start_block = 0;
1255 info->ld_config.span[0].num_blocks = info->size;
1256 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1257
1258 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1259 g_free(cmd->iov_buf);
1260 cmd->iov_size = dcmd_size - resid;
1261 cmd->iov_buf = NULL;
1262 return MFI_STAT_OK;
1263 }
1264
1265 static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1266 {
1267 struct mfi_ld_info info;
1268 size_t dcmd_size = sizeof(info);
1269 uint16_t ld_id;
1270 uint32_t max_ld_disks = s->fw_luns;
1271 SCSIDevice *sdev = NULL;
1272 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1273
1274 if (cmd->iov_size < dcmd_size) {
1275 return MFI_STAT_INVALID_PARAMETER;
1276 }
1277
1278 /* mbox0 has the ID */
1279 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1280 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1281
1282 if (megasas_is_jbod(s)) {
1283 return MFI_STAT_DEVICE_NOT_FOUND;
1284 }
1285
1286 if (ld_id < max_ld_disks) {
1287 sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1288 }
1289
1290 if (sdev) {
1291 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1292 }
1293
1294 return retval;
1295 }
1296
1297 static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1298 {
1299 uint8_t data[4096] = { 0 };
1300 struct mfi_config_data *info;
1301 int num_pd_disks = 0, array_offset, ld_offset;
1302 BusChild *kid;
1303
1304 if (cmd->iov_size > 4096) {
1305 return MFI_STAT_INVALID_PARAMETER;
1306 }
1307
1308 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1309 num_pd_disks++;
1310 }
1311 info = (struct mfi_config_data *)&data;
1312 /*
1313 * Array mapping:
1314 * - One array per SCSI device
1315 * - One logical drive per SCSI device
1316 * spanning the entire device
1317 */
1318 info->array_count = num_pd_disks;
1319 info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1320 info->log_drv_count = num_pd_disks;
1321 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1322 info->spares_count = 0;
1323 info->spares_size = sizeof(struct mfi_spare);
1324 info->size = sizeof(struct mfi_config_data) + info->array_size +
1325 info->log_drv_size;
1326 if (info->size > 4096) {
1327 return MFI_STAT_INVALID_PARAMETER;
1328 }
1329
1330 array_offset = sizeof(struct mfi_config_data);
1331 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1332
1333 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1334 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1335 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
1336 struct mfi_array *array;
1337 struct mfi_ld_config *ld;
1338 uint64_t pd_size;
1339 int i;
1340
1341 array = (struct mfi_array *)(data + array_offset);
1342 blk_get_geometry(sdev->conf.blk, &pd_size);
1343 array->size = cpu_to_le64(pd_size);
1344 array->num_drives = 1;
1345 array->array_ref = cpu_to_le16(sdev_id);
1346 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1347 array->pd[0].ref.v.seq_num = 0;
1348 array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1349 array->pd[0].encl.pd = 0xFF;
1350 array->pd[0].encl.slot = (sdev->id & 0xFF);
1351 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1352 array->pd[i].ref.v.device_id = 0xFFFF;
1353 array->pd[i].ref.v.seq_num = 0;
1354 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1355 array->pd[i].encl.pd = 0xFF;
1356 array->pd[i].encl.slot = 0xFF;
1357 }
1358 array_offset += sizeof(struct mfi_array);
1359 ld = (struct mfi_ld_config *)(data + ld_offset);
1360 memset(ld, 0, sizeof(struct mfi_ld_config));
1361 ld->properties.ld.v.target_id = sdev->id;
1362 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1363 MR_LD_CACHE_READ_ADAPTIVE;
1364 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1365 MR_LD_CACHE_READ_ADAPTIVE;
1366 ld->params.state = MFI_LD_STATE_OPTIMAL;
1367 ld->params.stripe_size = 3;
1368 ld->params.num_drives = 1;
1369 ld->params.span_depth = 1;
1370 ld->params.is_consistent = 1;
1371 ld->span[0].start_block = 0;
1372 ld->span[0].num_blocks = cpu_to_le64(pd_size);
1373 ld->span[0].array_ref = cpu_to_le16(sdev_id);
1374 ld_offset += sizeof(struct mfi_ld_config);
1375 }
1376
1377 cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg);
1378 return MFI_STAT_OK;
1379 }
1380
1381 static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1382 {
1383 struct mfi_ctrl_props info;
1384 size_t dcmd_size = sizeof(info);
1385
1386 memset(&info, 0x0, dcmd_size);
1387 if (cmd->iov_size < dcmd_size) {
1388 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1389 dcmd_size);
1390 return MFI_STAT_INVALID_PARAMETER;
1391 }
1392 info.pred_fail_poll_interval = cpu_to_le16(300);
1393 info.intr_throttle_cnt = cpu_to_le16(16);
1394 info.intr_throttle_timeout = cpu_to_le16(50);
1395 info.rebuild_rate = 30;
1396 info.patrol_read_rate = 30;
1397 info.bgi_rate = 30;
1398 info.cc_rate = 30;
1399 info.recon_rate = 30;
1400 info.cache_flush_interval = 4;
1401 info.spinup_drv_cnt = 2;
1402 info.spinup_delay = 6;
1403 info.ecc_bucket_size = 15;
1404 info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1405 info.expose_encl_devices = 1;
1406
1407 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1408 return MFI_STAT_OK;
1409 }
1410
1411 static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1412 {
1413 blk_drain_all();
1414 return MFI_STAT_OK;
1415 }
1416
1417 static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1418 {
1419 s->fw_state = MFI_FWSTATE_READY;
1420 return MFI_STAT_OK;
1421 }
1422
1423 /* Some implementations use CLUSTER RESET LD to simulate a device reset */
1424 static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1425 {
1426 uint16_t target_id;
1427 int i;
1428
1429 /* mbox0 contains the device index */
1430 target_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1431 trace_megasas_dcmd_reset_ld(cmd->index, target_id);
1432 for (i = 0; i < s->fw_cmds; i++) {
1433 MegasasCmd *tmp_cmd = &s->frames[i];
1434 if (tmp_cmd->req && tmp_cmd->req->dev->id == target_id) {
1435 SCSIDevice *d = tmp_cmd->req->dev;
1436 qdev_reset_all(&d->qdev);
1437 }
1438 }
1439 return MFI_STAT_OK;
1440 }
1441
1442 static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1443 {
1444 struct mfi_ctrl_props info;
1445 size_t dcmd_size = sizeof(info);
1446
1447 if (cmd->iov_size < dcmd_size) {
1448 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1449 dcmd_size);
1450 return MFI_STAT_INVALID_PARAMETER;
1451 }
1452 dma_buf_write((uint8_t *)&info, dcmd_size, &cmd->qsg);
1453 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
1454 return MFI_STAT_OK;
1455 }
1456
1457 static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1458 {
1459 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1460 return MFI_STAT_OK;
1461 }
1462
1463 static const struct dcmd_cmd_tbl_t {
1464 int opcode;
1465 const char *desc;
1466 int (*func)(MegasasState *s, MegasasCmd *cmd);
1467 } dcmd_cmd_tbl[] = {
1468 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1469 megasas_dcmd_dummy },
1470 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1471 megasas_ctrl_get_info },
1472 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1473 megasas_dcmd_get_properties },
1474 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1475 megasas_dcmd_set_properties },
1476 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1477 megasas_dcmd_dummy },
1478 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1479 megasas_dcmd_dummy },
1480 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1481 megasas_dcmd_dummy },
1482 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1483 megasas_dcmd_dummy },
1484 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1485 megasas_dcmd_dummy },
1486 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1487 megasas_event_info },
1488 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1489 megasas_dcmd_dummy },
1490 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1491 megasas_event_wait },
1492 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1493 megasas_ctrl_shutdown },
1494 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1495 megasas_dcmd_dummy },
1496 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1497 megasas_dcmd_get_fw_time },
1498 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1499 megasas_dcmd_set_fw_time },
1500 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1501 megasas_dcmd_get_bios_info },
1502 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1503 megasas_dcmd_dummy },
1504 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1505 megasas_mfc_get_defaults },
1506 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1507 megasas_dcmd_dummy },
1508 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1509 megasas_cache_flush },
1510 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1511 megasas_dcmd_pd_get_list },
1512 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1513 megasas_dcmd_pd_list_query },
1514 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1515 megasas_dcmd_pd_get_info },
1516 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1517 megasas_dcmd_dummy },
1518 { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1519 megasas_dcmd_dummy },
1520 { MFI_DCMD_PD_BLINK, "PD_BLINK",
1521 megasas_dcmd_dummy },
1522 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1523 megasas_dcmd_dummy },
1524 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1525 megasas_dcmd_ld_get_list},
1526 { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1527 megasas_dcmd_ld_list_query },
1528 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1529 megasas_dcmd_ld_get_info },
1530 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1531 megasas_dcmd_dummy },
1532 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1533 megasas_dcmd_dummy },
1534 { MFI_DCMD_LD_DELETE, "LD_DELETE",
1535 megasas_dcmd_dummy },
1536 { MFI_DCMD_CFG_READ, "CFG_READ",
1537 megasas_dcmd_cfg_read },
1538 { MFI_DCMD_CFG_ADD, "CFG_ADD",
1539 megasas_dcmd_dummy },
1540 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1541 megasas_dcmd_dummy },
1542 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1543 megasas_dcmd_dummy },
1544 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1545 megasas_dcmd_dummy },
1546 { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1547 megasas_dcmd_dummy },
1548 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1549 megasas_dcmd_dummy },
1550 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1551 megasas_dcmd_dummy },
1552 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1553 megasas_dcmd_dummy },
1554 { MFI_DCMD_CLUSTER, "CLUSTER",
1555 megasas_dcmd_dummy },
1556 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1557 megasas_dcmd_dummy },
1558 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1559 megasas_cluster_reset_ld },
1560 { -1, NULL, NULL }
1561 };
1562
1563 static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1564 {
1565 int opcode, len;
1566 int retval = 0;
1567 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1568
1569 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1570 trace_megasas_handle_dcmd(cmd->index, opcode);
1571 len = megasas_map_dcmd(s, cmd);
1572 if (len < 0) {
1573 return MFI_STAT_MEMORY_NOT_AVAILABLE;
1574 }
1575 while (cmdptr->opcode != -1 && cmdptr->opcode != opcode) {
1576 cmdptr++;
1577 }
1578 if (cmdptr->opcode == -1) {
1579 trace_megasas_dcmd_unhandled(cmd->index, opcode, len);
1580 retval = megasas_dcmd_dummy(s, cmd);
1581 } else {
1582 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1583 retval = cmdptr->func(s, cmd);
1584 }
1585 if (retval != MFI_STAT_INVALID_STATUS) {
1586 megasas_finish_dcmd(cmd, len);
1587 }
1588 return retval;
1589 }
1590
1591 static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
1592 SCSIRequest *req)
1593 {
1594 int opcode;
1595 int retval = MFI_STAT_OK;
1596 int lun = req->lun;
1597
1598 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1599 scsi_req_unref(req);
1600 trace_megasas_dcmd_internal_finish(cmd->index, opcode, lun);
1601 switch (opcode) {
1602 case MFI_DCMD_PD_GET_INFO:
1603 retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1604 break;
1605 case MFI_DCMD_LD_GET_INFO:
1606 retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1607 break;
1608 default:
1609 trace_megasas_dcmd_internal_invalid(cmd->index, opcode);
1610 retval = MFI_STAT_INVALID_DCMD;
1611 break;
1612 }
1613 if (retval != MFI_STAT_INVALID_STATUS) {
1614 megasas_finish_dcmd(cmd, cmd->iov_size);
1615 }
1616 return retval;
1617 }
1618
1619 static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1620 {
1621 int len;
1622
1623 len = scsi_req_enqueue(cmd->req);
1624 if (len < 0) {
1625 len = -len;
1626 }
1627 if (len > 0) {
1628 if (len > cmd->iov_size) {
1629 if (is_write) {
1630 trace_megasas_iov_write_overflow(cmd->index, len,
1631 cmd->iov_size);
1632 } else {
1633 trace_megasas_iov_read_overflow(cmd->index, len,
1634 cmd->iov_size);
1635 }
1636 }
1637 if (len < cmd->iov_size) {
1638 if (is_write) {
1639 trace_megasas_iov_write_underflow(cmd->index, len,
1640 cmd->iov_size);
1641 } else {
1642 trace_megasas_iov_read_underflow(cmd->index, len,
1643 cmd->iov_size);
1644 }
1645 cmd->iov_size = len;
1646 }
1647 scsi_req_continue(cmd->req);
1648 }
1649 return len;
1650 }
1651
1652 static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
1653 bool is_logical)
1654 {
1655 uint8_t *cdb;
1656 bool is_write;
1657 struct SCSIDevice *sdev = NULL;
1658
1659 cdb = cmd->frame->pass.cdb;
1660
1661 if (is_logical) {
1662 if (cmd->frame->header.target_id >= MFI_MAX_LD ||
1663 cmd->frame->header.lun_id != 0) {
1664 trace_megasas_scsi_target_not_present(
1665 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1666 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1667 return MFI_STAT_DEVICE_NOT_FOUND;
1668 }
1669 }
1670 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1671 cmd->frame->header.lun_id);
1672
1673 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
1674 trace_megasas_handle_scsi(mfi_frame_desc[cmd->frame->header.frame_cmd],
1675 is_logical, cmd->frame->header.target_id,
1676 cmd->frame->header.lun_id, sdev, cmd->iov_size);
1677
1678 if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1679 trace_megasas_scsi_target_not_present(
1680 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1681 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1682 return MFI_STAT_DEVICE_NOT_FOUND;
1683 }
1684
1685 if (cmd->frame->header.cdb_len > 16) {
1686 trace_megasas_scsi_invalid_cdb_len(
1687 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1688 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1689 cmd->frame->header.cdb_len);
1690 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1691 cmd->frame->header.scsi_status = CHECK_CONDITION;
1692 s->event_count++;
1693 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1694 }
1695
1696 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1697 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1698 cmd->frame->header.scsi_status = CHECK_CONDITION;
1699 s->event_count++;
1700 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1701 }
1702
1703 cmd->req = scsi_req_new(sdev, cmd->index,
1704 cmd->frame->header.lun_id, cdb, cmd);
1705 if (!cmd->req) {
1706 trace_megasas_scsi_req_alloc_failed(
1707 mfi_frame_desc[cmd->frame->header.frame_cmd],
1708 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1709 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1710 cmd->frame->header.scsi_status = BUSY;
1711 s->event_count++;
1712 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1713 }
1714
1715 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
1716 if (cmd->iov_size) {
1717 if (is_write) {
1718 trace_megasas_scsi_write_start(cmd->index, cmd->iov_size);
1719 } else {
1720 trace_megasas_scsi_read_start(cmd->index, cmd->iov_size);
1721 }
1722 } else {
1723 trace_megasas_scsi_nodata(cmd->index);
1724 }
1725 megasas_enqueue_req(cmd, is_write);
1726 return MFI_STAT_INVALID_STATUS;
1727 }
1728
1729 static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd)
1730 {
1731 uint32_t lba_count, lba_start_hi, lba_start_lo;
1732 uint64_t lba_start;
1733 bool is_write = (cmd->frame->header.frame_cmd == MFI_CMD_LD_WRITE);
1734 uint8_t cdb[16];
1735 int len;
1736 struct SCSIDevice *sdev = NULL;
1737
1738 lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1739 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1740 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1741 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1742
1743 if (cmd->frame->header.target_id < MFI_MAX_LD &&
1744 cmd->frame->header.lun_id == 0) {
1745 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1746 cmd->frame->header.lun_id);
1747 }
1748
1749 trace_megasas_handle_io(cmd->index,
1750 mfi_frame_desc[cmd->frame->header.frame_cmd],
1751 cmd->frame->header.target_id,
1752 cmd->frame->header.lun_id,
1753 (unsigned long)lba_start, (unsigned long)lba_count);
1754 if (!sdev) {
1755 trace_megasas_io_target_not_present(cmd->index,
1756 mfi_frame_desc[cmd->frame->header.frame_cmd],
1757 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1758 return MFI_STAT_DEVICE_NOT_FOUND;
1759 }
1760
1761 if (cmd->frame->header.cdb_len > 16) {
1762 trace_megasas_scsi_invalid_cdb_len(
1763 mfi_frame_desc[cmd->frame->header.frame_cmd], 1,
1764 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1765 cmd->frame->header.cdb_len);
1766 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1767 cmd->frame->header.scsi_status = CHECK_CONDITION;
1768 s->event_count++;
1769 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1770 }
1771
1772 cmd->iov_size = lba_count * sdev->blocksize;
1773 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1774 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1775 cmd->frame->header.scsi_status = CHECK_CONDITION;
1776 s->event_count++;
1777 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1778 }
1779
1780 megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1781 cmd->req = scsi_req_new(sdev, cmd->index,
1782 cmd->frame->header.lun_id, cdb, cmd);
1783 if (!cmd->req) {
1784 trace_megasas_scsi_req_alloc_failed(
1785 mfi_frame_desc[cmd->frame->header.frame_cmd],
1786 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1787 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1788 cmd->frame->header.scsi_status = BUSY;
1789 s->event_count++;
1790 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1791 }
1792 len = megasas_enqueue_req(cmd, is_write);
1793 if (len > 0) {
1794 if (is_write) {
1795 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1796 } else {
1797 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1798 }
1799 }
1800 return MFI_STAT_INVALID_STATUS;
1801 }
1802
1803 static int megasas_finish_internal_command(MegasasCmd *cmd,
1804 SCSIRequest *req, size_t resid)
1805 {
1806 int retval = MFI_STAT_INVALID_CMD;
1807
1808 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1809 cmd->iov_size -= resid;
1810 retval = megasas_finish_internal_dcmd(cmd, req);
1811 }
1812 return retval;
1813 }
1814
1815 static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1816 {
1817 MegasasCmd *cmd = req->hba_private;
1818
1819 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1820 return NULL;
1821 } else {
1822 return &cmd->qsg;
1823 }
1824 }
1825
1826 static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1827 {
1828 MegasasCmd *cmd = req->hba_private;
1829 uint8_t *buf;
1830 uint32_t opcode;
1831
1832 trace_megasas_io_complete(cmd->index, len);
1833
1834 if (cmd->frame->header.frame_cmd != MFI_CMD_DCMD) {
1835 scsi_req_continue(req);
1836 return;
1837 }
1838
1839 buf = scsi_req_get_buf(req);
1840 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1841 if (opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
1842 struct mfi_pd_info *info = cmd->iov_buf;
1843
1844 if (info->inquiry_data[0] == 0x7f) {
1845 memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1846 memcpy(info->inquiry_data, buf, len);
1847 } else if (info->vpd_page83[0] == 0x7f) {
1848 memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1849 memcpy(info->vpd_page83, buf, len);
1850 }
1851 scsi_req_continue(req);
1852 } else if (opcode == MFI_DCMD_LD_GET_INFO) {
1853 struct mfi_ld_info *info = cmd->iov_buf;
1854
1855 if (cmd->iov_buf) {
1856 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1857 scsi_req_continue(req);
1858 }
1859 }
1860 }
1861
1862 static void megasas_command_complete(SCSIRequest *req, uint32_t status,
1863 size_t resid)
1864 {
1865 MegasasCmd *cmd = req->hba_private;
1866 uint8_t cmd_status = MFI_STAT_OK;
1867
1868 trace_megasas_command_complete(cmd->index, status, resid);
1869
1870 if (cmd->req != req) {
1871 /*
1872 * Internal command complete
1873 */
1874 cmd_status = megasas_finish_internal_command(cmd, req, resid);
1875 if (cmd_status == MFI_STAT_INVALID_STATUS) {
1876 return;
1877 }
1878 } else {
1879 req->status = status;
1880 trace_megasas_scsi_complete(cmd->index, req->status,
1881 cmd->iov_size, req->cmd.xfer);
1882 if (req->status != GOOD) {
1883 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1884 }
1885 if (req->status == CHECK_CONDITION) {
1886 megasas_copy_sense(cmd);
1887 }
1888
1889 megasas_unmap_sgl(cmd);
1890 cmd->frame->header.scsi_status = req->status;
1891 scsi_req_unref(cmd->req);
1892 cmd->req = NULL;
1893 }
1894 cmd->frame->header.cmd_status = cmd_status;
1895 megasas_unmap_frame(cmd->state, cmd);
1896 megasas_complete_frame(cmd->state, cmd->context);
1897 }
1898
1899 static void megasas_command_cancel(SCSIRequest *req)
1900 {
1901 MegasasCmd *cmd = req->hba_private;
1902
1903 if (cmd) {
1904 megasas_abort_command(cmd);
1905 } else {
1906 scsi_req_unref(req);
1907 }
1908 }
1909
1910 static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1911 {
1912 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
1913 hwaddr abort_addr, addr_hi, addr_lo;
1914 MegasasCmd *abort_cmd;
1915
1916 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1917 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1918 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1919
1920 abort_cmd = megasas_lookup_frame(s, abort_addr);
1921 if (!abort_cmd) {
1922 trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1923 s->event_count++;
1924 return MFI_STAT_OK;
1925 }
1926 if (!megasas_use_queue64(s)) {
1927 abort_ctx &= (uint64_t)0xFFFFFFFF;
1928 }
1929 if (abort_cmd->context != abort_ctx) {
1930 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->index,
1931 abort_cmd->context);
1932 s->event_count++;
1933 return MFI_STAT_ABORT_NOT_POSSIBLE;
1934 }
1935 trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1936 megasas_abort_command(abort_cmd);
1937 if (!s->event_cmd || abort_cmd != s->event_cmd) {
1938 s->event_cmd = NULL;
1939 }
1940 s->event_count++;
1941 return MFI_STAT_OK;
1942 }
1943
1944 static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1945 uint32_t frame_count)
1946 {
1947 uint8_t frame_status = MFI_STAT_INVALID_CMD;
1948 uint64_t frame_context;
1949 MegasasCmd *cmd;
1950
1951 /*
1952 * Always read 64bit context, top bits will be
1953 * masked out if required in megasas_enqueue_frame()
1954 */
1955 frame_context = megasas_frame_get_context(s, frame_addr);
1956
1957 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1958 if (!cmd) {
1959 /* reply queue full */
1960 trace_megasas_frame_busy(frame_addr);
1961 megasas_frame_set_scsi_status(s, frame_addr, BUSY);
1962 megasas_frame_set_cmd_status(s, frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
1963 megasas_complete_frame(s, frame_context);
1964 s->event_count++;
1965 return;
1966 }
1967 switch (cmd->frame->header.frame_cmd) {
1968 case MFI_CMD_INIT:
1969 frame_status = megasas_init_firmware(s, cmd);
1970 break;
1971 case MFI_CMD_DCMD:
1972 frame_status = megasas_handle_dcmd(s, cmd);
1973 break;
1974 case MFI_CMD_ABORT:
1975 frame_status = megasas_handle_abort(s, cmd);
1976 break;
1977 case MFI_CMD_PD_SCSI_IO:
1978 frame_status = megasas_handle_scsi(s, cmd, 0);
1979 break;
1980 case MFI_CMD_LD_SCSI_IO:
1981 frame_status = megasas_handle_scsi(s, cmd, 1);
1982 break;
1983 case MFI_CMD_LD_READ:
1984 case MFI_CMD_LD_WRITE:
1985 frame_status = megasas_handle_io(s, cmd);
1986 break;
1987 default:
1988 trace_megasas_unhandled_frame_cmd(cmd->index,
1989 cmd->frame->header.frame_cmd);
1990 s->event_count++;
1991 break;
1992 }
1993 if (frame_status != MFI_STAT_INVALID_STATUS) {
1994 if (cmd->frame) {
1995 cmd->frame->header.cmd_status = frame_status;
1996 } else {
1997 megasas_frame_set_cmd_status(s, frame_addr, frame_status);
1998 }
1999 megasas_unmap_frame(s, cmd);
2000 megasas_complete_frame(s, cmd->context);
2001 }
2002 }
2003
2004 static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
2005 unsigned size)
2006 {
2007 MegasasState *s = opaque;
2008 PCIDevice *pci_dev = PCI_DEVICE(s);
2009 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
2010 uint32_t retval = 0;
2011
2012 switch (addr) {
2013 case MFI_IDB:
2014 retval = 0;
2015 trace_megasas_mmio_readl("MFI_IDB", retval);
2016 break;
2017 case MFI_OMSG0:
2018 case MFI_OSP0:
2019 retval = (msix_present(pci_dev) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
2020 (s->fw_state & MFI_FWSTATE_MASK) |
2021 ((s->fw_sge & 0xff) << 16) |
2022 (s->fw_cmds & 0xFFFF);
2023 trace_megasas_mmio_readl(addr == MFI_OMSG0 ? "MFI_OMSG0" : "MFI_OSP0",
2024 retval);
2025 break;
2026 case MFI_OSTS:
2027 if (megasas_intr_enabled(s) && s->doorbell) {
2028 retval = base_class->osts;
2029 }
2030 trace_megasas_mmio_readl("MFI_OSTS", retval);
2031 break;
2032 case MFI_OMSK:
2033 retval = s->intr_mask;
2034 trace_megasas_mmio_readl("MFI_OMSK", retval);
2035 break;
2036 case MFI_ODCR0:
2037 retval = s->doorbell ? 1 : 0;
2038 trace_megasas_mmio_readl("MFI_ODCR0", retval);
2039 break;
2040 case MFI_DIAG:
2041 retval = s->diag;
2042 trace_megasas_mmio_readl("MFI_DIAG", retval);
2043 break;
2044 case MFI_OSP1:
2045 retval = 15;
2046 trace_megasas_mmio_readl("MFI_OSP1", retval);
2047 break;
2048 default:
2049 trace_megasas_mmio_invalid_readl(addr);
2050 break;
2051 }
2052 return retval;
2053 }
2054
2055 static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d};
2056
2057 static void megasas_mmio_write(void *opaque, hwaddr addr,
2058 uint64_t val, unsigned size)
2059 {
2060 MegasasState *s = opaque;
2061 PCIDevice *pci_dev = PCI_DEVICE(s);
2062 uint64_t frame_addr;
2063 uint32_t frame_count;
2064 int i;
2065
2066 switch (addr) {
2067 case MFI_IDB:
2068 trace_megasas_mmio_writel("MFI_IDB", val);
2069 if (val & MFI_FWINIT_ABORT) {
2070 /* Abort all pending cmds */
2071 for (i = 0; i < s->fw_cmds; i++) {
2072 megasas_abort_command(&s->frames[i]);
2073 }
2074 }
2075 if (val & MFI_FWINIT_READY) {
2076 /* move to FW READY */
2077 megasas_soft_reset(s);
2078 }
2079 if (val & MFI_FWINIT_MFIMODE) {
2080 /* discard MFIs */
2081 }
2082 if (val & MFI_FWINIT_STOP_ADP) {
2083 /* Terminal error, stop processing */
2084 s->fw_state = MFI_FWSTATE_FAULT;
2085 }
2086 break;
2087 case MFI_OMSK:
2088 trace_megasas_mmio_writel("MFI_OMSK", val);
2089 s->intr_mask = val;
2090 if (!megasas_intr_enabled(s) &&
2091 !msi_enabled(pci_dev) &&
2092 !msix_enabled(pci_dev)) {
2093 trace_megasas_irq_lower();
2094 pci_irq_deassert(pci_dev);
2095 }
2096 if (megasas_intr_enabled(s)) {
2097 if (msix_enabled(pci_dev)) {
2098 trace_megasas_msix_enabled(0);
2099 } else if (msi_enabled(pci_dev)) {
2100 trace_megasas_msi_enabled(0);
2101 } else {
2102 trace_megasas_intr_enabled();
2103 }
2104 } else {
2105 trace_megasas_intr_disabled();
2106 megasas_soft_reset(s);
2107 }
2108 break;
2109 case MFI_ODCR0:
2110 trace_megasas_mmio_writel("MFI_ODCR0", val);
2111 s->doorbell = 0;
2112 if (megasas_intr_enabled(s)) {
2113 if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) {
2114 trace_megasas_irq_lower();
2115 pci_irq_deassert(pci_dev);
2116 }
2117 }
2118 break;
2119 case MFI_IQPH:
2120 trace_megasas_mmio_writel("MFI_IQPH", val);
2121 /* Received high 32 bits of a 64 bit MFI frame address */
2122 s->frame_hi = val;
2123 break;
2124 case MFI_IQPL:
2125 trace_megasas_mmio_writel("MFI_IQPL", val);
2126 /* Received low 32 bits of a 64 bit MFI frame address */
2127 /* Fallthrough */
2128 case MFI_IQP:
2129 if (addr == MFI_IQP) {
2130 trace_megasas_mmio_writel("MFI_IQP", val);
2131 /* Received 64 bit MFI frame address */
2132 s->frame_hi = 0;
2133 }
2134 frame_addr = (val & ~0x1F);
2135 /* Add possible 64 bit offset */
2136 frame_addr |= ((uint64_t)s->frame_hi << 32);
2137 s->frame_hi = 0;
2138 frame_count = (val >> 1) & 0xF;
2139 megasas_handle_frame(s, frame_addr, frame_count);
2140 break;
2141 case MFI_SEQ:
2142 trace_megasas_mmio_writel("MFI_SEQ", val);
2143 /* Magic sequence to start ADP reset */
2144 if (adp_reset_seq[s->adp_reset] == val) {
2145 s->adp_reset++;
2146 } else {
2147 s->adp_reset = 0;
2148 s->diag = 0;
2149 }
2150 if (s->adp_reset == 6) {
2151 s->diag = MFI_DIAG_WRITE_ENABLE;
2152 }
2153 break;
2154 case MFI_DIAG:
2155 trace_megasas_mmio_writel("MFI_DIAG", val);
2156 /* ADP reset */
2157 if ((s->diag & MFI_DIAG_WRITE_ENABLE) &&
2158 (val & MFI_DIAG_RESET_ADP)) {
2159 s->diag |= MFI_DIAG_RESET_ADP;
2160 megasas_soft_reset(s);
2161 s->adp_reset = 0;
2162 s->diag = 0;
2163 }
2164 break;
2165 default:
2166 trace_megasas_mmio_invalid_writel(addr, val);
2167 break;
2168 }
2169 }
2170
2171 static const MemoryRegionOps megasas_mmio_ops = {
2172 .read = megasas_mmio_read,
2173 .write = megasas_mmio_write,
2174 .endianness = DEVICE_LITTLE_ENDIAN,
2175 .impl = {
2176 .min_access_size = 8,
2177 .max_access_size = 8,
2178 }
2179 };
2180
2181 static uint64_t megasas_port_read(void *opaque, hwaddr addr,
2182 unsigned size)
2183 {
2184 return megasas_mmio_read(opaque, addr & 0xff, size);
2185 }
2186
2187 static void megasas_port_write(void *opaque, hwaddr addr,
2188 uint64_t val, unsigned size)
2189 {
2190 megasas_mmio_write(opaque, addr & 0xff, val, size);
2191 }
2192
2193 static const MemoryRegionOps megasas_port_ops = {
2194 .read = megasas_port_read,
2195 .write = megasas_port_write,
2196 .endianness = DEVICE_LITTLE_ENDIAN,
2197 .impl = {
2198 .min_access_size = 4,
2199 .max_access_size = 4,
2200 }
2201 };
2202
2203 static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
2204 unsigned size)
2205 {
2206 return 0;
2207 }
2208
2209 static void megasas_queue_write(void *opaque, hwaddr addr,
2210 uint64_t val, unsigned size)
2211 {
2212 return;
2213 }
2214
2215 static const MemoryRegionOps megasas_queue_ops = {
2216 .read = megasas_queue_read,
2217 .write = megasas_queue_write,
2218 .endianness = DEVICE_LITTLE_ENDIAN,
2219 .impl = {
2220 .min_access_size = 8,
2221 .max_access_size = 8,
2222 }
2223 };
2224
2225 static void megasas_soft_reset(MegasasState *s)
2226 {
2227 int i;
2228 MegasasCmd *cmd;
2229
2230 trace_megasas_reset(s->fw_state);
2231 for (i = 0; i < s->fw_cmds; i++) {
2232 cmd = &s->frames[i];
2233 megasas_abort_command(cmd);
2234 }
2235 if (s->fw_state == MFI_FWSTATE_READY) {
2236 BusChild *kid;
2237
2238 /*
2239 * The EFI firmware doesn't handle UA,
2240 * so we need to clear the Power On/Reset UA
2241 * after the initial reset.
2242 */
2243 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
2244 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
2245
2246 sdev->unit_attention = SENSE_CODE(NO_SENSE);
2247 scsi_device_unit_attention_reported(sdev);
2248 }
2249 }
2250 megasas_reset_frames(s);
2251 s->reply_queue_len = s->fw_cmds;
2252 s->reply_queue_pa = 0;
2253 s->consumer_pa = 0;
2254 s->producer_pa = 0;
2255 s->fw_state = MFI_FWSTATE_READY;
2256 s->doorbell = 0;
2257 s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2258 s->frame_hi = 0;
2259 s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2260 s->event_count++;
2261 s->boot_event = s->event_count;
2262 }
2263
2264 static void megasas_scsi_reset(DeviceState *dev)
2265 {
2266 MegasasState *s = MEGASAS(dev);
2267
2268 megasas_soft_reset(s);
2269 }
2270
2271 static const VMStateDescription vmstate_megasas_gen1 = {
2272 .name = "megasas",
2273 .version_id = 0,
2274 .minimum_version_id = 0,
2275 .fields = (VMStateField[]) {
2276 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
2277 VMSTATE_MSIX(parent_obj, MegasasState),
2278
2279 VMSTATE_INT32(fw_state, MegasasState),
2280 VMSTATE_INT32(intr_mask, MegasasState),
2281 VMSTATE_INT32(doorbell, MegasasState),
2282 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2283 VMSTATE_UINT64(consumer_pa, MegasasState),
2284 VMSTATE_UINT64(producer_pa, MegasasState),
2285 VMSTATE_END_OF_LIST()
2286 }
2287 };
2288
2289 static const VMStateDescription vmstate_megasas_gen2 = {
2290 .name = "megasas-gen2",
2291 .version_id = 0,
2292 .minimum_version_id = 0,
2293 .minimum_version_id_old = 0,
2294 .fields = (VMStateField[]) {
2295 VMSTATE_PCIE_DEVICE(parent_obj, MegasasState),
2296 VMSTATE_MSIX(parent_obj, MegasasState),
2297
2298 VMSTATE_INT32(fw_state, MegasasState),
2299 VMSTATE_INT32(intr_mask, MegasasState),
2300 VMSTATE_INT32(doorbell, MegasasState),
2301 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2302 VMSTATE_UINT64(consumer_pa, MegasasState),
2303 VMSTATE_UINT64(producer_pa, MegasasState),
2304 VMSTATE_END_OF_LIST()
2305 }
2306 };
2307
2308 static void megasas_scsi_uninit(PCIDevice *d)
2309 {
2310 MegasasState *s = MEGASAS(d);
2311
2312 if (megasas_use_msix(s)) {
2313 msix_uninit(d, &s->mmio_io, &s->mmio_io);
2314 }
2315 if (megasas_use_msi(s)) {
2316 msi_uninit(d);
2317 }
2318 }
2319
2320 static const struct SCSIBusInfo megasas_scsi_info = {
2321 .tcq = true,
2322 .max_target = MFI_MAX_LD,
2323 .max_lun = 255,
2324
2325 .transfer_data = megasas_xfer_complete,
2326 .get_sg_list = megasas_get_sg_list,
2327 .complete = megasas_command_complete,
2328 .cancel = megasas_command_cancel,
2329 };
2330
2331 static void megasas_scsi_realize(PCIDevice *dev, Error **errp)
2332 {
2333 DeviceState *d = DEVICE(dev);
2334 MegasasState *s = MEGASAS(dev);
2335 MegasasBaseClass *b = MEGASAS_DEVICE_GET_CLASS(s);
2336 uint8_t *pci_conf;
2337 int i, bar_type;
2338
2339 pci_conf = dev->config;
2340
2341 /* PCI latency timer = 0 */
2342 pci_conf[PCI_LATENCY_TIMER] = 0;
2343 /* Interrupt pin 1 */
2344 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2345
2346 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
2347 "megasas-mmio", 0x4000);
2348 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
2349 "megasas-io", 256);
2350 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
2351 "megasas-queue", 0x40000);
2352
2353 if (megasas_use_msi(s) &&
2354 msi_init(dev, 0x50, 1, true, false)) {
2355 s->flags &= ~MEGASAS_MASK_USE_MSI;
2356 }
2357 if (megasas_use_msix(s) &&
2358 msix_init(dev, 15, &s->mmio_io, b->mmio_bar, 0x2000,
2359 &s->mmio_io, b->mmio_bar, 0x3800, 0x68)) {
2360 s->flags &= ~MEGASAS_MASK_USE_MSIX;
2361 }
2362 if (pci_is_express(dev)) {
2363 pcie_endpoint_cap_init(dev, 0xa0);
2364 }
2365
2366 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
2367 pci_register_bar(dev, b->ioport_bar,
2368 PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2369 pci_register_bar(dev, b->mmio_bar, bar_type, &s->mmio_io);
2370 pci_register_bar(dev, 3, bar_type, &s->queue_io);
2371
2372 if (megasas_use_msix(s)) {
2373 msix_vector_use(dev, 0);
2374 }
2375
2376 s->fw_state = MFI_FWSTATE_READY;
2377 if (!s->sas_addr) {
2378 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2379 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
2380 s->sas_addr |= (pci_bus_num(dev->bus) << 16);
2381 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
2382 s->sas_addr |= PCI_FUNC(dev->devfn);
2383 }
2384 if (!s->hba_serial) {
2385 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
2386 }
2387 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
2388 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE;
2389 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
2390 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
2391 } else {
2392 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
2393 }
2394 if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2395 s->fw_cmds = MEGASAS_MAX_FRAMES;
2396 }
2397 trace_megasas_init(s->fw_sge, s->fw_cmds,
2398 megasas_is_jbod(s) ? "jbod" : "raid");
2399
2400 if (megasas_is_jbod(s)) {
2401 s->fw_luns = MFI_MAX_SYS_PDS;
2402 } else {
2403 s->fw_luns = MFI_MAX_LD;
2404 }
2405 s->producer_pa = 0;
2406 s->consumer_pa = 0;
2407 for (i = 0; i < s->fw_cmds; i++) {
2408 s->frames[i].index = i;
2409 s->frames[i].context = -1;
2410 s->frames[i].pa = 0;
2411 s->frames[i].state = s;
2412 }
2413
2414 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
2415 &megasas_scsi_info, NULL);
2416 if (!d->hotplugged) {
2417 scsi_bus_legacy_handle_cmdline(&s->bus, errp);
2418 }
2419 }
2420
2421 static Property megasas_properties_gen1[] = {
2422 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2423 MEGASAS_DEFAULT_SGE),
2424 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2425 MEGASAS_DEFAULT_FRAMES),
2426 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2427 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2428 DEFINE_PROP_BIT("use_msi", MegasasState, flags,
2429 MEGASAS_FLAG_USE_MSI, false),
2430 DEFINE_PROP_BIT("use_msix", MegasasState, flags,
2431 MEGASAS_FLAG_USE_MSIX, false),
2432 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2433 MEGASAS_FLAG_USE_JBOD, false),
2434 DEFINE_PROP_END_OF_LIST(),
2435 };
2436
2437 static Property megasas_properties_gen2[] = {
2438 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2439 MEGASAS_DEFAULT_SGE),
2440 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2441 MEGASAS_GEN2_DEFAULT_FRAMES),
2442 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2443 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2444 DEFINE_PROP_BIT("use_msi", MegasasState, flags,
2445 MEGASAS_FLAG_USE_MSI, true),
2446 DEFINE_PROP_BIT("use_msix", MegasasState, flags,
2447 MEGASAS_FLAG_USE_MSIX, true),
2448 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2449 MEGASAS_FLAG_USE_JBOD, false),
2450 DEFINE_PROP_END_OF_LIST(),
2451 };
2452
2453 typedef struct MegasasInfo {
2454 const char *name;
2455 const char *desc;
2456 const char *product_name;
2457 const char *product_version;
2458 uint16_t device_id;
2459 uint16_t subsystem_id;
2460 int ioport_bar;
2461 int mmio_bar;
2462 bool is_express;
2463 int osts;
2464 const VMStateDescription *vmsd;
2465 Property *props;
2466 } MegasasInfo;
2467
2468 static struct MegasasInfo megasas_devices[] = {
2469 {
2470 .name = TYPE_MEGASAS_GEN1,
2471 .desc = "LSI MegaRAID SAS 1078",
2472 .product_name = "LSI MegaRAID SAS 8708EM2",
2473 .product_version = MEGASAS_VERSION_GEN1,
2474 .device_id = PCI_DEVICE_ID_LSI_SAS1078,
2475 .subsystem_id = 0x1013,
2476 .ioport_bar = 2,
2477 .mmio_bar = 0,
2478 .osts = MFI_1078_RM | 1,
2479 .is_express = false,
2480 .vmsd = &vmstate_megasas_gen1,
2481 .props = megasas_properties_gen1,
2482 },{
2483 .name = TYPE_MEGASAS_GEN2,
2484 .desc = "LSI MegaRAID SAS 2108",
2485 .product_name = "LSI MegaRAID SAS 9260-8i",
2486 .product_version = MEGASAS_VERSION_GEN2,
2487 .device_id = PCI_DEVICE_ID_LSI_SAS0079,
2488 .subsystem_id = 0x9261,
2489 .ioport_bar = 0,
2490 .mmio_bar = 1,
2491 .osts = MFI_GEN2_RM,
2492 .is_express = true,
2493 .vmsd = &vmstate_megasas_gen2,
2494 .props = megasas_properties_gen2,
2495 }
2496 };
2497
2498 static void megasas_class_init(ObjectClass *oc, void *data)
2499 {
2500 DeviceClass *dc = DEVICE_CLASS(oc);
2501 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
2502 MegasasBaseClass *e = MEGASAS_DEVICE_CLASS(oc);
2503 const MegasasInfo *info = data;
2504
2505 pc->realize = megasas_scsi_realize;
2506 pc->exit = megasas_scsi_uninit;
2507 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2508 pc->device_id = info->device_id;
2509 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2510 pc->subsystem_id = info->subsystem_id;
2511 pc->class_id = PCI_CLASS_STORAGE_RAID;
2512 pc->is_express = info->is_express;
2513 e->mmio_bar = info->mmio_bar;
2514 e->ioport_bar = info->ioport_bar;
2515 e->osts = info->osts;
2516 e->product_name = info->product_name;
2517 e->product_version = info->product_version;
2518 dc->props = info->props;
2519 dc->reset = megasas_scsi_reset;
2520 dc->vmsd = info->vmsd;
2521 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2522 dc->desc = info->desc;
2523 }
2524
2525 static const TypeInfo megasas_info = {
2526 .name = TYPE_MEGASAS_BASE,
2527 .parent = TYPE_PCI_DEVICE,
2528 .instance_size = sizeof(MegasasState),
2529 .class_size = sizeof(MegasasBaseClass),
2530 .abstract = true,
2531 };
2532
2533 static void megasas_register_types(void)
2534 {
2535 int i;
2536
2537 type_register_static(&megasas_info);
2538 for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) {
2539 const MegasasInfo *info = &megasas_devices[i];
2540 TypeInfo type_info = {};
2541
2542 type_info.name = info->name;
2543 type_info.parent = TYPE_MEGASAS_BASE;
2544 type_info.class_data = (void *)info;
2545 type_info.class_init = megasas_class_init;
2546
2547 type_register(&type_info);
2548 }
2549 }
2550
2551 type_init(megasas_register_types)
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