hw/i386/pc_q35.c

   1 /*
   2  * Q35 chipset based pc system emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2009, 2010
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on pc.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "hw/hw.h"
  31 #include "hw/loader.h"
  32 #include "sysemu/arch_init.h"
  33 #include "hw/i2c/smbus.h"
  34 #include "hw/boards.h"
  35 #include "hw/timer/mc146818rtc.h"
  36 #include "hw/xen/xen.h"
  37 #include "sysemu/kvm.h"
  38 #include "hw/kvm/clock.h"
  39 #include "hw/pci-host/q35.h"
  40 #include "exec/address-spaces.h"
  41 #include "hw/i386/ich9.h"
  42 #include "hw/i386/smbios.h"
  43 #include "hw/ide/pci.h"
  44 #include "hw/ide/ahci.h"
  45 #include "hw/usb.h"
  46 #include "hw/cpu/icc_bus.h"
  47 #include "qemu/error-report.h"
  48 #include "migration/migration.h"
  49
  50 /* ICH9 AHCI has 6 ports */
  51 #define MAX_SATA_PORTS     6
  52
  53 static bool has_acpi_build = true;
  54 static bool rsdp_in_ram = true;
  55 static bool smbios_defaults = true;
  56 static bool smbios_legacy_mode;
  57 static bool smbios_uuid_encoded = true;
  58 /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to
  59  * host addresses aligned at 1Gbyte boundaries.  This way we can use 1GByte
  60  * pages in the host.
  61  */
  62 static bool gigabyte_align = true;
  63 static bool has_reserved_memory = true;
  64
  65 /* PC hardware initialisation */
  66 static void pc_q35_init(MachineState *machine)
  67 {
  68     PCMachineState *pcms = PC_MACHINE(machine);
  69     Q35PCIHost *q35_host;
  70     PCIHostState *phb;
  71     PCIBus *host_bus;
  72     PCIDevice *lpc;
  73     BusState *idebus[MAX_SATA_PORTS];
  74     ISADevice *rtc_state;
  75     MemoryRegion *pci_memory;
  76     MemoryRegion *rom_memory;
  77     MemoryRegion *ram_memory;
  78     GSIState *gsi_state;
  79     ISABus *isa_bus;
  80     int pci_enabled = 1;
  81     qemu_irq *gsi;
  82     qemu_irq *i8259;
  83     int i;
  84     ICH9LPCState *ich9_lpc;
  85     PCIDevice *ahci;
  86     DeviceState *icc_bridge;
  87     PcGuestInfo *guest_info;
  88     ram_addr_t lowmem;
  89     DriveInfo *hd[MAX_SATA_PORTS];
  90     MachineClass *mc = MACHINE_GET_CLASS(machine);
  91
  92     /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
  93      * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
  94      * also known as MMCFG).
  95      * If it doesn't, we need to split it in chunks below and above 4G.
  96      * In any case, try to make sure that guest addresses aligned at
  97      * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
  98      * For old machine types, use whatever split we used historically to avoid
  99      * breaking migration.
 100      */
 101     if (machine->ram_size >= 0xb0000000) {
 102         lowmem = gigabyte_align ? 0x80000000 : 0xb0000000;
 103     } else {
 104         lowmem = 0xb0000000;
 105     }
 106
 107     /* Handle the machine opt max-ram-below-4g.  It is basically doing
 108      * min(qemu limit, user limit).
 109      */
 110     if (lowmem > pcms->max_ram_below_4g) {
 111         lowmem = pcms->max_ram_below_4g;
 112         if (machine->ram_size - lowmem > lowmem &&
 113             lowmem & ((1ULL << 30) - 1)) {
 114             error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64
 115                          ") not a multiple of 1G; possible bad performance.",
 116                          pcms->max_ram_below_4g);
 117         }
 118     }
 119
 120     if (machine->ram_size >= lowmem) {
 121         pcms->above_4g_mem_size = machine->ram_size - lowmem;
 122         pcms->below_4g_mem_size = lowmem;
 123     } else {
 124         pcms->above_4g_mem_size = 0;
 125         pcms->below_4g_mem_size = machine->ram_size;
 126     }
 127
 128     if (xen_enabled() && xen_hvm_init(&pcms->below_4g_mem_size,
 129                                       &pcms->above_4g_mem_size,
 130                                       &ram_memory) != 0) {
 131         fprintf(stderr, "xen hardware virtual machine initialisation failed\n");
 132         exit(1);
 133     }
 134
 135     icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE);
 136     object_property_add_child(qdev_get_machine(), "icc-bridge",
 137                               OBJECT(icc_bridge), NULL);
 138
 139     pc_cpus_init(machine->cpu_model, icc_bridge);
 140     pc_acpi_init("q35-acpi-dsdt.aml");
 141
 142     kvmclock_create();
 143
 144     /* pci enabled */
 145     if (pci_enabled) {
 146         pci_memory = g_new(MemoryRegion, 1);
 147         memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
 148         rom_memory = pci_memory;
 149     } else {
 150         pci_memory = NULL;
 151         rom_memory = get_system_memory();
 152     }
 153
 154     guest_info = pc_guest_info_init(pcms->below_4g_mem_size,
 155                                     pcms->above_4g_mem_size);
 156     guest_info->isapc_ram_fw = false;
 157     guest_info->has_acpi_build = has_acpi_build;
 158     guest_info->has_reserved_memory = has_reserved_memory;
 159     guest_info->rsdp_in_ram = rsdp_in_ram;
 160
 161     /* Migration was not supported in 2.0 for Q35, so do not bother
 162      * with this hack (see hw/i386/acpi-build.c).
 163      */
 164     guest_info->legacy_acpi_table_size = 0;
 165
 166     if (smbios_defaults) {
 167         /* These values are guest ABI, do not change */
 168         smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 169                             mc->name, smbios_legacy_mode, smbios_uuid_encoded);
 170     }
 171
 172     /* allocate ram and load rom/bios */
 173     if (!xen_enabled()) {
 174         pc_memory_init(pcms, get_system_memory(),
 175                        pcms->below_4g_mem_size, pcms->above_4g_mem_size,
 176                        rom_memory, &ram_memory, guest_info);
 177     }
 178
 179     /* irq lines */
 180     gsi_state = g_malloc0(sizeof(*gsi_state));
 181     if (kvm_irqchip_in_kernel()) {
 182         kvm_pc_setup_irq_routing(pci_enabled);
 183         gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
 184                                  GSI_NUM_PINS);
 185     } else {
 186         gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
 187     }
 188
 189     /* create pci host bus */
 190     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 191
 192     object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
 193     q35_host->mch.ram_memory = ram_memory;
 194     q35_host->mch.pci_address_space = pci_memory;
 195     q35_host->mch.system_memory = get_system_memory();
 196     q35_host->mch.address_space_io = get_system_io();
 197     q35_host->mch.below_4g_mem_size = pcms->below_4g_mem_size;
 198     q35_host->mch.above_4g_mem_size = pcms->above_4g_mem_size;
 199     q35_host->mch.guest_info = guest_info;
 200     /* pci */
 201     qdev_init_nofail(DEVICE(q35_host));
 202     phb = PCI_HOST_BRIDGE(q35_host);
 203     host_bus = phb->bus;
 204     /* create ISA bus */
 205     lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 206                                           ICH9_LPC_FUNC), true,
 207                                           TYPE_ICH9_LPC_DEVICE);
 208
 209     object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 210                              TYPE_HOTPLUG_HANDLER,
 211                              (Object **)&pcms->acpi_dev,
 212                              object_property_allow_set_link,
 213                              OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
 214     object_property_set_link(OBJECT(machine), OBJECT(lpc),
 215                              PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
 216
 217     ich9_lpc = ICH9_LPC_DEVICE(lpc);
 218     ich9_lpc->pic = gsi;
 219     ich9_lpc->ioapic = gsi_state->ioapic_irq;
 220     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 221                  ICH9_LPC_NB_PIRQS);
 222     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 223     isa_bus = ich9_lpc->isa_bus;
 224
 225     /*end early*/
 226     isa_bus_irqs(isa_bus, gsi);
 227
 228     if (kvm_irqchip_in_kernel()) {
 229         i8259 = kvm_i8259_init(isa_bus);
 230     } else if (xen_enabled()) {
 231         i8259 = xen_interrupt_controller_init();
 232     } else {
 233         i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
 234     }
 235
 236     for (i = 0; i < ISA_NUM_IRQS; i++) {
 237         gsi_state->i8259_irq[i] = i8259[i];
 238     }
 239     if (pci_enabled) {
 240         ioapic_init_gsi(gsi_state, "q35");
 241     }
 242     qdev_init_nofail(icc_bridge);
 243
 244     pc_register_ferr_irq(gsi[13]);
 245
 246     assert(pcms->vmport != ON_OFF_AUTO_MAX);
 247     if (pcms->vmport == ON_OFF_AUTO_AUTO) {
 248         pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
 249     }
 250
 251     /* init basic PC hardware */
 252     pc_basic_device_init(isa_bus, gsi, &rtc_state, !mc->no_floppy,
 253                          (pcms->vmport != ON_OFF_AUTO_ON), 0xff0104);
 254
 255     /* connect pm stuff to lpc */
 256     ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms), !mc->no_tco);
 257
 258     /* ahci and SATA device, for q35 1 ahci controller is built-in */
 259     ahci = pci_create_simple_multifunction(host_bus,
 260                                            PCI_DEVFN(ICH9_SATA1_DEV,
 261                                                      ICH9_SATA1_FUNC),
 262                                            true, "ich9-ahci");
 263     idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 264     idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 265     g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports);
 266     ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports);
 267     ahci_ide_create_devs(ahci, hd);
 268
 269     if (usb_enabled()) {
 270         /* Should we create 6 UHCI according to ich9 spec? */
 271         ehci_create_ich9_with_companions(host_bus, 0x1d);
 272     }
 273
 274     /* TODO: Populate SPD eeprom data.  */
 275     smbus_eeprom_init(ich9_smb_init(host_bus,
 276                                     PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 277                                     0xb100),
 278                       8, NULL, 0);
 279
 280     pc_cmos_init(pcms,
 281                  pcms->below_4g_mem_size, pcms->above_4g_mem_size,
 282                  machine->boot_order,
 283                  idebus[0], idebus[1], rtc_state);
 284
 285     /* the rest devices to which pci devfn is automatically assigned */
 286     pc_vga_init(isa_bus, host_bus);
 287     pc_nic_init(isa_bus, host_bus);
 288     if (pci_enabled) {
 289         pc_pci_device_init(host_bus);
 290     }
 291 }
 292
 293 static void pc_compat_2_3(MachineState *machine)
 294 {
 295     PCMachineState *pcms = PC_MACHINE(machine);
 296     savevm_skip_section_footers();
 297     if (kvm_enabled()) {
 298         pcms->smm = ON_OFF_AUTO_OFF;
 299     }
 300     global_state_set_optional();
 301     savevm_skip_configuration();
 302 }
 303
 304 static void pc_compat_2_2(MachineState *machine)
 305 {
 306     pc_compat_2_3(machine);
 307     rsdp_in_ram = false;
 308     machine->suppress_vmdesc = true;
 309 }
 310
 311 static void pc_compat_2_1(MachineState *machine)
 312 {
 313     PCMachineState *pcms = PC_MACHINE(machine);
 314
 315     pc_compat_2_2(machine);
 316     pcms->enforce_aligned_dimm = false;
 317     smbios_uuid_encoded = false;
 318     x86_cpu_compat_kvm_no_autodisable(FEAT_8000_0001_ECX, CPUID_EXT3_SVM);
 319 }
 320
 321 static void pc_compat_2_0(MachineState *machine)
 322 {
 323     pc_compat_2_1(machine);
 324     smbios_legacy_mode = true;
 325     has_reserved_memory = false;
 326     pc_set_legacy_acpi_data_size();
 327 }
 328
 329 static void pc_compat_1_7(MachineState *machine)
 330 {
 331     pc_compat_2_0(machine);
 332     smbios_defaults = false;
 333     gigabyte_align = false;
 334     option_rom_has_mr = true;
 335     x86_cpu_compat_kvm_no_autoenable(FEAT_1_ECX, CPUID_EXT_X2APIC);
 336 }
 337
 338 static void pc_compat_1_6(MachineState *machine)
 339 {
 340     pc_compat_1_7(machine);
 341     rom_file_has_mr = false;
 342     has_acpi_build = false;
 343 }
 344
 345 static void pc_compat_1_5(MachineState *machine)
 346 {
 347     pc_compat_1_6(machine);
 348 }
 349
 350 static void pc_compat_1_4(MachineState *machine)
 351 {
 352     pc_compat_1_5(machine);
 353 }
 354
 355 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
 356     static void pc_init_##suffix(MachineState *machine) \
 357     { \
 358         void (*compat)(MachineState *m) = (compatfn); \
 359         if (compat) { \
 360             compat(machine); \
 361         } \
 362         pc_q35_init(machine); \
 363     } \
 364     DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
 365
 366
 367 static void pc_q35_machine_options(MachineClass *m)
 368 {
 369     m->family = "pc_q35";
 370     m->desc = "Standard PC (Q35 + ICH9, 2009)";
 371     m->hot_add_cpu = pc_hot_add_cpu;
 372     m->units_per_default_bus = 1;
 373 }
 374
 375 static void pc_q35_2_4_machine_options(MachineClass *m)
 376 {
 377     pc_q35_machine_options(m);
 378     m->default_machine_opts = "firmware=bios-256k.bin";
 379     m->default_display = "std";
 380     m->no_floppy = 1;
 381     m->no_tco = 0;
 382     m->alias = "q35";
 383 }
 384
 385 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
 386                    pc_q35_2_4_machine_options);
 387
 388
 389 static void pc_q35_2_3_machine_options(MachineClass *m)
 390 {
 391     pc_q35_2_4_machine_options(m);
 392     m->no_floppy = 0;
 393     m->no_tco = 1;
 394     m->alias = NULL;
 395     SET_MACHINE_COMPAT(m, PC_COMPAT_2_3);
 396 }
 397
 398 DEFINE_Q35_MACHINE(v2_3, "pc-q35-2.3", pc_compat_2_3,
 399                    pc_q35_2_3_machine_options);
 400
 401
 402 static void pc_q35_2_2_machine_options(MachineClass *m)
 403 {
 404     pc_q35_2_3_machine_options(m);
 405     SET_MACHINE_COMPAT(m, PC_COMPAT_2_2);
 406 }
 407
 408 DEFINE_Q35_MACHINE(v2_2, "pc-q35-2.2", pc_compat_2_2,
 409                    pc_q35_2_2_machine_options);
 410
 411
 412 static void pc_q35_2_1_machine_options(MachineClass *m)
 413 {
 414     pc_q35_2_2_machine_options(m);
 415     m->default_display = NULL;
 416     SET_MACHINE_COMPAT(m, PC_COMPAT_2_1);
 417 }
 418
 419 DEFINE_Q35_MACHINE(v2_1, "pc-q35-2.1", pc_compat_2_1,
 420                    pc_q35_2_1_machine_options);
 421
 422
 423 static void pc_q35_2_0_machine_options(MachineClass *m)
 424 {
 425     pc_q35_2_1_machine_options(m);
 426     SET_MACHINE_COMPAT(m, PC_COMPAT_2_0);
 427 }
 428
 429 DEFINE_Q35_MACHINE(v2_0, "pc-q35-2.0", pc_compat_2_0,
 430                    pc_q35_2_0_machine_options);
 431
 432
 433 static void pc_q35_1_7_machine_options(MachineClass *m)
 434 {
 435     pc_q35_2_0_machine_options(m);
 436     m->default_machine_opts = NULL;
 437     SET_MACHINE_COMPAT(m, PC_COMPAT_1_7);
 438 }
 439
 440 DEFINE_Q35_MACHINE(v1_7, "pc-q35-1.7", pc_compat_1_7,
 441                    pc_q35_1_7_machine_options);
 442
 443
 444 static void pc_q35_1_6_machine_options(MachineClass *m)
 445 {
 446     pc_q35_machine_options(m);
 447     SET_MACHINE_COMPAT(m, PC_COMPAT_1_6);
 448 }
 449
 450 DEFINE_Q35_MACHINE(v1_6, "pc-q35-1.6", pc_compat_1_6,
 451                    pc_q35_1_6_machine_options);
 452
 453
 454 static void pc_q35_1_5_machine_options(MachineClass *m)
 455 {
 456     pc_q35_1_6_machine_options(m);
 457     SET_MACHINE_COMPAT(m, PC_COMPAT_1_5);
 458 }
 459
 460 DEFINE_Q35_MACHINE(v1_5, "pc-q35-1.5", pc_compat_1_5,
 461                    pc_q35_1_5_machine_options);
 462
 463
 464 static void pc_q35_1_4_machine_options(MachineClass *m)
 465 {
 466     pc_q35_1_5_machine_options(m);
 467     m->hot_add_cpu = NULL;
 468     SET_MACHINE_COMPAT(m, PC_COMPAT_1_4);
 469 }
 470
 471 DEFINE_Q35_MACHINE(v1_4, "pc-q35-1.4", pc_compat_1_4,
 472                    pc_q35_1_4_machine_options);