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target/i386: Pass buffer and length to XSAVE helper
[qemu/kevin.git] / target / i386 / kvm / kvm.c
blob41b0764ab770592b895f1035b16e8b7161151475
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/qapi-events-run-state.h"
17 #include "qapi/error.h"
18 #include <sys/ioctl.h>
19 #include <sys/utsname.h>
20
21 #include <linux/kvm.h>
22 #include "standard-headers/asm-x86/kvm_para.h"
23
24 #include "cpu.h"
25 #include "host-cpu.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/hw_accel.h"
28 #include "sysemu/kvm_int.h"
29 #include "sysemu/runstate.h"
30 #include "kvm_i386.h"
31 #include "sev_i386.h"
32 #include "hyperv.h"
33 #include "hyperv-proto.h"
34
35 #include "exec/gdbstub.h"
36 #include "qemu/host-utils.h"
37 #include "qemu/main-loop.h"
38 #include "qemu/config-file.h"
39 #include "qemu/error-report.h"
40 #include "hw/i386/x86.h"
41 #include "hw/i386/apic.h"
42 #include "hw/i386/apic_internal.h"
43 #include "hw/i386/apic-msidef.h"
44 #include "hw/i386/intel_iommu.h"
45 #include "hw/i386/x86-iommu.h"
46 #include "hw/i386/e820_memory_layout.h"
47 #include "sysemu/sev.h"
48
49 #include "hw/pci/pci.h"
50 #include "hw/pci/msi.h"
51 #include "hw/pci/msix.h"
52 #include "migration/blocker.h"
53 #include "exec/memattrs.h"
54 #include "trace.h"
55
56 //#define DEBUG_KVM
57
58 #ifdef DEBUG_KVM
59 #define DPRINTF(fmt, ...) \
60 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
61 #else
62 #define DPRINTF(fmt, ...) \
63 do { } while (0)
64 #endif
65
66 /* From arch/x86/kvm/lapic.h */
67 #define KVM_APIC_BUS_CYCLE_NS 1
68 #define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS)
69
70 #define MSR_KVM_WALL_CLOCK 0x11
71 #define MSR_KVM_SYSTEM_TIME 0x12
72
73 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
74 * 255 kvm_msr_entry structs */
75 #define MSR_BUF_SIZE 4096
76
77 static void kvm_init_msrs(X86CPU *cpu);
78
79 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
80 KVM_CAP_INFO(SET_TSS_ADDR),
81 KVM_CAP_INFO(EXT_CPUID),
82 KVM_CAP_INFO(MP_STATE),
83 KVM_CAP_LAST_INFO
84 };
85
86 static bool has_msr_star;
87 static bool has_msr_hsave_pa;
88 static bool has_msr_tsc_aux;
89 static bool has_msr_tsc_adjust;
90 static bool has_msr_tsc_deadline;
91 static bool has_msr_feature_control;
92 static bool has_msr_misc_enable;
93 static bool has_msr_smbase;
94 static bool has_msr_bndcfgs;
95 static int lm_capable_kernel;
96 static bool has_msr_hv_hypercall;
97 static bool has_msr_hv_crash;
98 static bool has_msr_hv_reset;
99 static bool has_msr_hv_vpindex;
100 static bool hv_vpindex_settable;
101 static bool has_msr_hv_runtime;
102 static bool has_msr_hv_synic;
103 static bool has_msr_hv_stimer;
104 static bool has_msr_hv_frequencies;
105 static bool has_msr_hv_reenlightenment;
106 static bool has_msr_xss;
107 static bool has_msr_umwait;
108 static bool has_msr_spec_ctrl;
109 static bool has_msr_tsx_ctrl;
110 static bool has_msr_virt_ssbd;
111 static bool has_msr_smi_count;
112 static bool has_msr_arch_capabs;
113 static bool has_msr_core_capabs;
114 static bool has_msr_vmx_vmfunc;
115 static bool has_msr_ucode_rev;
116 static bool has_msr_vmx_procbased_ctls2;
117 static bool has_msr_perf_capabs;
118 static bool has_msr_pkrs;
119
120 static uint32_t has_architectural_pmu_version;
121 static uint32_t num_architectural_pmu_gp_counters;
122 static uint32_t num_architectural_pmu_fixed_counters;
123
124 static int has_xsave;
125 static int has_xcrs;
126 static int has_pit_state2;
127 static int has_exception_payload;
128
129 static bool has_msr_mcg_ext_ctl;
130
131 static struct kvm_cpuid2 *cpuid_cache;
132 static struct kvm_cpuid2 *hv_cpuid_cache;
133 static struct kvm_msr_list *kvm_feature_msrs;
134
135 #define BUS_LOCK_SLICE_TIME 1000000000ULL /* ns */
136 static RateLimit bus_lock_ratelimit_ctrl;
137
138 int kvm_has_pit_state2(void)
139 {
140 return has_pit_state2;
141 }
142
143 bool kvm_has_smm(void)
144 {
145 return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM);
146 }
147
148 bool kvm_has_adjust_clock_stable(void)
149 {
150 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
151
152 return (ret == KVM_CLOCK_TSC_STABLE);
153 }
154
155 bool kvm_has_adjust_clock(void)
156 {
157 return kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
158 }
159
160 bool kvm_has_exception_payload(void)
161 {
162 return has_exception_payload;
163 }
164
165 static bool kvm_x2apic_api_set_flags(uint64_t flags)
166 {
167 KVMState *s = KVM_STATE(current_accel());
168
169 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
170 }
171
172 #define MEMORIZE(fn, _result) \
173 ({ \
174 static bool _memorized; \
175 \
176 if (_memorized) { \
177 return _result; \
178 } \
179 _memorized = true; \
180 _result = fn; \
181 })
182
183 static bool has_x2apic_api;
184
185 bool kvm_has_x2apic_api(void)
186 {
187 return has_x2apic_api;
188 }
189
190 bool kvm_enable_x2apic(void)
191 {
192 return MEMORIZE(
193 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
194 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
195 has_x2apic_api);
196 }
197
198 bool kvm_hv_vpindex_settable(void)
199 {
200 return hv_vpindex_settable;
201 }
202
203 static int kvm_get_tsc(CPUState *cs)
204 {
205 X86CPU *cpu = X86_CPU(cs);
206 CPUX86State *env = &cpu->env;
207 struct {
208 struct kvm_msrs info;
209 struct kvm_msr_entry entries[1];
210 } msr_data = {};
211 int ret;
212
213 if (env->tsc_valid) {
214 return 0;
215 }
216
217 memset(&msr_data, 0, sizeof(msr_data));
218 msr_data.info.nmsrs = 1;
219 msr_data.entries[0].index = MSR_IA32_TSC;
220 env->tsc_valid = !runstate_is_running();
221
222 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
223 if (ret < 0) {
224 return ret;
225 }
226
227 assert(ret == 1);
228 env->tsc = msr_data.entries[0].data;
229 return 0;
230 }
231
232 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
233 {
234 kvm_get_tsc(cpu);
235 }
236
237 void kvm_synchronize_all_tsc(void)
238 {
239 CPUState *cpu;
240
241 if (kvm_enabled()) {
242 CPU_FOREACH(cpu) {
243 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
244 }
245 }
246 }
247
248 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
249 {
250 struct kvm_cpuid2 *cpuid;
251 int r, size;
252
253 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
254 cpuid = g_malloc0(size);
255 cpuid->nent = max;
256 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
257 if (r == 0 && cpuid->nent >= max) {
258 r = -E2BIG;
259 }
260 if (r < 0) {
261 if (r == -E2BIG) {
262 g_free(cpuid);
263 return NULL;
264 } else {
265 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
266 strerror(-r));
267 exit(1);
268 }
269 }
270 return cpuid;
271 }
272
273 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
274 * for all entries.
275 */
276 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
277 {
278 struct kvm_cpuid2 *cpuid;
279 int max = 1;
280
281 if (cpuid_cache != NULL) {
282 return cpuid_cache;
283 }
284 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
285 max *= 2;
286 }
287 cpuid_cache = cpuid;
288 return cpuid;
289 }
290
291 static bool host_tsx_broken(void)
292 {
293 int family, model, stepping;\
294 char vendor[CPUID_VENDOR_SZ + 1];
295
296 host_cpu_vendor_fms(vendor, &family, &model, &stepping);
297
298 /* Check if we are running on a Haswell host known to have broken TSX */
299 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
300 (family == 6) &&
301 ((model == 63 && stepping < 4) ||
302 model == 60 || model == 69 || model == 70);
303 }
304
305 /* Returns the value for a specific register on the cpuid entry
306 */
307 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
308 {
309 uint32_t ret = 0;
310 switch (reg) {
311 case R_EAX:
312 ret = entry->eax;
313 break;
314 case R_EBX:
315 ret = entry->ebx;
316 break;
317 case R_ECX:
318 ret = entry->ecx;
319 break;
320 case R_EDX:
321 ret = entry->edx;
322 break;
323 }
324 return ret;
325 }
326
327 /* Find matching entry for function/index on kvm_cpuid2 struct
328 */
329 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
330 uint32_t function,
331 uint32_t index)
332 {
333 int i;
334 for (i = 0; i < cpuid->nent; ++i) {
335 if (cpuid->entries[i].function == function &&
336 cpuid->entries[i].index == index) {
337 return &cpuid->entries[i];
338 }
339 }
340 /* not found: */
341 return NULL;
342 }
343
344 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
345 uint32_t index, int reg)
346 {
347 struct kvm_cpuid2 *cpuid;
348 uint32_t ret = 0;
349 uint32_t cpuid_1_edx;
350
351 cpuid = get_supported_cpuid(s);
352
353 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
354 if (entry) {
355 ret = cpuid_entry_get_reg(entry, reg);
356 }
357
358 /* Fixups for the data returned by KVM, below */
359
360 if (function == 1 && reg == R_EDX) {
361 /* KVM before 2.6.30 misreports the following features */
362 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
363 } else if (function == 1 && reg == R_ECX) {
364 /* We can set the hypervisor flag, even if KVM does not return it on
365 * GET_SUPPORTED_CPUID
366 */
367 ret |= CPUID_EXT_HYPERVISOR;
368 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
369 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
370 * and the irqchip is in the kernel.
371 */
372 if (kvm_irqchip_in_kernel() &&
373 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
374 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
375 }
376
377 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
378 * without the in-kernel irqchip
379 */
380 if (!kvm_irqchip_in_kernel()) {
381 ret &= ~CPUID_EXT_X2APIC;
382 }
383
384 if (enable_cpu_pm) {
385 int disable_exits = kvm_check_extension(s,
386 KVM_CAP_X86_DISABLE_EXITS);
387
388 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
389 ret |= CPUID_EXT_MONITOR;
390 }
391 }
392 } else if (function == 6 && reg == R_EAX) {
393 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
394 } else if (function == 7 && index == 0 && reg == R_EBX) {
395 if (host_tsx_broken()) {
396 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
397 }
398 } else if (function == 7 && index == 0 && reg == R_EDX) {
399 /*
400 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
401 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
402 * returned by KVM_GET_MSR_INDEX_LIST.
403 */
404 if (!has_msr_arch_capabs) {
405 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
406 }
407 } else if (function == 0x80000001 && reg == R_ECX) {
408 /*
409 * It's safe to enable TOPOEXT even if it's not returned by
410 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
411 * us to keep CPU models including TOPOEXT runnable on older kernels.
412 */
413 ret |= CPUID_EXT3_TOPOEXT;
414 } else if (function == 0x80000001 && reg == R_EDX) {
415 /* On Intel, kvm returns cpuid according to the Intel spec,
416 * so add missing bits according to the AMD spec:
417 */
418 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
419 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
420 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
421 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
422 * be enabled without the in-kernel irqchip
423 */
424 if (!kvm_irqchip_in_kernel()) {
425 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
426 }
427 if (kvm_irqchip_is_split()) {
428 ret |= 1U << KVM_FEATURE_MSI_EXT_DEST_ID;
429 }
430 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
431 ret |= 1U << KVM_HINTS_REALTIME;
432 }
433
434 return ret;
435 }
436
437 uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
438 {
439 struct {
440 struct kvm_msrs info;
441 struct kvm_msr_entry entries[1];
442 } msr_data = {};
443 uint64_t value;
444 uint32_t ret, can_be_one, must_be_one;
445
446 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
447 return 0;
448 }
449
450 /* Check if requested MSR is supported feature MSR */
451 int i;
452 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
453 if (kvm_feature_msrs->indices[i] == index) {
454 break;
455 }
456 if (i == kvm_feature_msrs->nmsrs) {
457 return 0; /* if the feature MSR is not supported, simply return 0 */
458 }
459
460 msr_data.info.nmsrs = 1;
461 msr_data.entries[0].index = index;
462
463 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
464 if (ret != 1) {
465 error_report("KVM get MSR (index=0x%x) feature failed, %s",
466 index, strerror(-ret));
467 exit(1);
468 }
469
470 value = msr_data.entries[0].data;
471 switch (index) {
472 case MSR_IA32_VMX_PROCBASED_CTLS2:
473 if (!has_msr_vmx_procbased_ctls2) {
474 /* KVM forgot to add these bits for some time, do this ourselves. */
475 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) &
476 CPUID_XSAVE_XSAVES) {
477 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
478 }
479 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) &
480 CPUID_EXT_RDRAND) {
481 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
482 }
483 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
484 CPUID_7_0_EBX_INVPCID) {
485 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
486 }
487 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
488 CPUID_7_0_EBX_RDSEED) {
489 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
490 }
491 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) &
492 CPUID_EXT2_RDTSCP) {
493 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
494 }
495 }
496 /* fall through */
497 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
498 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
499 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
500 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
501 /*
502 * Return true for bits that can be one, but do not have to be one.
503 * The SDM tells us which bits could have a "must be one" setting,
504 * so we can do the opposite transformation in make_vmx_msr_value.
505 */
506 must_be_one = (uint32_t)value;
507 can_be_one = (uint32_t)(value >> 32);
508 return can_be_one & ~must_be_one;
509
510 default:
511 return value;
512 }
513 }
514
515 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
516 int *max_banks)
517 {
518 int r;
519
520 r = kvm_check_extension(s, KVM_CAP_MCE);
521 if (r > 0) {
522 *max_banks = r;
523 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
524 }
525 return -ENOSYS;
526 }
527
528 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
529 {
530 CPUState *cs = CPU(cpu);
531 CPUX86State *env = &cpu->env;
532 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
533 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
534 uint64_t mcg_status = MCG_STATUS_MCIP;
535 int flags = 0;
536
537 if (code == BUS_MCEERR_AR) {
538 status |= MCI_STATUS_AR | 0x134;
539 mcg_status |= MCG_STATUS_EIPV;
540 } else {
541 status |= 0xc0;
542 mcg_status |= MCG_STATUS_RIPV;
543 }
544
545 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
546 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
547 * guest kernel back into env->mcg_ext_ctl.
548 */
549 cpu_synchronize_state(cs);
550 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
551 mcg_status |= MCG_STATUS_LMCE;
552 flags = 0;
553 }
554
555 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
556 (MCM_ADDR_PHYS << 6) | 0xc, flags);
557 }
558
559 static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar)
560 {
561 MemoryFailureFlags mff = {.action_required = ar, .recursive = false};
562
563 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action,
564 &mff);
565 }
566
567 static void hardware_memory_error(void *host_addr)
568 {
569 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true);
570 error_report("QEMU got Hardware memory error at addr %p", host_addr);
571 exit(1);
572 }
573
574 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
575 {
576 X86CPU *cpu = X86_CPU(c);
577 CPUX86State *env = &cpu->env;
578 ram_addr_t ram_addr;
579 hwaddr paddr;
580
581 /* If we get an action required MCE, it has been injected by KVM
582 * while the VM was running. An action optional MCE instead should
583 * be coming from the main thread, which qemu_init_sigbus identifies
584 * as the "early kill" thread.
585 */
586 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
587
588 if ((env->mcg_cap & MCG_SER_P) && addr) {
589 ram_addr = qemu_ram_addr_from_host(addr);
590 if (ram_addr != RAM_ADDR_INVALID &&
591 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
592 kvm_hwpoison_page_add(ram_addr);
593 kvm_mce_inject(cpu, paddr, code);
594
595 /*
596 * Use different logging severity based on error type.
597 * If there is additional MCE reporting on the hypervisor, QEMU VA
598 * could be another source to identify the PA and MCE details.
599 */
600 if (code == BUS_MCEERR_AR) {
601 error_report("Guest MCE Memory Error at QEMU addr %p and "
602 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
603 addr, paddr, "BUS_MCEERR_AR");
604 } else {
605 warn_report("Guest MCE Memory Error at QEMU addr %p and "
606 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
607 addr, paddr, "BUS_MCEERR_AO");
608 }
609
610 return;
611 }
612
613 if (code == BUS_MCEERR_AO) {
614 warn_report("Hardware memory error at addr %p of type %s "
615 "for memory used by QEMU itself instead of guest system!",
616 addr, "BUS_MCEERR_AO");
617 }
618 }
619
620 if (code == BUS_MCEERR_AR) {
621 hardware_memory_error(addr);
622 }
623
624 /* Hope we are lucky for AO MCE, just notify a event */
625 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false);
626 }
627
628 static void kvm_reset_exception(CPUX86State *env)
629 {
630 env->exception_nr = -1;
631 env->exception_pending = 0;
632 env->exception_injected = 0;
633 env->exception_has_payload = false;
634 env->exception_payload = 0;
635 }
636
637 static void kvm_queue_exception(CPUX86State *env,
638 int32_t exception_nr,
639 uint8_t exception_has_payload,
640 uint64_t exception_payload)
641 {
642 assert(env->exception_nr == -1);
643 assert(!env->exception_pending);
644 assert(!env->exception_injected);
645 assert(!env->exception_has_payload);
646
647 env->exception_nr = exception_nr;
648
649 if (has_exception_payload) {
650 env->exception_pending = 1;
651
652 env->exception_has_payload = exception_has_payload;
653 env->exception_payload = exception_payload;
654 } else {
655 env->exception_injected = 1;
656
657 if (exception_nr == EXCP01_DB) {
658 assert(exception_has_payload);
659 env->dr[6] = exception_payload;
660 } else if (exception_nr == EXCP0E_PAGE) {
661 assert(exception_has_payload);
662 env->cr[2] = exception_payload;
663 } else {
664 assert(!exception_has_payload);
665 }
666 }
667 }
668
669 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
670 {
671 CPUX86State *env = &cpu->env;
672
673 if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) {
674 unsigned int bank, bank_num = env->mcg_cap & 0xff;
675 struct kvm_x86_mce mce;
676
677 kvm_reset_exception(env);
678
679 /*
680 * There must be at least one bank in use if an MCE is pending.
681 * Find it and use its values for the event injection.
682 */
683 for (bank = 0; bank < bank_num; bank++) {
684 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
685 break;
686 }
687 }
688 assert(bank < bank_num);
689
690 mce.bank = bank;
691 mce.status = env->mce_banks[bank * 4 + 1];
692 mce.mcg_status = env->mcg_status;
693 mce.addr = env->mce_banks[bank * 4 + 2];
694 mce.misc = env->mce_banks[bank * 4 + 3];
695
696 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
697 }
698 return 0;
699 }
700
701 static void cpu_update_state(void *opaque, bool running, RunState state)
702 {
703 CPUX86State *env = opaque;
704
705 if (running) {
706 env->tsc_valid = false;
707 }
708 }
709
710 unsigned long kvm_arch_vcpu_id(CPUState *cs)
711 {
712 X86CPU *cpu = X86_CPU(cs);
713 return cpu->apic_id;
714 }
715
716 #ifndef KVM_CPUID_SIGNATURE_NEXT
717 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
718 #endif
719
720 static bool hyperv_enabled(X86CPU *cpu)
721 {
722 return kvm_check_extension(kvm_state, KVM_CAP_HYPERV) > 0 &&
723 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) ||
724 cpu->hyperv_features || cpu->hyperv_passthrough);
725 }
726
727 /*
728 * Check whether target_freq is within conservative
729 * ntp correctable bounds (250ppm) of freq
730 */
731 static inline bool freq_within_bounds(int freq, int target_freq)
732 {
733 int max_freq = freq + (freq * 250 / 1000000);
734 int min_freq = freq - (freq * 250 / 1000000);
735
736 if (target_freq >= min_freq && target_freq <= max_freq) {
737 return true;
738 }
739
740 return false;
741 }
742
743 static int kvm_arch_set_tsc_khz(CPUState *cs)
744 {
745 X86CPU *cpu = X86_CPU(cs);
746 CPUX86State *env = &cpu->env;
747 int r, cur_freq;
748 bool set_ioctl = false;
749
750 if (!env->tsc_khz) {
751 return 0;
752 }
753
754 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
755 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP;
756
757 /*
758 * If TSC scaling is supported, attempt to set TSC frequency.
759 */
760 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) {
761 set_ioctl = true;
762 }
763
764 /*
765 * If desired TSC frequency is within bounds of NTP correction,
766 * attempt to set TSC frequency.
767 */
768 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) {
769 set_ioctl = true;
770 }
771
772 r = set_ioctl ?
773 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
774 -ENOTSUP;
775
776 if (r < 0) {
777 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
778 * TSC frequency doesn't match the one we want.
779 */
780 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
781 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
782 -ENOTSUP;
783 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
784 warn_report("TSC frequency mismatch between "
785 "VM (%" PRId64 " kHz) and host (%d kHz), "
786 "and TSC scaling unavailable",
787 env->tsc_khz, cur_freq);
788 return r;
789 }
790 }
791
792 return 0;
793 }
794
795 static bool tsc_is_stable_and_known(CPUX86State *env)
796 {
797 if (!env->tsc_khz) {
798 return false;
799 }
800 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
801 || env->user_tsc_khz;
802 }
803
804 static struct {
805 const char *desc;
806 struct {
807 uint32_t func;
808 int reg;
809 uint32_t bits;
810 } flags[2];
811 uint64_t dependencies;
812 } kvm_hyperv_properties[] = {
813 [HYPERV_FEAT_RELAXED] = {
814 .desc = "relaxed timing (hv-relaxed)",
815 .flags = {
816 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
817 .bits = HV_HYPERCALL_AVAILABLE},
818 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
819 .bits = HV_RELAXED_TIMING_RECOMMENDED}
820 }
821 },
822 [HYPERV_FEAT_VAPIC] = {
823 .desc = "virtual APIC (hv-vapic)",
824 .flags = {
825 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
826 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
827 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
828 .bits = HV_APIC_ACCESS_RECOMMENDED}
829 }
830 },
831 [HYPERV_FEAT_TIME] = {
832 .desc = "clocksources (hv-time)",
833 .flags = {
834 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
835 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
836 HV_REFERENCE_TSC_AVAILABLE}
837 }
838 },
839 [HYPERV_FEAT_CRASH] = {
840 .desc = "crash MSRs (hv-crash)",
841 .flags = {
842 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
843 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
844 }
845 },
846 [HYPERV_FEAT_RESET] = {
847 .desc = "reset MSR (hv-reset)",
848 .flags = {
849 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
850 .bits = HV_RESET_AVAILABLE}
851 }
852 },
853 [HYPERV_FEAT_VPINDEX] = {
854 .desc = "VP_INDEX MSR (hv-vpindex)",
855 .flags = {
856 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
857 .bits = HV_VP_INDEX_AVAILABLE}
858 }
859 },
860 [HYPERV_FEAT_RUNTIME] = {
861 .desc = "VP_RUNTIME MSR (hv-runtime)",
862 .flags = {
863 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
864 .bits = HV_VP_RUNTIME_AVAILABLE}
865 }
866 },
867 [HYPERV_FEAT_SYNIC] = {
868 .desc = "synthetic interrupt controller (hv-synic)",
869 .flags = {
870 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
871 .bits = HV_SYNIC_AVAILABLE}
872 }
873 },
874 [HYPERV_FEAT_STIMER] = {
875 .desc = "synthetic timers (hv-stimer)",
876 .flags = {
877 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
878 .bits = HV_SYNTIMERS_AVAILABLE}
879 },
880 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
881 },
882 [HYPERV_FEAT_FREQUENCIES] = {
883 .desc = "frequency MSRs (hv-frequencies)",
884 .flags = {
885 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
886 .bits = HV_ACCESS_FREQUENCY_MSRS},
887 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
888 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
889 }
890 },
891 [HYPERV_FEAT_REENLIGHTENMENT] = {
892 .desc = "reenlightenment MSRs (hv-reenlightenment)",
893 .flags = {
894 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
895 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
896 }
897 },
898 [HYPERV_FEAT_TLBFLUSH] = {
899 .desc = "paravirtualized TLB flush (hv-tlbflush)",
900 .flags = {
901 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
902 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
903 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
904 },
905 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
906 },
907 [HYPERV_FEAT_EVMCS] = {
908 .desc = "enlightened VMCS (hv-evmcs)",
909 .flags = {
910 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
911 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
912 },
913 .dependencies = BIT(HYPERV_FEAT_VAPIC)
914 },
915 [HYPERV_FEAT_IPI] = {
916 .desc = "paravirtualized IPI (hv-ipi)",
917 .flags = {
918 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
919 .bits = HV_CLUSTER_IPI_RECOMMENDED |
920 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
921 },
922 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
923 },
924 [HYPERV_FEAT_STIMER_DIRECT] = {
925 .desc = "direct mode synthetic timers (hv-stimer-direct)",
926 .flags = {
927 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
928 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
929 },
930 .dependencies = BIT(HYPERV_FEAT_STIMER)
931 },
932 };
933
934 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max,
935 bool do_sys_ioctl)
936 {
937 struct kvm_cpuid2 *cpuid;
938 int r, size;
939
940 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
941 cpuid = g_malloc0(size);
942 cpuid->nent = max;
943
944 if (do_sys_ioctl) {
945 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
946 } else {
947 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
948 }
949 if (r == 0 && cpuid->nent >= max) {
950 r = -E2BIG;
951 }
952 if (r < 0) {
953 if (r == -E2BIG) {
954 g_free(cpuid);
955 return NULL;
956 } else {
957 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
958 strerror(-r));
959 exit(1);
960 }
961 }
962 return cpuid;
963 }
964
965 /*
966 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
967 * for all entries.
968 */
969 static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
970 {
971 struct kvm_cpuid2 *cpuid;
972 /* 0x40000000..0x40000005, 0x4000000A, 0x40000080..0x40000080 leaves */
973 int max = 10;
974 int i;
975 bool do_sys_ioctl;
976
977 do_sys_ioctl =
978 kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID) > 0;
979
980 /*
981 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
982 * -E2BIG, however, it doesn't report back the right size. Keep increasing
983 * it and re-trying until we succeed.
984 */
985 while ((cpuid = try_get_hv_cpuid(cs, max, do_sys_ioctl)) == NULL) {
986 max++;
987 }
988
989 /*
990 * KVM_GET_SUPPORTED_HV_CPUID does not set EVMCS CPUID bit before
991 * KVM_CAP_HYPERV_ENLIGHTENED_VMCS is enabled but we want to get the
992 * information early, just check for the capability and set the bit
993 * manually.
994 */
995 if (!do_sys_ioctl && kvm_check_extension(cs->kvm_state,
996 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
997 for (i = 0; i < cpuid->nent; i++) {
998 if (cpuid->entries[i].function == HV_CPUID_ENLIGHTMENT_INFO) {
999 cpuid->entries[i].eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1000 }
1001 }
1002 }
1003
1004 return cpuid;
1005 }
1006
1007 /*
1008 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
1009 * leaves from KVM_CAP_HYPERV* and present MSRs data.
1010 */
1011 static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
1012 {
1013 X86CPU *cpu = X86_CPU(cs);
1014 struct kvm_cpuid2 *cpuid;
1015 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
1016
1017 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
1018 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
1019 cpuid->nent = 2;
1020
1021 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
1022 entry_feat = &cpuid->entries[0];
1023 entry_feat->function = HV_CPUID_FEATURES;
1024
1025 entry_recomm = &cpuid->entries[1];
1026 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
1027 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
1028
1029 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
1030 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
1031 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
1032 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1033 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1034 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1035 }
1036
1037 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1038 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1039 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
1040 }
1041
1042 if (has_msr_hv_frequencies) {
1043 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1044 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
1045 }
1046
1047 if (has_msr_hv_crash) {
1048 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
1049 }
1050
1051 if (has_msr_hv_reenlightenment) {
1052 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
1053 }
1054
1055 if (has_msr_hv_reset) {
1056 entry_feat->eax |= HV_RESET_AVAILABLE;
1057 }
1058
1059 if (has_msr_hv_vpindex) {
1060 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
1061 }
1062
1063 if (has_msr_hv_runtime) {
1064 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
1065 }
1066
1067 if (has_msr_hv_synic) {
1068 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1069 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1070
1071 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1072 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1073 }
1074 }
1075
1076 if (has_msr_hv_stimer) {
1077 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
1078 }
1079
1080 if (kvm_check_extension(cs->kvm_state,
1081 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1082 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1083 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1084 }
1085
1086 if (kvm_check_extension(cs->kvm_state,
1087 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1088 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1089 }
1090
1091 if (kvm_check_extension(cs->kvm_state,
1092 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1093 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1094 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1095 }
1096
1097 return cpuid;
1098 }
1099
1100 static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg)
1101 {
1102 struct kvm_cpuid_entry2 *entry;
1103 struct kvm_cpuid2 *cpuid;
1104
1105 if (hv_cpuid_cache) {
1106 cpuid = hv_cpuid_cache;
1107 } else {
1108 if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1109 cpuid = get_supported_hv_cpuid(cs);
1110 } else {
1111 cpuid = get_supported_hv_cpuid_legacy(cs);
1112 }
1113 hv_cpuid_cache = cpuid;
1114 }
1115
1116 if (!cpuid) {
1117 return 0;
1118 }
1119
1120 entry = cpuid_find_entry(cpuid, func, 0);
1121 if (!entry) {
1122 return 0;
1123 }
1124
1125 return cpuid_entry_get_reg(entry, reg);
1126 }
1127
1128 static bool hyperv_feature_supported(CPUState *cs, int feature)
1129 {
1130 uint32_t func, bits;
1131 int i, reg;
1132
1133 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1134
1135 func = kvm_hyperv_properties[feature].flags[i].func;
1136 reg = kvm_hyperv_properties[feature].flags[i].reg;
1137 bits = kvm_hyperv_properties[feature].flags[i].bits;
1138
1139 if (!func) {
1140 continue;
1141 }
1142
1143 if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) {
1144 return false;
1145 }
1146 }
1147
1148 return true;
1149 }
1150
1151 static int hv_cpuid_check_and_set(CPUState *cs, int feature, Error **errp)
1152 {
1153 X86CPU *cpu = X86_CPU(cs);
1154 uint64_t deps;
1155 int dep_feat;
1156
1157 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
1158 return 0;
1159 }
1160
1161 deps = kvm_hyperv_properties[feature].dependencies;
1162 while (deps) {
1163 dep_feat = ctz64(deps);
1164 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1165 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1166 kvm_hyperv_properties[feature].desc,
1167 kvm_hyperv_properties[dep_feat].desc);
1168 return 1;
1169 }
1170 deps &= ~(1ull << dep_feat);
1171 }
1172
1173 if (!hyperv_feature_supported(cs, feature)) {
1174 if (hyperv_feat_enabled(cpu, feature)) {
1175 error_setg(errp, "Hyper-V %s is not supported by kernel",
1176 kvm_hyperv_properties[feature].desc);
1177 return 1;
1178 } else {
1179 return 0;
1180 }
1181 }
1182
1183 if (cpu->hyperv_passthrough) {
1184 cpu->hyperv_features |= BIT(feature);
1185 }
1186
1187 return 0;
1188 }
1189
1190 static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg)
1191 {
1192 X86CPU *cpu = X86_CPU(cs);
1193 uint32_t r = 0;
1194 int i, j;
1195
1196 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) {
1197 if (!hyperv_feat_enabled(cpu, i)) {
1198 continue;
1199 }
1200
1201 for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) {
1202 if (kvm_hyperv_properties[i].flags[j].func != func) {
1203 continue;
1204 }
1205 if (kvm_hyperv_properties[i].flags[j].reg != reg) {
1206 continue;
1207 }
1208
1209 r |= kvm_hyperv_properties[i].flags[j].bits;
1210 }
1211 }
1212
1213 return r;
1214 }
1215
1216 /*
1217 * Expand Hyper-V CPU features. In partucular, check that all the requested
1218 * features are supported by the host and the sanity of the configuration
1219 * (that all the required dependencies are included). Also, this takes care
1220 * of 'hv_passthrough' mode and fills the environment with all supported
1221 * Hyper-V features.
1222 */
1223 static void hyperv_expand_features(CPUState *cs, Error **errp)
1224 {
1225 X86CPU *cpu = X86_CPU(cs);
1226
1227 if (!hyperv_enabled(cpu))
1228 return;
1229
1230 if (cpu->hyperv_passthrough) {
1231 cpu->hyperv_vendor_id[0] =
1232 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX);
1233 cpu->hyperv_vendor_id[1] =
1234 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX);
1235 cpu->hyperv_vendor_id[2] =
1236 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX);
1237 cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor,
1238 sizeof(cpu->hyperv_vendor_id) + 1);
1239 memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id,
1240 sizeof(cpu->hyperv_vendor_id));
1241 cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0;
1242
1243 cpu->hyperv_interface_id[0] =
1244 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX);
1245 cpu->hyperv_interface_id[1] =
1246 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX);
1247 cpu->hyperv_interface_id[2] =
1248 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX);
1249 cpu->hyperv_interface_id[3] =
1250 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX);
1251
1252 cpu->hyperv_version_id[0] =
1253 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX);
1254 cpu->hyperv_version_id[1] =
1255 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX);
1256 cpu->hyperv_version_id[2] =
1257 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX);
1258 cpu->hyperv_version_id[3] =
1259 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX);
1260
1261 cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS,
1262 R_EAX);
1263 cpu->hyperv_limits[0] =
1264 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX);
1265 cpu->hyperv_limits[1] =
1266 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX);
1267 cpu->hyperv_limits[2] =
1268 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX);
1269
1270 cpu->hyperv_spinlock_attempts =
1271 hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX);
1272 }
1273
1274 /* Features */
1275 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_RELAXED, errp)) {
1276 return;
1277 }
1278 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_VAPIC, errp)) {
1279 return;
1280 }
1281 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_TIME, errp)) {
1282 return;
1283 }
1284 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_CRASH, errp)) {
1285 return;
1286 }
1287 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_RESET, errp)) {
1288 return;
1289 }
1290 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_VPINDEX, errp)) {
1291 return;
1292 }
1293 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_RUNTIME, errp)) {
1294 return;
1295 }
1296 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_SYNIC, errp)) {
1297 return;
1298 }
1299 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_STIMER, errp)) {
1300 return;
1301 }
1302 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_FREQUENCIES, errp)) {
1303 return;
1304 }
1305 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_REENLIGHTENMENT, errp)) {
1306 return;
1307 }
1308 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_TLBFLUSH, errp)) {
1309 return;
1310 }
1311 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_EVMCS, errp)) {
1312 return;
1313 }
1314 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_IPI, errp)) {
1315 return;
1316 }
1317 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_STIMER_DIRECT, errp)) {
1318 return;
1319 }
1320
1321 /* Additional dependencies not covered by kvm_hyperv_properties[] */
1322 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1323 !cpu->hyperv_synic_kvm_only &&
1324 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
1325 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1326 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1327 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1328 }
1329 }
1330
1331 /*
1332 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent.
1333 */
1334 static int hyperv_fill_cpuids(CPUState *cs,
1335 struct kvm_cpuid_entry2 *cpuid_ent)
1336 {
1337 X86CPU *cpu = X86_CPU(cs);
1338 struct kvm_cpuid_entry2 *c;
1339 uint32_t cpuid_i = 0;
1340
1341 c = &cpuid_ent[cpuid_i++];
1342 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1343 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1344 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1345 c->ebx = cpu->hyperv_vendor_id[0];
1346 c->ecx = cpu->hyperv_vendor_id[1];
1347 c->edx = cpu->hyperv_vendor_id[2];
1348
1349 c = &cpuid_ent[cpuid_i++];
1350 c->function = HV_CPUID_INTERFACE;
1351 c->eax = cpu->hyperv_interface_id[0];
1352 c->ebx = cpu->hyperv_interface_id[1];
1353 c->ecx = cpu->hyperv_interface_id[2];
1354 c->edx = cpu->hyperv_interface_id[3];
1355
1356 c = &cpuid_ent[cpuid_i++];
1357 c->function = HV_CPUID_VERSION;
1358 c->eax = cpu->hyperv_version_id[0];
1359 c->ebx = cpu->hyperv_version_id[1];
1360 c->ecx = cpu->hyperv_version_id[2];
1361 c->edx = cpu->hyperv_version_id[3];
1362
1363 c = &cpuid_ent[cpuid_i++];
1364 c->function = HV_CPUID_FEATURES;
1365 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX);
1366 c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX);
1367 c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX);
1368
1369 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1370 c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1371
1372 c = &cpuid_ent[cpuid_i++];
1373 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1374 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX);
1375 c->ebx = cpu->hyperv_spinlock_attempts;
1376
1377 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1378 c->eax |= HV_NO_NONARCH_CORESHARING;
1379 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
1380 c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) &
1381 HV_NO_NONARCH_CORESHARING;
1382 }
1383
1384 c = &cpuid_ent[cpuid_i++];
1385 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1386 c->eax = cpu->hv_max_vps;
1387 c->ebx = cpu->hyperv_limits[0];
1388 c->ecx = cpu->hyperv_limits[1];
1389 c->edx = cpu->hyperv_limits[2];
1390
1391 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1392 __u32 function;
1393
1394 /* Create zeroed 0x40000006..0x40000009 leaves */
1395 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1396 function < HV_CPUID_NESTED_FEATURES; function++) {
1397 c = &cpuid_ent[cpuid_i++];
1398 c->function = function;
1399 }
1400
1401 c = &cpuid_ent[cpuid_i++];
1402 c->function = HV_CPUID_NESTED_FEATURES;
1403 c->eax = cpu->hyperv_nested[0];
1404 }
1405
1406 return cpuid_i;
1407 }
1408
1409 static Error *hv_passthrough_mig_blocker;
1410 static Error *hv_no_nonarch_cs_mig_blocker;
1411
1412 static int hyperv_init_vcpu(X86CPU *cpu)
1413 {
1414 CPUState *cs = CPU(cpu);
1415 Error *local_err = NULL;
1416 int ret;
1417
1418 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1419 error_setg(&hv_passthrough_mig_blocker,
1420 "'hv-passthrough' CPU flag prevents migration, use explicit"
1421 " set of hv-* flags instead");
1422 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1423 if (local_err) {
1424 error_report_err(local_err);
1425 error_free(hv_passthrough_mig_blocker);
1426 return ret;
1427 }
1428 }
1429
1430 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1431 hv_no_nonarch_cs_mig_blocker == NULL) {
1432 error_setg(&hv_no_nonarch_cs_mig_blocker,
1433 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1434 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1435 " make sure SMT is disabled and/or that vCPUs are properly"
1436 " pinned)");
1437 ret = migrate_add_blocker(hv_no_nonarch_cs_mig_blocker, &local_err);
1438 if (local_err) {
1439 error_report_err(local_err);
1440 error_free(hv_no_nonarch_cs_mig_blocker);
1441 return ret;
1442 }
1443 }
1444
1445 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
1446 /*
1447 * the kernel doesn't support setting vp_index; assert that its value
1448 * is in sync
1449 */
1450 struct {
1451 struct kvm_msrs info;
1452 struct kvm_msr_entry entries[1];
1453 } msr_data = {
1454 .info.nmsrs = 1,
1455 .entries[0].index = HV_X64_MSR_VP_INDEX,
1456 };
1457
1458 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
1459 if (ret < 0) {
1460 return ret;
1461 }
1462 assert(ret == 1);
1463
1464 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
1465 error_report("kernel's vp_index != QEMU's vp_index");
1466 return -ENXIO;
1467 }
1468 }
1469
1470 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1471 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1472 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1473 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
1474 if (ret < 0) {
1475 error_report("failed to turn on HyperV SynIC in KVM: %s",
1476 strerror(-ret));
1477 return ret;
1478 }
1479
1480 if (!cpu->hyperv_synic_kvm_only) {
1481 ret = hyperv_x86_synic_add(cpu);
1482 if (ret < 0) {
1483 error_report("failed to create HyperV SynIC: %s",
1484 strerror(-ret));
1485 return ret;
1486 }
1487 }
1488 }
1489
1490 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1491 uint16_t evmcs_version;
1492
1493 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1494 (uintptr_t)&evmcs_version);
1495
1496 if (ret < 0) {
1497 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1498 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
1499 return ret;
1500 }
1501
1502 cpu->hyperv_nested[0] = evmcs_version;
1503 }
1504
1505 return 0;
1506 }
1507
1508 static Error *invtsc_mig_blocker;
1509
1510 #define KVM_MAX_CPUID_ENTRIES 100
1511
1512 int kvm_arch_init_vcpu(CPUState *cs)
1513 {
1514 struct {
1515 struct kvm_cpuid2 cpuid;
1516 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
1517 } cpuid_data;
1518 /*
1519 * The kernel defines these structs with padding fields so there
1520 * should be no extra padding in our cpuid_data struct.
1521 */
1522 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1523 sizeof(struct kvm_cpuid2) +
1524 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1525
1526 X86CPU *cpu = X86_CPU(cs);
1527 CPUX86State *env = &cpu->env;
1528 uint32_t limit, i, j, cpuid_i;
1529 uint32_t unused;
1530 struct kvm_cpuid_entry2 *c;
1531 uint32_t signature[3];
1532 int kvm_base = KVM_CPUID_SIGNATURE;
1533 int max_nested_state_len;
1534 int r;
1535 Error *local_err = NULL;
1536
1537 memset(&cpuid_data, 0, sizeof(cpuid_data));
1538
1539 cpuid_i = 0;
1540
1541 r = kvm_arch_set_tsc_khz(cs);
1542 if (r < 0) {
1543 return r;
1544 }
1545
1546 /* vcpu's TSC frequency is either specified by user, or following
1547 * the value used by KVM if the former is not present. In the
1548 * latter case, we query it from KVM and record in env->tsc_khz,
1549 * so that vcpu's TSC frequency can be migrated later via this field.
1550 */
1551 if (!env->tsc_khz) {
1552 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1553 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1554 -ENOTSUP;
1555 if (r > 0) {
1556 env->tsc_khz = r;
1557 }
1558 }
1559
1560 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY;
1561
1562 /* Paravirtualization CPUIDs */
1563 hyperv_expand_features(cs, &local_err);
1564 if (local_err) {
1565 error_report_err(local_err);
1566 return -ENOSYS;
1567 }
1568
1569 if (hyperv_enabled(cpu)) {
1570 r = hyperv_init_vcpu(cpu);
1571 if (r) {
1572 return r;
1573 }
1574
1575 cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries);
1576 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
1577 has_msr_hv_hypercall = true;
1578 }
1579
1580 if (cpu->expose_kvm) {
1581 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1582 c = &cpuid_data.entries[cpuid_i++];
1583 c->function = KVM_CPUID_SIGNATURE | kvm_base;
1584 c->eax = KVM_CPUID_FEATURES | kvm_base;
1585 c->ebx = signature[0];
1586 c->ecx = signature[1];
1587 c->edx = signature[2];
1588
1589 c = &cpuid_data.entries[cpuid_i++];
1590 c->function = KVM_CPUID_FEATURES | kvm_base;
1591 c->eax = env->features[FEAT_KVM];
1592 c->edx = env->features[FEAT_KVM_HINTS];
1593 }
1594
1595 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1596
1597 for (i = 0; i <= limit; i++) {
1598 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1599 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1600 abort();
1601 }
1602 c = &cpuid_data.entries[cpuid_i++];
1603
1604 switch (i) {
1605 case 2: {
1606 /* Keep reading function 2 till all the input is received */
1607 int times;
1608
1609 c->function = i;
1610 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1611 KVM_CPUID_FLAG_STATE_READ_NEXT;
1612 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1613 times = c->eax & 0xff;
1614
1615 for (j = 1; j < times; ++j) {
1616 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1617 fprintf(stderr, "cpuid_data is full, no space for "
1618 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1619 abort();
1620 }
1621 c = &cpuid_data.entries[cpuid_i++];
1622 c->function = i;
1623 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1624 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1625 }
1626 break;
1627 }
1628 case 0x1f:
1629 if (env->nr_dies < 2) {
1630 break;
1631 }
1632 /* fallthrough */
1633 case 4:
1634 case 0xb:
1635 case 0xd:
1636 for (j = 0; ; j++) {
1637 if (i == 0xd && j == 64) {
1638 break;
1639 }
1640
1641 if (i == 0x1f && j == 64) {
1642 break;
1643 }
1644
1645 c->function = i;
1646 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1647 c->index = j;
1648 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1649
1650 if (i == 4 && c->eax == 0) {
1651 break;
1652 }
1653 if (i == 0xb && !(c->ecx & 0xff00)) {
1654 break;
1655 }
1656 if (i == 0x1f && !(c->ecx & 0xff00)) {
1657 break;
1658 }
1659 if (i == 0xd && c->eax == 0) {
1660 continue;
1661 }
1662 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1663 fprintf(stderr, "cpuid_data is full, no space for "
1664 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1665 abort();
1666 }
1667 c = &cpuid_data.entries[cpuid_i++];
1668 }
1669 break;
1670 case 0x7:
1671 case 0x14: {
1672 uint32_t times;
1673
1674 c->function = i;
1675 c->index = 0;
1676 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1677 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1678 times = c->eax;
1679
1680 for (j = 1; j <= times; ++j) {
1681 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1682 fprintf(stderr, "cpuid_data is full, no space for "
1683 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1684 abort();
1685 }
1686 c = &cpuid_data.entries[cpuid_i++];
1687 c->function = i;
1688 c->index = j;
1689 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1690 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1691 }
1692 break;
1693 }
1694 default:
1695 c->function = i;
1696 c->flags = 0;
1697 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1698 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1699 /*
1700 * KVM already returns all zeroes if a CPUID entry is missing,
1701 * so we can omit it and avoid hitting KVM's 80-entry limit.
1702 */
1703 cpuid_i--;
1704 }
1705 break;
1706 }
1707 }
1708
1709 if (limit >= 0x0a) {
1710 uint32_t eax, edx;
1711
1712 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1713
1714 has_architectural_pmu_version = eax & 0xff;
1715 if (has_architectural_pmu_version > 0) {
1716 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1717
1718 /* Shouldn't be more than 32, since that's the number of bits
1719 * available in EBX to tell us _which_ counters are available.
1720 * Play it safe.
1721 */
1722 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1723 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1724 }
1725
1726 if (has_architectural_pmu_version > 1) {
1727 num_architectural_pmu_fixed_counters = edx & 0x1f;
1728
1729 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1730 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1731 }
1732 }
1733 }
1734 }
1735
1736 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1737
1738 for (i = 0x80000000; i <= limit; i++) {
1739 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1740 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1741 abort();
1742 }
1743 c = &cpuid_data.entries[cpuid_i++];
1744
1745 switch (i) {
1746 case 0x8000001d:
1747 /* Query for all AMD cache information leaves */
1748 for (j = 0; ; j++) {
1749 c->function = i;
1750 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1751 c->index = j;
1752 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1753
1754 if (c->eax == 0) {
1755 break;
1756 }
1757 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1758 fprintf(stderr, "cpuid_data is full, no space for "
1759 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1760 abort();
1761 }
1762 c = &cpuid_data.entries[cpuid_i++];
1763 }
1764 break;
1765 default:
1766 c->function = i;
1767 c->flags = 0;
1768 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1769 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1770 /*
1771 * KVM already returns all zeroes if a CPUID entry is missing,
1772 * so we can omit it and avoid hitting KVM's 80-entry limit.
1773 */
1774 cpuid_i--;
1775 }
1776 break;
1777 }
1778 }
1779
1780 /* Call Centaur's CPUID instructions they are supported. */
1781 if (env->cpuid_xlevel2 > 0) {
1782 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1783
1784 for (i = 0xC0000000; i <= limit; i++) {
1785 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1786 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1787 abort();
1788 }
1789 c = &cpuid_data.entries[cpuid_i++];
1790
1791 c->function = i;
1792 c->flags = 0;
1793 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1794 }
1795 }
1796
1797 cpuid_data.cpuid.nent = cpuid_i;
1798
1799 if (((env->cpuid_version >> 8)&0xF) >= 6
1800 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
1801 (CPUID_MCE | CPUID_MCA)
1802 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
1803 uint64_t mcg_cap, unsupported_caps;
1804 int banks;
1805 int ret;
1806
1807 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
1808 if (ret < 0) {
1809 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1810 return ret;
1811 }
1812
1813 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
1814 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1815 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
1816 return -ENOTSUP;
1817 }
1818
1819 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1820 if (unsupported_caps) {
1821 if (unsupported_caps & MCG_LMCE_P) {
1822 error_report("kvm: LMCE not supported");
1823 return -ENOTSUP;
1824 }
1825 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1826 unsupported_caps);
1827 }
1828
1829 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1830 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
1831 if (ret < 0) {
1832 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1833 return ret;
1834 }
1835 }
1836
1837 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env);
1838
1839 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1840 if (c) {
1841 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1842 !!(c->ecx & CPUID_EXT_SMX);
1843 }
1844
1845 if (env->mcg_cap & MCG_LMCE_P) {
1846 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1847 }
1848
1849 if (!env->user_tsc_khz) {
1850 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1851 invtsc_mig_blocker == NULL) {
1852 error_setg(&invtsc_mig_blocker,
1853 "State blocked by non-migratable CPU device"
1854 " (invtsc flag)");
1855 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1856 if (local_err) {
1857 error_report_err(local_err);
1858 error_free(invtsc_mig_blocker);
1859 return r;
1860 }
1861 }
1862 }
1863
1864 if (cpu->vmware_cpuid_freq
1865 /* Guests depend on 0x40000000 to detect this feature, so only expose
1866 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1867 && cpu->expose_kvm
1868 && kvm_base == KVM_CPUID_SIGNATURE
1869 /* TSC clock must be stable and known for this feature. */
1870 && tsc_is_stable_and_known(env)) {
1871
1872 c = &cpuid_data.entries[cpuid_i++];
1873 c->function = KVM_CPUID_SIGNATURE | 0x10;
1874 c->eax = env->tsc_khz;
1875 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
1876 c->ecx = c->edx = 0;
1877
1878 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1879 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1880 }
1881
1882 cpuid_data.cpuid.nent = cpuid_i;
1883
1884 cpuid_data.cpuid.padding = 0;
1885 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1886 if (r) {
1887 goto fail;
1888 }
1889
1890 if (has_xsave) {
1891 env->xsave_buf_len = sizeof(struct kvm_xsave);
1892 env->xsave_buf = qemu_memalign(4096, env->xsave_buf_len);
1893 memset(env->xsave_buf, 0, env->xsave_buf_len);
1894 }
1895
1896 max_nested_state_len = kvm_max_nested_state_length();
1897 if (max_nested_state_len > 0) {
1898 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
1899
1900 if (cpu_has_vmx(env) || cpu_has_svm(env)) {
1901 struct kvm_vmx_nested_state_hdr *vmx_hdr;
1902
1903 env->nested_state = g_malloc0(max_nested_state_len);
1904 env->nested_state->size = max_nested_state_len;
1905
1906 if (cpu_has_vmx(env)) {
1907 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1908 vmx_hdr = &env->nested_state->hdr.vmx;
1909 vmx_hdr->vmxon_pa = -1ull;
1910 vmx_hdr->vmcs12_pa = -1ull;
1911 } else {
1912 env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM;
1913 }
1914 }
1915 }
1916
1917 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1918
1919 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1920 has_msr_tsc_aux = false;
1921 }
1922
1923 kvm_init_msrs(cpu);
1924
1925 return 0;
1926
1927 fail:
1928 migrate_del_blocker(invtsc_mig_blocker);
1929
1930 return r;
1931 }
1932
1933 int kvm_arch_destroy_vcpu(CPUState *cs)
1934 {
1935 X86CPU *cpu = X86_CPU(cs);
1936 CPUX86State *env = &cpu->env;
1937
1938 if (cpu->kvm_msr_buf) {
1939 g_free(cpu->kvm_msr_buf);
1940 cpu->kvm_msr_buf = NULL;
1941 }
1942
1943 if (env->nested_state) {
1944 g_free(env->nested_state);
1945 env->nested_state = NULL;
1946 }
1947
1948 qemu_del_vm_change_state_handler(cpu->vmsentry);
1949
1950 return 0;
1951 }
1952
1953 void kvm_arch_reset_vcpu(X86CPU *cpu)
1954 {
1955 CPUX86State *env = &cpu->env;
1956
1957 env->xcr0 = 1;
1958 if (kvm_irqchip_in_kernel()) {
1959 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1960 KVM_MP_STATE_UNINITIALIZED;
1961 } else {
1962 env->mp_state = KVM_MP_STATE_RUNNABLE;
1963 }
1964
1965 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1966 int i;
1967 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1968 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1969 }
1970
1971 hyperv_x86_synic_reset(cpu);
1972 }
1973 /* enabled by default */
1974 env->poll_control_msr = 1;
1975
1976 sev_es_set_reset_vector(CPU(cpu));
1977 }
1978
1979 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1980 {
1981 CPUX86State *env = &cpu->env;
1982
1983 /* APs get directly into wait-for-SIPI state. */
1984 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1985 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1986 }
1987 }
1988
1989 static int kvm_get_supported_feature_msrs(KVMState *s)
1990 {
1991 int ret = 0;
1992
1993 if (kvm_feature_msrs != NULL) {
1994 return 0;
1995 }
1996
1997 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1998 return 0;
1999 }
2000
2001 struct kvm_msr_list msr_list;
2002
2003 msr_list.nmsrs = 0;
2004 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
2005 if (ret < 0 && ret != -E2BIG) {
2006 error_report("Fetch KVM feature MSR list failed: %s",
2007 strerror(-ret));
2008 return ret;
2009 }
2010
2011 assert(msr_list.nmsrs > 0);
2012 kvm_feature_msrs = (struct kvm_msr_list *) \
2013 g_malloc0(sizeof(msr_list) +
2014 msr_list.nmsrs * sizeof(msr_list.indices[0]));
2015
2016 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
2017 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
2018
2019 if (ret < 0) {
2020 error_report("Fetch KVM feature MSR list failed: %s",
2021 strerror(-ret));
2022 g_free(kvm_feature_msrs);
2023 kvm_feature_msrs = NULL;
2024 return ret;
2025 }
2026
2027 return 0;
2028 }
2029
2030 static int kvm_get_supported_msrs(KVMState *s)
2031 {
2032 int ret = 0;
2033 struct kvm_msr_list msr_list, *kvm_msr_list;
2034
2035 /*
2036 * Obtain MSR list from KVM. These are the MSRs that we must
2037 * save/restore.
2038 */
2039 msr_list.nmsrs = 0;
2040 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
2041 if (ret < 0 && ret != -E2BIG) {
2042 return ret;
2043 }
2044 /*
2045 * Old kernel modules had a bug and could write beyond the provided
2046 * memory. Allocate at least a safe amount of 1K.
2047 */
2048 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
2049 msr_list.nmsrs *
2050 sizeof(msr_list.indices[0])));
2051
2052 kvm_msr_list->nmsrs = msr_list.nmsrs;
2053 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
2054 if (ret >= 0) {
2055 int i;
2056
2057 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
2058 switch (kvm_msr_list->indices[i]) {
2059 case MSR_STAR:
2060 has_msr_star = true;
2061 break;
2062 case MSR_VM_HSAVE_PA:
2063 has_msr_hsave_pa = true;
2064 break;
2065 case MSR_TSC_AUX:
2066 has_msr_tsc_aux = true;
2067 break;
2068 case MSR_TSC_ADJUST:
2069 has_msr_tsc_adjust = true;
2070 break;
2071 case MSR_IA32_TSCDEADLINE:
2072 has_msr_tsc_deadline = true;
2073 break;
2074 case MSR_IA32_SMBASE:
2075 has_msr_smbase = true;
2076 break;
2077 case MSR_SMI_COUNT:
2078 has_msr_smi_count = true;
2079 break;
2080 case MSR_IA32_MISC_ENABLE:
2081 has_msr_misc_enable = true;
2082 break;
2083 case MSR_IA32_BNDCFGS:
2084 has_msr_bndcfgs = true;
2085 break;
2086 case MSR_IA32_XSS:
2087 has_msr_xss = true;
2088 break;
2089 case MSR_IA32_UMWAIT_CONTROL:
2090 has_msr_umwait = true;
2091 break;
2092 case HV_X64_MSR_CRASH_CTL:
2093 has_msr_hv_crash = true;
2094 break;
2095 case HV_X64_MSR_RESET:
2096 has_msr_hv_reset = true;
2097 break;
2098 case HV_X64_MSR_VP_INDEX:
2099 has_msr_hv_vpindex = true;
2100 break;
2101 case HV_X64_MSR_VP_RUNTIME:
2102 has_msr_hv_runtime = true;
2103 break;
2104 case HV_X64_MSR_SCONTROL:
2105 has_msr_hv_synic = true;
2106 break;
2107 case HV_X64_MSR_STIMER0_CONFIG:
2108 has_msr_hv_stimer = true;
2109 break;
2110 case HV_X64_MSR_TSC_FREQUENCY:
2111 has_msr_hv_frequencies = true;
2112 break;
2113 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2114 has_msr_hv_reenlightenment = true;
2115 break;
2116 case MSR_IA32_SPEC_CTRL:
2117 has_msr_spec_ctrl = true;
2118 break;
2119 case MSR_IA32_TSX_CTRL:
2120 has_msr_tsx_ctrl = true;
2121 break;
2122 case MSR_VIRT_SSBD:
2123 has_msr_virt_ssbd = true;
2124 break;
2125 case MSR_IA32_ARCH_CAPABILITIES:
2126 has_msr_arch_capabs = true;
2127 break;
2128 case MSR_IA32_CORE_CAPABILITY:
2129 has_msr_core_capabs = true;
2130 break;
2131 case MSR_IA32_PERF_CAPABILITIES:
2132 has_msr_perf_capabs = true;
2133 break;
2134 case MSR_IA32_VMX_VMFUNC:
2135 has_msr_vmx_vmfunc = true;
2136 break;
2137 case MSR_IA32_UCODE_REV:
2138 has_msr_ucode_rev = true;
2139 break;
2140 case MSR_IA32_VMX_PROCBASED_CTLS2:
2141 has_msr_vmx_procbased_ctls2 = true;
2142 break;
2143 case MSR_IA32_PKRS:
2144 has_msr_pkrs = true;
2145 break;
2146 }
2147 }
2148 }
2149
2150 g_free(kvm_msr_list);
2151
2152 return ret;
2153 }
2154
2155 static Notifier smram_machine_done;
2156 static KVMMemoryListener smram_listener;
2157 static AddressSpace smram_address_space;
2158 static MemoryRegion smram_as_root;
2159 static MemoryRegion smram_as_mem;
2160
2161 static void register_smram_listener(Notifier *n, void *unused)
2162 {
2163 MemoryRegion *smram =
2164 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2165
2166 /* Outer container... */
2167 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2168 memory_region_set_enabled(&smram_as_root, true);
2169
2170 /* ... with two regions inside: normal system memory with low
2171 * priority, and...
2172 */
2173 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2174 get_system_memory(), 0, ~0ull);
2175 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2176 memory_region_set_enabled(&smram_as_mem, true);
2177
2178 if (smram) {
2179 /* ... SMRAM with higher priority */
2180 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2181 memory_region_set_enabled(smram, true);
2182 }
2183
2184 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2185 kvm_memory_listener_register(kvm_state, &smram_listener,
2186 &smram_address_space, 1);
2187 }
2188
2189 int kvm_arch_init(MachineState *ms, KVMState *s)
2190 {
2191 uint64_t identity_base = 0xfffbc000;
2192 uint64_t shadow_mem;
2193 int ret;
2194 struct utsname utsname;
2195 Error *local_err = NULL;
2196
2197 /*
2198 * Initialize SEV context, if required
2199 *
2200 * If no memory encryption is requested (ms->cgs == NULL) this is
2201 * a no-op.
2202 *
2203 * It's also a no-op if a non-SEV confidential guest support
2204 * mechanism is selected. SEV is the only mechanism available to
2205 * select on x86 at present, so this doesn't arise, but if new
2206 * mechanisms are supported in future (e.g. TDX), they'll need
2207 * their own initialization either here or elsewhere.
2208 */
2209 ret = sev_kvm_init(ms->cgs, &local_err);
2210 if (ret < 0) {
2211 error_report_err(local_err);
2212 return ret;
2213 }
2214
2215 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2216 error_report("kvm: KVM_CAP_IRQ_ROUTING not supported by KVM");
2217 return -ENOTSUP;
2218 }
2219
2220 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
2221 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
2222 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
2223
2224 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
2225
2226 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
2227 if (has_exception_payload) {
2228 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
2229 if (ret < 0) {
2230 error_report("kvm: Failed to enable exception payload cap: %s",
2231 strerror(-ret));
2232 return ret;
2233 }
2234 }
2235
2236 ret = kvm_get_supported_msrs(s);
2237 if (ret < 0) {
2238 return ret;
2239 }
2240
2241 kvm_get_supported_feature_msrs(s);
2242
2243 uname(&utsname);
2244 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
2245
2246 /*
2247 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2248 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2249 * Since these must be part of guest physical memory, we need to allocate
2250 * them, both by setting their start addresses in the kernel and by
2251 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2252 *
2253 * Older KVM versions may not support setting the identity map base. In
2254 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2255 * size.
2256 */
2257 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
2258 /* Allows up to 16M BIOSes. */
2259 identity_base = 0xfeffc000;
2260
2261 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
2262 if (ret < 0) {
2263 return ret;
2264 }
2265 }
2266
2267 /* Set TSS base one page after EPT identity map. */
2268 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
2269 if (ret < 0) {
2270 return ret;
2271 }
2272
2273 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2274 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
2275 if (ret < 0) {
2276 fprintf(stderr, "e820_add_entry() table is full\n");
2277 return ret;
2278 }
2279
2280 shadow_mem = object_property_get_int(OBJECT(s), "kvm-shadow-mem", &error_abort);
2281 if (shadow_mem != -1) {
2282 shadow_mem /= 4096;
2283 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
2284 if (ret < 0) {
2285 return ret;
2286 }
2287 }
2288
2289 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
2290 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) &&
2291 x86_machine_is_smm_enabled(X86_MACHINE(ms))) {
2292 smram_machine_done.notify = register_smram_listener;
2293 qemu_add_machine_init_done_notifier(&smram_machine_done);
2294 }
2295
2296 if (enable_cpu_pm) {
2297 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2298 int ret;
2299
2300 /* Work around for kernel header with a typo. TODO: fix header and drop. */
2301 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2302 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2303 #endif
2304 if (disable_exits) {
2305 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2306 KVM_X86_DISABLE_EXITS_HLT |
2307 KVM_X86_DISABLE_EXITS_PAUSE |
2308 KVM_X86_DISABLE_EXITS_CSTATE);
2309 }
2310
2311 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2312 disable_exits);
2313 if (ret < 0) {
2314 error_report("kvm: guest stopping CPU not supported: %s",
2315 strerror(-ret));
2316 }
2317 }
2318
2319 if (object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE)) {
2320 X86MachineState *x86ms = X86_MACHINE(ms);
2321
2322 if (x86ms->bus_lock_ratelimit > 0) {
2323 ret = kvm_check_extension(s, KVM_CAP_X86_BUS_LOCK_EXIT);
2324 if (!(ret & KVM_BUS_LOCK_DETECTION_EXIT)) {
2325 error_report("kvm: bus lock detection unsupported");
2326 return -ENOTSUP;
2327 }
2328 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_BUS_LOCK_EXIT, 0,
2329 KVM_BUS_LOCK_DETECTION_EXIT);
2330 if (ret < 0) {
2331 error_report("kvm: Failed to enable bus lock detection cap: %s",
2332 strerror(-ret));
2333 return ret;
2334 }
2335 ratelimit_init(&bus_lock_ratelimit_ctrl);
2336 ratelimit_set_speed(&bus_lock_ratelimit_ctrl,
2337 x86ms->bus_lock_ratelimit, BUS_LOCK_SLICE_TIME);
2338 }
2339 }
2340
2341 return 0;
2342 }
2343
2344 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2345 {
2346 lhs->selector = rhs->selector;
2347 lhs->base = rhs->base;
2348 lhs->limit = rhs->limit;
2349 lhs->type = 3;
2350 lhs->present = 1;
2351 lhs->dpl = 3;
2352 lhs->db = 0;
2353 lhs->s = 1;
2354 lhs->l = 0;
2355 lhs->g = 0;
2356 lhs->avl = 0;
2357 lhs->unusable = 0;
2358 }
2359
2360 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2361 {
2362 unsigned flags = rhs->flags;
2363 lhs->selector = rhs->selector;
2364 lhs->base = rhs->base;
2365 lhs->limit = rhs->limit;
2366 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2367 lhs->present = (flags & DESC_P_MASK) != 0;
2368 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
2369 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2370 lhs->s = (flags & DESC_S_MASK) != 0;
2371 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2372 lhs->g = (flags & DESC_G_MASK) != 0;
2373 lhs->avl = (flags & DESC_AVL_MASK) != 0;
2374 lhs->unusable = !lhs->present;
2375 lhs->padding = 0;
2376 }
2377
2378 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2379 {
2380 lhs->selector = rhs->selector;
2381 lhs->base = rhs->base;
2382 lhs->limit = rhs->limit;
2383 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2384 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2385 (rhs->dpl << DESC_DPL_SHIFT) |
2386 (rhs->db << DESC_B_SHIFT) |
2387 (rhs->s * DESC_S_MASK) |
2388 (rhs->l << DESC_L_SHIFT) |
2389 (rhs->g * DESC_G_MASK) |
2390 (rhs->avl * DESC_AVL_MASK);
2391 }
2392
2393 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2394 {
2395 if (set) {
2396 *kvm_reg = *qemu_reg;
2397 } else {
2398 *qemu_reg = *kvm_reg;
2399 }
2400 }
2401
2402 static int kvm_getput_regs(X86CPU *cpu, int set)
2403 {
2404 CPUX86State *env = &cpu->env;
2405 struct kvm_regs regs;
2406 int ret = 0;
2407
2408 if (!set) {
2409 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
2410 if (ret < 0) {
2411 return ret;
2412 }
2413 }
2414
2415 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2416 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2417 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2418 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2419 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2420 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2421 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2422 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2423 #ifdef TARGET_X86_64
2424 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2425 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2426 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2427 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2428 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2429 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2430 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2431 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2432 #endif
2433
2434 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2435 kvm_getput_reg(&regs.rip, &env->eip, set);
2436
2437 if (set) {
2438 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
2439 }
2440
2441 return ret;
2442 }
2443
2444 static int kvm_put_fpu(X86CPU *cpu)
2445 {
2446 CPUX86State *env = &cpu->env;
2447 struct kvm_fpu fpu;
2448 int i;
2449
2450 memset(&fpu, 0, sizeof fpu);
2451 fpu.fsw = env->fpus & ~(7 << 11);
2452 fpu.fsw |= (env->fpstt & 7) << 11;
2453 fpu.fcw = env->fpuc;
2454 fpu.last_opcode = env->fpop;
2455 fpu.last_ip = env->fpip;
2456 fpu.last_dp = env->fpdp;
2457 for (i = 0; i < 8; ++i) {
2458 fpu.ftwx |= (!env->fptags[i]) << i;
2459 }
2460 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
2461 for (i = 0; i < CPU_NB_REGS; i++) {
2462 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2463 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
2464 }
2465 fpu.mxcsr = env->mxcsr;
2466
2467 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
2468 }
2469
2470 static int kvm_put_xsave(X86CPU *cpu)
2471 {
2472 CPUX86State *env = &cpu->env;
2473 void *xsave = env->xsave_buf;
2474
2475 if (!has_xsave) {
2476 return kvm_put_fpu(cpu);
2477 }
2478 x86_cpu_xsave_all_areas(cpu, xsave, env->xsave_buf_len);
2479
2480 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
2481 }
2482
2483 static int kvm_put_xcrs(X86CPU *cpu)
2484 {
2485 CPUX86State *env = &cpu->env;
2486 struct kvm_xcrs xcrs = {};
2487
2488 if (!has_xcrs) {
2489 return 0;
2490 }
2491
2492 xcrs.nr_xcrs = 1;
2493 xcrs.flags = 0;
2494 xcrs.xcrs[0].xcr = 0;
2495 xcrs.xcrs[0].value = env->xcr0;
2496 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
2497 }
2498
2499 static int kvm_put_sregs(X86CPU *cpu)
2500 {
2501 CPUX86State *env = &cpu->env;
2502 struct kvm_sregs sregs;
2503
2504 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2505 if (env->interrupt_injected >= 0) {
2506 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2507 (uint64_t)1 << (env->interrupt_injected % 64);
2508 }
2509
2510 if ((env->eflags & VM_MASK)) {
2511 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2512 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2513 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2514 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2515 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2516 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
2517 } else {
2518 set_seg(&sregs.cs, &env->segs[R_CS]);
2519 set_seg(&sregs.ds, &env->segs[R_DS]);
2520 set_seg(&sregs.es, &env->segs[R_ES]);
2521 set_seg(&sregs.fs, &env->segs[R_FS]);
2522 set_seg(&sregs.gs, &env->segs[R_GS]);
2523 set_seg(&sregs.ss, &env->segs[R_SS]);
2524 }
2525
2526 set_seg(&sregs.tr, &env->tr);
2527 set_seg(&sregs.ldt, &env->ldt);
2528
2529 sregs.idt.limit = env->idt.limit;
2530 sregs.idt.base = env->idt.base;
2531 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
2532 sregs.gdt.limit = env->gdt.limit;
2533 sregs.gdt.base = env->gdt.base;
2534 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
2535
2536 sregs.cr0 = env->cr[0];
2537 sregs.cr2 = env->cr[2];
2538 sregs.cr3 = env->cr[3];
2539 sregs.cr4 = env->cr[4];
2540
2541 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2542 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
2543
2544 sregs.efer = env->efer;
2545
2546 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
2547 }
2548
2549 static void kvm_msr_buf_reset(X86CPU *cpu)
2550 {
2551 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2552 }
2553
2554 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2555 {
2556 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2557 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2558 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2559
2560 assert((void *)(entry + 1) <= limit);
2561
2562 entry->index = index;
2563 entry->reserved = 0;
2564 entry->data = value;
2565 msrs->nmsrs++;
2566 }
2567
2568 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2569 {
2570 kvm_msr_buf_reset(cpu);
2571 kvm_msr_entry_add(cpu, index, value);
2572
2573 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2574 }
2575
2576 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2577 {
2578 int ret;
2579
2580 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2581 assert(ret == 1);
2582 }
2583
2584 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2585 {
2586 CPUX86State *env = &cpu->env;
2587 int ret;
2588
2589 if (!has_msr_tsc_deadline) {
2590 return 0;
2591 }
2592
2593 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
2594 if (ret < 0) {
2595 return ret;
2596 }
2597
2598 assert(ret == 1);
2599 return 0;
2600 }
2601
2602 /*
2603 * Provide a separate write service for the feature control MSR in order to
2604 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2605 * before writing any other state because forcibly leaving nested mode
2606 * invalidates the VCPU state.
2607 */
2608 static int kvm_put_msr_feature_control(X86CPU *cpu)
2609 {
2610 int ret;
2611
2612 if (!has_msr_feature_control) {
2613 return 0;
2614 }
2615
2616 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2617 cpu->env.msr_ia32_feature_control);
2618 if (ret < 0) {
2619 return ret;
2620 }
2621
2622 assert(ret == 1);
2623 return 0;
2624 }
2625
2626 static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
2627 {
2628 uint32_t default1, can_be_one, can_be_zero;
2629 uint32_t must_be_one;
2630
2631 switch (index) {
2632 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2633 default1 = 0x00000016;
2634 break;
2635 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2636 default1 = 0x0401e172;
2637 break;
2638 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2639 default1 = 0x000011ff;
2640 break;
2641 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2642 default1 = 0x00036dff;
2643 break;
2644 case MSR_IA32_VMX_PROCBASED_CTLS2:
2645 default1 = 0;
2646 break;
2647 default:
2648 abort();
2649 }
2650
2651 /* If a feature bit is set, the control can be either set or clear.
2652 * Otherwise the value is limited to either 0 or 1 by default1.
2653 */
2654 can_be_one = features | default1;
2655 can_be_zero = features | ~default1;
2656 must_be_one = ~can_be_zero;
2657
2658 /*
2659 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
2660 * Bit 32:63 -> 1 if the control bit can be one.
2661 */
2662 return must_be_one | (((uint64_t)can_be_one) << 32);
2663 }
2664
2665 static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
2666 {
2667 uint64_t kvm_vmx_basic =
2668 kvm_arch_get_supported_msr_feature(kvm_state,
2669 MSR_IA32_VMX_BASIC);
2670
2671 if (!kvm_vmx_basic) {
2672 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
2673 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
2674 */
2675 return;
2676 }
2677
2678 uint64_t kvm_vmx_misc =
2679 kvm_arch_get_supported_msr_feature(kvm_state,
2680 MSR_IA32_VMX_MISC);
2681 uint64_t kvm_vmx_ept_vpid =
2682 kvm_arch_get_supported_msr_feature(kvm_state,
2683 MSR_IA32_VMX_EPT_VPID_CAP);
2684
2685 /*
2686 * If the guest is 64-bit, a value of 1 is allowed for the host address
2687 * space size vmexit control.
2688 */
2689 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
2690 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
2691
2692 /*
2693 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
2694 * not change them for backwards compatibility.
2695 */
2696 uint64_t fixed_vmx_basic = kvm_vmx_basic &
2697 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
2698 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
2699 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
2700
2701 /*
2702 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
2703 * change in the future but are always zero for now, clear them to be
2704 * future proof. Bits 32-63 in theory could change, though KVM does
2705 * not support dual-monitor treatment and probably never will; mask
2706 * them out as well.
2707 */
2708 uint64_t fixed_vmx_misc = kvm_vmx_misc &
2709 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
2710 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
2711
2712 /*
2713 * EPT memory types should not change either, so we do not bother
2714 * adding features for them.
2715 */
2716 uint64_t fixed_vmx_ept_mask =
2717 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
2718 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
2719 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
2720
2721 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2722 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2723 f[FEAT_VMX_PROCBASED_CTLS]));
2724 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2725 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2726 f[FEAT_VMX_PINBASED_CTLS]));
2727 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
2728 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
2729 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
2730 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2731 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2732 f[FEAT_VMX_ENTRY_CTLS]));
2733 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
2734 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
2735 f[FEAT_VMX_SECONDARY_CTLS]));
2736 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
2737 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
2738 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
2739 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
2740 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
2741 f[FEAT_VMX_MISC] | fixed_vmx_misc);
2742 if (has_msr_vmx_vmfunc) {
2743 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
2744 }
2745
2746 /*
2747 * Just to be safe, write these with constant values. The CRn_FIXED1
2748 * MSRs are generated by KVM based on the vCPU's CPUID.
2749 */
2750 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
2751 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
2752 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
2753 CR4_VMXE_MASK);
2754
2755 if (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_TSC_SCALING) {
2756 /* TSC multiplier (0x2032). */
2757 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x32);
2758 } else {
2759 /* Preemption timer (0x482E). */
2760 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x2E);
2761 }
2762 }
2763
2764 static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f)
2765 {
2766 uint64_t kvm_perf_cap =
2767 kvm_arch_get_supported_msr_feature(kvm_state,
2768 MSR_IA32_PERF_CAPABILITIES);
2769
2770 if (kvm_perf_cap) {
2771 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES,
2772 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]);
2773 }
2774 }
2775
2776 static int kvm_buf_set_msrs(X86CPU *cpu)
2777 {
2778 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2779 if (ret < 0) {
2780 return ret;
2781 }
2782
2783 if (ret < cpu->kvm_msr_buf->nmsrs) {
2784 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2785 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2786 (uint32_t)e->index, (uint64_t)e->data);
2787 }
2788
2789 assert(ret == cpu->kvm_msr_buf->nmsrs);
2790 return 0;
2791 }
2792
2793 static void kvm_init_msrs(X86CPU *cpu)
2794 {
2795 CPUX86State *env = &cpu->env;
2796
2797 kvm_msr_buf_reset(cpu);
2798 if (has_msr_arch_capabs) {
2799 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2800 env->features[FEAT_ARCH_CAPABILITIES]);
2801 }
2802
2803 if (has_msr_core_capabs) {
2804 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
2805 env->features[FEAT_CORE_CAPABILITY]);
2806 }
2807
2808 if (has_msr_perf_capabs && cpu->enable_pmu) {
2809 kvm_msr_entry_add_perf(cpu, env->features);
2810 }
2811
2812 if (has_msr_ucode_rev) {
2813 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
2814 }
2815
2816 /*
2817 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
2818 * all kernels with MSR features should have them.
2819 */
2820 if (kvm_feature_msrs && cpu_has_vmx(env)) {
2821 kvm_msr_entry_add_vmx(cpu, env->features);
2822 }
2823
2824 assert(kvm_buf_set_msrs(cpu) == 0);
2825 }
2826
2827 static int kvm_put_msrs(X86CPU *cpu, int level)
2828 {
2829 CPUX86State *env = &cpu->env;
2830 int i;
2831
2832 kvm_msr_buf_reset(cpu);
2833
2834 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2835 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2836 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2837 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
2838 if (has_msr_star) {
2839 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
2840 }
2841 if (has_msr_hsave_pa) {
2842 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
2843 }
2844 if (has_msr_tsc_aux) {
2845 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
2846 }
2847 if (has_msr_tsc_adjust) {
2848 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
2849 }
2850 if (has_msr_misc_enable) {
2851 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
2852 env->msr_ia32_misc_enable);
2853 }
2854 if (has_msr_smbase) {
2855 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
2856 }
2857 if (has_msr_smi_count) {
2858 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2859 }
2860 if (has_msr_pkrs) {
2861 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs);
2862 }
2863 if (has_msr_bndcfgs) {
2864 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
2865 }
2866 if (has_msr_xss) {
2867 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
2868 }
2869 if (has_msr_umwait) {
2870 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
2871 }
2872 if (has_msr_spec_ctrl) {
2873 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2874 }
2875 if (has_msr_tsx_ctrl) {
2876 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
2877 }
2878 if (has_msr_virt_ssbd) {
2879 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2880 }
2881
2882 #ifdef TARGET_X86_64
2883 if (lm_capable_kernel) {
2884 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2885 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2886 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2887 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
2888 }
2889 #endif
2890
2891 /*
2892 * The following MSRs have side effects on the guest or are too heavy
2893 * for normal writeback. Limit them to reset or full state updates.
2894 */
2895 if (level >= KVM_PUT_RESET_STATE) {
2896 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2897 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2898 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
2899 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
2900 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr);
2901 }
2902 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2903 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
2904 }
2905 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2906 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
2907 }
2908 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2909 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
2910 }
2911
2912 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
2913 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
2914 }
2915
2916 if (has_architectural_pmu_version > 0) {
2917 if (has_architectural_pmu_version > 1) {
2918 /* Stop the counter. */
2919 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2920 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2921 }
2922
2923 /* Set the counter values. */
2924 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2925 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
2926 env->msr_fixed_counters[i]);
2927 }
2928 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2929 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
2930 env->msr_gp_counters[i]);
2931 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
2932 env->msr_gp_evtsel[i]);
2933 }
2934 if (has_architectural_pmu_version > 1) {
2935 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2936 env->msr_global_status);
2937 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2938 env->msr_global_ovf_ctrl);
2939
2940 /* Now start the PMU. */
2941 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2942 env->msr_fixed_ctr_ctrl);
2943 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2944 env->msr_global_ctrl);
2945 }
2946 }
2947 /*
2948 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2949 * only sync them to KVM on the first cpu
2950 */
2951 if (current_cpu == first_cpu) {
2952 if (has_msr_hv_hypercall) {
2953 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2954 env->msr_hv_guest_os_id);
2955 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2956 env->msr_hv_hypercall);
2957 }
2958 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
2959 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2960 env->msr_hv_tsc);
2961 }
2962 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
2963 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2964 env->msr_hv_reenlightenment_control);
2965 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2966 env->msr_hv_tsc_emulation_control);
2967 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2968 env->msr_hv_tsc_emulation_status);
2969 }
2970 }
2971 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
2972 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
2973 env->msr_hv_vapic);
2974 }
2975 if (has_msr_hv_crash) {
2976 int j;
2977
2978 for (j = 0; j < HV_CRASH_PARAMS; j++)
2979 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
2980 env->msr_hv_crash_params[j]);
2981
2982 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
2983 }
2984 if (has_msr_hv_runtime) {
2985 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
2986 }
2987 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2988 && hv_vpindex_settable) {
2989 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2990 hyperv_vp_index(CPU(cpu)));
2991 }
2992 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
2993 int j;
2994
2995 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2996
2997 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
2998 env->msr_hv_synic_control);
2999 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
3000 env->msr_hv_synic_evt_page);
3001 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
3002 env->msr_hv_synic_msg_page);
3003
3004 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
3005 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
3006 env->msr_hv_synic_sint[j]);
3007 }
3008 }
3009 if (has_msr_hv_stimer) {
3010 int j;
3011
3012 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
3013 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
3014 env->msr_hv_stimer_config[j]);
3015 }
3016
3017 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
3018 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
3019 env->msr_hv_stimer_count[j]);
3020 }
3021 }
3022 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
3023 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
3024
3025 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
3026 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
3027 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
3028 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
3029 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
3030 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
3031 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
3032 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
3033 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
3034 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
3035 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
3036 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
3037 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
3038 /* The CPU GPs if we write to a bit above the physical limit of
3039 * the host CPU (and KVM emulates that)
3040 */
3041 uint64_t mask = env->mtrr_var[i].mask;
3042 mask &= phys_mask;
3043
3044 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
3045 env->mtrr_var[i].base);
3046 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
3047 }
3048 }
3049 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3050 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
3051 0x14, 1, R_EAX) & 0x7;
3052
3053 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
3054 env->msr_rtit_ctrl);
3055 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
3056 env->msr_rtit_status);
3057 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
3058 env->msr_rtit_output_base);
3059 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
3060 env->msr_rtit_output_mask);
3061 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
3062 env->msr_rtit_cr3_match);
3063 for (i = 0; i < addr_num; i++) {
3064 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
3065 env->msr_rtit_addrs[i]);
3066 }
3067 }
3068
3069 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
3070 * kvm_put_msr_feature_control. */
3071 }
3072
3073 if (env->mcg_cap) {
3074 int i;
3075
3076 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
3077 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
3078 if (has_msr_mcg_ext_ctl) {
3079 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
3080 }
3081 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
3082 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
3083 }
3084 }
3085
3086 return kvm_buf_set_msrs(cpu);
3087 }
3088
3089
3090 static int kvm_get_fpu(X86CPU *cpu)
3091 {
3092 CPUX86State *env = &cpu->env;
3093 struct kvm_fpu fpu;
3094 int i, ret;
3095
3096 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
3097 if (ret < 0) {
3098 return ret;
3099 }
3100
3101 env->fpstt = (fpu.fsw >> 11) & 7;
3102 env->fpus = fpu.fsw;
3103 env->fpuc = fpu.fcw;
3104 env->fpop = fpu.last_opcode;
3105 env->fpip = fpu.last_ip;
3106 env->fpdp = fpu.last_dp;
3107 for (i = 0; i < 8; ++i) {
3108 env->fptags[i] = !((fpu.ftwx >> i) & 1);
3109 }
3110 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
3111 for (i = 0; i < CPU_NB_REGS; i++) {
3112 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
3113 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
3114 }
3115 env->mxcsr = fpu.mxcsr;
3116
3117 return 0;
3118 }
3119
3120 static int kvm_get_xsave(X86CPU *cpu)
3121 {
3122 CPUX86State *env = &cpu->env;
3123 void *xsave = env->xsave_buf;
3124 int ret;
3125
3126 if (!has_xsave) {
3127 return kvm_get_fpu(cpu);
3128 }
3129
3130 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
3131 if (ret < 0) {
3132 return ret;
3133 }
3134 x86_cpu_xrstor_all_areas(cpu, xsave, env->xsave_buf_len);
3135
3136 return 0;
3137 }
3138
3139 static int kvm_get_xcrs(X86CPU *cpu)
3140 {
3141 CPUX86State *env = &cpu->env;
3142 int i, ret;
3143 struct kvm_xcrs xcrs;
3144
3145 if (!has_xcrs) {
3146 return 0;
3147 }
3148
3149 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
3150 if (ret < 0) {
3151 return ret;
3152 }
3153
3154 for (i = 0; i < xcrs.nr_xcrs; i++) {
3155 /* Only support xcr0 now */
3156 if (xcrs.xcrs[i].xcr == 0) {
3157 env->xcr0 = xcrs.xcrs[i].value;
3158 break;
3159 }
3160 }
3161 return 0;
3162 }
3163
3164 static int kvm_get_sregs(X86CPU *cpu)
3165 {
3166 CPUX86State *env = &cpu->env;
3167 struct kvm_sregs sregs;
3168 int bit, i, ret;
3169
3170 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
3171 if (ret < 0) {
3172 return ret;
3173 }
3174
3175 /* There can only be one pending IRQ set in the bitmap at a time, so try
3176 to find it and save its number instead (-1 for none). */
3177 env->interrupt_injected = -1;
3178 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
3179 if (sregs.interrupt_bitmap[i]) {
3180 bit = ctz64(sregs.interrupt_bitmap[i]);
3181 env->interrupt_injected = i * 64 + bit;
3182 break;
3183 }
3184 }
3185
3186 get_seg(&env->segs[R_CS], &sregs.cs);
3187 get_seg(&env->segs[R_DS], &sregs.ds);
3188 get_seg(&env->segs[R_ES], &sregs.es);
3189 get_seg(&env->segs[R_FS], &sregs.fs);
3190 get_seg(&env->segs[R_GS], &sregs.gs);
3191 get_seg(&env->segs[R_SS], &sregs.ss);
3192
3193 get_seg(&env->tr, &sregs.tr);
3194 get_seg(&env->ldt, &sregs.ldt);
3195
3196 env->idt.limit = sregs.idt.limit;
3197 env->idt.base = sregs.idt.base;
3198 env->gdt.limit = sregs.gdt.limit;
3199 env->gdt.base = sregs.gdt.base;
3200
3201 env->cr[0] = sregs.cr0;
3202 env->cr[2] = sregs.cr2;
3203 env->cr[3] = sregs.cr3;
3204 env->cr[4] = sregs.cr4;
3205
3206 env->efer = sregs.efer;
3207
3208 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
3209 x86_update_hflags(env);
3210
3211 return 0;
3212 }
3213
3214 static int kvm_get_msrs(X86CPU *cpu)
3215 {
3216 CPUX86State *env = &cpu->env;
3217 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
3218 int ret, i;
3219 uint64_t mtrr_top_bits;
3220
3221 kvm_msr_buf_reset(cpu);
3222
3223 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
3224 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
3225 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
3226 kvm_msr_entry_add(cpu, MSR_PAT, 0);
3227 if (has_msr_star) {
3228 kvm_msr_entry_add(cpu, MSR_STAR, 0);
3229 }
3230 if (has_msr_hsave_pa) {
3231 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
3232 }
3233 if (has_msr_tsc_aux) {
3234 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
3235 }
3236 if (has_msr_tsc_adjust) {
3237 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
3238 }
3239 if (has_msr_tsc_deadline) {
3240 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
3241 }
3242 if (has_msr_misc_enable) {
3243 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
3244 }
3245 if (has_msr_smbase) {
3246 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
3247 }
3248 if (has_msr_smi_count) {
3249 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
3250 }
3251 if (has_msr_feature_control) {
3252 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
3253 }
3254 if (has_msr_pkrs) {
3255 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0);
3256 }
3257 if (has_msr_bndcfgs) {
3258 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
3259 }
3260 if (has_msr_xss) {
3261 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
3262 }
3263 if (has_msr_umwait) {
3264 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
3265 }
3266 if (has_msr_spec_ctrl) {
3267 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
3268 }
3269 if (has_msr_tsx_ctrl) {
3270 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
3271 }
3272 if (has_msr_virt_ssbd) {
3273 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
3274 }
3275 if (!env->tsc_valid) {
3276 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
3277 env->tsc_valid = !runstate_is_running();
3278 }
3279
3280 #ifdef TARGET_X86_64
3281 if (lm_capable_kernel) {
3282 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
3283 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
3284 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
3285 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
3286 }
3287 #endif
3288 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
3289 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
3290 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
3291 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0);
3292 }
3293 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
3294 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
3295 }
3296 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
3297 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
3298 }
3299 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
3300 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
3301 }
3302 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
3303 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
3304 }
3305 if (has_architectural_pmu_version > 0) {
3306 if (has_architectural_pmu_version > 1) {
3307 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
3308 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
3309 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
3310 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
3311 }
3312 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
3313 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
3314 }
3315 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
3316 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
3317 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
3318 }
3319 }
3320
3321 if (env->mcg_cap) {
3322 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
3323 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
3324 if (has_msr_mcg_ext_ctl) {
3325 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
3326 }
3327 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
3328 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
3329 }
3330 }
3331
3332 if (has_msr_hv_hypercall) {
3333 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
3334 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
3335 }
3336 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
3337 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
3338 }
3339 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
3340 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
3341 }
3342 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
3343 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
3344 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
3345 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
3346 }
3347 if (has_msr_hv_crash) {
3348 int j;
3349
3350 for (j = 0; j < HV_CRASH_PARAMS; j++) {
3351 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
3352 }
3353 }
3354 if (has_msr_hv_runtime) {
3355 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
3356 }
3357 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
3358 uint32_t msr;
3359
3360 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
3361 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
3362 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
3363 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
3364 kvm_msr_entry_add(cpu, msr, 0);
3365 }
3366 }
3367 if (has_msr_hv_stimer) {
3368 uint32_t msr;
3369
3370 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
3371 msr++) {
3372 kvm_msr_entry_add(cpu, msr, 0);
3373 }
3374 }
3375 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
3376 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
3377 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
3378 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
3379 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
3380 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
3381 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
3382 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
3383 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
3384 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
3385 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
3386 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
3387 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
3388 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
3389 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
3390 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
3391 }
3392 }
3393
3394 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3395 int addr_num =
3396 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
3397
3398 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
3399 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
3400 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
3401 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
3402 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
3403 for (i = 0; i < addr_num; i++) {
3404 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
3405 }
3406 }
3407
3408 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
3409 if (ret < 0) {
3410 return ret;
3411 }
3412
3413 if (ret < cpu->kvm_msr_buf->nmsrs) {
3414 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3415 error_report("error: failed to get MSR 0x%" PRIx32,
3416 (uint32_t)e->index);
3417 }
3418
3419 assert(ret == cpu->kvm_msr_buf->nmsrs);
3420 /*
3421 * MTRR masks: Each mask consists of 5 parts
3422 * a 10..0: must be zero
3423 * b 11 : valid bit
3424 * c n-1.12: actual mask bits
3425 * d 51..n: reserved must be zero
3426 * e 63.52: reserved must be zero
3427 *
3428 * 'n' is the number of physical bits supported by the CPU and is
3429 * apparently always <= 52. We know our 'n' but don't know what
3430 * the destinations 'n' is; it might be smaller, in which case
3431 * it masks (c) on loading. It might be larger, in which case
3432 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3433 * we're migrating to.
3434 */
3435
3436 if (cpu->fill_mtrr_mask) {
3437 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
3438 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
3439 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
3440 } else {
3441 mtrr_top_bits = 0;
3442 }
3443
3444 for (i = 0; i < ret; i++) {
3445 uint32_t index = msrs[i].index;
3446 switch (index) {
3447 case MSR_IA32_SYSENTER_CS:
3448 env->sysenter_cs = msrs[i].data;
3449 break;
3450 case MSR_IA32_SYSENTER_ESP:
3451 env->sysenter_esp = msrs[i].data;
3452 break;
3453 case MSR_IA32_SYSENTER_EIP:
3454 env->sysenter_eip = msrs[i].data;
3455 break;
3456 case MSR_PAT:
3457 env->pat = msrs[i].data;
3458 break;
3459 case MSR_STAR:
3460 env->star = msrs[i].data;
3461 break;
3462 #ifdef TARGET_X86_64
3463 case MSR_CSTAR:
3464 env->cstar = msrs[i].data;
3465 break;
3466 case MSR_KERNELGSBASE:
3467 env->kernelgsbase = msrs[i].data;
3468 break;
3469 case MSR_FMASK:
3470 env->fmask = msrs[i].data;
3471 break;
3472 case MSR_LSTAR:
3473 env->lstar = msrs[i].data;
3474 break;
3475 #endif
3476 case MSR_IA32_TSC:
3477 env->tsc = msrs[i].data;
3478 break;
3479 case MSR_TSC_AUX:
3480 env->tsc_aux = msrs[i].data;
3481 break;
3482 case MSR_TSC_ADJUST:
3483 env->tsc_adjust = msrs[i].data;
3484 break;
3485 case MSR_IA32_TSCDEADLINE:
3486 env->tsc_deadline = msrs[i].data;
3487 break;
3488 case MSR_VM_HSAVE_PA:
3489 env->vm_hsave = msrs[i].data;
3490 break;
3491 case MSR_KVM_SYSTEM_TIME:
3492 env->system_time_msr = msrs[i].data;
3493 break;
3494 case MSR_KVM_WALL_CLOCK:
3495 env->wall_clock_msr = msrs[i].data;
3496 break;
3497 case MSR_MCG_STATUS:
3498 env->mcg_status = msrs[i].data;
3499 break;
3500 case MSR_MCG_CTL:
3501 env->mcg_ctl = msrs[i].data;
3502 break;
3503 case MSR_MCG_EXT_CTL:
3504 env->mcg_ext_ctl = msrs[i].data;
3505 break;
3506 case MSR_IA32_MISC_ENABLE:
3507 env->msr_ia32_misc_enable = msrs[i].data;
3508 break;
3509 case MSR_IA32_SMBASE:
3510 env->smbase = msrs[i].data;
3511 break;
3512 case MSR_SMI_COUNT:
3513 env->msr_smi_count = msrs[i].data;
3514 break;
3515 case MSR_IA32_FEATURE_CONTROL:
3516 env->msr_ia32_feature_control = msrs[i].data;
3517 break;
3518 case MSR_IA32_BNDCFGS:
3519 env->msr_bndcfgs = msrs[i].data;
3520 break;
3521 case MSR_IA32_XSS:
3522 env->xss = msrs[i].data;
3523 break;
3524 case MSR_IA32_UMWAIT_CONTROL:
3525 env->umwait = msrs[i].data;
3526 break;
3527 case MSR_IA32_PKRS:
3528 env->pkrs = msrs[i].data;
3529 break;
3530 default:
3531 if (msrs[i].index >= MSR_MC0_CTL &&
3532 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
3533 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
3534 }
3535 break;
3536 case MSR_KVM_ASYNC_PF_EN:
3537 env->async_pf_en_msr = msrs[i].data;
3538 break;
3539 case MSR_KVM_ASYNC_PF_INT:
3540 env->async_pf_int_msr = msrs[i].data;
3541 break;
3542 case MSR_KVM_PV_EOI_EN:
3543 env->pv_eoi_en_msr = msrs[i].data;
3544 break;
3545 case MSR_KVM_STEAL_TIME:
3546 env->steal_time_msr = msrs[i].data;
3547 break;
3548 case MSR_KVM_POLL_CONTROL: {
3549 env->poll_control_msr = msrs[i].data;
3550 break;
3551 }
3552 case MSR_CORE_PERF_FIXED_CTR_CTRL:
3553 env->msr_fixed_ctr_ctrl = msrs[i].data;
3554 break;
3555 case MSR_CORE_PERF_GLOBAL_CTRL:
3556 env->msr_global_ctrl = msrs[i].data;
3557 break;
3558 case MSR_CORE_PERF_GLOBAL_STATUS:
3559 env->msr_global_status = msrs[i].data;
3560 break;
3561 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3562 env->msr_global_ovf_ctrl = msrs[i].data;
3563 break;
3564 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3565 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3566 break;
3567 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3568 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3569 break;
3570 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3571 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3572 break;
3573 case HV_X64_MSR_HYPERCALL:
3574 env->msr_hv_hypercall = msrs[i].data;
3575 break;
3576 case HV_X64_MSR_GUEST_OS_ID:
3577 env->msr_hv_guest_os_id = msrs[i].data;
3578 break;
3579 case HV_X64_MSR_APIC_ASSIST_PAGE:
3580 env->msr_hv_vapic = msrs[i].data;
3581 break;
3582 case HV_X64_MSR_REFERENCE_TSC:
3583 env->msr_hv_tsc = msrs[i].data;
3584 break;
3585 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3586 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3587 break;
3588 case HV_X64_MSR_VP_RUNTIME:
3589 env->msr_hv_runtime = msrs[i].data;
3590 break;
3591 case HV_X64_MSR_SCONTROL:
3592 env->msr_hv_synic_control = msrs[i].data;
3593 break;
3594 case HV_X64_MSR_SIEFP:
3595 env->msr_hv_synic_evt_page = msrs[i].data;
3596 break;
3597 case HV_X64_MSR_SIMP:
3598 env->msr_hv_synic_msg_page = msrs[i].data;
3599 break;
3600 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3601 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
3602 break;
3603 case HV_X64_MSR_STIMER0_CONFIG:
3604 case HV_X64_MSR_STIMER1_CONFIG:
3605 case HV_X64_MSR_STIMER2_CONFIG:
3606 case HV_X64_MSR_STIMER3_CONFIG:
3607 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3608 msrs[i].data;
3609 break;
3610 case HV_X64_MSR_STIMER0_COUNT:
3611 case HV_X64_MSR_STIMER1_COUNT:
3612 case HV_X64_MSR_STIMER2_COUNT:
3613 case HV_X64_MSR_STIMER3_COUNT:
3614 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3615 msrs[i].data;
3616 break;
3617 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3618 env->msr_hv_reenlightenment_control = msrs[i].data;
3619 break;
3620 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3621 env->msr_hv_tsc_emulation_control = msrs[i].data;
3622 break;
3623 case HV_X64_MSR_TSC_EMULATION_STATUS:
3624 env->msr_hv_tsc_emulation_status = msrs[i].data;
3625 break;
3626 case MSR_MTRRdefType:
3627 env->mtrr_deftype = msrs[i].data;
3628 break;
3629 case MSR_MTRRfix64K_00000:
3630 env->mtrr_fixed[0] = msrs[i].data;
3631 break;
3632 case MSR_MTRRfix16K_80000:
3633 env->mtrr_fixed[1] = msrs[i].data;
3634 break;
3635 case MSR_MTRRfix16K_A0000:
3636 env->mtrr_fixed[2] = msrs[i].data;
3637 break;
3638 case MSR_MTRRfix4K_C0000:
3639 env->mtrr_fixed[3] = msrs[i].data;
3640 break;
3641 case MSR_MTRRfix4K_C8000:
3642 env->mtrr_fixed[4] = msrs[i].data;
3643 break;
3644 case MSR_MTRRfix4K_D0000:
3645 env->mtrr_fixed[5] = msrs[i].data;
3646 break;
3647 case MSR_MTRRfix4K_D8000:
3648 env->mtrr_fixed[6] = msrs[i].data;
3649 break;
3650 case MSR_MTRRfix4K_E0000:
3651 env->mtrr_fixed[7] = msrs[i].data;
3652 break;
3653 case MSR_MTRRfix4K_E8000:
3654 env->mtrr_fixed[8] = msrs[i].data;
3655 break;
3656 case MSR_MTRRfix4K_F0000:
3657 env->mtrr_fixed[9] = msrs[i].data;
3658 break;
3659 case MSR_MTRRfix4K_F8000:
3660 env->mtrr_fixed[10] = msrs[i].data;
3661 break;
3662 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3663 if (index & 1) {
3664 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3665 mtrr_top_bits;
3666 } else {
3667 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3668 }
3669 break;
3670 case MSR_IA32_SPEC_CTRL:
3671 env->spec_ctrl = msrs[i].data;
3672 break;
3673 case MSR_IA32_TSX_CTRL:
3674 env->tsx_ctrl = msrs[i].data;
3675 break;
3676 case MSR_VIRT_SSBD:
3677 env->virt_ssbd = msrs[i].data;
3678 break;
3679 case MSR_IA32_RTIT_CTL:
3680 env->msr_rtit_ctrl = msrs[i].data;
3681 break;
3682 case MSR_IA32_RTIT_STATUS:
3683 env->msr_rtit_status = msrs[i].data;
3684 break;
3685 case MSR_IA32_RTIT_OUTPUT_BASE:
3686 env->msr_rtit_output_base = msrs[i].data;
3687 break;
3688 case MSR_IA32_RTIT_OUTPUT_MASK:
3689 env->msr_rtit_output_mask = msrs[i].data;
3690 break;
3691 case MSR_IA32_RTIT_CR3_MATCH:
3692 env->msr_rtit_cr3_match = msrs[i].data;
3693 break;
3694 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3695 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3696 break;
3697 }
3698 }
3699
3700 return 0;
3701 }
3702
3703 static int kvm_put_mp_state(X86CPU *cpu)
3704 {
3705 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
3706
3707 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
3708 }
3709
3710 static int kvm_get_mp_state(X86CPU *cpu)
3711 {
3712 CPUState *cs = CPU(cpu);
3713 CPUX86State *env = &cpu->env;
3714 struct kvm_mp_state mp_state;
3715 int ret;
3716
3717 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
3718 if (ret < 0) {
3719 return ret;
3720 }
3721 env->mp_state = mp_state.mp_state;
3722 if (kvm_irqchip_in_kernel()) {
3723 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
3724 }
3725 return 0;
3726 }
3727
3728 static int kvm_get_apic(X86CPU *cpu)
3729 {
3730 DeviceState *apic = cpu->apic_state;
3731 struct kvm_lapic_state kapic;
3732 int ret;
3733
3734 if (apic && kvm_irqchip_in_kernel()) {
3735 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
3736 if (ret < 0) {
3737 return ret;
3738 }
3739
3740 kvm_get_apic_state(apic, &kapic);
3741 }
3742 return 0;
3743 }
3744
3745 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
3746 {
3747 CPUState *cs = CPU(cpu);
3748 CPUX86State *env = &cpu->env;
3749 struct kvm_vcpu_events events = {};
3750
3751 if (!kvm_has_vcpu_events()) {
3752 return 0;
3753 }
3754
3755 events.flags = 0;
3756
3757 if (has_exception_payload) {
3758 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3759 events.exception.pending = env->exception_pending;
3760 events.exception_has_payload = env->exception_has_payload;
3761 events.exception_payload = env->exception_payload;
3762 }
3763 events.exception.nr = env->exception_nr;
3764 events.exception.injected = env->exception_injected;
3765 events.exception.has_error_code = env->has_error_code;
3766 events.exception.error_code = env->error_code;
3767
3768 events.interrupt.injected = (env->interrupt_injected >= 0);
3769 events.interrupt.nr = env->interrupt_injected;
3770 events.interrupt.soft = env->soft_interrupt;
3771
3772 events.nmi.injected = env->nmi_injected;
3773 events.nmi.pending = env->nmi_pending;
3774 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3775
3776 events.sipi_vector = env->sipi_vector;
3777
3778 if (has_msr_smbase) {
3779 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3780 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3781 if (kvm_irqchip_in_kernel()) {
3782 /* As soon as these are moved to the kernel, remove them
3783 * from cs->interrupt_request.
3784 */
3785 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3786 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3787 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3788 } else {
3789 /* Keep these in cs->interrupt_request. */
3790 events.smi.pending = 0;
3791 events.smi.latched_init = 0;
3792 }
3793 /* Stop SMI delivery on old machine types to avoid a reboot
3794 * on an inward migration of an old VM.
3795 */
3796 if (!cpu->kvm_no_smi_migration) {
3797 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3798 }
3799 }
3800
3801 if (level >= KVM_PUT_RESET_STATE) {
3802 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3803 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3804 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3805 }
3806 }
3807
3808 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
3809 }
3810
3811 static int kvm_get_vcpu_events(X86CPU *cpu)
3812 {
3813 CPUX86State *env = &cpu->env;
3814 struct kvm_vcpu_events events;
3815 int ret;
3816
3817 if (!kvm_has_vcpu_events()) {
3818 return 0;
3819 }
3820
3821 memset(&events, 0, sizeof(events));
3822 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
3823 if (ret < 0) {
3824 return ret;
3825 }
3826
3827 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3828 env->exception_pending = events.exception.pending;
3829 env->exception_has_payload = events.exception_has_payload;
3830 env->exception_payload = events.exception_payload;
3831 } else {
3832 env->exception_pending = 0;
3833 env->exception_has_payload = false;
3834 }
3835 env->exception_injected = events.exception.injected;
3836 env->exception_nr =
3837 (env->exception_pending || env->exception_injected) ?
3838 events.exception.nr : -1;
3839 env->has_error_code = events.exception.has_error_code;
3840 env->error_code = events.exception.error_code;
3841
3842 env->interrupt_injected =
3843 events.interrupt.injected ? events.interrupt.nr : -1;
3844 env->soft_interrupt = events.interrupt.soft;
3845
3846 env->nmi_injected = events.nmi.injected;
3847 env->nmi_pending = events.nmi.pending;
3848 if (events.nmi.masked) {
3849 env->hflags2 |= HF2_NMI_MASK;
3850 } else {
3851 env->hflags2 &= ~HF2_NMI_MASK;
3852 }
3853
3854 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3855 if (events.smi.smm) {
3856 env->hflags |= HF_SMM_MASK;
3857 } else {
3858 env->hflags &= ~HF_SMM_MASK;
3859 }
3860 if (events.smi.pending) {
3861 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3862 } else {
3863 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3864 }
3865 if (events.smi.smm_inside_nmi) {
3866 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3867 } else {
3868 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3869 }
3870 if (events.smi.latched_init) {
3871 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3872 } else {
3873 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3874 }
3875 }
3876
3877 env->sipi_vector = events.sipi_vector;
3878
3879 return 0;
3880 }
3881
3882 static int kvm_guest_debug_workarounds(X86CPU *cpu)
3883 {
3884 CPUState *cs = CPU(cpu);
3885 CPUX86State *env = &cpu->env;
3886 int ret = 0;
3887 unsigned long reinject_trap = 0;
3888
3889 if (!kvm_has_vcpu_events()) {
3890 if (env->exception_nr == EXCP01_DB) {
3891 reinject_trap = KVM_GUESTDBG_INJECT_DB;
3892 } else if (env->exception_injected == EXCP03_INT3) {
3893 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3894 }
3895 kvm_reset_exception(env);
3896 }
3897
3898 /*
3899 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3900 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3901 * by updating the debug state once again if single-stepping is on.
3902 * Another reason to call kvm_update_guest_debug here is a pending debug
3903 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3904 * reinject them via SET_GUEST_DEBUG.
3905 */
3906 if (reinject_trap ||
3907 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
3908 ret = kvm_update_guest_debug(cs, reinject_trap);
3909 }
3910 return ret;
3911 }
3912
3913 static int kvm_put_debugregs(X86CPU *cpu)
3914 {
3915 CPUX86State *env = &cpu->env;
3916 struct kvm_debugregs dbgregs;
3917 int i;
3918
3919 if (!kvm_has_debugregs()) {
3920 return 0;
3921 }
3922
3923 memset(&dbgregs, 0, sizeof(dbgregs));
3924 for (i = 0; i < 4; i++) {
3925 dbgregs.db[i] = env->dr[i];
3926 }
3927 dbgregs.dr6 = env->dr[6];
3928 dbgregs.dr7 = env->dr[7];
3929 dbgregs.flags = 0;
3930
3931 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
3932 }
3933
3934 static int kvm_get_debugregs(X86CPU *cpu)
3935 {
3936 CPUX86State *env = &cpu->env;
3937 struct kvm_debugregs dbgregs;
3938 int i, ret;
3939
3940 if (!kvm_has_debugregs()) {
3941 return 0;
3942 }
3943
3944 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
3945 if (ret < 0) {
3946 return ret;
3947 }
3948 for (i = 0; i < 4; i++) {
3949 env->dr[i] = dbgregs.db[i];
3950 }
3951 env->dr[4] = env->dr[6] = dbgregs.dr6;
3952 env->dr[5] = env->dr[7] = dbgregs.dr7;
3953
3954 return 0;
3955 }
3956
3957 static int kvm_put_nested_state(X86CPU *cpu)
3958 {
3959 CPUX86State *env = &cpu->env;
3960 int max_nested_state_len = kvm_max_nested_state_length();
3961
3962 if (!env->nested_state) {
3963 return 0;
3964 }
3965
3966 /*
3967 * Copy flags that are affected by reset from env->hflags and env->hflags2.
3968 */
3969 if (env->hflags & HF_GUEST_MASK) {
3970 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE;
3971 } else {
3972 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE;
3973 }
3974
3975 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */
3976 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) {
3977 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET;
3978 } else {
3979 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET;
3980 }
3981
3982 assert(env->nested_state->size <= max_nested_state_len);
3983 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
3984 }
3985
3986 static int kvm_get_nested_state(X86CPU *cpu)
3987 {
3988 CPUX86State *env = &cpu->env;
3989 int max_nested_state_len = kvm_max_nested_state_length();
3990 int ret;
3991
3992 if (!env->nested_state) {
3993 return 0;
3994 }
3995
3996 /*
3997 * It is possible that migration restored a smaller size into
3998 * nested_state->hdr.size than what our kernel support.
3999 * We preserve migration origin nested_state->hdr.size for
4000 * call to KVM_SET_NESTED_STATE but wish that our next call
4001 * to KVM_GET_NESTED_STATE will use max size our kernel support.
4002 */
4003 env->nested_state->size = max_nested_state_len;
4004
4005 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
4006 if (ret < 0) {
4007 return ret;
4008 }
4009
4010 /*
4011 * Copy flags that are affected by reset to env->hflags and env->hflags2.
4012 */
4013 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
4014 env->hflags |= HF_GUEST_MASK;
4015 } else {
4016 env->hflags &= ~HF_GUEST_MASK;
4017 }
4018
4019 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */
4020 if (cpu_has_svm(env)) {
4021 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) {
4022 env->hflags2 |= HF2_GIF_MASK;
4023 } else {
4024 env->hflags2 &= ~HF2_GIF_MASK;
4025 }
4026 }
4027
4028 return ret;
4029 }
4030
4031 int kvm_arch_put_registers(CPUState *cpu, int level)
4032 {
4033 X86CPU *x86_cpu = X86_CPU(cpu);
4034 int ret;
4035
4036 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
4037
4038 /* must be before kvm_put_nested_state so that EFER.SVME is set */
4039 ret = kvm_put_sregs(x86_cpu);
4040 if (ret < 0) {
4041 return ret;
4042 }
4043
4044 if (level >= KVM_PUT_RESET_STATE) {
4045 ret = kvm_put_nested_state(x86_cpu);
4046 if (ret < 0) {
4047 return ret;
4048 }
4049
4050 ret = kvm_put_msr_feature_control(x86_cpu);
4051 if (ret < 0) {
4052 return ret;
4053 }
4054 }
4055
4056 if (level == KVM_PUT_FULL_STATE) {
4057 /* We don't check for kvm_arch_set_tsc_khz() errors here,
4058 * because TSC frequency mismatch shouldn't abort migration,
4059 * unless the user explicitly asked for a more strict TSC
4060 * setting (e.g. using an explicit "tsc-freq" option).
4061 */
4062 kvm_arch_set_tsc_khz(cpu);
4063 }
4064
4065 ret = kvm_getput_regs(x86_cpu, 1);
4066 if (ret < 0) {
4067 return ret;
4068 }
4069 ret = kvm_put_xsave(x86_cpu);
4070 if (ret < 0) {
4071 return ret;
4072 }
4073 ret = kvm_put_xcrs(x86_cpu);
4074 if (ret < 0) {
4075 return ret;
4076 }
4077 /* must be before kvm_put_msrs */
4078 ret = kvm_inject_mce_oldstyle(x86_cpu);
4079 if (ret < 0) {
4080 return ret;
4081 }
4082 ret = kvm_put_msrs(x86_cpu, level);
4083 if (ret < 0) {
4084 return ret;
4085 }
4086 ret = kvm_put_vcpu_events(x86_cpu, level);
4087 if (ret < 0) {
4088 return ret;
4089 }
4090 if (level >= KVM_PUT_RESET_STATE) {
4091 ret = kvm_put_mp_state(x86_cpu);
4092 if (ret < 0) {
4093 return ret;
4094 }
4095 }
4096
4097 ret = kvm_put_tscdeadline_msr(x86_cpu);
4098 if (ret < 0) {
4099 return ret;
4100 }
4101 ret = kvm_put_debugregs(x86_cpu);
4102 if (ret < 0) {
4103 return ret;
4104 }
4105 /* must be last */
4106 ret = kvm_guest_debug_workarounds(x86_cpu);
4107 if (ret < 0) {
4108 return ret;
4109 }
4110 return 0;
4111 }
4112
4113 int kvm_arch_get_registers(CPUState *cs)
4114 {
4115 X86CPU *cpu = X86_CPU(cs);
4116 int ret;
4117
4118 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
4119
4120 ret = kvm_get_vcpu_events(cpu);
4121 if (ret < 0) {
4122 goto out;
4123 }
4124 /*
4125 * KVM_GET_MPSTATE can modify CS and RIP, call it before
4126 * KVM_GET_REGS and KVM_GET_SREGS.
4127 */
4128 ret = kvm_get_mp_state(cpu);
4129 if (ret < 0) {
4130 goto out;
4131 }
4132 ret = kvm_getput_regs(cpu, 0);
4133 if (ret < 0) {
4134 goto out;
4135 }
4136 ret = kvm_get_xsave(cpu);
4137 if (ret < 0) {
4138 goto out;
4139 }
4140 ret = kvm_get_xcrs(cpu);
4141 if (ret < 0) {
4142 goto out;
4143 }
4144 ret = kvm_get_sregs(cpu);
4145 if (ret < 0) {
4146 goto out;
4147 }
4148 ret = kvm_get_msrs(cpu);
4149 if (ret < 0) {
4150 goto out;
4151 }
4152 ret = kvm_get_apic(cpu);
4153 if (ret < 0) {
4154 goto out;
4155 }
4156 ret = kvm_get_debugregs(cpu);
4157 if (ret < 0) {
4158 goto out;
4159 }
4160 ret = kvm_get_nested_state(cpu);
4161 if (ret < 0) {
4162 goto out;
4163 }
4164 ret = 0;
4165 out:
4166 cpu_sync_bndcs_hflags(&cpu->env);
4167 return ret;
4168 }
4169
4170 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
4171 {
4172 X86CPU *x86_cpu = X86_CPU(cpu);
4173 CPUX86State *env = &x86_cpu->env;
4174 int ret;
4175
4176 /* Inject NMI */
4177 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
4178 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
4179 qemu_mutex_lock_iothread();
4180 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
4181 qemu_mutex_unlock_iothread();
4182 DPRINTF("injected NMI\n");
4183 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
4184 if (ret < 0) {
4185 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
4186 strerror(-ret));
4187 }
4188 }
4189 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
4190 qemu_mutex_lock_iothread();
4191 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
4192 qemu_mutex_unlock_iothread();
4193 DPRINTF("injected SMI\n");
4194 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
4195 if (ret < 0) {
4196 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
4197 strerror(-ret));
4198 }
4199 }
4200 }
4201
4202 if (!kvm_pic_in_kernel()) {
4203 qemu_mutex_lock_iothread();
4204 }
4205
4206 /* Force the VCPU out of its inner loop to process any INIT requests
4207 * or (for userspace APIC, but it is cheap to combine the checks here)
4208 * pending TPR access reports.
4209 */
4210 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
4211 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
4212 !(env->hflags & HF_SMM_MASK)) {
4213 cpu->exit_request = 1;
4214 }
4215 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
4216 cpu->exit_request = 1;
4217 }
4218 }
4219
4220 if (!kvm_pic_in_kernel()) {
4221 /* Try to inject an interrupt if the guest can accept it */
4222 if (run->ready_for_interrupt_injection &&
4223 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
4224 (env->eflags & IF_MASK)) {
4225 int irq;
4226
4227 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
4228 irq = cpu_get_pic_interrupt(env);
4229 if (irq >= 0) {
4230 struct kvm_interrupt intr;
4231
4232 intr.irq = irq;
4233 DPRINTF("injected interrupt %d\n", irq);
4234 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
4235 if (ret < 0) {
4236 fprintf(stderr,
4237 "KVM: injection failed, interrupt lost (%s)\n",
4238 strerror(-ret));
4239 }
4240 }
4241 }
4242
4243 /* If we have an interrupt but the guest is not ready to receive an
4244 * interrupt, request an interrupt window exit. This will
4245 * cause a return to userspace as soon as the guest is ready to
4246 * receive interrupts. */
4247 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
4248 run->request_interrupt_window = 1;
4249 } else {
4250 run->request_interrupt_window = 0;
4251 }
4252
4253 DPRINTF("setting tpr\n");
4254 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4255
4256 qemu_mutex_unlock_iothread();
4257 }
4258 }
4259
4260 static void kvm_rate_limit_on_bus_lock(void)
4261 {
4262 uint64_t delay_ns = ratelimit_calculate_delay(&bus_lock_ratelimit_ctrl, 1);
4263
4264 if (delay_ns) {
4265 g_usleep(delay_ns / SCALE_US);
4266 }
4267 }
4268
4269 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
4270 {
4271 X86CPU *x86_cpu = X86_CPU(cpu);
4272 CPUX86State *env = &x86_cpu->env;
4273
4274 if (run->flags & KVM_RUN_X86_SMM) {
4275 env->hflags |= HF_SMM_MASK;
4276 } else {
4277 env->hflags &= ~HF_SMM_MASK;
4278 }
4279 if (run->if_flag) {
4280 env->eflags |= IF_MASK;
4281 } else {
4282 env->eflags &= ~IF_MASK;
4283 }
4284 if (run->flags & KVM_RUN_X86_BUS_LOCK) {
4285 kvm_rate_limit_on_bus_lock();
4286 }
4287
4288 /* We need to protect the apic state against concurrent accesses from
4289 * different threads in case the userspace irqchip is used. */
4290 if (!kvm_irqchip_in_kernel()) {
4291 qemu_mutex_lock_iothread();
4292 }
4293 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
4294 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4295 if (!kvm_irqchip_in_kernel()) {
4296 qemu_mutex_unlock_iothread();
4297 }
4298 return cpu_get_mem_attrs(env);
4299 }
4300
4301 int kvm_arch_process_async_events(CPUState *cs)
4302 {
4303 X86CPU *cpu = X86_CPU(cs);
4304 CPUX86State *env = &cpu->env;
4305
4306 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
4307 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
4308 assert(env->mcg_cap);
4309
4310 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
4311
4312 kvm_cpu_synchronize_state(cs);
4313
4314 if (env->exception_nr == EXCP08_DBLE) {
4315 /* this means triple fault */
4316 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
4317 cs->exit_request = 1;
4318 return 0;
4319 }
4320 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
4321 env->has_error_code = 0;
4322
4323 cs->halted = 0;
4324 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
4325 env->mp_state = KVM_MP_STATE_RUNNABLE;
4326 }
4327 }
4328
4329 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
4330 !(env->hflags & HF_SMM_MASK)) {
4331 kvm_cpu_synchronize_state(cs);
4332 do_cpu_init(cpu);
4333 }
4334
4335 if (kvm_irqchip_in_kernel()) {
4336 return 0;
4337 }
4338
4339 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
4340 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
4341 apic_poll_irq(cpu->apic_state);
4342 }
4343 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4344 (env->eflags & IF_MASK)) ||
4345 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4346 cs->halted = 0;
4347 }
4348 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
4349 kvm_cpu_synchronize_state(cs);
4350 do_cpu_sipi(cpu);
4351 }
4352 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
4353 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
4354 kvm_cpu_synchronize_state(cs);
4355 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
4356 env->tpr_access_type);
4357 }
4358
4359 return cs->halted;
4360 }
4361
4362 static int kvm_handle_halt(X86CPU *cpu)
4363 {
4364 CPUState *cs = CPU(cpu);
4365 CPUX86State *env = &cpu->env;
4366
4367 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4368 (env->eflags & IF_MASK)) &&
4369 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4370 cs->halted = 1;
4371 return EXCP_HLT;
4372 }
4373
4374 return 0;
4375 }
4376
4377 static int kvm_handle_tpr_access(X86CPU *cpu)
4378 {
4379 CPUState *cs = CPU(cpu);
4380 struct kvm_run *run = cs->kvm_run;
4381
4382 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
4383 run->tpr_access.is_write ? TPR_ACCESS_WRITE
4384 : TPR_ACCESS_READ);
4385 return 1;
4386 }
4387
4388 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
4389 {
4390 static const uint8_t int3 = 0xcc;
4391
4392 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
4393 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
4394 return -EINVAL;
4395 }
4396 return 0;
4397 }
4398
4399 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
4400 {
4401 uint8_t int3;
4402
4403 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) {
4404 return -EINVAL;
4405 }
4406 if (int3 != 0xcc) {
4407 return 0;
4408 }
4409 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
4410 return -EINVAL;
4411 }
4412 return 0;
4413 }
4414
4415 static struct {
4416 target_ulong addr;
4417 int len;
4418 int type;
4419 } hw_breakpoint[4];
4420
4421 static int nb_hw_breakpoint;
4422
4423 static int find_hw_breakpoint(target_ulong addr, int len, int type)
4424 {
4425 int n;
4426
4427 for (n = 0; n < nb_hw_breakpoint; n++) {
4428 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
4429 (hw_breakpoint[n].len == len || len == -1)) {
4430 return n;
4431 }
4432 }
4433 return -1;
4434 }
4435
4436 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
4437 target_ulong len, int type)
4438 {
4439 switch (type) {
4440 case GDB_BREAKPOINT_HW:
4441 len = 1;
4442 break;
4443 case GDB_WATCHPOINT_WRITE:
4444 case GDB_WATCHPOINT_ACCESS:
4445 switch (len) {
4446 case 1:
4447 break;
4448 case 2:
4449 case 4:
4450 case 8:
4451 if (addr & (len - 1)) {
4452 return -EINVAL;
4453 }
4454 break;
4455 default:
4456 return -EINVAL;
4457 }
4458 break;
4459 default:
4460 return -ENOSYS;
4461 }
4462
4463 if (nb_hw_breakpoint == 4) {
4464 return -ENOBUFS;
4465 }
4466 if (find_hw_breakpoint(addr, len, type) >= 0) {
4467 return -EEXIST;
4468 }
4469 hw_breakpoint[nb_hw_breakpoint].addr = addr;
4470 hw_breakpoint[nb_hw_breakpoint].len = len;
4471 hw_breakpoint[nb_hw_breakpoint].type = type;
4472 nb_hw_breakpoint++;
4473
4474 return 0;
4475 }
4476
4477 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
4478 target_ulong len, int type)
4479 {
4480 int n;
4481
4482 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
4483 if (n < 0) {
4484 return -ENOENT;
4485 }
4486 nb_hw_breakpoint--;
4487 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
4488
4489 return 0;
4490 }
4491
4492 void kvm_arch_remove_all_hw_breakpoints(void)
4493 {
4494 nb_hw_breakpoint = 0;
4495 }
4496
4497 static CPUWatchpoint hw_watchpoint;
4498
4499 static int kvm_handle_debug(X86CPU *cpu,
4500 struct kvm_debug_exit_arch *arch_info)
4501 {
4502 CPUState *cs = CPU(cpu);
4503 CPUX86State *env = &cpu->env;
4504 int ret = 0;
4505 int n;
4506
4507 if (arch_info->exception == EXCP01_DB) {
4508 if (arch_info->dr6 & DR6_BS) {
4509 if (cs->singlestep_enabled) {
4510 ret = EXCP_DEBUG;
4511 }
4512 } else {
4513 for (n = 0; n < 4; n++) {
4514 if (arch_info->dr6 & (1 << n)) {
4515 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
4516 case 0x0:
4517 ret = EXCP_DEBUG;
4518 break;
4519 case 0x1:
4520 ret = EXCP_DEBUG;
4521 cs->watchpoint_hit = &hw_watchpoint;
4522 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4523 hw_watchpoint.flags = BP_MEM_WRITE;
4524 break;
4525 case 0x3:
4526 ret = EXCP_DEBUG;
4527 cs->watchpoint_hit = &hw_watchpoint;
4528 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4529 hw_watchpoint.flags = BP_MEM_ACCESS;
4530 break;
4531 }
4532 }
4533 }
4534 }
4535 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
4536 ret = EXCP_DEBUG;
4537 }
4538 if (ret == 0) {
4539 cpu_synchronize_state(cs);
4540 assert(env->exception_nr == -1);
4541
4542 /* pass to guest */
4543 kvm_queue_exception(env, arch_info->exception,
4544 arch_info->exception == EXCP01_DB,
4545 arch_info->dr6);
4546 env->has_error_code = 0;
4547 }
4548
4549 return ret;
4550 }
4551
4552 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
4553 {
4554 const uint8_t type_code[] = {
4555 [GDB_BREAKPOINT_HW] = 0x0,
4556 [GDB_WATCHPOINT_WRITE] = 0x1,
4557 [GDB_WATCHPOINT_ACCESS] = 0x3
4558 };
4559 const uint8_t len_code[] = {
4560 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
4561 };
4562 int n;
4563
4564 if (kvm_sw_breakpoints_active(cpu)) {
4565 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
4566 }
4567 if (nb_hw_breakpoint > 0) {
4568 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
4569 dbg->arch.debugreg[7] = 0x0600;
4570 for (n = 0; n < nb_hw_breakpoint; n++) {
4571 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
4572 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
4573 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
4574 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
4575 }
4576 }
4577 }
4578
4579 static bool host_supports_vmx(void)
4580 {
4581 uint32_t ecx, unused;
4582
4583 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
4584 return ecx & CPUID_EXT_VMX;
4585 }
4586
4587 #define VMX_INVALID_GUEST_STATE 0x80000021
4588
4589 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
4590 {
4591 X86CPU *cpu = X86_CPU(cs);
4592 uint64_t code;
4593 int ret;
4594
4595 switch (run->exit_reason) {
4596 case KVM_EXIT_HLT:
4597 DPRINTF("handle_hlt\n");
4598 qemu_mutex_lock_iothread();
4599 ret = kvm_handle_halt(cpu);
4600 qemu_mutex_unlock_iothread();
4601 break;
4602 case KVM_EXIT_SET_TPR:
4603 ret = 0;
4604 break;
4605 case KVM_EXIT_TPR_ACCESS:
4606 qemu_mutex_lock_iothread();
4607 ret = kvm_handle_tpr_access(cpu);
4608 qemu_mutex_unlock_iothread();
4609 break;
4610 case KVM_EXIT_FAIL_ENTRY:
4611 code = run->fail_entry.hardware_entry_failure_reason;
4612 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
4613 code);
4614 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
4615 fprintf(stderr,
4616 "\nIf you're running a guest on an Intel machine without "
4617 "unrestricted mode\n"
4618 "support, the failure can be most likely due to the guest "
4619 "entering an invalid\n"
4620 "state for Intel VT. For example, the guest maybe running "
4621 "in big real mode\n"
4622 "which is not supported on less recent Intel processors."
4623 "\n\n");
4624 }
4625 ret = -1;
4626 break;
4627 case KVM_EXIT_EXCEPTION:
4628 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
4629 run->ex.exception, run->ex.error_code);
4630 ret = -1;
4631 break;
4632 case KVM_EXIT_DEBUG:
4633 DPRINTF("kvm_exit_debug\n");
4634 qemu_mutex_lock_iothread();
4635 ret = kvm_handle_debug(cpu, &run->debug.arch);
4636 qemu_mutex_unlock_iothread();
4637 break;
4638 case KVM_EXIT_HYPERV:
4639 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
4640 break;
4641 case KVM_EXIT_IOAPIC_EOI:
4642 ioapic_eoi_broadcast(run->eoi.vector);
4643 ret = 0;
4644 break;
4645 case KVM_EXIT_X86_BUS_LOCK:
4646 /* already handled in kvm_arch_post_run */
4647 ret = 0;
4648 break;
4649 default:
4650 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
4651 ret = -1;
4652 break;
4653 }
4654
4655 return ret;
4656 }
4657
4658 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4659 {
4660 X86CPU *cpu = X86_CPU(cs);
4661 CPUX86State *env = &cpu->env;
4662
4663 kvm_cpu_synchronize_state(cs);
4664 return !(env->cr[0] & CR0_PE_MASK) ||
4665 ((env->segs[R_CS].selector & 3) != 3);
4666 }
4667
4668 void kvm_arch_init_irq_routing(KVMState *s)
4669 {
4670 /* We know at this point that we're using the in-kernel
4671 * irqchip, so we can use irqfds, and on x86 we know
4672 * we can use msi via irqfd and GSI routing.
4673 */
4674 kvm_msi_via_irqfd_allowed = true;
4675 kvm_gsi_routing_allowed = true;
4676
4677 if (kvm_irqchip_is_split()) {
4678 int i;
4679
4680 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4681 MSI routes for signaling interrupts to the local apics. */
4682 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
4683 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
4684 error_report("Could not enable split IRQ mode.");
4685 exit(1);
4686 }
4687 }
4688 }
4689 }
4690
4691 int kvm_arch_irqchip_create(KVMState *s)
4692 {
4693 int ret;
4694 if (kvm_kernel_irqchip_split()) {
4695 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4696 if (ret) {
4697 error_report("Could not enable split irqchip mode: %s",
4698 strerror(-ret));
4699 exit(1);
4700 } else {
4701 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4702 kvm_split_irqchip = true;
4703 return 1;
4704 }
4705 } else {
4706 return 0;
4707 }
4708 }
4709
4710 uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address)
4711 {
4712 CPUX86State *env;
4713 uint64_t ext_id;
4714
4715 if (!first_cpu) {
4716 return address;
4717 }
4718 env = &X86_CPU(first_cpu)->env;
4719 if (!(env->features[FEAT_KVM] & (1 << KVM_FEATURE_MSI_EXT_DEST_ID))) {
4720 return address;
4721 }
4722
4723 /*
4724 * If the remappable format bit is set, or the upper bits are
4725 * already set in address_hi, or the low extended bits aren't
4726 * there anyway, do nothing.
4727 */
4728 ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT);
4729 if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) {
4730 return address;
4731 }
4732
4733 address &= ~ext_id;
4734 address |= ext_id << 35;
4735 return address;
4736 }
4737
4738 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
4739 uint64_t address, uint32_t data, PCIDevice *dev)
4740 {
4741 X86IOMMUState *iommu = x86_iommu_get_default();
4742
4743 if (iommu) {
4744 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu);
4745
4746 if (class->int_remap) {
4747 int ret;
4748 MSIMessage src, dst;
4749
4750 src.address = route->u.msi.address_hi;
4751 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4752 src.address |= route->u.msi.address_lo;
4753 src.data = route->u.msi.data;
4754
4755 ret = class->int_remap(iommu, &src, &dst, dev ? \
4756 pci_requester_id(dev) : \
4757 X86_IOMMU_SID_INVALID);
4758 if (ret) {
4759 trace_kvm_x86_fixup_msi_error(route->gsi);
4760 return 1;
4761 }
4762
4763 /*
4764 * Handled untranslated compatibilty format interrupt with
4765 * extended destination ID in the low bits 11-5. */
4766 dst.address = kvm_swizzle_msi_ext_dest_id(dst.address);
4767
4768 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4769 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4770 route->u.msi.data = dst.data;
4771 return 0;
4772 }
4773 }
4774
4775 address = kvm_swizzle_msi_ext_dest_id(address);
4776 route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT;
4777 route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK;
4778 return 0;
4779 }
4780
4781 typedef struct MSIRouteEntry MSIRouteEntry;
4782
4783 struct MSIRouteEntry {
4784 PCIDevice *dev; /* Device pointer */
4785 int vector; /* MSI/MSIX vector index */
4786 int virq; /* Virtual IRQ index */
4787 QLIST_ENTRY(MSIRouteEntry) list;
4788 };
4789
4790 /* List of used GSI routes */
4791 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4792 QLIST_HEAD_INITIALIZER(msi_route_list);
4793
4794 static void kvm_update_msi_routes_all(void *private, bool global,
4795 uint32_t index, uint32_t mask)
4796 {
4797 int cnt = 0, vector;
4798 MSIRouteEntry *entry;
4799 MSIMessage msg;
4800 PCIDevice *dev;
4801
4802 /* TODO: explicit route update */
4803 QLIST_FOREACH(entry, &msi_route_list, list) {
4804 cnt++;
4805 vector = entry->vector;
4806 dev = entry->dev;
4807 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4808 msg = msix_get_message(dev, vector);
4809 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4810 msg = msi_get_message(dev, vector);
4811 } else {
4812 /*
4813 * Either MSI/MSIX is disabled for the device, or the
4814 * specific message was masked out. Skip this one.
4815 */
4816 continue;
4817 }
4818 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
4819 }
4820 kvm_irqchip_commit_routes(kvm_state);
4821 trace_kvm_x86_update_msi_routes(cnt);
4822 }
4823
4824 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4825 int vector, PCIDevice *dev)
4826 {
4827 static bool notify_list_inited = false;
4828 MSIRouteEntry *entry;
4829
4830 if (!dev) {
4831 /* These are (possibly) IOAPIC routes only used for split
4832 * kernel irqchip mode, while what we are housekeeping are
4833 * PCI devices only. */
4834 return 0;
4835 }
4836
4837 entry = g_new0(MSIRouteEntry, 1);
4838 entry->dev = dev;
4839 entry->vector = vector;
4840 entry->virq = route->gsi;
4841 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4842
4843 trace_kvm_x86_add_msi_route(route->gsi);
4844
4845 if (!notify_list_inited) {
4846 /* For the first time we do add route, add ourselves into
4847 * IOMMU's IEC notify list if needed. */
4848 X86IOMMUState *iommu = x86_iommu_get_default();
4849 if (iommu) {
4850 x86_iommu_iec_register_notifier(iommu,
4851 kvm_update_msi_routes_all,
4852 NULL);
4853 }
4854 notify_list_inited = true;
4855 }
4856 return 0;
4857 }
4858
4859 int kvm_arch_release_virq_post(int virq)
4860 {
4861 MSIRouteEntry *entry, *next;
4862 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4863 if (entry->virq == virq) {
4864 trace_kvm_x86_remove_msi_route(virq);
4865 QLIST_REMOVE(entry, list);
4866 g_free(entry);
4867 break;
4868 }
4869 }
4870 return 0;
4871 }
4872
4873 int kvm_arch_msi_data_to_gsi(uint32_t data)
4874 {
4875 abort();
4876 }
4877
4878 bool kvm_has_waitpkg(void)
4879 {
4880 return has_msr_umwait;
4881 }
4882
4883 bool kvm_arch_cpu_check_are_resettable(void)
4884 {
4885 return !sev_es_enabled();
4886 }
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