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spapr/drc: Clean up local variable shadowing in rtas_ibm_configure_connector()
[qemu/kevin.git] / hw / i386 / pc.c
blob5d399b6247eaac922ee1e9f00c9c12d8d96cdaf3
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/topology.h"
32 #include "hw/i386/fw_cfg.h"
33 #include "hw/i386/vmport.h"
34 #include "sysemu/cpus.h"
35 #include "hw/block/fdc.h"
36 #include "hw/ide/internal.h"
37 #include "hw/ide/isa.h"
38 #include "hw/pci/pci.h"
39 #include "hw/pci/pci_bus.h"
40 #include "hw/pci-bridge/pci_expander_bridge.h"
41 #include "hw/nvram/fw_cfg.h"
42 #include "hw/timer/hpet.h"
43 #include "hw/firmware/smbios.h"
44 #include "hw/loader.h"
45 #include "elf.h"
46 #include "migration/vmstate.h"
47 #include "multiboot.h"
48 #include "hw/rtc/mc146818rtc.h"
49 #include "hw/intc/i8259.h"
50 #include "hw/intc/ioapic.h"
51 #include "hw/timer/i8254.h"
52 #include "hw/input/i8042.h"
53 #include "hw/irq.h"
54 #include "hw/audio/pcspk.h"
55 #include "hw/pci/msi.h"
56 #include "hw/sysbus.h"
57 #include "sysemu/sysemu.h"
58 #include "sysemu/tcg.h"
59 #include "sysemu/numa.h"
60 #include "sysemu/kvm.h"
61 #include "sysemu/xen.h"
62 #include "sysemu/reset.h"
63 #include "sysemu/runstate.h"
64 #include "kvm/kvm_i386.h"
65 #include "hw/xen/xen.h"
66 #include "hw/xen/start_info.h"
67 #include "ui/qemu-spice.h"
68 #include "exec/memory.h"
69 #include "qemu/bitmap.h"
70 #include "qemu/config-file.h"
71 #include "qemu/error-report.h"
72 #include "qemu/option.h"
73 #include "qemu/cutils.h"
74 #include "hw/acpi/acpi.h"
75 #include "hw/acpi/cpu_hotplug.h"
76 #include "acpi-build.h"
77 #include "hw/mem/pc-dimm.h"
78 #include "hw/mem/nvdimm.h"
79 #include "hw/cxl/cxl.h"
80 #include "hw/cxl/cxl_host.h"
81 #include "qapi/error.h"
82 #include "qapi/qapi-visit-common.h"
83 #include "qapi/qapi-visit-machine.h"
84 #include "qapi/visitor.h"
85 #include "hw/core/cpu.h"
86 #include "hw/usb.h"
87 #include "hw/i386/intel_iommu.h"
88 #include "hw/net/ne2000-isa.h"
89 #include "standard-headers/asm-x86/bootparam.h"
90 #include "hw/virtio/virtio-iommu.h"
91 #include "hw/virtio/virtio-md-pci.h"
92 #include "hw/i386/kvm/xen_overlay.h"
93 #include "hw/i386/kvm/xen_evtchn.h"
94 #include "hw/i386/kvm/xen_gnttab.h"
95 #include "hw/i386/kvm/xen_xenstore.h"
96 #include "sysemu/replay.h"
97 #include "target/i386/cpu.h"
98 #include "e820_memory_layout.h"
99 #include "fw_cfg.h"
100 #include "trace.h"
101 #include CONFIG_DEVICES
102
103 #ifdef CONFIG_XEN_EMU
104 #include "hw/xen/xen-legacy-backend.h"
105 #include "hw/xen/xen-bus.h"
106 #endif
107
108 /*
109 * Helper for setting model-id for CPU models that changed model-id
110 * depending on QEMU versions up to QEMU 2.4.
111 */
112 #define PC_CPU_MODEL_IDS(v) \
113 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
114 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
115 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
116
117 GlobalProperty pc_compat_8_1[] = {};
118 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1);
119
120 GlobalProperty pc_compat_8_0[] = {
121 { "virtio-mem", "unplugged-inaccessible", "auto" },
122 };
123 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0);
124
125 GlobalProperty pc_compat_7_2[] = {
126 { "ICH9-LPC", "noreboot", "true" },
127 };
128 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2);
129
130 GlobalProperty pc_compat_7_1[] = {};
131 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1);
132
133 GlobalProperty pc_compat_7_0[] = {};
134 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
135
136 GlobalProperty pc_compat_6_2[] = {
137 { "virtio-mem", "unplugged-inaccessible", "off" },
138 };
139 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
140
141 GlobalProperty pc_compat_6_1[] = {
142 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
143 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
144 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
145 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
146 };
147 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
148
149 GlobalProperty pc_compat_6_0[] = {
150 { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
151 { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
152 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
153 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
154 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
155 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
156 };
157 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
158
159 GlobalProperty pc_compat_5_2[] = {
160 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
161 };
162 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
163
164 GlobalProperty pc_compat_5_1[] = {
165 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
166 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
167 };
168 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
169
170 GlobalProperty pc_compat_5_0[] = {
171 };
172 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
173
174 GlobalProperty pc_compat_4_2[] = {
175 { "mch", "smbase-smram", "off" },
176 };
177 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
178
179 GlobalProperty pc_compat_4_1[] = {};
180 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
181
182 GlobalProperty pc_compat_4_0[] = {};
183 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
184
185 GlobalProperty pc_compat_3_1[] = {
186 { "intel-iommu", "dma-drain", "off" },
187 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
188 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
189 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
190 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
191 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
192 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
193 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
194 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
195 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
196 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
197 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
198 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
199 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
200 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
201 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
202 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
203 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
204 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
205 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
206 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
207 };
208 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
209
210 GlobalProperty pc_compat_3_0[] = {
211 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
212 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
213 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
214 };
215 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
216
217 GlobalProperty pc_compat_2_12[] = {
218 { TYPE_X86_CPU, "legacy-cache", "on" },
219 { TYPE_X86_CPU, "topoext", "off" },
220 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
221 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
222 };
223 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
224
225 GlobalProperty pc_compat_2_11[] = {
226 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
227 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
228 };
229 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
230
231 GlobalProperty pc_compat_2_10[] = {
232 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
233 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
234 { "q35-pcihost", "x-pci-hole64-fix", "off" },
235 };
236 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
237
238 GlobalProperty pc_compat_2_9[] = {
239 { "mch", "extended-tseg-mbytes", "0" },
240 };
241 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
242
243 GlobalProperty pc_compat_2_8[] = {
244 { TYPE_X86_CPU, "tcg-cpuid", "off" },
245 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
246 { "ICH9-LPC", "x-smi-broadcast", "off" },
247 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
248 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
249 };
250 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
251
252 GlobalProperty pc_compat_2_7[] = {
253 { TYPE_X86_CPU, "l3-cache", "off" },
254 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
255 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
256 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
257 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
258 { "isa-pcspk", "migrate", "off" },
259 };
260 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
261
262 GlobalProperty pc_compat_2_6[] = {
263 { TYPE_X86_CPU, "cpuid-0xb", "off" },
264 { "vmxnet3", "romfile", "" },
265 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
266 { "apic-common", "legacy-instance-id", "on", }
267 };
268 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
269
270 GlobalProperty pc_compat_2_5[] = {};
271 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
272
273 GlobalProperty pc_compat_2_4[] = {
274 PC_CPU_MODEL_IDS("2.4.0")
275 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
276 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
277 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
278 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
279 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
280 { TYPE_X86_CPU, "check", "off" },
281 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
282 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
283 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
284 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
285 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
286 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
287 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
288 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
289 };
290 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
291
292 GlobalProperty pc_compat_2_3[] = {
293 PC_CPU_MODEL_IDS("2.3.0")
294 { TYPE_X86_CPU, "arat", "off" },
295 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
296 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
297 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
298 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
299 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
300 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
301 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
302 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
303 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
304 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
305 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
306 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
307 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
308 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
309 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
310 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
311 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
312 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
313 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
314 };
315 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
316
317 GlobalProperty pc_compat_2_2[] = {
318 PC_CPU_MODEL_IDS("2.2.0")
319 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
320 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
321 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
322 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
323 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
324 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
325 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
326 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
327 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
328 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
329 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
330 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
331 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
332 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
333 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
334 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
335 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
336 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
337 };
338 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
339
340 GlobalProperty pc_compat_2_1[] = {
341 PC_CPU_MODEL_IDS("2.1.0")
342 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
343 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
344 };
345 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
346
347 GlobalProperty pc_compat_2_0[] = {
348 PC_CPU_MODEL_IDS("2.0.0")
349 { "virtio-scsi-pci", "any_layout", "off" },
350 { "PIIX4_PM", "memory-hotplug-support", "off" },
351 { "apic", "version", "0x11" },
352 { "nec-usb-xhci", "superspeed-ports-first", "off" },
353 { "nec-usb-xhci", "force-pcie-endcap", "on" },
354 { "pci-serial", "prog_if", "0" },
355 { "pci-serial-2x", "prog_if", "0" },
356 { "pci-serial-4x", "prog_if", "0" },
357 { "virtio-net-pci", "guest_announce", "off" },
358 { "ICH9-LPC", "memory-hotplug-support", "off" },
359 };
360 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
361
362 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
363 {
364 GSIState *s;
365
366 s = g_new0(GSIState, 1);
367 if (kvm_ioapic_in_kernel()) {
368 kvm_pc_setup_irq_routing(pci_enabled);
369 }
370 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS);
371
372 return s;
373 }
374
375 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
376 unsigned size)
377 {
378 }
379
380 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
381 {
382 return 0xffffffffffffffffULL;
383 }
384
385 /* MS-DOS compatibility mode FPU exception support */
386 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
387 unsigned size)
388 {
389 if (tcg_enabled()) {
390 cpu_set_ignne();
391 }
392 }
393
394 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
395 {
396 return 0xffffffffffffffffULL;
397 }
398
399 /* PC cmos mappings */
400
401 #define REG_EQUIPMENT_BYTE 0x14
402
403 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs,
404 int16_t cylinders, int8_t heads, int8_t sectors)
405 {
406 mc146818rtc_set_cmos_data(s, type_ofs, 47);
407 mc146818rtc_set_cmos_data(s, info_ofs, cylinders);
408 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8);
409 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads);
410 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff);
411 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff);
412 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
413 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders);
414 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8);
415 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors);
416 }
417
418 /* convert boot_device letter to something recognizable by the bios */
419 static int boot_device2nibble(char boot_device)
420 {
421 switch(boot_device) {
422 case 'a':
423 case 'b':
424 return 0x01; /* floppy boot */
425 case 'c':
426 return 0x02; /* hard drive boot */
427 case 'd':
428 return 0x03; /* CD-ROM boot */
429 case 'n':
430 return 0x04; /* Network boot */
431 }
432 return 0;
433 }
434
435 static void set_boot_dev(MC146818RtcState *s, const char *boot_device,
436 Error **errp)
437 {
438 #define PC_MAX_BOOT_DEVICES 3
439 int nbds, bds[3] = { 0, };
440 int i;
441
442 nbds = strlen(boot_device);
443 if (nbds > PC_MAX_BOOT_DEVICES) {
444 error_setg(errp, "Too many boot devices for PC");
445 return;
446 }
447 for (i = 0; i < nbds; i++) {
448 bds[i] = boot_device2nibble(boot_device[i]);
449 if (bds[i] == 0) {
450 error_setg(errp, "Invalid boot device for PC: '%c'",
451 boot_device[i]);
452 return;
453 }
454 }
455 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]);
456 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
457 }
458
459 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
460 {
461 set_boot_dev(opaque, boot_device, errp);
462 }
463
464 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy)
465 {
466 int val, nb, i;
467 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
468 FLOPPY_DRIVE_TYPE_NONE };
469
470 /* floppy type */
471 if (floppy) {
472 for (i = 0; i < 2; i++) {
473 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
474 }
475 }
476 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
477 cmos_get_fd_drive_type(fd_type[1]);
478 mc146818rtc_set_cmos_data(rtc_state, 0x10, val);
479
480 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE);
481 nb = 0;
482 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
483 nb++;
484 }
485 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
486 nb++;
487 }
488 switch (nb) {
489 case 0:
490 break;
491 case 1:
492 val |= 0x01; /* 1 drive, ready for boot */
493 break;
494 case 2:
495 val |= 0x41; /* 2 drives, ready for boot */
496 break;
497 }
498 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val);
499 }
500
501 typedef struct pc_cmos_init_late_arg {
502 MC146818RtcState *rtc_state;
503 BusState *idebus[2];
504 } pc_cmos_init_late_arg;
505
506 typedef struct check_fdc_state {
507 ISADevice *floppy;
508 bool multiple;
509 } CheckFdcState;
510
511 static int check_fdc(Object *obj, void *opaque)
512 {
513 CheckFdcState *state = opaque;
514 Object *fdc;
515 uint32_t iobase;
516 Error *local_err = NULL;
517
518 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
519 if (!fdc) {
520 return 0;
521 }
522
523 iobase = object_property_get_uint(obj, "iobase", &local_err);
524 if (local_err || iobase != 0x3f0) {
525 error_free(local_err);
526 return 0;
527 }
528
529 if (state->floppy) {
530 state->multiple = true;
531 } else {
532 state->floppy = ISA_DEVICE(obj);
533 }
534 return 0;
535 }
536
537 static const char * const fdc_container_path[] = {
538 "/unattached", "/peripheral", "/peripheral-anon"
539 };
540
541 /*
542 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
543 * and ACPI objects.
544 */
545 static ISADevice *pc_find_fdc0(void)
546 {
547 int i;
548 Object *container;
549 CheckFdcState state = { 0 };
550
551 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
552 container = container_get(qdev_get_machine(), fdc_container_path[i]);
553 object_child_foreach(container, check_fdc, &state);
554 }
555
556 if (state.multiple) {
557 warn_report("multiple floppy disk controllers with "
558 "iobase=0x3f0 have been found");
559 error_printf("the one being picked for CMOS setup might not reflect "
560 "your intent");
561 }
562
563 return state.floppy;
564 }
565
566 static void pc_cmos_init_late(void *opaque)
567 {
568 pc_cmos_init_late_arg *arg = opaque;
569 MC146818RtcState *s = arg->rtc_state;
570 int16_t cylinders;
571 int8_t heads, sectors;
572 int val;
573 int i, trans;
574
575 val = 0;
576 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
577 &cylinders, &heads, &sectors) >= 0) {
578 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
579 val |= 0xf0;
580 }
581 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
582 &cylinders, &heads, &sectors) >= 0) {
583 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
584 val |= 0x0f;
585 }
586 mc146818rtc_set_cmos_data(s, 0x12, val);
587
588 val = 0;
589 for (i = 0; i < 4; i++) {
590 /* NOTE: ide_get_geometry() returns the physical
591 geometry. It is always such that: 1 <= sects <= 63, 1
592 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
593 geometry can be different if a translation is done. */
594 if (arg->idebus[i / 2] &&
595 ide_get_geometry(arg->idebus[i / 2], i % 2,
596 &cylinders, &heads, &sectors) >= 0) {
597 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
598 assert((trans & ~3) == 0);
599 val |= trans << (i * 2);
600 }
601 }
602 mc146818rtc_set_cmos_data(s, 0x39, val);
603
604 pc_cmos_init_floppy(s, pc_find_fdc0());
605
606 qemu_unregister_reset(pc_cmos_init_late, opaque);
607 }
608
609 void pc_cmos_init(PCMachineState *pcms,
610 BusState *idebus0, BusState *idebus1,
611 ISADevice *rtc)
612 {
613 int val;
614 static pc_cmos_init_late_arg arg;
615 X86MachineState *x86ms = X86_MACHINE(pcms);
616 MC146818RtcState *s = MC146818_RTC(rtc);
617
618 /* various important CMOS locations needed by PC/Bochs bios */
619
620 /* memory size */
621 /* base memory (first MiB) */
622 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
623 mc146818rtc_set_cmos_data(s, 0x15, val);
624 mc146818rtc_set_cmos_data(s, 0x16, val >> 8);
625 /* extended memory (next 64MiB) */
626 if (x86ms->below_4g_mem_size > 1 * MiB) {
627 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
628 } else {
629 val = 0;
630 }
631 if (val > 65535)
632 val = 65535;
633 mc146818rtc_set_cmos_data(s, 0x17, val);
634 mc146818rtc_set_cmos_data(s, 0x18, val >> 8);
635 mc146818rtc_set_cmos_data(s, 0x30, val);
636 mc146818rtc_set_cmos_data(s, 0x31, val >> 8);
637 /* memory between 16MiB and 4GiB */
638 if (x86ms->below_4g_mem_size > 16 * MiB) {
639 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
640 } else {
641 val = 0;
642 }
643 if (val > 65535)
644 val = 65535;
645 mc146818rtc_set_cmos_data(s, 0x34, val);
646 mc146818rtc_set_cmos_data(s, 0x35, val >> 8);
647 /* memory above 4GiB */
648 val = x86ms->above_4g_mem_size / 65536;
649 mc146818rtc_set_cmos_data(s, 0x5b, val);
650 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8);
651 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16);
652
653 object_property_add_link(OBJECT(pcms), "rtc_state",
654 TYPE_ISA_DEVICE,
655 (Object **)&x86ms->rtc,
656 object_property_allow_set_link,
657 OBJ_PROP_LINK_STRONG);
658 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
659 &error_abort);
660
661 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal);
662
663 val = 0;
664 val |= 0x02; /* FPU is there */
665 val |= 0x04; /* PS/2 mouse installed */
666 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val);
667
668 /* hard drives and FDC */
669 arg.rtc_state = s;
670 arg.idebus[0] = idebus0;
671 arg.idebus[1] = idebus1;
672 qemu_register_reset(pc_cmos_init_late, &arg);
673 }
674
675 static void handle_a20_line_change(void *opaque, int irq, int level)
676 {
677 X86CPU *cpu = opaque;
678
679 /* XXX: send to all CPUs ? */
680 /* XXX: add logic to handle multiple A20 line sources */
681 x86_cpu_set_a20(cpu, level);
682 }
683
684 #define NE2000_NB_MAX 6
685
686 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
687 0x280, 0x380 };
688 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
689
690 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
691 {
692 static int nb_ne2k = 0;
693
694 if (nb_ne2k == NE2000_NB_MAX)
695 return;
696 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
697 ne2000_irq[nb_ne2k], nd);
698 nb_ne2k++;
699 }
700
701 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
702 {
703 X86CPU *cpu = opaque;
704
705 if (level) {
706 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
707 }
708 }
709
710 static
711 void pc_machine_done(Notifier *notifier, void *data)
712 {
713 PCMachineState *pcms = container_of(notifier,
714 PCMachineState, machine_done);
715 X86MachineState *x86ms = X86_MACHINE(pcms);
716
717 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state,
718 &error_fatal);
719
720 if (pcms->cxl_devices_state.is_enabled) {
721 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
722 }
723
724 /* set the number of CPUs */
725 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
726
727 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
728
729 acpi_setup();
730 if (x86ms->fw_cfg) {
731 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
732 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
733 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
734 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
735 }
736 }
737
738 void pc_guest_info_init(PCMachineState *pcms)
739 {
740 X86MachineState *x86ms = X86_MACHINE(pcms);
741
742 x86ms->apic_xrupt_override = true;
743 pcms->machine_done.notify = pc_machine_done;
744 qemu_add_machine_init_done_notifier(&pcms->machine_done);
745 }
746
747 /* setup pci memory address space mapping into system address space */
748 void pc_pci_as_mapping_init(MemoryRegion *system_memory,
749 MemoryRegion *pci_address_space)
750 {
751 /* Set to lower priority than RAM */
752 memory_region_add_subregion_overlap(system_memory, 0x0,
753 pci_address_space, -1);
754 }
755
756 void xen_load_linux(PCMachineState *pcms)
757 {
758 int i;
759 FWCfgState *fw_cfg;
760 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
761 X86MachineState *x86ms = X86_MACHINE(pcms);
762
763 assert(MACHINE(pcms)->kernel_filename != NULL);
764
765 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
766 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
767 rom_set_fw(fw_cfg);
768
769 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
770 pcmc->pvh_enabled);
771 for (i = 0; i < nb_option_roms; i++) {
772 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
773 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
774 !strcmp(option_rom[i].name, "pvh.bin") ||
775 !strcmp(option_rom[i].name, "multiboot.bin") ||
776 !strcmp(option_rom[i].name, "multiboot_dma.bin"));
777 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
778 }
779 x86ms->fw_cfg = fw_cfg;
780 }
781
782 #define PC_ROM_MIN_VGA 0xc0000
783 #define PC_ROM_MIN_OPTION 0xc8000
784 #define PC_ROM_MAX 0xe0000
785 #define PC_ROM_ALIGN 0x800
786 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
787
788 static hwaddr pc_above_4g_end(PCMachineState *pcms)
789 {
790 X86MachineState *x86ms = X86_MACHINE(pcms);
791
792 if (pcms->sgx_epc.size != 0) {
793 return sgx_epc_above_4g_end(&pcms->sgx_epc);
794 }
795
796 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
797 }
798
799 static void pc_get_device_memory_range(PCMachineState *pcms,
800 hwaddr *base,
801 ram_addr_t *device_mem_size)
802 {
803 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
804 MachineState *machine = MACHINE(pcms);
805 ram_addr_t size;
806 hwaddr addr;
807
808 size = machine->maxram_size - machine->ram_size;
809 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
810
811 if (pcmc->enforce_aligned_dimm) {
812 /* size device region assuming 1G page max alignment per slot */
813 size += (1 * GiB) * machine->ram_slots;
814 }
815
816 *base = addr;
817 *device_mem_size = size;
818 }
819
820 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
821 {
822 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
823 hwaddr cxl_base;
824 ram_addr_t size;
825
826 if (pcmc->has_reserved_memory) {
827 pc_get_device_memory_range(pcms, &cxl_base, &size);
828 cxl_base += size;
829 } else {
830 cxl_base = pc_above_4g_end(pcms);
831 }
832
833 return cxl_base;
834 }
835
836 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
837 {
838 uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
839
840 if (pcms->cxl_devices_state.fixed_windows) {
841 GList *it;
842
843 start = ROUND_UP(start, 256 * MiB);
844 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
845 CXLFixedWindow *fw = it->data;
846 start += fw->size;
847 }
848 }
849
850 return start;
851 }
852
853 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
854 {
855 X86CPU *cpu = X86_CPU(first_cpu);
856
857 /* 32-bit systems don't have hole64 thus return max CPU address */
858 if (cpu->phys_bits <= 32) {
859 return ((hwaddr)1 << cpu->phys_bits) - 1;
860 }
861
862 return pc_pci_hole64_start() + pci_hole64_size - 1;
863 }
864
865 /*
866 * AMD systems with an IOMMU have an additional hole close to the
867 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
868 * on kernel version, VFIO may or may not let you DMA map those ranges.
869 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
870 * with certain memory sizes. It's also wrong to use those IOVA ranges
871 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
872 * The ranges reserved for Hyper-Transport are:
873 *
874 * FD_0000_0000h - FF_FFFF_FFFFh
875 *
876 * The ranges represent the following:
877 *
878 * Base Address Top Address Use
879 *
880 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
881 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
882 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
883 * FD_F910_0000h FD_F91F_FFFFh System Management
884 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
885 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
886 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
887 * FD_FE00_0000h FD_FFFF_FFFFh Configuration
888 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
889 * FE_2000_0000h FF_FFFF_FFFFh Reserved
890 *
891 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
892 * Table 3: Special Address Controls (GPA) for more information.
893 */
894 #define AMD_HT_START 0xfd00000000UL
895 #define AMD_HT_END 0xffffffffffUL
896 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1)
897 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START)
898
899 void pc_memory_init(PCMachineState *pcms,
900 MemoryRegion *system_memory,
901 MemoryRegion *rom_memory,
902 uint64_t pci_hole64_size)
903 {
904 int linux_boot, i;
905 MemoryRegion *option_rom_mr;
906 MemoryRegion *ram_below_4g, *ram_above_4g;
907 FWCfgState *fw_cfg;
908 MachineState *machine = MACHINE(pcms);
909 MachineClass *mc = MACHINE_GET_CLASS(machine);
910 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
911 X86MachineState *x86ms = X86_MACHINE(pcms);
912 hwaddr maxphysaddr, maxusedaddr;
913 hwaddr cxl_base, cxl_resv_end = 0;
914 X86CPU *cpu = X86_CPU(first_cpu);
915
916 assert(machine->ram_size == x86ms->below_4g_mem_size +
917 x86ms->above_4g_mem_size);
918
919 linux_boot = (machine->kernel_filename != NULL);
920
921 /*
922 * The HyperTransport range close to the 1T boundary is unique to AMD
923 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
924 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
925 * older machine types (<= 7.0) for compatibility purposes.
926 */
927 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) {
928 /* Bail out if max possible address does not cross HT range */
929 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) {
930 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START;
931 }
932
933 /*
934 * Advertise the HT region if address space covers the reserved
935 * region or if we relocate.
936 */
937 if (cpu->phys_bits >= 40) {
938 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED);
939 }
940 }
941
942 /*
943 * phys-bits is required to be appropriately configured
944 * to make sure max used GPA is reachable.
945 */
946 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
947 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
948 if (maxphysaddr < maxusedaddr) {
949 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
950 " phys-bits too low (%u)",
951 maxphysaddr, maxusedaddr, cpu->phys_bits);
952 exit(EXIT_FAILURE);
953 }
954
955 /*
956 * Split single memory region and use aliases to address portions of it,
957 * done for backwards compatibility with older qemus.
958 */
959 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
960 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
961 0, x86ms->below_4g_mem_size);
962 memory_region_add_subregion(system_memory, 0, ram_below_4g);
963 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
964 if (x86ms->above_4g_mem_size > 0) {
965 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
966 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
967 machine->ram,
968 x86ms->below_4g_mem_size,
969 x86ms->above_4g_mem_size);
970 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
971 ram_above_4g);
972 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
973 E820_RAM);
974 }
975
976 if (pcms->sgx_epc.size != 0) {
977 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
978 }
979
980 if (!pcmc->has_reserved_memory &&
981 (machine->ram_slots ||
982 (machine->maxram_size > machine->ram_size))) {
983
984 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
985 mc->name);
986 exit(EXIT_FAILURE);
987 }
988
989 /* initialize device memory address space */
990 if (pcmc->has_reserved_memory &&
991 (machine->ram_size < machine->maxram_size)) {
992 ram_addr_t device_mem_size;
993 hwaddr device_mem_base;
994
995 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
996 error_report("unsupported amount of memory slots: %"PRIu64,
997 machine->ram_slots);
998 exit(EXIT_FAILURE);
999 }
1000
1001 if (QEMU_ALIGN_UP(machine->maxram_size,
1002 TARGET_PAGE_SIZE) != machine->maxram_size) {
1003 error_report("maximum memory size must by aligned to multiple of "
1004 "%d bytes", TARGET_PAGE_SIZE);
1005 exit(EXIT_FAILURE);
1006 }
1007
1008 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size);
1009
1010 if (device_mem_base + device_mem_size < device_mem_size) {
1011 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1012 machine->maxram_size);
1013 exit(EXIT_FAILURE);
1014 }
1015 machine_memory_devices_init(machine, device_mem_base, device_mem_size);
1016 }
1017
1018 if (pcms->cxl_devices_state.is_enabled) {
1019 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1020 hwaddr cxl_size = MiB;
1021
1022 cxl_base = pc_get_cxl_range_start(pcms);
1023 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
1024 memory_region_add_subregion(system_memory, cxl_base, mr);
1025 cxl_resv_end = cxl_base + cxl_size;
1026 if (pcms->cxl_devices_state.fixed_windows) {
1027 hwaddr cxl_fmw_base;
1028 GList *it;
1029
1030 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
1031 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
1032 CXLFixedWindow *fw = it->data;
1033
1034 fw->base = cxl_fmw_base;
1035 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
1036 "cxl-fixed-memory-region", fw->size);
1037 memory_region_add_subregion(system_memory, fw->base, &fw->mr);
1038 cxl_fmw_base += fw->size;
1039 cxl_resv_end = cxl_fmw_base;
1040 }
1041 }
1042 }
1043
1044 /* Initialize PC system firmware */
1045 pc_system_firmware_init(pcms, rom_memory);
1046
1047 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1048 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1049 &error_fatal);
1050 if (pcmc->pci_enabled) {
1051 memory_region_set_readonly(option_rom_mr, true);
1052 }
1053 memory_region_add_subregion_overlap(rom_memory,
1054 PC_ROM_MIN_VGA,
1055 option_rom_mr,
1056 1);
1057
1058 fw_cfg = fw_cfg_arch_create(machine,
1059 x86ms->boot_cpus, x86ms->apic_id_limit);
1060
1061 rom_set_fw(fw_cfg);
1062
1063 if (machine->device_memory) {
1064 uint64_t *val = g_malloc(sizeof(*val));
1065 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1066 uint64_t res_mem_end = machine->device_memory->base;
1067
1068 if (!pcmc->broken_reserved_end) {
1069 res_mem_end += memory_region_size(&machine->device_memory->mr);
1070 }
1071
1072 if (pcms->cxl_devices_state.is_enabled) {
1073 res_mem_end = cxl_resv_end;
1074 }
1075 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1076 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1077 }
1078
1079 if (linux_boot) {
1080 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1081 pcmc->pvh_enabled);
1082 }
1083
1084 for (i = 0; i < nb_option_roms; i++) {
1085 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1086 }
1087 x86ms->fw_cfg = fw_cfg;
1088
1089 /* Init default IOAPIC address space */
1090 x86ms->ioapic_as = &address_space_memory;
1091
1092 /* Init ACPI memory hotplug IO base address */
1093 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1094 }
1095
1096 /*
1097 * The 64bit pci hole starts after "above 4G RAM" and
1098 * potentially the space reserved for memory hotplug.
1099 */
1100 uint64_t pc_pci_hole64_start(void)
1101 {
1102 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1103 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1104 MachineState *ms = MACHINE(pcms);
1105 uint64_t hole64_start = 0;
1106 ram_addr_t size = 0;
1107
1108 if (pcms->cxl_devices_state.is_enabled) {
1109 hole64_start = pc_get_cxl_range_end(pcms);
1110 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
1111 pc_get_device_memory_range(pcms, &hole64_start, &size);
1112 if (!pcmc->broken_reserved_end) {
1113 hole64_start += size;
1114 }
1115 } else {
1116 hole64_start = pc_above_4g_end(pcms);
1117 }
1118
1119 return ROUND_UP(hole64_start, 1 * GiB);
1120 }
1121
1122 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1123 {
1124 DeviceState *dev = NULL;
1125
1126 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1127 if (pci_bus) {
1128 PCIDevice *pcidev = pci_vga_init(pci_bus);
1129 dev = pcidev ? &pcidev->qdev : NULL;
1130 } else if (isa_bus) {
1131 ISADevice *isadev = isa_vga_init(isa_bus);
1132 dev = isadev ? DEVICE(isadev) : NULL;
1133 }
1134 rom_reset_order_override();
1135 return dev;
1136 }
1137
1138 static const MemoryRegionOps ioport80_io_ops = {
1139 .write = ioport80_write,
1140 .read = ioport80_read,
1141 .endianness = DEVICE_NATIVE_ENDIAN,
1142 .impl = {
1143 .min_access_size = 1,
1144 .max_access_size = 1,
1145 },
1146 };
1147
1148 static const MemoryRegionOps ioportF0_io_ops = {
1149 .write = ioportF0_write,
1150 .read = ioportF0_read,
1151 .endianness = DEVICE_NATIVE_ENDIAN,
1152 .impl = {
1153 .min_access_size = 1,
1154 .max_access_size = 1,
1155 },
1156 };
1157
1158 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1159 bool create_i8042, bool no_vmport)
1160 {
1161 int i;
1162 DriveInfo *fd[MAX_FD];
1163 qemu_irq *a20_line;
1164 ISADevice *fdc, *i8042, *port92, *vmmouse;
1165
1166 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1167 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1168
1169 for (i = 0; i < MAX_FD; i++) {
1170 fd[i] = drive_get(IF_FLOPPY, 0, i);
1171 create_fdctrl |= !!fd[i];
1172 }
1173 if (create_fdctrl) {
1174 fdc = isa_new(TYPE_ISA_FDC);
1175 if (fdc) {
1176 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1177 isa_fdc_init_drives(fdc, fd);
1178 }
1179 }
1180
1181 if (!create_i8042) {
1182 return;
1183 }
1184
1185 i8042 = isa_create_simple(isa_bus, TYPE_I8042);
1186 if (!no_vmport) {
1187 isa_create_simple(isa_bus, TYPE_VMPORT);
1188 vmmouse = isa_try_new("vmmouse");
1189 } else {
1190 vmmouse = NULL;
1191 }
1192 if (vmmouse) {
1193 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
1194 &error_abort);
1195 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1196 }
1197 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1198
1199 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1200 i8042_setup_a20_line(i8042, a20_line[0]);
1201 qdev_connect_gpio_out_named(DEVICE(port92),
1202 PORT92_A20_LINE, 0, a20_line[1]);
1203 g_free(a20_line);
1204 }
1205
1206 void pc_basic_device_init(struct PCMachineState *pcms,
1207 ISABus *isa_bus, qemu_irq *gsi,
1208 ISADevice *rtc_state,
1209 bool create_fdctrl,
1210 uint32_t hpet_irqs)
1211 {
1212 int i;
1213 DeviceState *hpet = NULL;
1214 int pit_isa_irq = 0;
1215 qemu_irq pit_alt_irq = NULL;
1216 qemu_irq rtc_irq = NULL;
1217 ISADevice *pit = NULL;
1218 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1219 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1220 X86MachineState *x86ms = X86_MACHINE(pcms);
1221
1222 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1223 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1224
1225 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1226 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1227
1228 /*
1229 * Check if an HPET shall be created.
1230 *
1231 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1232 * when the HPET wants to take over. Thus we have to disable the latter.
1233 */
1234 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
1235 kvm_has_pit_state2())) {
1236 hpet = qdev_try_new(TYPE_HPET);
1237 if (!hpet) {
1238 error_report("couldn't create HPET device");
1239 exit(1);
1240 }
1241 /*
1242 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*,
1243 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set
1244 * the property, use whatever mask they specified.
1245 */
1246 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1247 HPET_INTCAP, NULL);
1248 if (!compat) {
1249 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1250 }
1251 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1252 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1253
1254 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1255 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1256 }
1257 pit_isa_irq = -1;
1258 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1259 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1260 }
1261
1262 if (rtc_irq) {
1263 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq);
1264 } else {
1265 uint32_t irq = object_property_get_uint(OBJECT(rtc_state),
1266 "irq",
1267 &error_fatal);
1268 isa_connect_gpio_out(rtc_state, 0, irq);
1269 }
1270 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state),
1271 "date");
1272
1273 #ifdef CONFIG_XEN_EMU
1274 if (xen_mode == XEN_EMULATE) {
1275 xen_overlay_create();
1276 xen_evtchn_create(IOAPIC_NUM_PINS, gsi);
1277 xen_gnttab_create();
1278 xen_xenstore_create();
1279 if (pcms->bus) {
1280 pci_create_simple(pcms->bus, -1, "xen-platform");
1281 }
1282 xen_bus_init();
1283 xen_be_init();
1284 }
1285 #endif
1286
1287 qemu_register_boot_set(pc_boot_set, rtc_state);
1288
1289 if (!xen_enabled() &&
1290 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
1291 if (kvm_pit_in_kernel()) {
1292 pit = kvm_pit_init(isa_bus, 0x40);
1293 } else {
1294 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1295 }
1296 if (hpet) {
1297 /* connect PIT to output control line of the HPET */
1298 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1299 }
1300 pcspk_init(pcms->pcspk, isa_bus, pit);
1301 }
1302
1303 /* Super I/O */
1304 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1305 pcms->vmport != ON_OFF_AUTO_ON);
1306 }
1307
1308 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1309 {
1310 MachineClass *mc = MACHINE_CLASS(pcmc);
1311 int i;
1312
1313 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1314 for (i = 0; i < nb_nics; i++) {
1315 NICInfo *nd = &nd_table[i];
1316 const char *model = nd->model ? nd->model : mc->default_nic;
1317
1318 if (g_str_equal(model, "ne2k_isa")) {
1319 pc_init_ne2k_isa(isa_bus, nd);
1320 } else {
1321 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1322 }
1323 }
1324 rom_reset_order_override();
1325 }
1326
1327 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1328 {
1329 qemu_irq *i8259;
1330
1331 if (kvm_pic_in_kernel()) {
1332 i8259 = kvm_i8259_init(isa_bus);
1333 } else if (xen_enabled()) {
1334 i8259 = xen_interrupt_controller_init();
1335 } else {
1336 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1337 }
1338
1339 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1340 i8259_irqs[i] = i8259[i];
1341 }
1342
1343 g_free(i8259);
1344 }
1345
1346 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1347 Error **errp)
1348 {
1349 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1350 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1351 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1352 const MachineState *ms = MACHINE(hotplug_dev);
1353 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1354 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1355 Error *local_err = NULL;
1356
1357 /*
1358 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1359 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1360 * addition to cover this case.
1361 */
1362 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1363 error_setg(errp,
1364 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1365 return;
1366 }
1367
1368 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1369 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1370 return;
1371 }
1372
1373 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1374 if (local_err) {
1375 error_propagate(errp, local_err);
1376 return;
1377 }
1378
1379 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1380 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1381 }
1382
1383 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1384 DeviceState *dev, Error **errp)
1385 {
1386 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1387 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1388 MachineState *ms = MACHINE(hotplug_dev);
1389 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1390
1391 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1392
1393 if (is_nvdimm) {
1394 nvdimm_plug(ms->nvdimms_state);
1395 }
1396
1397 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1398 }
1399
1400 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1401 DeviceState *dev, Error **errp)
1402 {
1403 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1404
1405 /*
1406 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1407 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1408 * addition to cover this case.
1409 */
1410 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1411 error_setg(errp,
1412 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1413 return;
1414 }
1415
1416 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1417 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1418 return;
1419 }
1420
1421 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1422 errp);
1423 }
1424
1425 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1426 DeviceState *dev, Error **errp)
1427 {
1428 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1429 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1430 Error *local_err = NULL;
1431
1432 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1433 if (local_err) {
1434 goto out;
1435 }
1436
1437 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1438 qdev_unrealize(dev);
1439 out:
1440 error_propagate(errp, local_err);
1441 }
1442
1443 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1444 DeviceState *dev, Error **errp)
1445 {
1446 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1447 pc_memory_pre_plug(hotplug_dev, dev, errp);
1448 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1449 x86_cpu_pre_plug(hotplug_dev, dev, errp);
1450 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1451 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1452 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1453 /* Declare the APIC range as the reserved MSI region */
1454 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1455 VIRTIO_IOMMU_RESV_MEM_T_MSI);
1456
1457 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
1458 object_property_set_str(OBJECT(dev), "reserved-regions[0]",
1459 resv_prop_str, errp);
1460 g_free(resv_prop_str);
1461 }
1462
1463 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1464 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1465 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1466
1467 if (pcms->iommu) {
1468 error_setg(errp, "QEMU does not support multiple vIOMMUs "
1469 "for x86 yet.");
1470 return;
1471 }
1472 pcms->iommu = dev;
1473 }
1474 }
1475
1476 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1477 DeviceState *dev, Error **errp)
1478 {
1479 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1480 pc_memory_plug(hotplug_dev, dev, errp);
1481 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1482 x86_cpu_plug(hotplug_dev, dev, errp);
1483 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1484 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1485 }
1486 }
1487
1488 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1489 DeviceState *dev, Error **errp)
1490 {
1491 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1492 pc_memory_unplug_request(hotplug_dev, dev, errp);
1493 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1494 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1495 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1496 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
1497 errp);
1498 } else {
1499 error_setg(errp, "acpi: device unplug request for not supported device"
1500 " type: %s", object_get_typename(OBJECT(dev)));
1501 }
1502 }
1503
1504 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1505 DeviceState *dev, Error **errp)
1506 {
1507 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1508 pc_memory_unplug(hotplug_dev, dev, errp);
1509 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1510 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1511 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1512 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1513 } else {
1514 error_setg(errp, "acpi: device unplug for not supported device"
1515 " type: %s", object_get_typename(OBJECT(dev)));
1516 }
1517 }
1518
1519 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1520 DeviceState *dev)
1521 {
1522 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1523 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1524 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
1525 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1526 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1527 return HOTPLUG_HANDLER(machine);
1528 }
1529
1530 return NULL;
1531 }
1532
1533 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1534 void *opaque, Error **errp)
1535 {
1536 PCMachineState *pcms = PC_MACHINE(obj);
1537 OnOffAuto vmport = pcms->vmport;
1538
1539 visit_type_OnOffAuto(v, name, &vmport, errp);
1540 }
1541
1542 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1543 void *opaque, Error **errp)
1544 {
1545 PCMachineState *pcms = PC_MACHINE(obj);
1546
1547 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1548 }
1549
1550 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1551 {
1552 PCMachineState *pcms = PC_MACHINE(obj);
1553
1554 return pcms->smbus_enabled;
1555 }
1556
1557 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1558 {
1559 PCMachineState *pcms = PC_MACHINE(obj);
1560
1561 pcms->smbus_enabled = value;
1562 }
1563
1564 static bool pc_machine_get_sata(Object *obj, Error **errp)
1565 {
1566 PCMachineState *pcms = PC_MACHINE(obj);
1567
1568 return pcms->sata_enabled;
1569 }
1570
1571 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1572 {
1573 PCMachineState *pcms = PC_MACHINE(obj);
1574
1575 pcms->sata_enabled = value;
1576 }
1577
1578 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1579 {
1580 PCMachineState *pcms = PC_MACHINE(obj);
1581
1582 return pcms->hpet_enabled;
1583 }
1584
1585 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1586 {
1587 PCMachineState *pcms = PC_MACHINE(obj);
1588
1589 pcms->hpet_enabled = value;
1590 }
1591
1592 static bool pc_machine_get_i8042(Object *obj, Error **errp)
1593 {
1594 PCMachineState *pcms = PC_MACHINE(obj);
1595
1596 return pcms->i8042_enabled;
1597 }
1598
1599 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1600 {
1601 PCMachineState *pcms = PC_MACHINE(obj);
1602
1603 pcms->i8042_enabled = value;
1604 }
1605
1606 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1607 {
1608 PCMachineState *pcms = PC_MACHINE(obj);
1609
1610 return pcms->default_bus_bypass_iommu;
1611 }
1612
1613 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1614 Error **errp)
1615 {
1616 PCMachineState *pcms = PC_MACHINE(obj);
1617
1618 pcms->default_bus_bypass_iommu = value;
1619 }
1620
1621 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1622 void *opaque, Error **errp)
1623 {
1624 PCMachineState *pcms = PC_MACHINE(obj);
1625 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1626
1627 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1628 }
1629
1630 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1631 void *opaque, Error **errp)
1632 {
1633 PCMachineState *pcms = PC_MACHINE(obj);
1634
1635 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1636 }
1637
1638 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1639 const char *name, void *opaque,
1640 Error **errp)
1641 {
1642 PCMachineState *pcms = PC_MACHINE(obj);
1643 uint64_t value = pcms->max_ram_below_4g;
1644
1645 visit_type_size(v, name, &value, errp);
1646 }
1647
1648 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1649 const char *name, void *opaque,
1650 Error **errp)
1651 {
1652 PCMachineState *pcms = PC_MACHINE(obj);
1653 uint64_t value;
1654
1655 if (!visit_type_size(v, name, &value, errp)) {
1656 return;
1657 }
1658 if (value > 4 * GiB) {
1659 error_setg(errp,
1660 "Machine option 'max-ram-below-4g=%"PRIu64
1661 "' expects size less than or equal to 4G", value);
1662 return;
1663 }
1664
1665 if (value < 1 * MiB) {
1666 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1667 "BIOS may not work with less than 1MiB", value);
1668 }
1669
1670 pcms->max_ram_below_4g = value;
1671 }
1672
1673 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1674 const char *name, void *opaque,
1675 Error **errp)
1676 {
1677 PCMachineState *pcms = PC_MACHINE(obj);
1678 uint64_t value = pcms->max_fw_size;
1679
1680 visit_type_size(v, name, &value, errp);
1681 }
1682
1683 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1684 const char *name, void *opaque,
1685 Error **errp)
1686 {
1687 PCMachineState *pcms = PC_MACHINE(obj);
1688 uint64_t value;
1689
1690 if (!visit_type_size(v, name, &value, errp)) {
1691 return;
1692 }
1693
1694 /*
1695 * We don't have a theoretically justifiable exact lower bound on the base
1696 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1697 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1698 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to
1699 * 16MiB in size.
1700 */
1701 if (value > 16 * MiB) {
1702 error_setg(errp,
1703 "User specified max allowed firmware size %" PRIu64 " is "
1704 "greater than 16MiB. If combined firmware size exceeds "
1705 "16MiB the system may not boot, or experience intermittent"
1706 "stability issues.",
1707 value);
1708 return;
1709 }
1710
1711 pcms->max_fw_size = value;
1712 }
1713
1714
1715 static void pc_machine_initfn(Object *obj)
1716 {
1717 PCMachineState *pcms = PC_MACHINE(obj);
1718 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1719
1720 #ifdef CONFIG_VMPORT
1721 pcms->vmport = ON_OFF_AUTO_AUTO;
1722 #else
1723 pcms->vmport = ON_OFF_AUTO_OFF;
1724 #endif /* CONFIG_VMPORT */
1725 pcms->max_ram_below_4g = 0; /* use default */
1726 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type;
1727
1728 /* acpi build is enabled by default if machine supports it */
1729 pcms->acpi_build_enabled = pcmc->has_acpi_build;
1730 pcms->smbus_enabled = true;
1731 pcms->sata_enabled = true;
1732 pcms->i8042_enabled = true;
1733 pcms->max_fw_size = 8 * MiB;
1734 #ifdef CONFIG_HPET
1735 pcms->hpet_enabled = true;
1736 #endif
1737 pcms->default_bus_bypass_iommu = false;
1738
1739 pc_system_flash_create(pcms);
1740 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1741 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1742 OBJECT(pcms->pcspk), "audiodev");
1743 cxl_machine_init(obj, &pcms->cxl_devices_state);
1744 }
1745
1746 int pc_machine_kvm_type(MachineState *machine, const char *kvm_type)
1747 {
1748 return 0;
1749 }
1750
1751 static void pc_machine_reset(MachineState *machine, ShutdownCause reason)
1752 {
1753 CPUState *cs;
1754 X86CPU *cpu;
1755
1756 qemu_devices_reset(reason);
1757
1758 /* Reset APIC after devices have been reset to cancel
1759 * any changes that qemu_devices_reset() might have done.
1760 */
1761 CPU_FOREACH(cs) {
1762 cpu = X86_CPU(cs);
1763
1764 x86_cpu_after_reset(cpu);
1765 }
1766 }
1767
1768 static void pc_machine_wakeup(MachineState *machine)
1769 {
1770 cpu_synchronize_all_states();
1771 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE);
1772 cpu_synchronize_all_post_reset();
1773 }
1774
1775 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1776 {
1777 X86IOMMUState *iommu = x86_iommu_get_default();
1778 IntelIOMMUState *intel_iommu;
1779
1780 if (iommu &&
1781 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1782 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1783 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1784 if (!intel_iommu->caching_mode) {
1785 error_setg(errp, "Device assignment is not allowed without "
1786 "enabling caching-mode=on for Intel IOMMU.");
1787 return false;
1788 }
1789 }
1790
1791 return true;
1792 }
1793
1794 static void pc_machine_class_init(ObjectClass *oc, void *data)
1795 {
1796 MachineClass *mc = MACHINE_CLASS(oc);
1797 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1798 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1799
1800 pcmc->pci_enabled = true;
1801 pcmc->has_acpi_build = true;
1802 pcmc->rsdp_in_ram = true;
1803 pcmc->smbios_defaults = true;
1804 pcmc->smbios_uuid_encoded = true;
1805 pcmc->gigabyte_align = true;
1806 pcmc->has_reserved_memory = true;
1807 pcmc->kvmclock_enabled = true;
1808 pcmc->enforce_aligned_dimm = true;
1809 pcmc->enforce_amd_1tb_hole = true;
1810 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1811 * to be used at the moment, 32K should be enough for a while. */
1812 pcmc->acpi_data_size = 0x20000 + 0x8000;
1813 pcmc->pvh_enabled = true;
1814 pcmc->kvmclock_create_always = true;
1815 pcmc->resizable_acpi_blob = true;
1816 assert(!mc->get_hotplug_handler);
1817 mc->get_hotplug_handler = pc_get_hotplug_handler;
1818 mc->hotplug_allowed = pc_hotplug_allowed;
1819 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1820 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1821 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1822 mc->auto_enable_numa_with_memhp = true;
1823 mc->auto_enable_numa_with_memdev = true;
1824 mc->has_hotpluggable_cpus = true;
1825 mc->default_boot_order = "cad";
1826 mc->block_default_type = IF_IDE;
1827 mc->max_cpus = 255;
1828 mc->reset = pc_machine_reset;
1829 mc->wakeup = pc_machine_wakeup;
1830 hc->pre_plug = pc_machine_device_pre_plug_cb;
1831 hc->plug = pc_machine_device_plug_cb;
1832 hc->unplug_request = pc_machine_device_unplug_request_cb;
1833 hc->unplug = pc_machine_device_unplug_cb;
1834 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1835 mc->nvdimm_supported = true;
1836 mc->smp_props.dies_supported = true;
1837 mc->default_ram_id = "pc.ram";
1838 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64;
1839
1840 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1841 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1842 NULL, NULL);
1843 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1844 "Maximum ram below the 4G boundary (32bit boundary)");
1845
1846 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1847 pc_machine_get_vmport, pc_machine_set_vmport,
1848 NULL, NULL);
1849 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1850 "Enable vmport (pc & q35)");
1851
1852 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1853 pc_machine_get_smbus, pc_machine_set_smbus);
1854 object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1855 "Enable/disable system management bus");
1856
1857 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1858 pc_machine_get_sata, pc_machine_set_sata);
1859 object_class_property_set_description(oc, PC_MACHINE_SATA,
1860 "Enable/disable Serial ATA bus");
1861
1862 object_class_property_add_bool(oc, "hpet",
1863 pc_machine_get_hpet, pc_machine_set_hpet);
1864 object_class_property_set_description(oc, "hpet",
1865 "Enable/disable high precision event timer emulation");
1866
1867 object_class_property_add_bool(oc, PC_MACHINE_I8042,
1868 pc_machine_get_i8042, pc_machine_set_i8042);
1869
1870 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
1871 pc_machine_get_default_bus_bypass_iommu,
1872 pc_machine_set_default_bus_bypass_iommu);
1873
1874 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1875 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1876 NULL, NULL);
1877 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1878 "Maximum combined firmware size");
1879
1880 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1881 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1882 NULL, NULL);
1883 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1884 "SMBIOS Entry Point type [32, 64]");
1885 }
1886
1887 static const TypeInfo pc_machine_info = {
1888 .name = TYPE_PC_MACHINE,
1889 .parent = TYPE_X86_MACHINE,
1890 .abstract = true,
1891 .instance_size = sizeof(PCMachineState),
1892 .instance_init = pc_machine_initfn,
1893 .class_size = sizeof(PCMachineClass),
1894 .class_init = pc_machine_class_init,
1895 .interfaces = (InterfaceInfo[]) {
1896 { TYPE_HOTPLUG_HANDLER },
1897 { }
1898 },
1899 };
1900
1901 static void pc_machine_register_types(void)
1902 {
1903 type_register_static(&pc_machine_info);
1904 }
1905
1906 type_init(pc_machine_register_types)
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