include/exec/cpu-defs.h

   1 /*
   2  * common defines for all CPUs
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_DEFS_H
  20 #define CPU_DEFS_H
  21
  22 #ifndef NEED_CPU_H
  23 #error cpu.h included from common code
  24 #endif
  25
  26 #include "qemu/host-utils.h"
  27 #include "qemu/thread.h"
  28 #ifndef CONFIG_USER_ONLY
  29 #include "exec/hwaddr.h"
  30 #endif
  31 #include "exec/memattrs.h"
  32 #include "hw/core/cpu.h"
  33
  34 #include "cpu-param.h"
  35
  36 #ifndef TARGET_LONG_BITS
  37 # error TARGET_LONG_BITS must be defined in cpu-param.h
  38 #endif
  39 #ifndef TARGET_PHYS_ADDR_SPACE_BITS
  40 # error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h
  41 #endif
  42 #ifndef TARGET_VIRT_ADDR_SPACE_BITS
  43 # error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h
  44 #endif
  45 #ifndef TARGET_PAGE_BITS
  46 # ifdef TARGET_PAGE_BITS_VARY
  47 #  ifndef TARGET_PAGE_BITS_MIN
  48 #   error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h
  49 #  endif
  50 # else
  51 #  error TARGET_PAGE_BITS must be defined in cpu-param.h
  52 # endif
  53 #endif
  54
  55 #include "exec/target_long.h"
  56
  57 /*
  58  * Fix the number of mmu modes to 16, which is also the maximum
  59  * supported by the softmmu tlb api.
  60  */
  61 #define NB_MMU_MODES 16
  62
  63 #if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG)
  64 #include "exec/tlb-common.h"
  65
  66 /* use a fully associative victim tlb of 8 entries */
  67 #define CPU_VTLB_SIZE 8
  68
  69 #define CPU_TLB_DYN_MIN_BITS 6
  70 #define CPU_TLB_DYN_DEFAULT_BITS 8
  71
  72 # if HOST_LONG_BITS == 32
  73 /* Make sure we do not require a double-word shift for the TLB load */
  74 #  define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS)
  75 # else /* HOST_LONG_BITS == 64 */
  76 /*
  77  * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) ==
  78  * 2**34 == 16G of address space. This is roughly what one would expect a
  79  * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel
  80  * Skylake's Level-2 STLB has 16 1G entries.
  81  * Also, make sure we do not size the TLB past the guest's address space.
  82  */
  83 #  ifdef TARGET_PAGE_BITS_VARY
  84 #   define CPU_TLB_DYN_MAX_BITS                                  \
  85     MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
  86 #  else
  87 #   define CPU_TLB_DYN_MAX_BITS                                  \
  88     MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
  89 #  endif
  90 # endif
  91
  92 #endif /* CONFIG_SOFTMMU && CONFIG_TCG */
  93
  94 #if defined(CONFIG_SOFTMMU)
  95 /*
  96  * The full TLB entry, which is not accessed by generated TCG code,
  97  * so the layout is not as critical as that of CPUTLBEntry. This is
  98  * also why we don't want to combine the two structs.
  99  */
 100 typedef struct CPUTLBEntryFull {
 101     /*
 102      * @xlat_section contains:
 103      *  - For ram, an offset which must be added to the virtual address
 104      *    to obtain the ram_addr_t of the target RAM
 105      *  - For other memory regions,
 106      *     + in the lower TARGET_PAGE_BITS, the physical section number
 107      *     + with the TARGET_PAGE_BITS masked off, the offset within
 108      *       the target MemoryRegion
 109      */
 110     hwaddr xlat_section;
 111
 112     /*
 113      * @phys_addr contains the physical address in the address space
 114      * given by cpu_asidx_from_attrs(cpu, @attrs).
 115      */
 116     hwaddr phys_addr;
 117
 118     /* @attrs contains the memory transaction attributes for the page. */
 119     MemTxAttrs attrs;
 120
 121     /* @prot contains the complete protections for the page. */
 122     uint8_t prot;
 123
 124     /* @lg_page_size contains the log2 of the page size. */
 125     uint8_t lg_page_size;
 126
 127     /*
 128      * Additional tlb flags for use by the slow path. If non-zero,
 129      * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW.
 130      */
 131     uint8_t slow_flags[MMU_ACCESS_COUNT];
 132
 133     /*
 134      * Allow target-specific additions to this structure.
 135      * This may be used to cache items from the guest cpu
 136      * page tables for later use by the implementation.
 137      */
 138 #ifdef TARGET_PAGE_ENTRY_EXTRA
 139     TARGET_PAGE_ENTRY_EXTRA
 140 #endif
 141 } CPUTLBEntryFull;
 142 #endif /* CONFIG_SOFTMMU */
 143
 144 #if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG)
 145 /*
 146  * Data elements that are per MMU mode, minus the bits accessed by
 147  * the TCG fast path.
 148  */
 149 typedef struct CPUTLBDesc {
 150     /*
 151      * Describe a region covering all of the large pages allocated
 152      * into the tlb.  When any page within this region is flushed,
 153      * we must flush the entire tlb.  The region is matched if
 154      * (addr & large_page_mask) == large_page_addr.
 155      */
 156     vaddr large_page_addr;
 157     vaddr large_page_mask;
 158     /* host time (in ns) at the beginning of the time window */
 159     int64_t window_begin_ns;
 160     /* maximum number of entries observed in the window */
 161     size_t window_max_entries;
 162     size_t n_used_entries;
 163     /* The next index to use in the tlb victim table.  */
 164     size_t vindex;
 165     /* The tlb victim table, in two parts.  */
 166     CPUTLBEntry vtable[CPU_VTLB_SIZE];
 167     CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE];
 168     CPUTLBEntryFull *fulltlb;
 169 } CPUTLBDesc;
 170
 171 /*
 172  * Data elements that are shared between all MMU modes.
 173  */
 174 typedef struct CPUTLBCommon {
 175     /* Serialize updates to f.table and d.vtable, and others as noted. */
 176     QemuSpin lock;
 177     /*
 178      * Within dirty, for each bit N, modifications have been made to
 179      * mmu_idx N since the last time that mmu_idx was flushed.
 180      * Protected by tlb_c.lock.
 181      */
 182     uint16_t dirty;
 183     /*
 184      * Statistics.  These are not lock protected, but are read and
 185      * written atomically.  This allows the monitor to print a snapshot
 186      * of the stats without interfering with the cpu.
 187      */
 188     size_t full_flush_count;
 189     size_t part_flush_count;
 190     size_t elide_flush_count;
 191 } CPUTLBCommon;
 192
 193 /*
 194  * The entire softmmu tlb, for all MMU modes.
 195  * The meaning of each of the MMU modes is defined in the target code.
 196  * Since this is placed within CPUNegativeOffsetState, the smallest
 197  * negative offsets are at the end of the struct.
 198  */
 199
 200 typedef struct CPUTLB {
 201     CPUTLBCommon c;
 202     CPUTLBDesc d[NB_MMU_MODES];
 203     CPUTLBDescFast f[NB_MMU_MODES];
 204 } CPUTLB;
 205
 206 #else
 207
 208 typedef struct CPUTLB { } CPUTLB;
 209
 210 #endif /* CONFIG_SOFTMMU && CONFIG_TCG */
 211
 212 /*
 213  * This structure must be placed in ArchCPU immediately
 214  * before CPUArchState, as a field named "neg".
 215  */
 216 typedef struct CPUNegativeOffsetState {
 217     CPUTLB tlb;
 218     IcountDecr icount_decr;
 219 } CPUNegativeOffsetState;
 220
 221 #endif