target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include <linux/kvm_para.h>
  22
  23 #include "qemu-common.h"
  24 #include "sysemu.h"
  25 #include "kvm.h"
  26 #include "kvm_i386.h"
  27 #include "cpu.h"
  28 #include "gdbstub.h"
  29 #include "host-utils.h"
  30 #include "hw/pc.h"
  31 #include "hw/apic.h"
  32 #include "ioport.h"
  33 #include "hyperv.h"
  34 #include "hw/pci.h"
  35
  36 //#define DEBUG_KVM
  37
  38 #ifdef DEBUG_KVM
  39 #define DPRINTF(fmt, ...) \
  40     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  41 #else
  42 #define DPRINTF(fmt, ...) \
  43     do { } while (0)
  44 #endif
  45
  46 #define MSR_KVM_WALL_CLOCK  0x11
  47 #define MSR_KVM_SYSTEM_TIME 0x12
  48
  49 #ifndef BUS_MCEERR_AR
  50 #define BUS_MCEERR_AR 4
  51 #endif
  52 #ifndef BUS_MCEERR_AO
  53 #define BUS_MCEERR_AO 5
  54 #endif
  55
  56 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  57     KVM_CAP_INFO(SET_TSS_ADDR),
  58     KVM_CAP_INFO(EXT_CPUID),
  59     KVM_CAP_INFO(MP_STATE),
  60     KVM_CAP_LAST_INFO
  61 };
  62
  63 static bool has_msr_star;
  64 static bool has_msr_hsave_pa;
  65 static bool has_msr_tsc_deadline;
  66 static bool has_msr_async_pf_en;
  67 static bool has_msr_pv_eoi_en;
  68 static bool has_msr_misc_enable;
  69 static int lm_capable_kernel;
  70
  71 bool kvm_allows_irq0_override(void)
  72 {
  73     return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
  74 }
  75
  76 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  77 {
  78     struct kvm_cpuid2 *cpuid;
  79     int r, size;
  80
  81     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  82     cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
  83     cpuid->nent = max;
  84     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  85     if (r == 0 && cpuid->nent >= max) {
  86         r = -E2BIG;
  87     }
  88     if (r < 0) {
  89         if (r == -E2BIG) {
  90             g_free(cpuid);
  91             return NULL;
  92         } else {
  93             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  94                     strerror(-r));
  95             exit(1);
  96         }
  97     }
  98     return cpuid;
  99 }
 100
 101 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
 102  * for all entries.
 103  */
 104 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
 105 {
 106     struct kvm_cpuid2 *cpuid;
 107     int max = 1;
 108     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 109         max *= 2;
 110     }
 111     return cpuid;
 112 }
 113
 114 struct kvm_para_features {
 115     int cap;
 116     int feature;
 117 } para_features[] = {
 118     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 119     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 120     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 121     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 122     { -1, -1 }
 123 };
 124
 125 static int get_para_features(KVMState *s)
 126 {
 127     int i, features = 0;
 128
 129     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 130         if (kvm_check_extension(s, para_features[i].cap)) {
 131             features |= (1 << para_features[i].feature);
 132         }
 133     }
 134
 135     return features;
 136 }
 137
 138
 139 /* Returns the value for a specific register on the cpuid entry
 140  */
 141 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
 142 {
 143     uint32_t ret = 0;
 144     switch (reg) {
 145     case R_EAX:
 146         ret = entry->eax;
 147         break;
 148     case R_EBX:
 149         ret = entry->ebx;
 150         break;
 151     case R_ECX:
 152         ret = entry->ecx;
 153         break;
 154     case R_EDX:
 155         ret = entry->edx;
 156         break;
 157     }
 158     return ret;
 159 }
 160
 161 /* Find matching entry for function/index on kvm_cpuid2 struct
 162  */
 163 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
 164                                                  uint32_t function,
 165                                                  uint32_t index)
 166 {
 167     int i;
 168     for (i = 0; i < cpuid->nent; ++i) {
 169         if (cpuid->entries[i].function == function &&
 170             cpuid->entries[i].index == index) {
 171             return &cpuid->entries[i];
 172         }
 173     }
 174     /* not found: */
 175     return NULL;
 176 }
 177
 178 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 179                                       uint32_t index, int reg)
 180 {
 181     struct kvm_cpuid2 *cpuid;
 182     uint32_t ret = 0;
 183     uint32_t cpuid_1_edx;
 184     bool found = false;
 185
 186     cpuid = get_supported_cpuid(s);
 187
 188     struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
 189     if (entry) {
 190         found = true;
 191         ret = cpuid_entry_get_reg(entry, reg);
 192     }
 193
 194     /* Fixups for the data returned by KVM, below */
 195
 196     if (function == 1 && reg == R_EDX) {
 197         /* KVM before 2.6.30 misreports the following features */
 198         ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 199     } else if (function == 1 && reg == R_ECX) {
 200         /* We can set the hypervisor flag, even if KVM does not return it on
 201          * GET_SUPPORTED_CPUID
 202          */
 203         ret |= CPUID_EXT_HYPERVISOR;
 204         /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
 205          * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
 206          * and the irqchip is in the kernel.
 207          */
 208         if (kvm_irqchip_in_kernel() &&
 209                 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
 210             ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
 211         }
 212
 213         /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
 214          * without the in-kernel irqchip
 215          */
 216         if (!kvm_irqchip_in_kernel()) {
 217             ret &= ~CPUID_EXT_X2APIC;
 218         }
 219     } else if (function == 0x80000001 && reg == R_EDX) {
 220         /* On Intel, kvm returns cpuid according to the Intel spec,
 221          * so add missing bits according to the AMD spec:
 222          */
 223         cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 224         ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
 225     }
 226
 227     g_free(cpuid);
 228
 229     /* fallback for older kernels */
 230     if ((function == KVM_CPUID_FEATURES) && !found) {
 231         ret = get_para_features(s);
 232     }
 233
 234     return ret;
 235 }
 236
 237 typedef struct HWPoisonPage {
 238     ram_addr_t ram_addr;
 239     QLIST_ENTRY(HWPoisonPage) list;
 240 } HWPoisonPage;
 241
 242 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 243     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 244
 245 static void kvm_unpoison_all(void *param)
 246 {
 247     HWPoisonPage *page, *next_page;
 248
 249     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 250         QLIST_REMOVE(page, list);
 251         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 252         g_free(page);
 253     }
 254 }
 255
 256 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 257 {
 258     HWPoisonPage *page;
 259
 260     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 261         if (page->ram_addr == ram_addr) {
 262             return;
 263         }
 264     }
 265     page = g_malloc(sizeof(HWPoisonPage));
 266     page->ram_addr = ram_addr;
 267     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 268 }
 269
 270 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 271                                      int *max_banks)
 272 {
 273     int r;
 274
 275     r = kvm_check_extension(s, KVM_CAP_MCE);
 276     if (r > 0) {
 277         *max_banks = r;
 278         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 279     }
 280     return -ENOSYS;
 281 }
 282
 283 static void kvm_mce_inject(CPUX86State *env, hwaddr paddr, int code)
 284 {
 285     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 286                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 287     uint64_t mcg_status = MCG_STATUS_MCIP;
 288
 289     if (code == BUS_MCEERR_AR) {
 290         status |= MCI_STATUS_AR | 0x134;
 291         mcg_status |= MCG_STATUS_EIPV;
 292     } else {
 293         status |= 0xc0;
 294         mcg_status |= MCG_STATUS_RIPV;
 295     }
 296     cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr,
 297                        (MCM_ADDR_PHYS << 6) | 0xc,
 298                        cpu_x86_support_mca_broadcast(env) ?
 299                        MCE_INJECT_BROADCAST : 0);
 300 }
 301
 302 static void hardware_memory_error(void)
 303 {
 304     fprintf(stderr, "Hardware memory error!\n");
 305     exit(1);
 306 }
 307
 308 int kvm_arch_on_sigbus_vcpu(CPUX86State *env, int code, void *addr)
 309 {
 310     ram_addr_t ram_addr;
 311     hwaddr paddr;
 312
 313     if ((env->mcg_cap & MCG_SER_P) && addr
 314         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 315         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 316             !kvm_physical_memory_addr_from_host(env->kvm_state, addr, &paddr)) {
 317             fprintf(stderr, "Hardware memory error for memory used by "
 318                     "QEMU itself instead of guest system!\n");
 319             /* Hope we are lucky for AO MCE */
 320             if (code == BUS_MCEERR_AO) {
 321                 return 0;
 322             } else {
 323                 hardware_memory_error();
 324             }
 325         }
 326         kvm_hwpoison_page_add(ram_addr);
 327         kvm_mce_inject(env, paddr, code);
 328     } else {
 329         if (code == BUS_MCEERR_AO) {
 330             return 0;
 331         } else if (code == BUS_MCEERR_AR) {
 332             hardware_memory_error();
 333         } else {
 334             return 1;
 335         }
 336     }
 337     return 0;
 338 }
 339
 340 int kvm_arch_on_sigbus(int code, void *addr)
 341 {
 342     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 343         ram_addr_t ram_addr;
 344         hwaddr paddr;
 345
 346         /* Hope we are lucky for AO MCE */
 347         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 348             !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, addr,
 349                                                 &paddr)) {
 350             fprintf(stderr, "Hardware memory error for memory used by "
 351                     "QEMU itself instead of guest system!: %p\n", addr);
 352             return 0;
 353         }
 354         kvm_hwpoison_page_add(ram_addr);
 355         kvm_mce_inject(first_cpu, paddr, code);
 356     } else {
 357         if (code == BUS_MCEERR_AO) {
 358             return 0;
 359         } else if (code == BUS_MCEERR_AR) {
 360             hardware_memory_error();
 361         } else {
 362             return 1;
 363         }
 364     }
 365     return 0;
 366 }
 367
 368 static int kvm_inject_mce_oldstyle(CPUX86State *env)
 369 {
 370     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 371         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 372         struct kvm_x86_mce mce;
 373
 374         env->exception_injected = -1;
 375
 376         /*
 377          * There must be at least one bank in use if an MCE is pending.
 378          * Find it and use its values for the event injection.
 379          */
 380         for (bank = 0; bank < bank_num; bank++) {
 381             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 382                 break;
 383             }
 384         }
 385         assert(bank < bank_num);
 386
 387         mce.bank = bank;
 388         mce.status = env->mce_banks[bank * 4 + 1];
 389         mce.mcg_status = env->mcg_status;
 390         mce.addr = env->mce_banks[bank * 4 + 2];
 391         mce.misc = env->mce_banks[bank * 4 + 3];
 392
 393         return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
 394     }
 395     return 0;
 396 }
 397
 398 static void cpu_update_state(void *opaque, int running, RunState state)
 399 {
 400     CPUX86State *env = opaque;
 401
 402     if (running) {
 403         env->tsc_valid = false;
 404     }
 405 }
 406
 407 int kvm_arch_init_vcpu(CPUX86State *env)
 408 {
 409     struct {
 410         struct kvm_cpuid2 cpuid;
 411         struct kvm_cpuid_entry2 entries[100];
 412     } QEMU_PACKED cpuid_data;
 413     uint32_t limit, i, j, cpuid_i;
 414     uint32_t unused;
 415     struct kvm_cpuid_entry2 *c;
 416     uint32_t signature[3];
 417     int r;
 418
 419     cpuid_i = 0;
 420
 421     /* Paravirtualization CPUIDs */
 422     c = &cpuid_data.entries[cpuid_i++];
 423     memset(c, 0, sizeof(*c));
 424     c->function = KVM_CPUID_SIGNATURE;
 425     if (!hyperv_enabled()) {
 426         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 427         c->eax = 0;
 428     } else {
 429         memcpy(signature, "Microsoft Hv", 12);
 430         c->eax = HYPERV_CPUID_MIN;
 431     }
 432     c->ebx = signature[0];
 433     c->ecx = signature[1];
 434     c->edx = signature[2];
 435
 436     c = &cpuid_data.entries[cpuid_i++];
 437     memset(c, 0, sizeof(*c));
 438     c->function = KVM_CPUID_FEATURES;
 439     c->eax = env->cpuid_kvm_features;
 440
 441     if (hyperv_enabled()) {
 442         memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
 443         c->eax = signature[0];
 444
 445         c = &cpuid_data.entries[cpuid_i++];
 446         memset(c, 0, sizeof(*c));
 447         c->function = HYPERV_CPUID_VERSION;
 448         c->eax = 0x00001bbc;
 449         c->ebx = 0x00060001;
 450
 451         c = &cpuid_data.entries[cpuid_i++];
 452         memset(c, 0, sizeof(*c));
 453         c->function = HYPERV_CPUID_FEATURES;
 454         if (hyperv_relaxed_timing_enabled()) {
 455             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 456         }
 457         if (hyperv_vapic_recommended()) {
 458             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 459             c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
 460         }
 461
 462         c = &cpuid_data.entries[cpuid_i++];
 463         memset(c, 0, sizeof(*c));
 464         c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
 465         if (hyperv_relaxed_timing_enabled()) {
 466             c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
 467         }
 468         if (hyperv_vapic_recommended()) {
 469             c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
 470         }
 471         c->ebx = hyperv_get_spinlock_retries();
 472
 473         c = &cpuid_data.entries[cpuid_i++];
 474         memset(c, 0, sizeof(*c));
 475         c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
 476         c->eax = 0x40;
 477         c->ebx = 0x40;
 478
 479         c = &cpuid_data.entries[cpuid_i++];
 480         memset(c, 0, sizeof(*c));
 481         c->function = KVM_CPUID_SIGNATURE_NEXT;
 482         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 483         c->eax = 0;
 484         c->ebx = signature[0];
 485         c->ecx = signature[1];
 486         c->edx = signature[2];
 487     }
 488
 489     has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
 490
 491     has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
 492
 493     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 494
 495     for (i = 0; i <= limit; i++) {
 496         c = &cpuid_data.entries[cpuid_i++];
 497
 498         switch (i) {
 499         case 2: {
 500             /* Keep reading function 2 till all the input is received */
 501             int times;
 502
 503             c->function = i;
 504             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 505                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 506             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 507             times = c->eax & 0xff;
 508
 509             for (j = 1; j < times; ++j) {
 510                 c = &cpuid_data.entries[cpuid_i++];
 511                 c->function = i;
 512                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 513                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 514             }
 515             break;
 516         }
 517         case 4:
 518         case 0xb:
 519         case 0xd:
 520             for (j = 0; ; j++) {
 521                 if (i == 0xd && j == 64) {
 522                     break;
 523                 }
 524                 c->function = i;
 525                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 526                 c->index = j;
 527                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 528
 529                 if (i == 4 && c->eax == 0) {
 530                     break;
 531                 }
 532                 if (i == 0xb && !(c->ecx & 0xff00)) {
 533                     break;
 534                 }
 535                 if (i == 0xd && c->eax == 0) {
 536                     continue;
 537                 }
 538                 c = &cpuid_data.entries[cpuid_i++];
 539             }
 540             break;
 541         default:
 542             c->function = i;
 543             c->flags = 0;
 544             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 545             break;
 546         }
 547     }
 548     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 549
 550     for (i = 0x80000000; i <= limit; i++) {
 551         c = &cpuid_data.entries[cpuid_i++];
 552
 553         c->function = i;
 554         c->flags = 0;
 555         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 556     }
 557
 558     /* Call Centaur's CPUID instructions they are supported. */
 559     if (env->cpuid_xlevel2 > 0) {
 560         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
 561
 562         for (i = 0xC0000000; i <= limit; i++) {
 563             c = &cpuid_data.entries[cpuid_i++];
 564
 565             c->function = i;
 566             c->flags = 0;
 567             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 568         }
 569     }
 570
 571     cpuid_data.cpuid.nent = cpuid_i;
 572
 573     if (((env->cpuid_version >> 8)&0xF) >= 6
 574         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 575         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 576         uint64_t mcg_cap;
 577         int banks;
 578         int ret;
 579
 580         ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks);
 581         if (ret < 0) {
 582             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 583             return ret;
 584         }
 585
 586         if (banks > MCE_BANKS_DEF) {
 587             banks = MCE_BANKS_DEF;
 588         }
 589         mcg_cap &= MCE_CAP_DEF;
 590         mcg_cap |= banks;
 591         ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap);
 592         if (ret < 0) {
 593             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 594             return ret;
 595         }
 596
 597         env->mcg_cap = mcg_cap;
 598     }
 599
 600     qemu_add_vm_change_state_handler(cpu_update_state, env);
 601
 602     cpuid_data.cpuid.padding = 0;
 603     r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 604     if (r) {
 605         return r;
 606     }
 607
 608     r = kvm_check_extension(env->kvm_state, KVM_CAP_TSC_CONTROL);
 609     if (r && env->tsc_khz) {
 610         r = kvm_vcpu_ioctl(env, KVM_SET_TSC_KHZ, env->tsc_khz);
 611         if (r < 0) {
 612             fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
 613             return r;
 614         }
 615     }
 616
 617     if (kvm_has_xsave()) {
 618         env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
 619     }
 620
 621     return 0;
 622 }
 623
 624 void kvm_arch_reset_vcpu(CPUX86State *env)
 625 {
 626     X86CPU *cpu = x86_env_get_cpu(env);
 627
 628     env->exception_injected = -1;
 629     env->interrupt_injected = -1;
 630     env->xcr0 = 1;
 631     if (kvm_irqchip_in_kernel()) {
 632         env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
 633                                           KVM_MP_STATE_UNINITIALIZED;
 634     } else {
 635         env->mp_state = KVM_MP_STATE_RUNNABLE;
 636     }
 637 }
 638
 639 static int kvm_get_supported_msrs(KVMState *s)
 640 {
 641     static int kvm_supported_msrs;
 642     int ret = 0;
 643
 644     /* first time */
 645     if (kvm_supported_msrs == 0) {
 646         struct kvm_msr_list msr_list, *kvm_msr_list;
 647
 648         kvm_supported_msrs = -1;
 649
 650         /* Obtain MSR list from KVM.  These are the MSRs that we must
 651          * save/restore */
 652         msr_list.nmsrs = 0;
 653         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 654         if (ret < 0 && ret != -E2BIG) {
 655             return ret;
 656         }
 657         /* Old kernel modules had a bug and could write beyond the provided
 658            memory. Allocate at least a safe amount of 1K. */
 659         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
 660                                               msr_list.nmsrs *
 661                                               sizeof(msr_list.indices[0])));
 662
 663         kvm_msr_list->nmsrs = msr_list.nmsrs;
 664         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 665         if (ret >= 0) {
 666             int i;
 667
 668             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 669                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 670                     has_msr_star = true;
 671                     continue;
 672                 }
 673                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 674                     has_msr_hsave_pa = true;
 675                     continue;
 676                 }
 677                 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
 678                     has_msr_tsc_deadline = true;
 679                     continue;
 680                 }
 681                 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
 682                     has_msr_misc_enable = true;
 683                     continue;
 684                 }
 685             }
 686         }
 687
 688         g_free(kvm_msr_list);
 689     }
 690
 691     return ret;
 692 }
 693
 694 int kvm_arch_init(KVMState *s)
 695 {
 696     QemuOptsList *list = qemu_find_opts("machine");
 697     uint64_t identity_base = 0xfffbc000;
 698     uint64_t shadow_mem;
 699     int ret;
 700     struct utsname utsname;
 701
 702     ret = kvm_get_supported_msrs(s);
 703     if (ret < 0) {
 704         return ret;
 705     }
 706
 707     uname(&utsname);
 708     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 709
 710     /*
 711      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 712      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 713      * Since these must be part of guest physical memory, we need to allocate
 714      * them, both by setting their start addresses in the kernel and by
 715      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 716      *
 717      * Older KVM versions may not support setting the identity map base. In
 718      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 719      * size.
 720      */
 721     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 722         /* Allows up to 16M BIOSes. */
 723         identity_base = 0xfeffc000;
 724
 725         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 726         if (ret < 0) {
 727             return ret;
 728         }
 729     }
 730
 731     /* Set TSS base one page after EPT identity map. */
 732     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 733     if (ret < 0) {
 734         return ret;
 735     }
 736
 737     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 738     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 739     if (ret < 0) {
 740         fprintf(stderr, "e820_add_entry() table is full\n");
 741         return ret;
 742     }
 743     qemu_register_reset(kvm_unpoison_all, NULL);
 744
 745     if (!QTAILQ_EMPTY(&list->head)) {
 746         shadow_mem = qemu_opt_get_size(QTAILQ_FIRST(&list->head),
 747                                        "kvm_shadow_mem", -1);
 748         if (shadow_mem != -1) {
 749             shadow_mem /= 4096;
 750             ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
 751             if (ret < 0) {
 752                 return ret;
 753             }
 754         }
 755     }
 756     return 0;
 757 }
 758
 759 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 760 {
 761     lhs->selector = rhs->selector;
 762     lhs->base = rhs->base;
 763     lhs->limit = rhs->limit;
 764     lhs->type = 3;
 765     lhs->present = 1;
 766     lhs->dpl = 3;
 767     lhs->db = 0;
 768     lhs->s = 1;
 769     lhs->l = 0;
 770     lhs->g = 0;
 771     lhs->avl = 0;
 772     lhs->unusable = 0;
 773 }
 774
 775 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 776 {
 777     unsigned flags = rhs->flags;
 778     lhs->selector = rhs->selector;
 779     lhs->base = rhs->base;
 780     lhs->limit = rhs->limit;
 781     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 782     lhs->present = (flags & DESC_P_MASK) != 0;
 783     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 784     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 785     lhs->s = (flags & DESC_S_MASK) != 0;
 786     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 787     lhs->g = (flags & DESC_G_MASK) != 0;
 788     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 789     lhs->unusable = 0;
 790     lhs->padding = 0;
 791 }
 792
 793 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 794 {
 795     lhs->selector = rhs->selector;
 796     lhs->base = rhs->base;
 797     lhs->limit = rhs->limit;
 798     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 799                  (rhs->present * DESC_P_MASK) |
 800                  (rhs->dpl << DESC_DPL_SHIFT) |
 801                  (rhs->db << DESC_B_SHIFT) |
 802                  (rhs->s * DESC_S_MASK) |
 803                  (rhs->l << DESC_L_SHIFT) |
 804                  (rhs->g * DESC_G_MASK) |
 805                  (rhs->avl * DESC_AVL_MASK);
 806 }
 807
 808 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 809 {
 810     if (set) {
 811         *kvm_reg = *qemu_reg;
 812     } else {
 813         *qemu_reg = *kvm_reg;
 814     }
 815 }
 816
 817 static int kvm_getput_regs(CPUX86State *env, int set)
 818 {
 819     struct kvm_regs regs;
 820     int ret = 0;
 821
 822     if (!set) {
 823         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 824         if (ret < 0) {
 825             return ret;
 826         }
 827     }
 828
 829     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 830     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 831     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 832     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 833     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 834     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 835     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 836     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 837 #ifdef TARGET_X86_64
 838     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 839     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 840     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 841     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 842     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 843     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 844     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 845     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 846 #endif
 847
 848     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 849     kvm_getput_reg(&regs.rip, &env->eip, set);
 850
 851     if (set) {
 852         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 853     }
 854
 855     return ret;
 856 }
 857
 858 static int kvm_put_fpu(CPUX86State *env)
 859 {
 860     struct kvm_fpu fpu;
 861     int i;
 862
 863     memset(&fpu, 0, sizeof fpu);
 864     fpu.fsw = env->fpus & ~(7 << 11);
 865     fpu.fsw |= (env->fpstt & 7) << 11;
 866     fpu.fcw = env->fpuc;
 867     fpu.last_opcode = env->fpop;
 868     fpu.last_ip = env->fpip;
 869     fpu.last_dp = env->fpdp;
 870     for (i = 0; i < 8; ++i) {
 871         fpu.ftwx |= (!env->fptags[i]) << i;
 872     }
 873     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 874     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 875     fpu.mxcsr = env->mxcsr;
 876
 877     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 878 }
 879
 880 #define XSAVE_FCW_FSW     0
 881 #define XSAVE_FTW_FOP     1
 882 #define XSAVE_CWD_RIP     2
 883 #define XSAVE_CWD_RDP     4
 884 #define XSAVE_MXCSR       6
 885 #define XSAVE_ST_SPACE    8
 886 #define XSAVE_XMM_SPACE   40
 887 #define XSAVE_XSTATE_BV   128
 888 #define XSAVE_YMMH_SPACE  144
 889
 890 static int kvm_put_xsave(CPUX86State *env)
 891 {
 892     struct kvm_xsave* xsave = env->kvm_xsave_buf;
 893     uint16_t cwd, swd, twd;
 894     int i, r;
 895
 896     if (!kvm_has_xsave()) {
 897         return kvm_put_fpu(env);
 898     }
 899
 900     memset(xsave, 0, sizeof(struct kvm_xsave));
 901     twd = 0;
 902     swd = env->fpus & ~(7 << 11);
 903     swd |= (env->fpstt & 7) << 11;
 904     cwd = env->fpuc;
 905     for (i = 0; i < 8; ++i) {
 906         twd |= (!env->fptags[i]) << i;
 907     }
 908     xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
 909     xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
 910     memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
 911     memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
 912     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 913             sizeof env->fpregs);
 914     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 915             sizeof env->xmm_regs);
 916     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 917     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 918     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 919             sizeof env->ymmh_regs);
 920     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 921     return r;
 922 }
 923
 924 static int kvm_put_xcrs(CPUX86State *env)
 925 {
 926     struct kvm_xcrs xcrs;
 927
 928     if (!kvm_has_xcrs()) {
 929         return 0;
 930     }
 931
 932     xcrs.nr_xcrs = 1;
 933     xcrs.flags = 0;
 934     xcrs.xcrs[0].xcr = 0;
 935     xcrs.xcrs[0].value = env->xcr0;
 936     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 937 }
 938
 939 static int kvm_put_sregs(CPUX86State *env)
 940 {
 941     struct kvm_sregs sregs;
 942
 943     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 944     if (env->interrupt_injected >= 0) {
 945         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 946                 (uint64_t)1 << (env->interrupt_injected % 64);
 947     }
 948
 949     if ((env->eflags & VM_MASK)) {
 950         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 951         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 952         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 953         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 954         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 955         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 956     } else {
 957         set_seg(&sregs.cs, &env->segs[R_CS]);
 958         set_seg(&sregs.ds, &env->segs[R_DS]);
 959         set_seg(&sregs.es, &env->segs[R_ES]);
 960         set_seg(&sregs.fs, &env->segs[R_FS]);
 961         set_seg(&sregs.gs, &env->segs[R_GS]);
 962         set_seg(&sregs.ss, &env->segs[R_SS]);
 963     }
 964
 965     set_seg(&sregs.tr, &env->tr);
 966     set_seg(&sregs.ldt, &env->ldt);
 967
 968     sregs.idt.limit = env->idt.limit;
 969     sregs.idt.base = env->idt.base;
 970     memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
 971     sregs.gdt.limit = env->gdt.limit;
 972     sregs.gdt.base = env->gdt.base;
 973     memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
 974
 975     sregs.cr0 = env->cr[0];
 976     sregs.cr2 = env->cr[2];
 977     sregs.cr3 = env->cr[3];
 978     sregs.cr4 = env->cr[4];
 979
 980     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 981     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 982
 983     sregs.efer = env->efer;
 984
 985     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 986 }
 987
 988 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 989                               uint32_t index, uint64_t value)
 990 {
 991     entry->index = index;
 992     entry->data = value;
 993 }
 994
 995 static int kvm_put_msrs(CPUX86State *env, int level)
 996 {
 997     struct {
 998         struct kvm_msrs info;
 999         struct kvm_msr_entry entries[100];
1000     } msr_data;
1001     struct kvm_msr_entry *msrs = msr_data.entries;
1002     int n = 0;
1003
1004     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1005     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1006     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1007     kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1008     if (has_msr_star) {
1009         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1010     }
1011     if (has_msr_hsave_pa) {
1012         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1013     }
1014     if (has_msr_tsc_deadline) {
1015         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1016     }
1017     if (has_msr_misc_enable) {
1018         kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1019                           env->msr_ia32_misc_enable);
1020     }
1021 #ifdef TARGET_X86_64
1022     if (lm_capable_kernel) {
1023         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1024         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1025         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1026         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1027     }
1028 #endif
1029     if (level == KVM_PUT_FULL_STATE) {
1030         /*
1031          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
1032          * writeback. Until this is fixed, we only write the offset to SMP
1033          * guests after migration, desynchronizing the VCPUs, but avoiding
1034          * huge jump-backs that would occur without any writeback at all.
1035          */
1036         if (smp_cpus == 1 || env->tsc != 0) {
1037             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1038         }
1039     }
1040     /*
1041      * The following paravirtual MSRs have side effects on the guest or are
1042      * too heavy for normal writeback. Limit them to reset or full state
1043      * updates.
1044      */
1045     if (level >= KVM_PUT_RESET_STATE) {
1046         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1047                           env->system_time_msr);
1048         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1049         if (has_msr_async_pf_en) {
1050             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1051                               env->async_pf_en_msr);
1052         }
1053         if (has_msr_pv_eoi_en) {
1054             kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1055                               env->pv_eoi_en_msr);
1056         }
1057         if (hyperv_hypercall_available()) {
1058             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
1059             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
1060         }
1061         if (hyperv_vapic_recommended()) {
1062             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
1063         }
1064     }
1065     if (env->mcg_cap) {
1066         int i;
1067
1068         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1069         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1070         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1071             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1072         }
1073     }
1074
1075     msr_data.info.nmsrs = n;
1076
1077     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
1078
1079 }
1080
1081
1082 static int kvm_get_fpu(CPUX86State *env)
1083 {
1084     struct kvm_fpu fpu;
1085     int i, ret;
1086
1087     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
1088     if (ret < 0) {
1089         return ret;
1090     }
1091
1092     env->fpstt = (fpu.fsw >> 11) & 7;
1093     env->fpus = fpu.fsw;
1094     env->fpuc = fpu.fcw;
1095     env->fpop = fpu.last_opcode;
1096     env->fpip = fpu.last_ip;
1097     env->fpdp = fpu.last_dp;
1098     for (i = 0; i < 8; ++i) {
1099         env->fptags[i] = !((fpu.ftwx >> i) & 1);
1100     }
1101     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1102     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1103     env->mxcsr = fpu.mxcsr;
1104
1105     return 0;
1106 }
1107
1108 static int kvm_get_xsave(CPUX86State *env)
1109 {
1110     struct kvm_xsave* xsave = env->kvm_xsave_buf;
1111     int ret, i;
1112     uint16_t cwd, swd, twd;
1113
1114     if (!kvm_has_xsave()) {
1115         return kvm_get_fpu(env);
1116     }
1117
1118     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
1119     if (ret < 0) {
1120         return ret;
1121     }
1122
1123     cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1124     swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1125     twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1126     env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1127     env->fpstt = (swd >> 11) & 7;
1128     env->fpus = swd;
1129     env->fpuc = cwd;
1130     for (i = 0; i < 8; ++i) {
1131         env->fptags[i] = !((twd >> i) & 1);
1132     }
1133     memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1134     memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1135     env->mxcsr = xsave->region[XSAVE_MXCSR];
1136     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1137             sizeof env->fpregs);
1138     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1139             sizeof env->xmm_regs);
1140     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1141     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1142             sizeof env->ymmh_regs);
1143     return 0;
1144 }
1145
1146 static int kvm_get_xcrs(CPUX86State *env)
1147 {
1148     int i, ret;
1149     struct kvm_xcrs xcrs;
1150
1151     if (!kvm_has_xcrs()) {
1152         return 0;
1153     }
1154
1155     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
1156     if (ret < 0) {
1157         return ret;
1158     }
1159
1160     for (i = 0; i < xcrs.nr_xcrs; i++) {
1161         /* Only support xcr0 now */
1162         if (xcrs.xcrs[0].xcr == 0) {
1163             env->xcr0 = xcrs.xcrs[0].value;
1164             break;
1165         }
1166     }
1167     return 0;
1168 }
1169
1170 static int kvm_get_sregs(CPUX86State *env)
1171 {
1172     struct kvm_sregs sregs;
1173     uint32_t hflags;
1174     int bit, i, ret;
1175
1176     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
1177     if (ret < 0) {
1178         return ret;
1179     }
1180
1181     /* There can only be one pending IRQ set in the bitmap at a time, so try
1182        to find it and save its number instead (-1 for none). */
1183     env->interrupt_injected = -1;
1184     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1185         if (sregs.interrupt_bitmap[i]) {
1186             bit = ctz64(sregs.interrupt_bitmap[i]);
1187             env->interrupt_injected = i * 64 + bit;
1188             break;
1189         }
1190     }
1191
1192     get_seg(&env->segs[R_CS], &sregs.cs);
1193     get_seg(&env->segs[R_DS], &sregs.ds);
1194     get_seg(&env->segs[R_ES], &sregs.es);
1195     get_seg(&env->segs[R_FS], &sregs.fs);
1196     get_seg(&env->segs[R_GS], &sregs.gs);
1197     get_seg(&env->segs[R_SS], &sregs.ss);
1198
1199     get_seg(&env->tr, &sregs.tr);
1200     get_seg(&env->ldt, &sregs.ldt);
1201
1202     env->idt.limit = sregs.idt.limit;
1203     env->idt.base = sregs.idt.base;
1204     env->gdt.limit = sregs.gdt.limit;
1205     env->gdt.base = sregs.gdt.base;
1206
1207     env->cr[0] = sregs.cr0;
1208     env->cr[2] = sregs.cr2;
1209     env->cr[3] = sregs.cr3;
1210     env->cr[4] = sregs.cr4;
1211
1212     env->efer = sregs.efer;
1213
1214     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1215
1216 #define HFLAG_COPY_MASK \
1217     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1218        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1219        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1220        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1221
1222     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1223     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1224     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1225                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1226     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1227     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1228                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1229
1230     if (env->efer & MSR_EFER_LMA) {
1231         hflags |= HF_LMA_MASK;
1232     }
1233
1234     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1235         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1236     } else {
1237         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1238                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1239         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1240                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1241         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1242             !(hflags & HF_CS32_MASK)) {
1243             hflags |= HF_ADDSEG_MASK;
1244         } else {
1245             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1246                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1247         }
1248     }
1249     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1250
1251     return 0;
1252 }
1253
1254 static int kvm_get_msrs(CPUX86State *env)
1255 {
1256     struct {
1257         struct kvm_msrs info;
1258         struct kvm_msr_entry entries[100];
1259     } msr_data;
1260     struct kvm_msr_entry *msrs = msr_data.entries;
1261     int ret, i, n;
1262
1263     n = 0;
1264     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1265     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1266     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1267     msrs[n++].index = MSR_PAT;
1268     if (has_msr_star) {
1269         msrs[n++].index = MSR_STAR;
1270     }
1271     if (has_msr_hsave_pa) {
1272         msrs[n++].index = MSR_VM_HSAVE_PA;
1273     }
1274     if (has_msr_tsc_deadline) {
1275         msrs[n++].index = MSR_IA32_TSCDEADLINE;
1276     }
1277     if (has_msr_misc_enable) {
1278         msrs[n++].index = MSR_IA32_MISC_ENABLE;
1279     }
1280
1281     if (!env->tsc_valid) {
1282         msrs[n++].index = MSR_IA32_TSC;
1283         env->tsc_valid = !runstate_is_running();
1284     }
1285
1286 #ifdef TARGET_X86_64
1287     if (lm_capable_kernel) {
1288         msrs[n++].index = MSR_CSTAR;
1289         msrs[n++].index = MSR_KERNELGSBASE;
1290         msrs[n++].index = MSR_FMASK;
1291         msrs[n++].index = MSR_LSTAR;
1292     }
1293 #endif
1294     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1295     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1296     if (has_msr_async_pf_en) {
1297         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1298     }
1299     if (has_msr_pv_eoi_en) {
1300         msrs[n++].index = MSR_KVM_PV_EOI_EN;
1301     }
1302
1303     if (env->mcg_cap) {
1304         msrs[n++].index = MSR_MCG_STATUS;
1305         msrs[n++].index = MSR_MCG_CTL;
1306         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1307             msrs[n++].index = MSR_MC0_CTL + i;
1308         }
1309     }
1310
1311     msr_data.info.nmsrs = n;
1312     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1313     if (ret < 0) {
1314         return ret;
1315     }
1316
1317     for (i = 0; i < ret; i++) {
1318         switch (msrs[i].index) {
1319         case MSR_IA32_SYSENTER_CS:
1320             env->sysenter_cs = msrs[i].data;
1321             break;
1322         case MSR_IA32_SYSENTER_ESP:
1323             env->sysenter_esp = msrs[i].data;
1324             break;
1325         case MSR_IA32_SYSENTER_EIP:
1326             env->sysenter_eip = msrs[i].data;
1327             break;
1328         case MSR_PAT:
1329             env->pat = msrs[i].data;
1330             break;
1331         case MSR_STAR:
1332             env->star = msrs[i].data;
1333             break;
1334 #ifdef TARGET_X86_64
1335         case MSR_CSTAR:
1336             env->cstar = msrs[i].data;
1337             break;
1338         case MSR_KERNELGSBASE:
1339             env->kernelgsbase = msrs[i].data;
1340             break;
1341         case MSR_FMASK:
1342             env->fmask = msrs[i].data;
1343             break;
1344         case MSR_LSTAR:
1345             env->lstar = msrs[i].data;
1346             break;
1347 #endif
1348         case MSR_IA32_TSC:
1349             env->tsc = msrs[i].data;
1350             break;
1351         case MSR_IA32_TSCDEADLINE:
1352             env->tsc_deadline = msrs[i].data;
1353             break;
1354         case MSR_VM_HSAVE_PA:
1355             env->vm_hsave = msrs[i].data;
1356             break;
1357         case MSR_KVM_SYSTEM_TIME:
1358             env->system_time_msr = msrs[i].data;
1359             break;
1360         case MSR_KVM_WALL_CLOCK:
1361             env->wall_clock_msr = msrs[i].data;
1362             break;
1363         case MSR_MCG_STATUS:
1364             env->mcg_status = msrs[i].data;
1365             break;
1366         case MSR_MCG_CTL:
1367             env->mcg_ctl = msrs[i].data;
1368             break;
1369         case MSR_IA32_MISC_ENABLE:
1370             env->msr_ia32_misc_enable = msrs[i].data;
1371             break;
1372         default:
1373             if (msrs[i].index >= MSR_MC0_CTL &&
1374                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1375                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1376             }
1377             break;
1378         case MSR_KVM_ASYNC_PF_EN:
1379             env->async_pf_en_msr = msrs[i].data;
1380             break;
1381         case MSR_KVM_PV_EOI_EN:
1382             env->pv_eoi_en_msr = msrs[i].data;
1383             break;
1384         }
1385     }
1386
1387     return 0;
1388 }
1389
1390 static int kvm_put_mp_state(CPUX86State *env)
1391 {
1392     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1393
1394     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1395 }
1396
1397 static int kvm_get_mp_state(CPUX86State *env)
1398 {
1399     struct kvm_mp_state mp_state;
1400     int ret;
1401
1402     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1403     if (ret < 0) {
1404         return ret;
1405     }
1406     env->mp_state = mp_state.mp_state;
1407     if (kvm_irqchip_in_kernel()) {
1408         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1409     }
1410     return 0;
1411 }
1412
1413 static int kvm_get_apic(CPUX86State *env)
1414 {
1415     DeviceState *apic = env->apic_state;
1416     struct kvm_lapic_state kapic;
1417     int ret;
1418
1419     if (apic && kvm_irqchip_in_kernel()) {
1420         ret = kvm_vcpu_ioctl(env, KVM_GET_LAPIC, &kapic);
1421         if (ret < 0) {
1422             return ret;
1423         }
1424
1425         kvm_get_apic_state(apic, &kapic);
1426     }
1427     return 0;
1428 }
1429
1430 static int kvm_put_apic(CPUX86State *env)
1431 {
1432     DeviceState *apic = env->apic_state;
1433     struct kvm_lapic_state kapic;
1434
1435     if (apic && kvm_irqchip_in_kernel()) {
1436         kvm_put_apic_state(apic, &kapic);
1437
1438         return kvm_vcpu_ioctl(env, KVM_SET_LAPIC, &kapic);
1439     }
1440     return 0;
1441 }
1442
1443 static int kvm_put_vcpu_events(CPUX86State *env, int level)
1444 {
1445     struct kvm_vcpu_events events;
1446
1447     if (!kvm_has_vcpu_events()) {
1448         return 0;
1449     }
1450
1451     events.exception.injected = (env->exception_injected >= 0);
1452     events.exception.nr = env->exception_injected;
1453     events.exception.has_error_code = env->has_error_code;
1454     events.exception.error_code = env->error_code;
1455     events.exception.pad = 0;
1456
1457     events.interrupt.injected = (env->interrupt_injected >= 0);
1458     events.interrupt.nr = env->interrupt_injected;
1459     events.interrupt.soft = env->soft_interrupt;
1460
1461     events.nmi.injected = env->nmi_injected;
1462     events.nmi.pending = env->nmi_pending;
1463     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1464     events.nmi.pad = 0;
1465
1466     events.sipi_vector = env->sipi_vector;
1467
1468     events.flags = 0;
1469     if (level >= KVM_PUT_RESET_STATE) {
1470         events.flags |=
1471             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1472     }
1473
1474     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1475 }
1476
1477 static int kvm_get_vcpu_events(CPUX86State *env)
1478 {
1479     struct kvm_vcpu_events events;
1480     int ret;
1481
1482     if (!kvm_has_vcpu_events()) {
1483         return 0;
1484     }
1485
1486     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1487     if (ret < 0) {
1488        return ret;
1489     }
1490     env->exception_injected =
1491        events.exception.injected ? events.exception.nr : -1;
1492     env->has_error_code = events.exception.has_error_code;
1493     env->error_code = events.exception.error_code;
1494
1495     env->interrupt_injected =
1496         events.interrupt.injected ? events.interrupt.nr : -1;
1497     env->soft_interrupt = events.interrupt.soft;
1498
1499     env->nmi_injected = events.nmi.injected;
1500     env->nmi_pending = events.nmi.pending;
1501     if (events.nmi.masked) {
1502         env->hflags2 |= HF2_NMI_MASK;
1503     } else {
1504         env->hflags2 &= ~HF2_NMI_MASK;
1505     }
1506
1507     env->sipi_vector = events.sipi_vector;
1508
1509     return 0;
1510 }
1511
1512 static int kvm_guest_debug_workarounds(CPUX86State *env)
1513 {
1514     int ret = 0;
1515     unsigned long reinject_trap = 0;
1516
1517     if (!kvm_has_vcpu_events()) {
1518         if (env->exception_injected == 1) {
1519             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1520         } else if (env->exception_injected == 3) {
1521             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1522         }
1523         env->exception_injected = -1;
1524     }
1525
1526     /*
1527      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1528      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1529      * by updating the debug state once again if single-stepping is on.
1530      * Another reason to call kvm_update_guest_debug here is a pending debug
1531      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1532      * reinject them via SET_GUEST_DEBUG.
1533      */
1534     if (reinject_trap ||
1535         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1536         ret = kvm_update_guest_debug(env, reinject_trap);
1537     }
1538     return ret;
1539 }
1540
1541 static int kvm_put_debugregs(CPUX86State *env)
1542 {
1543     struct kvm_debugregs dbgregs;
1544     int i;
1545
1546     if (!kvm_has_debugregs()) {
1547         return 0;
1548     }
1549
1550     for (i = 0; i < 4; i++) {
1551         dbgregs.db[i] = env->dr[i];
1552     }
1553     dbgregs.dr6 = env->dr[6];
1554     dbgregs.dr7 = env->dr[7];
1555     dbgregs.flags = 0;
1556
1557     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1558 }
1559
1560 static int kvm_get_debugregs(CPUX86State *env)
1561 {
1562     struct kvm_debugregs dbgregs;
1563     int i, ret;
1564
1565     if (!kvm_has_debugregs()) {
1566         return 0;
1567     }
1568
1569     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1570     if (ret < 0) {
1571         return ret;
1572     }
1573     for (i = 0; i < 4; i++) {
1574         env->dr[i] = dbgregs.db[i];
1575     }
1576     env->dr[4] = env->dr[6] = dbgregs.dr6;
1577     env->dr[5] = env->dr[7] = dbgregs.dr7;
1578
1579     return 0;
1580 }
1581
1582 int kvm_arch_put_registers(CPUX86State *env, int level)
1583 {
1584     int ret;
1585
1586     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1587
1588     ret = kvm_getput_regs(env, 1);
1589     if (ret < 0) {
1590         return ret;
1591     }
1592     ret = kvm_put_xsave(env);
1593     if (ret < 0) {
1594         return ret;
1595     }
1596     ret = kvm_put_xcrs(env);
1597     if (ret < 0) {
1598         return ret;
1599     }
1600     ret = kvm_put_sregs(env);
1601     if (ret < 0) {
1602         return ret;
1603     }
1604     /* must be before kvm_put_msrs */
1605     ret = kvm_inject_mce_oldstyle(env);
1606     if (ret < 0) {
1607         return ret;
1608     }
1609     ret = kvm_put_msrs(env, level);
1610     if (ret < 0) {
1611         return ret;
1612     }
1613     if (level >= KVM_PUT_RESET_STATE) {
1614         ret = kvm_put_mp_state(env);
1615         if (ret < 0) {
1616             return ret;
1617         }
1618         ret = kvm_put_apic(env);
1619         if (ret < 0) {
1620             return ret;
1621         }
1622     }
1623     ret = kvm_put_vcpu_events(env, level);
1624     if (ret < 0) {
1625         return ret;
1626     }
1627     ret = kvm_put_debugregs(env);
1628     if (ret < 0) {
1629         return ret;
1630     }
1631     /* must be last */
1632     ret = kvm_guest_debug_workarounds(env);
1633     if (ret < 0) {
1634         return ret;
1635     }
1636     return 0;
1637 }
1638
1639 int kvm_arch_get_registers(CPUX86State *env)
1640 {
1641     int ret;
1642
1643     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1644
1645     ret = kvm_getput_regs(env, 0);
1646     if (ret < 0) {
1647         return ret;
1648     }
1649     ret = kvm_get_xsave(env);
1650     if (ret < 0) {
1651         return ret;
1652     }
1653     ret = kvm_get_xcrs(env);
1654     if (ret < 0) {
1655         return ret;
1656     }
1657     ret = kvm_get_sregs(env);
1658     if (ret < 0) {
1659         return ret;
1660     }
1661     ret = kvm_get_msrs(env);
1662     if (ret < 0) {
1663         return ret;
1664     }
1665     ret = kvm_get_mp_state(env);
1666     if (ret < 0) {
1667         return ret;
1668     }
1669     ret = kvm_get_apic(env);
1670     if (ret < 0) {
1671         return ret;
1672     }
1673     ret = kvm_get_vcpu_events(env);
1674     if (ret < 0) {
1675         return ret;
1676     }
1677     ret = kvm_get_debugregs(env);
1678     if (ret < 0) {
1679         return ret;
1680     }
1681     return 0;
1682 }
1683
1684 void kvm_arch_pre_run(CPUX86State *env, struct kvm_run *run)
1685 {
1686     int ret;
1687
1688     /* Inject NMI */
1689     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1690         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1691         DPRINTF("injected NMI\n");
1692         ret = kvm_vcpu_ioctl(env, KVM_NMI);
1693         if (ret < 0) {
1694             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1695                     strerror(-ret));
1696         }
1697     }
1698
1699     if (!kvm_irqchip_in_kernel()) {
1700         /* Force the VCPU out of its inner loop to process any INIT requests
1701          * or pending TPR access reports. */
1702         if (env->interrupt_request &
1703             (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
1704             env->exit_request = 1;
1705         }
1706
1707         /* Try to inject an interrupt if the guest can accept it */
1708         if (run->ready_for_interrupt_injection &&
1709             (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1710             (env->eflags & IF_MASK)) {
1711             int irq;
1712
1713             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1714             irq = cpu_get_pic_interrupt(env);
1715             if (irq >= 0) {
1716                 struct kvm_interrupt intr;
1717
1718                 intr.irq = irq;
1719                 DPRINTF("injected interrupt %d\n", irq);
1720                 ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1721                 if (ret < 0) {
1722                     fprintf(stderr,
1723                             "KVM: injection failed, interrupt lost (%s)\n",
1724                             strerror(-ret));
1725                 }
1726             }
1727         }
1728
1729         /* If we have an interrupt but the guest is not ready to receive an
1730          * interrupt, request an interrupt window exit.  This will
1731          * cause a return to userspace as soon as the guest is ready to
1732          * receive interrupts. */
1733         if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1734             run->request_interrupt_window = 1;
1735         } else {
1736             run->request_interrupt_window = 0;
1737         }
1738
1739         DPRINTF("setting tpr\n");
1740         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1741     }
1742 }
1743
1744 void kvm_arch_post_run(CPUX86State *env, struct kvm_run *run)
1745 {
1746     if (run->if_flag) {
1747         env->eflags |= IF_MASK;
1748     } else {
1749         env->eflags &= ~IF_MASK;
1750     }
1751     cpu_set_apic_tpr(env->apic_state, run->cr8);
1752     cpu_set_apic_base(env->apic_state, run->apic_base);
1753 }
1754
1755 int kvm_arch_process_async_events(CPUX86State *env)
1756 {
1757     X86CPU *cpu = x86_env_get_cpu(env);
1758
1759     if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1760         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1761         assert(env->mcg_cap);
1762
1763         env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1764
1765         kvm_cpu_synchronize_state(env);
1766
1767         if (env->exception_injected == EXCP08_DBLE) {
1768             /* this means triple fault */
1769             qemu_system_reset_request();
1770             env->exit_request = 1;
1771             return 0;
1772         }
1773         env->exception_injected = EXCP12_MCHK;
1774         env->has_error_code = 0;
1775
1776         env->halted = 0;
1777         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1778             env->mp_state = KVM_MP_STATE_RUNNABLE;
1779         }
1780     }
1781
1782     if (kvm_irqchip_in_kernel()) {
1783         return 0;
1784     }
1785
1786     if (env->interrupt_request & CPU_INTERRUPT_POLL) {
1787         env->interrupt_request &= ~CPU_INTERRUPT_POLL;
1788         apic_poll_irq(env->apic_state);
1789     }
1790     if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1791          (env->eflags & IF_MASK)) ||
1792         (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1793         env->halted = 0;
1794     }
1795     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1796         kvm_cpu_synchronize_state(env);
1797         do_cpu_init(cpu);
1798     }
1799     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1800         kvm_cpu_synchronize_state(env);
1801         do_cpu_sipi(cpu);
1802     }
1803     if (env->interrupt_request & CPU_INTERRUPT_TPR) {
1804         env->interrupt_request &= ~CPU_INTERRUPT_TPR;
1805         kvm_cpu_synchronize_state(env);
1806         apic_handle_tpr_access_report(env->apic_state, env->eip,
1807                                       env->tpr_access_type);
1808     }
1809
1810     return env->halted;
1811 }
1812
1813 static int kvm_handle_halt(CPUX86State *env)
1814 {
1815     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1816           (env->eflags & IF_MASK)) &&
1817         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1818         env->halted = 1;
1819         return EXCP_HLT;
1820     }
1821
1822     return 0;
1823 }
1824
1825 static int kvm_handle_tpr_access(CPUX86State *env)
1826 {
1827     struct kvm_run *run = env->kvm_run;
1828
1829     apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip,
1830                                   run->tpr_access.is_write ? TPR_ACCESS_WRITE
1831                                                            : TPR_ACCESS_READ);
1832     return 1;
1833 }
1834
1835 int kvm_arch_insert_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1836 {
1837     static const uint8_t int3 = 0xcc;
1838
1839     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1840         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1841         return -EINVAL;
1842     }
1843     return 0;
1844 }
1845
1846 int kvm_arch_remove_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1847 {
1848     uint8_t int3;
1849
1850     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1851         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1852         return -EINVAL;
1853     }
1854     return 0;
1855 }
1856
1857 static struct {
1858     target_ulong addr;
1859     int len;
1860     int type;
1861 } hw_breakpoint[4];
1862
1863 static int nb_hw_breakpoint;
1864
1865 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1866 {
1867     int n;
1868
1869     for (n = 0; n < nb_hw_breakpoint; n++) {
1870         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1871             (hw_breakpoint[n].len == len || len == -1)) {
1872             return n;
1873         }
1874     }
1875     return -1;
1876 }
1877
1878 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1879                                   target_ulong len, int type)
1880 {
1881     switch (type) {
1882     case GDB_BREAKPOINT_HW:
1883         len = 1;
1884         break;
1885     case GDB_WATCHPOINT_WRITE:
1886     case GDB_WATCHPOINT_ACCESS:
1887         switch (len) {
1888         case 1:
1889             break;
1890         case 2:
1891         case 4:
1892         case 8:
1893             if (addr & (len - 1)) {
1894                 return -EINVAL;
1895             }
1896             break;
1897         default:
1898             return -EINVAL;
1899         }
1900         break;
1901     default:
1902         return -ENOSYS;
1903     }
1904
1905     if (nb_hw_breakpoint == 4) {
1906         return -ENOBUFS;
1907     }
1908     if (find_hw_breakpoint(addr, len, type) >= 0) {
1909         return -EEXIST;
1910     }
1911     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1912     hw_breakpoint[nb_hw_breakpoint].len = len;
1913     hw_breakpoint[nb_hw_breakpoint].type = type;
1914     nb_hw_breakpoint++;
1915
1916     return 0;
1917 }
1918
1919 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1920                                   target_ulong len, int type)
1921 {
1922     int n;
1923
1924     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1925     if (n < 0) {
1926         return -ENOENT;
1927     }
1928     nb_hw_breakpoint--;
1929     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1930
1931     return 0;
1932 }
1933
1934 void kvm_arch_remove_all_hw_breakpoints(void)
1935 {
1936     nb_hw_breakpoint = 0;
1937 }
1938
1939 static CPUWatchpoint hw_watchpoint;
1940
1941 static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
1942 {
1943     int ret = 0;
1944     int n;
1945
1946     if (arch_info->exception == 1) {
1947         if (arch_info->dr6 & (1 << 14)) {
1948             if (cpu_single_env->singlestep_enabled) {
1949                 ret = EXCP_DEBUG;
1950             }
1951         } else {
1952             for (n = 0; n < 4; n++) {
1953                 if (arch_info->dr6 & (1 << n)) {
1954                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1955                     case 0x0:
1956                         ret = EXCP_DEBUG;
1957                         break;
1958                     case 0x1:
1959                         ret = EXCP_DEBUG;
1960                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1961                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1962                         hw_watchpoint.flags = BP_MEM_WRITE;
1963                         break;
1964                     case 0x3:
1965                         ret = EXCP_DEBUG;
1966                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1967                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1968                         hw_watchpoint.flags = BP_MEM_ACCESS;
1969                         break;
1970                     }
1971                 }
1972             }
1973         }
1974     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1975         ret = EXCP_DEBUG;
1976     }
1977     if (ret == 0) {
1978         cpu_synchronize_state(cpu_single_env);
1979         assert(cpu_single_env->exception_injected == -1);
1980
1981         /* pass to guest */
1982         cpu_single_env->exception_injected = arch_info->exception;
1983         cpu_single_env->has_error_code = 0;
1984     }
1985
1986     return ret;
1987 }
1988
1989 void kvm_arch_update_guest_debug(CPUX86State *env, struct kvm_guest_debug *dbg)
1990 {
1991     const uint8_t type_code[] = {
1992         [GDB_BREAKPOINT_HW] = 0x0,
1993         [GDB_WATCHPOINT_WRITE] = 0x1,
1994         [GDB_WATCHPOINT_ACCESS] = 0x3
1995     };
1996     const uint8_t len_code[] = {
1997         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1998     };
1999     int n;
2000
2001     if (kvm_sw_breakpoints_active(env)) {
2002         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2003     }
2004     if (nb_hw_breakpoint > 0) {
2005         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2006         dbg->arch.debugreg[7] = 0x0600;
2007         for (n = 0; n < nb_hw_breakpoint; n++) {
2008             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2009             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2010                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2011                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2012         }
2013     }
2014 }
2015
2016 static bool host_supports_vmx(void)
2017 {
2018     uint32_t ecx, unused;
2019
2020     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2021     return ecx & CPUID_EXT_VMX;
2022 }
2023
2024 #define VMX_INVALID_GUEST_STATE 0x80000021
2025
2026 int kvm_arch_handle_exit(CPUX86State *env, struct kvm_run *run)
2027 {
2028     uint64_t code;
2029     int ret;
2030
2031     switch (run->exit_reason) {
2032     case KVM_EXIT_HLT:
2033         DPRINTF("handle_hlt\n");
2034         ret = kvm_handle_halt(env);
2035         break;
2036     case KVM_EXIT_SET_TPR:
2037         ret = 0;
2038         break;
2039     case KVM_EXIT_TPR_ACCESS:
2040         ret = kvm_handle_tpr_access(env);
2041         break;
2042     case KVM_EXIT_FAIL_ENTRY:
2043         code = run->fail_entry.hardware_entry_failure_reason;
2044         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2045                 code);
2046         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2047             fprintf(stderr,
2048                     "\nIf you're running a guest on an Intel machine without "
2049                         "unrestricted mode\n"
2050                     "support, the failure can be most likely due to the guest "
2051                         "entering an invalid\n"
2052                     "state for Intel VT. For example, the guest maybe running "
2053                         "in big real mode\n"
2054                     "which is not supported on less recent Intel processors."
2055                         "\n\n");
2056         }
2057         ret = -1;
2058         break;
2059     case KVM_EXIT_EXCEPTION:
2060         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2061                 run->ex.exception, run->ex.error_code);
2062         ret = -1;
2063         break;
2064     case KVM_EXIT_DEBUG:
2065         DPRINTF("kvm_exit_debug\n");
2066         ret = kvm_handle_debug(&run->debug.arch);
2067         break;
2068     default:
2069         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2070         ret = -1;
2071         break;
2072     }
2073
2074     return ret;
2075 }
2076
2077 bool kvm_arch_stop_on_emulation_error(CPUX86State *env)
2078 {
2079     kvm_cpu_synchronize_state(env);
2080     return !(env->cr[0] & CR0_PE_MASK) ||
2081            ((env->segs[R_CS].selector  & 3) != 3);
2082 }
2083
2084 void kvm_arch_init_irq_routing(KVMState *s)
2085 {
2086     if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2087         /* If kernel can't do irq routing, interrupt source
2088          * override 0->2 cannot be set up as required by HPET.
2089          * So we have to disable it.
2090          */
2091         no_hpet = 1;
2092     }
2093     /* We know at this point that we're using the in-kernel
2094      * irqchip, so we can use irqfds, and on x86 we know
2095      * we can use msi via irqfd and GSI routing.
2096      */
2097     kvm_irqfds_allowed = true;
2098     kvm_msi_via_irqfd_allowed = true;
2099     kvm_gsi_routing_allowed = true;
2100 }
2101
2102 /* Classic KVM device assignment interface. Will remain x86 only. */
2103 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2104                           uint32_t flags, uint32_t *dev_id)
2105 {
2106     struct kvm_assigned_pci_dev dev_data = {
2107         .segnr = dev_addr->domain,
2108         .busnr = dev_addr->bus,
2109         .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2110         .flags = flags,
2111     };
2112     int ret;
2113
2114     dev_data.assigned_dev_id =
2115         (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2116
2117     ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2118     if (ret < 0) {
2119         return ret;
2120     }
2121
2122     *dev_id = dev_data.assigned_dev_id;
2123
2124     return 0;
2125 }
2126
2127 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2128 {
2129     struct kvm_assigned_pci_dev dev_data = {
2130         .assigned_dev_id = dev_id,
2131     };
2132
2133     return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2134 }
2135
2136 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2137                                    uint32_t irq_type, uint32_t guest_irq)
2138 {
2139     struct kvm_assigned_irq assigned_irq = {
2140         .assigned_dev_id = dev_id,
2141         .guest_irq = guest_irq,
2142         .flags = irq_type,
2143     };
2144
2145     if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2146         return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2147     } else {
2148         return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2149     }
2150 }
2151
2152 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2153                            uint32_t guest_irq)
2154 {
2155     uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2156         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2157
2158     return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2159 }
2160
2161 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2162 {
2163     struct kvm_assigned_pci_dev dev_data = {
2164         .assigned_dev_id = dev_id,
2165         .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2166     };
2167
2168     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2169 }
2170
2171 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2172                                      uint32_t type)
2173 {
2174     struct kvm_assigned_irq assigned_irq = {
2175         .assigned_dev_id = dev_id,
2176         .flags = type,
2177     };
2178
2179     return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2180 }
2181
2182 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2183 {
2184     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2185         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2186 }
2187
2188 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2189 {
2190     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2191                                               KVM_DEV_IRQ_GUEST_MSI, virq);
2192 }
2193
2194 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2195 {
2196     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2197                                                 KVM_DEV_IRQ_HOST_MSI);
2198 }
2199
2200 bool kvm_device_msix_supported(KVMState *s)
2201 {
2202     /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2203      * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2204     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2205 }
2206
2207 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2208                                  uint32_t nr_vectors)
2209 {
2210     struct kvm_assigned_msix_nr msix_nr = {
2211         .assigned_dev_id = dev_id,
2212         .entry_nr = nr_vectors,
2213     };
2214
2215     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2216 }
2217
2218 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2219                                int virq)
2220 {
2221     struct kvm_assigned_msix_entry msix_entry = {
2222         .assigned_dev_id = dev_id,
2223         .gsi = virq,
2224         .entry = vector,
2225     };
2226
2227     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2228 }
2229
2230 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2231 {
2232     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2233                                               KVM_DEV_IRQ_GUEST_MSIX, 0);
2234 }
2235
2236 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2237 {
2238     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2239                                                 KVM_DEV_IRQ_HOST_MSIX);
2240 }