include/hw/riscv/sifive_uart.h

   1 /*
   2  * SiFive UART interface
   3  *
   4  * Copyright (c) 2016 Stefan O'Rear
   5  * Copyright (c) 2017 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef HW_SIFIVE_UART_H
  21 #define HW_SIFIVE_UART_H
  22
  23 enum {
  24     SIFIVE_UART_TXFIFO        = 0,
  25     SIFIVE_UART_RXFIFO        = 4,
  26     SIFIVE_UART_TXCTRL        = 8,
  27     SIFIVE_UART_TXMARK        = 10,
  28     SIFIVE_UART_RXCTRL        = 12,
  29     SIFIVE_UART_RXMARK        = 14,
  30     SIFIVE_UART_IE            = 16,
  31     SIFIVE_UART_IP            = 20,
  32     SIFIVE_UART_DIV           = 24,
  33     SIFIVE_UART_MAX           = 32
  34 };
  35
  36 enum {
  37     SIFIVE_UART_IE_TXWM       = 1, /* Transmit watermark interrupt enable */
  38     SIFIVE_UART_IE_RXWM       = 2  /* Receive watermark interrupt enable */
  39 };
  40
  41 enum {
  42     SIFIVE_UART_IP_TXWM       = 1, /* Transmit watermark interrupt pending */
  43     SIFIVE_UART_IP_RXWM       = 2  /* Receive watermark interrupt pending */
  44 };
  45
  46 #define TYPE_SIFIVE_UART "riscv.sifive.uart"
  47
  48 #define SIFIVE_UART(obj) \
  49     OBJECT_CHECK(SiFiveUARTState, (obj), TYPE_SIFIVE_UART)
  50
  51 typedef struct SiFiveUARTState {
  52     /*< private >*/
  53     SysBusDevice parent_obj;
  54
  55     /*< public >*/
  56     qemu_irq irq;
  57     MemoryRegion mmio;
  58     CharBackend chr;
  59     uint8_t rx_fifo[8];
  60     unsigned int rx_fifo_len;
  61     uint32_t ie;
  62     uint32_t ip;
  63     uint32_t txctrl;
  64     uint32_t rxctrl;
  65     uint32_t div;
  66 } SiFiveUARTState;
  67
  68 SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
  69     Chardev *chr, qemu_irq irq);
  70
  71 #endif