hw/ide/pci.c

   1 /*
   2  * QEMU IDE Emulation: PCI Bus support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/irq.h"
  28 #include "hw/pci/pci.h"
  29 #include "migration/vmstate.h"
  30 #include "sysemu/dma.h"
  31 #include "qemu/error-report.h"
  32 #include "qemu/module.h"
  33 #include "hw/ide/pci.h"
  34 #include "trace.h"
  35
  36 #define BMDMA_PAGE_SIZE 4096
  37
  38 #define BM_MIGRATION_COMPAT_STATUS_BITS \
  39         (IDE_RETRY_DMA | IDE_RETRY_PIO | \
  40         IDE_RETRY_READ | IDE_RETRY_FLUSH)
  41
  42 static uint64_t pci_ide_status_read(void *opaque, hwaddr addr, unsigned size)
  43 {
  44     IDEBus *bus = opaque;
  45
  46     if (addr != 2 || size != 1) {
  47         return ((uint64_t)1 << (size * 8)) - 1;
  48     }
  49     return ide_status_read(bus, addr + 2);
  50 }
  51
  52 static void pci_ide_ctrl_write(void *opaque, hwaddr addr,
  53                                uint64_t data, unsigned size)
  54 {
  55     IDEBus *bus = opaque;
  56
  57     if (addr != 2 || size != 1) {
  58         return;
  59     }
  60     ide_ctrl_write(bus, addr + 2, data);
  61 }
  62
  63 const MemoryRegionOps pci_ide_cmd_le_ops = {
  64     .read = pci_ide_status_read,
  65     .write = pci_ide_ctrl_write,
  66     .endianness = DEVICE_LITTLE_ENDIAN,
  67 };
  68
  69 static uint64_t pci_ide_data_read(void *opaque, hwaddr addr, unsigned size)
  70 {
  71     IDEBus *bus = opaque;
  72
  73     if (size == 1) {
  74         return ide_ioport_read(bus, addr);
  75     } else if (addr == 0) {
  76         if (size == 2) {
  77             return ide_data_readw(bus, addr);
  78         } else {
  79             return ide_data_readl(bus, addr);
  80         }
  81     }
  82     return ((uint64_t)1 << (size * 8)) - 1;
  83 }
  84
  85 static void pci_ide_data_write(void *opaque, hwaddr addr,
  86                                uint64_t data, unsigned size)
  87 {
  88     IDEBus *bus = opaque;
  89
  90     if (size == 1) {
  91         ide_ioport_write(bus, addr, data);
  92     } else if (addr == 0) {
  93         if (size == 2) {
  94             ide_data_writew(bus, addr, data);
  95         } else {
  96             ide_data_writel(bus, addr, data);
  97         }
  98     }
  99 }
 100
 101 const MemoryRegionOps pci_ide_data_le_ops = {
 102     .read = pci_ide_data_read,
 103     .write = pci_ide_data_write,
 104     .endianness = DEVICE_LITTLE_ENDIAN,
 105 };
 106
 107 static IDEState *bmdma_active_if(BMDMAState *bmdma)
 108 {
 109     assert(bmdma->bus->retry_unit != (uint8_t)-1);
 110     return bmdma->bus->ifs + bmdma->bus->retry_unit;
 111 }
 112
 113 static void bmdma_start_dma(const IDEDMA *dma, IDEState *s,
 114                             BlockCompletionFunc *dma_cb)
 115 {
 116     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 117
 118     bm->dma_cb = dma_cb;
 119     bm->cur_prd_last = 0;
 120     bm->cur_prd_addr = 0;
 121     bm->cur_prd_len = 0;
 122
 123     if (bm->status & BM_STATUS_DMAING) {
 124         bm->dma_cb(bmdma_active_if(bm), 0);
 125     }
 126 }
 127
 128 /**
 129  * Prepare an sglist based on available PRDs.
 130  * @limit: How many bytes to prepare total.
 131  *
 132  * Returns the number of bytes prepared, -1 on error.
 133  * IDEState.io_buffer_size will contain the number of bytes described
 134  * by the PRDs, whether or not we added them to the sglist.
 135  */
 136 static int32_t bmdma_prepare_buf(const IDEDMA *dma, int32_t limit)
 137 {
 138     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 139     IDEState *s = bmdma_active_if(bm);
 140     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
 141     struct {
 142         uint32_t addr;
 143         uint32_t size;
 144     } prd;
 145     int l, len;
 146
 147     pci_dma_sglist_init(&s->sg, pci_dev,
 148                         s->nsector / (BMDMA_PAGE_SIZE / BDRV_SECTOR_SIZE) + 1);
 149     s->io_buffer_size = 0;
 150     for(;;) {
 151         if (bm->cur_prd_len == 0) {
 152             /* end of table (with a fail safe of one page) */
 153             if (bm->cur_prd_last ||
 154                 (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE) {
 155                 return s->sg.size;
 156             }
 157             pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
 158             bm->cur_addr += 8;
 159             prd.addr = le32_to_cpu(prd.addr);
 160             prd.size = le32_to_cpu(prd.size);
 161             len = prd.size & 0xfffe;
 162             if (len == 0)
 163                 len = 0x10000;
 164             bm->cur_prd_len = len;
 165             bm->cur_prd_addr = prd.addr;
 166             bm->cur_prd_last = (prd.size & 0x80000000);
 167         }
 168         l = bm->cur_prd_len;
 169         if (l > 0) {
 170             uint64_t sg_len;
 171
 172             /* Don't add extra bytes to the SGList; consume any remaining
 173              * PRDs from the guest, but ignore them. */
 174             sg_len = MIN(limit - s->sg.size, bm->cur_prd_len);
 175             if (sg_len) {
 176                 qemu_sglist_add(&s->sg, bm->cur_prd_addr, sg_len);
 177             }
 178
 179             bm->cur_prd_addr += l;
 180             bm->cur_prd_len -= l;
 181             s->io_buffer_size += l;
 182         }
 183     }
 184
 185     qemu_sglist_destroy(&s->sg);
 186     s->io_buffer_size = 0;
 187     return -1;
 188 }
 189
 190 /* return 0 if buffer completed */
 191 static int bmdma_rw_buf(const IDEDMA *dma, bool is_write)
 192 {
 193     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 194     IDEState *s = bmdma_active_if(bm);
 195     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
 196     struct {
 197         uint32_t addr;
 198         uint32_t size;
 199     } prd;
 200     int l, len;
 201
 202     for(;;) {
 203         l = s->io_buffer_size - s->io_buffer_index;
 204         if (l <= 0)
 205             break;
 206         if (bm->cur_prd_len == 0) {
 207             /* end of table (with a fail safe of one page) */
 208             if (bm->cur_prd_last ||
 209                 (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
 210                 return 0;
 211             pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
 212             bm->cur_addr += 8;
 213             prd.addr = le32_to_cpu(prd.addr);
 214             prd.size = le32_to_cpu(prd.size);
 215             len = prd.size & 0xfffe;
 216             if (len == 0)
 217                 len = 0x10000;
 218             bm->cur_prd_len = len;
 219             bm->cur_prd_addr = prd.addr;
 220             bm->cur_prd_last = (prd.size & 0x80000000);
 221         }
 222         if (l > bm->cur_prd_len)
 223             l = bm->cur_prd_len;
 224         if (l > 0) {
 225             if (is_write) {
 226                 pci_dma_write(pci_dev, bm->cur_prd_addr,
 227                               s->io_buffer + s->io_buffer_index, l);
 228             } else {
 229                 pci_dma_read(pci_dev, bm->cur_prd_addr,
 230                              s->io_buffer + s->io_buffer_index, l);
 231             }
 232             bm->cur_prd_addr += l;
 233             bm->cur_prd_len -= l;
 234             s->io_buffer_index += l;
 235         }
 236     }
 237     return 1;
 238 }
 239
 240 static void bmdma_set_inactive(const IDEDMA *dma, bool more)
 241 {
 242     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 243
 244     bm->dma_cb = NULL;
 245     if (more) {
 246         bm->status |= BM_STATUS_DMAING;
 247     } else {
 248         bm->status &= ~BM_STATUS_DMAING;
 249     }
 250 }
 251
 252 static void bmdma_restart_dma(const IDEDMA *dma)
 253 {
 254     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 255
 256     bm->cur_addr = bm->addr;
 257 }
 258
 259 static void bmdma_cancel(BMDMAState *bm)
 260 {
 261     if (bm->status & BM_STATUS_DMAING) {
 262         /* cancel DMA request */
 263         bmdma_set_inactive(&bm->dma, false);
 264     }
 265 }
 266
 267 static void bmdma_reset(const IDEDMA *dma)
 268 {
 269     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 270
 271     trace_bmdma_reset();
 272     bmdma_cancel(bm);
 273     bm->cmd = 0;
 274     bm->status = 0;
 275     bm->addr = 0;
 276     bm->cur_addr = 0;
 277     bm->cur_prd_last = 0;
 278     bm->cur_prd_addr = 0;
 279     bm->cur_prd_len = 0;
 280 }
 281
 282 static void bmdma_irq(void *opaque, int n, int level)
 283 {
 284     BMDMAState *bm = opaque;
 285
 286     if (!level) {
 287         /* pass through lower */
 288         qemu_set_irq(bm->irq, level);
 289         return;
 290     }
 291
 292     bm->status |= BM_STATUS_INT;
 293
 294     /* trigger the real irq */
 295     qemu_set_irq(bm->irq, level);
 296 }
 297
 298 void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
 299 {
 300     trace_bmdma_cmd_writeb(val);
 301
 302     /* Ignore writes to SSBM if it keeps the old value */
 303     if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
 304         if (!(val & BM_CMD_START)) {
 305             ide_cancel_dma_sync(ide_bus_active_if(bm->bus));
 306             bm->status &= ~BM_STATUS_DMAING;
 307         } else {
 308             bm->cur_addr = bm->addr;
 309             if (!(bm->status & BM_STATUS_DMAING)) {
 310                 bm->status |= BM_STATUS_DMAING;
 311                 /* start dma transfer if possible */
 312                 if (bm->dma_cb)
 313                     bm->dma_cb(bmdma_active_if(bm), 0);
 314             }
 315         }
 316     }
 317
 318     bm->cmd = val & 0x09;
 319 }
 320
 321 void bmdma_status_writeb(BMDMAState *bm, uint32_t val)
 322 {
 323     bm->status = (val & 0x60) | (bm->status & BM_STATUS_DMAING)
 324                  | (bm->status & ~val & (BM_STATUS_ERROR | BM_STATUS_INT));
 325 }
 326
 327 static uint64_t bmdma_addr_read(void *opaque, hwaddr addr,
 328                                 unsigned width)
 329 {
 330     BMDMAState *bm = opaque;
 331     uint32_t mask = (1ULL << (width * 8)) - 1;
 332     uint64_t data;
 333
 334     data = (bm->addr >> (addr * 8)) & mask;
 335     trace_bmdma_addr_read(data);
 336     return data;
 337 }
 338
 339 static void bmdma_addr_write(void *opaque, hwaddr addr,
 340                              uint64_t data, unsigned width)
 341 {
 342     BMDMAState *bm = opaque;
 343     int shift = addr * 8;
 344     uint32_t mask = (1ULL << (width * 8)) - 1;
 345
 346     trace_bmdma_addr_write(data);
 347     bm->addr &= ~(mask << shift);
 348     bm->addr |= ((data & mask) << shift) & ~3;
 349 }
 350
 351 MemoryRegionOps bmdma_addr_ioport_ops = {
 352     .read = bmdma_addr_read,
 353     .write = bmdma_addr_write,
 354     .endianness = DEVICE_LITTLE_ENDIAN,
 355 };
 356
 357 static bool ide_bmdma_current_needed(void *opaque)
 358 {
 359     BMDMAState *bm = opaque;
 360
 361     return (bm->cur_prd_len != 0);
 362 }
 363
 364 static bool ide_bmdma_status_needed(void *opaque)
 365 {
 366     BMDMAState *bm = opaque;
 367
 368     /* Older versions abused some bits in the status register for internal
 369      * error state. If any of these bits are set, we must add a subsection to
 370      * transfer the real status register */
 371     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 372
 373     return ((bm->status & abused_bits) != 0);
 374 }
 375
 376 static int ide_bmdma_pre_save(void *opaque)
 377 {
 378     BMDMAState *bm = opaque;
 379     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 380
 381     if (!(bm->status & BM_STATUS_DMAING) && bm->dma_cb) {
 382         bm->bus->error_status =
 383             ide_dma_cmd_to_retry(bmdma_active_if(bm)->dma_cmd);
 384     }
 385     bm->migration_retry_unit = bm->bus->retry_unit;
 386     bm->migration_retry_sector_num = bm->bus->retry_sector_num;
 387     bm->migration_retry_nsector = bm->bus->retry_nsector;
 388     bm->migration_compat_status =
 389         (bm->status & ~abused_bits) | (bm->bus->error_status & abused_bits);
 390
 391     return 0;
 392 }
 393
 394 /* This function accesses bm->bus->error_status which is loaded only after
 395  * BMDMA itself. This is why the function is called from ide_pci_post_load
 396  * instead of being registered with VMState where it would run too early. */
 397 static int ide_bmdma_post_load(void *opaque, int version_id)
 398 {
 399     BMDMAState *bm = opaque;
 400     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 401
 402     if (bm->status == 0) {
 403         bm->status = bm->migration_compat_status & ~abused_bits;
 404         bm->bus->error_status |= bm->migration_compat_status & abused_bits;
 405     }
 406     if (bm->bus->error_status) {
 407         bm->bus->retry_sector_num = bm->migration_retry_sector_num;
 408         bm->bus->retry_nsector = bm->migration_retry_nsector;
 409         bm->bus->retry_unit = bm->migration_retry_unit;
 410     }
 411
 412     return 0;
 413 }
 414
 415 static const VMStateDescription vmstate_bmdma_current = {
 416     .name = "ide bmdma_current",
 417     .version_id = 1,
 418     .minimum_version_id = 1,
 419     .needed = ide_bmdma_current_needed,
 420     .fields = (VMStateField[]) {
 421         VMSTATE_UINT32(cur_addr, BMDMAState),
 422         VMSTATE_UINT32(cur_prd_last, BMDMAState),
 423         VMSTATE_UINT32(cur_prd_addr, BMDMAState),
 424         VMSTATE_UINT32(cur_prd_len, BMDMAState),
 425         VMSTATE_END_OF_LIST()
 426     }
 427 };
 428
 429 static const VMStateDescription vmstate_bmdma_status = {
 430     .name ="ide bmdma/status",
 431     .version_id = 1,
 432     .minimum_version_id = 1,
 433     .needed = ide_bmdma_status_needed,
 434     .fields = (VMStateField[]) {
 435         VMSTATE_UINT8(status, BMDMAState),
 436         VMSTATE_END_OF_LIST()
 437     }
 438 };
 439
 440 static const VMStateDescription vmstate_bmdma = {
 441     .name = "ide bmdma",
 442     .version_id = 3,
 443     .minimum_version_id = 0,
 444     .pre_save  = ide_bmdma_pre_save,
 445     .fields = (VMStateField[]) {
 446         VMSTATE_UINT8(cmd, BMDMAState),
 447         VMSTATE_UINT8(migration_compat_status, BMDMAState),
 448         VMSTATE_UINT32(addr, BMDMAState),
 449         VMSTATE_INT64(migration_retry_sector_num, BMDMAState),
 450         VMSTATE_UINT32(migration_retry_nsector, BMDMAState),
 451         VMSTATE_UINT8(migration_retry_unit, BMDMAState),
 452         VMSTATE_END_OF_LIST()
 453     },
 454     .subsections = (const VMStateDescription*[]) {
 455         &vmstate_bmdma_current,
 456         &vmstate_bmdma_status,
 457         NULL
 458     }
 459 };
 460
 461 static int ide_pci_post_load(void *opaque, int version_id)
 462 {
 463     PCIIDEState *d = opaque;
 464     int i;
 465
 466     for(i = 0; i < 2; i++) {
 467         /* current versions always store 0/1, but older version
 468            stored bigger values. We only need last bit */
 469         d->bmdma[i].migration_retry_unit &= 1;
 470         ide_bmdma_post_load(&d->bmdma[i], -1);
 471     }
 472
 473     return 0;
 474 }
 475
 476 const VMStateDescription vmstate_ide_pci = {
 477     .name = "ide",
 478     .version_id = 3,
 479     .minimum_version_id = 0,
 480     .post_load = ide_pci_post_load,
 481     .fields = (VMStateField[]) {
 482         VMSTATE_PCI_DEVICE(parent_obj, PCIIDEState),
 483         VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
 484                              vmstate_bmdma, BMDMAState),
 485         VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
 486         VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
 487         VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
 488         VMSTATE_END_OF_LIST()
 489     }
 490 };
 491
 492 /* hd_table must contain 4 block drivers */
 493 void pci_ide_create_devs(PCIDevice *dev)
 494 {
 495     PCIIDEState *d = PCI_IDE(dev);
 496     DriveInfo *hd_table[2 * MAX_IDE_DEVS];
 497     static const int bus[4]  = { 0, 0, 1, 1 };
 498     static const int unit[4] = { 0, 1, 0, 1 };
 499     int i;
 500
 501     ide_drive_get(hd_table, ARRAY_SIZE(hd_table));
 502     for (i = 0; i < 4; i++) {
 503         if (hd_table[i]) {
 504             ide_bus_create_drive(d->bus + bus[i], unit[i], hd_table[i]);
 505         }
 506     }
 507 }
 508
 509 static const struct IDEDMAOps bmdma_ops = {
 510     .start_dma = bmdma_start_dma,
 511     .prepare_buf = bmdma_prepare_buf,
 512     .rw_buf = bmdma_rw_buf,
 513     .restart_dma = bmdma_restart_dma,
 514     .set_inactive = bmdma_set_inactive,
 515     .reset = bmdma_reset,
 516 };
 517
 518 void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
 519 {
 520     if (bus->dma == &bm->dma) {
 521         return;
 522     }
 523
 524     bm->dma.ops = &bmdma_ops;
 525     bus->dma = &bm->dma;
 526     bm->irq = bus->irq;
 527     bus->irq = qemu_allocate_irq(bmdma_irq, bm, 0);
 528     bm->bus = bus;
 529     bm->pci_dev = d;
 530 }
 531
 532 static void pci_ide_init(Object *obj)
 533 {
 534     PCIIDEState *d = PCI_IDE(obj);
 535
 536     qdev_init_gpio_out_named(DEVICE(d), d->isa_irq, "isa-irq",
 537                              ARRAY_SIZE(d->isa_irq));
 538 }
 539
 540 static const TypeInfo pci_ide_type_info = {
 541     .name = TYPE_PCI_IDE,
 542     .parent = TYPE_PCI_DEVICE,
 543     .instance_size = sizeof(PCIIDEState),
 544     .instance_init = pci_ide_init,
 545     .abstract = true,
 546     .interfaces = (InterfaceInfo[]) {
 547         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 548         { },
 549     },
 550 };
 551
 552 static void pci_ide_register_types(void)
 553 {
 554     type_register_static(&pci_ide_type_info);
 555 }
 556
 557 type_init(pci_ide_register_types)