target/loongarch/op_helper.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * LoongArch emulation helpers for QEMU.
   4  *
   5  * Copyright (c) 2021 Loongson Technology Corporation Limited
   6  */
   7
   8 #include "qemu/osdep.h"
   9 #include "qemu/log.h"
  10 #include "cpu.h"
  11 #include "qemu/host-utils.h"
  12 #include "exec/helper-proto.h"
  13 #include "exec/exec-all.h"
  14 #include "exec/cpu_ldst.h"
  15 #include "internals.h"
  16 #include "qemu/crc32c.h"
  17 #include <zlib.h>
  18 #include "cpu-csr.h"
  19
  20 /* Exceptions helpers */
  21 void helper_raise_exception(CPULoongArchState *env, uint32_t exception)
  22 {
  23     do_raise_exception(env, exception, GETPC());
  24 }
  25
  26 target_ulong helper_bitrev_w(target_ulong rj)
  27 {
  28     return (int32_t)revbit32(rj);
  29 }
  30
  31 target_ulong helper_bitrev_d(target_ulong rj)
  32 {
  33     return revbit64(rj);
  34 }
  35
  36 target_ulong helper_bitswap(target_ulong v)
  37 {
  38     v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
  39         ((v & (target_ulong)0x5555555555555555ULL) << 1);
  40     v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
  41         ((v & (target_ulong)0x3333333333333333ULL) << 2);
  42     v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
  43         ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
  44     return v;
  45 }
  46
  47 /* loongarch assert op */
  48 void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
  49 {
  50     if (rj > rk) {
  51         env->CSR_BADV = rj;
  52         do_raise_exception(env, EXCCODE_BCE, GETPC());
  53     }
  54 }
  55
  56 void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
  57 {
  58     if (rj <= rk) {
  59         env->CSR_BADV = rj;
  60         do_raise_exception(env, EXCCODE_BCE, GETPC());
  61     }
  62 }
  63
  64 target_ulong helper_crc32(target_ulong val, target_ulong m, uint64_t sz)
  65 {
  66     uint8_t buf[8];
  67     target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1);
  68
  69     m &= mask;
  70     stq_le_p(buf, m);
  71     return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff);
  72 }
  73
  74 target_ulong helper_crc32c(target_ulong val, target_ulong m, uint64_t sz)
  75 {
  76     uint8_t buf[8];
  77     target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1);
  78     m &= mask;
  79     stq_le_p(buf, m);
  80     return (int32_t) (crc32c(val, buf, sz) ^ 0xffffffff);
  81 }
  82
  83 target_ulong helper_cpucfg(CPULoongArchState *env, target_ulong rj)
  84 {
  85     return rj >= ARRAY_SIZE(env->cpucfg) ? 0 : env->cpucfg[rj];
  86 }
  87
  88 uint64_t helper_rdtime_d(CPULoongArchState *env)
  89 {
  90 #ifdef CONFIG_USER_ONLY
  91     return cpu_get_host_ticks();
  92 #else
  93     uint64_t plv;
  94     LoongArchCPU *cpu = env_archcpu(env);
  95
  96     plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
  97     if (extract64(env->CSR_MISC, R_CSR_MISC_DRDTL_SHIFT + plv, 1)) {
  98         do_raise_exception(env, EXCCODE_IPE, GETPC());
  99     }
 100
 101     return cpu_loongarch_get_constant_timer_counter(cpu);
 102 #endif
 103 }
 104
 105 #ifndef CONFIG_USER_ONLY
 106 void helper_ertn(CPULoongArchState *env)
 107 {
 108     uint64_t csr_pplv, csr_pie;
 109     if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
 110         csr_pplv = FIELD_EX64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV);
 111         csr_pie = FIELD_EX64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE);
 112
 113         env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
 114         env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 0);
 115         env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 1);
 116         set_pc(env, env->CSR_TLBRERA);
 117         qemu_log_mask(CPU_LOG_INT, "%s: TLBRERA " TARGET_FMT_lx "\n",
 118                       __func__, env->CSR_TLBRERA);
 119     } else {
 120         csr_pplv = FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PPLV);
 121         csr_pie = FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PIE);
 122
 123         set_pc(env, env->CSR_ERA);
 124         qemu_log_mask(CPU_LOG_INT, "%s: ERA " TARGET_FMT_lx "\n",
 125                       __func__, env->CSR_ERA);
 126     }
 127     env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, csr_pplv);
 128     env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, csr_pie);
 129
 130     env->lladdr = 1;
 131 }
 132
 133 void helper_idle(CPULoongArchState *env)
 134 {
 135     CPUState *cs = env_cpu(env);
 136
 137     cs->halted = 1;
 138     do_raise_exception(env, EXCP_HLT, 0);
 139 }
 140 #endif