hw/arm/stm32f205_soc.c

   1 /*
   2  * STM32F205 SoC
   3  *
   4  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qapi/error.h"
  27 #include "qemu-common.h"
  28 #include "hw/arm/arm.h"
  29 #include "exec/address-spaces.h"
  30 #include "hw/arm/stm32f205_soc.h"
  31
  32 /* At the moment only Timer 2 to 5 are modelled */
  33 static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
  34     0x40000800, 0x40000C00 };
  35 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
  36     0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
  37 static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
  38     0x40012200 };
  39
  40 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
  41 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
  42 #define ADC_IRQ 18
  43
  44 static void stm32f205_soc_initfn(Object *obj)
  45 {
  46     STM32F205State *s = STM32F205_SOC(obj);
  47     int i;
  48
  49     object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG);
  50     qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default());
  51
  52     for (i = 0; i < STM_NUM_USARTS; i++) {
  53         object_initialize(&s->usart[i], sizeof(s->usart[i]),
  54                           TYPE_STM32F2XX_USART);
  55         qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default());
  56     }
  57
  58     for (i = 0; i < STM_NUM_TIMERS; i++) {
  59         object_initialize(&s->timer[i], sizeof(s->timer[i]),
  60                           TYPE_STM32F2XX_TIMER);
  61         qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
  62     }
  63
  64     s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));
  65
  66     for (i = 0; i < STM_NUM_ADCS; i++) {
  67         object_initialize(&s->adc[i], sizeof(s->adc[i]),
  68                           TYPE_STM32F2XX_ADC);
  69         qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default());
  70     }
  71 }
  72
  73 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
  74 {
  75     STM32F205State *s = STM32F205_SOC(dev_soc);
  76     DeviceState *dev, *nvic;
  77     SysBusDevice *busdev;
  78     Error *err = NULL;
  79     int i;
  80
  81     MemoryRegion *system_memory = get_system_memory();
  82     MemoryRegion *sram = g_new(MemoryRegion, 1);
  83     MemoryRegion *flash = g_new(MemoryRegion, 1);
  84     MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
  85
  86     memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE,
  87                            &error_fatal);
  88     memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias",
  89                              flash, 0, FLASH_SIZE);
  90
  91     vmstate_register_ram_global(flash);
  92
  93     memory_region_set_readonly(flash, true);
  94     memory_region_set_readonly(flash_alias, true);
  95
  96     memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
  97     memory_region_add_subregion(system_memory, 0, flash_alias);
  98
  99     memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
 100                            &error_fatal);
 101     vmstate_register_ram_global(sram);
 102     memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
 103
 104     nvic = armv7m_init(get_system_memory(), FLASH_SIZE, 96,
 105                        s->kernel_filename, s->cpu_model);
 106
 107     /* System configuration controller */
 108     dev = DEVICE(&s->syscfg);
 109     object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
 110     if (err != NULL) {
 111         error_propagate(errp, err);
 112         return;
 113     }
 114     busdev = SYS_BUS_DEVICE(dev);
 115     sysbus_mmio_map(busdev, 0, 0x40013800);
 116     sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, 71));
 117
 118     /* Attach UART (uses USART registers) and USART controllers */
 119     for (i = 0; i < STM_NUM_USARTS; i++) {
 120         dev = DEVICE(&(s->usart[i]));
 121         qdev_prop_set_chr(dev, "chardev",
 122                           i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL);
 123         object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
 124         if (err != NULL) {
 125             error_propagate(errp, err);
 126             return;
 127         }
 128         busdev = SYS_BUS_DEVICE(dev);
 129         sysbus_mmio_map(busdev, 0, usart_addr[i]);
 130         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, usart_irq[i]));
 131     }
 132
 133     /* Timer 2 to 5 */
 134     for (i = 0; i < STM_NUM_TIMERS; i++) {
 135         dev = DEVICE(&(s->timer[i]));
 136         qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
 137         object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
 138         if (err != NULL) {
 139             error_propagate(errp, err);
 140             return;
 141         }
 142         busdev = SYS_BUS_DEVICE(dev);
 143         sysbus_mmio_map(busdev, 0, timer_addr[i]);
 144         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
 145     }
 146
 147     /* ADC 1 to 3 */
 148     object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS,
 149                             "num-lines", &err);
 150     object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err);
 151     if (err != NULL) {
 152         error_propagate(errp, err);
 153         return;
 154     }
 155     qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
 156                           qdev_get_gpio_in(nvic, ADC_IRQ));
 157
 158     for (i = 0; i < STM_NUM_ADCS; i++) {
 159         dev = DEVICE(&(s->adc[i]));
 160         object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
 161         if (err != NULL) {
 162             error_propagate(errp, err);
 163             return;
 164         }
 165         busdev = SYS_BUS_DEVICE(dev);
 166         sysbus_mmio_map(busdev, 0, adc_addr[i]);
 167         sysbus_connect_irq(busdev, 0,
 168                            qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
 169     }
 170 }
 171
 172 static Property stm32f205_soc_properties[] = {
 173     DEFINE_PROP_STRING("kernel-filename", STM32F205State, kernel_filename),
 174     DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model),
 175     DEFINE_PROP_END_OF_LIST(),
 176 };
 177
 178 static void stm32f205_soc_class_init(ObjectClass *klass, void *data)
 179 {
 180     DeviceClass *dc = DEVICE_CLASS(klass);
 181
 182     dc->realize = stm32f205_soc_realize;
 183     dc->props = stm32f205_soc_properties;
 184 }
 185
 186 static const TypeInfo stm32f205_soc_info = {
 187     .name          = TYPE_STM32F205_SOC,
 188     .parent        = TYPE_SYS_BUS_DEVICE,
 189     .instance_size = sizeof(STM32F205State),
 190     .instance_init = stm32f205_soc_initfn,
 191     .class_init    = stm32f205_soc_class_init,
 192 };
 193
 194 static void stm32f205_soc_types(void)
 195 {
 196     type_register_static(&stm32f205_soc_info);
 197 }
 198
 199 type_init(stm32f205_soc_types)