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ppc: spapr: use cpu type name directly
[qemu/kevin.git] / hw / ppc / spapr.c
blob2c32f33314391fa0e267374cb201da81d42887de
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "qapi/visitor.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/numa.h"
32 #include "hw/hw.h"
33 #include "qemu/log.h"
34 #include "hw/fw-path-provider.h"
35 #include "elf.h"
36 #include "net/net.h"
37 #include "sysemu/device_tree.h"
38 #include "sysemu/block-backend.h"
39 #include "sysemu/cpus.h"
40 #include "sysemu/hw_accel.h"
41 #include "kvm_ppc.h"
42 #include "migration/misc.h"
43 #include "migration/global_state.h"
44 #include "migration/register.h"
45 #include "mmu-hash64.h"
46 #include "mmu-book3s-v3.h"
47 #include "qom/cpu.h"
48
49 #include "hw/boards.h"
50 #include "hw/ppc/ppc.h"
51 #include "hw/loader.h"
52
53 #include "hw/ppc/fdt.h"
54 #include "hw/ppc/spapr.h"
55 #include "hw/ppc/spapr_vio.h"
56 #include "hw/pci-host/spapr.h"
57 #include "hw/ppc/xics.h"
58 #include "hw/pci/msi.h"
59
60 #include "hw/pci/pci.h"
61 #include "hw/scsi/scsi.h"
62 #include "hw/virtio/virtio-scsi.h"
63 #include "hw/virtio/vhost-scsi-common.h"
64
65 #include "exec/address-spaces.h"
66 #include "hw/usb.h"
67 #include "qemu/config-file.h"
68 #include "qemu/error-report.h"
69 #include "trace.h"
70 #include "hw/nmi.h"
71 #include "hw/intc/intc.h"
72
73 #include "hw/compat.h"
74 #include "qemu/cutils.h"
75 #include "hw/ppc/spapr_cpu_core.h"
76 #include "qmp-commands.h"
77
78 #include <libfdt.h>
79
80 /* SLOF memory layout:
81 *
82 * SLOF raw image loaded at 0, copies its romfs right below the flat
83 * device-tree, then position SLOF itself 31M below that
84 *
85 * So we set FW_OVERHEAD to 40MB which should account for all of that
86 * and more
87 *
88 * We load our kernel at 4M, leaving space for SLOF initial image
89 */
90 #define FDT_MAX_SIZE 0x100000
91 #define RTAS_MAX_SIZE 0x10000
92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
93 #define FW_MAX_SIZE 0x400000
94 #define FW_FILE_NAME "slof.bin"
95 #define FW_OVERHEAD 0x2800000
96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
97
98 #define MIN_RMA_SLOF 128UL
99
100 #define PHANDLE_XICP 0x00001111
101
102 static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
103 const char *type_ics,
104 int nr_irqs, Error **errp)
105 {
106 Error *local_err = NULL;
107 Object *obj;
108
109 obj = object_new(type_ics);
110 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
111 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
112 &error_abort);
113 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
114 if (local_err) {
115 goto error;
116 }
117 object_property_set_bool(obj, true, "realized", &local_err);
118 if (local_err) {
119 goto error;
120 }
121
122 return ICS_SIMPLE(obj);
123
124 error:
125 error_propagate(errp, local_err);
126 return NULL;
127 }
128
129 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
130 {
131 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
132 * and newer QEMUs don't even have them. In both cases, we don't want
133 * to send anything on the wire.
134 */
135 return false;
136 }
137
138 static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
139 .name = "icp/server",
140 .version_id = 1,
141 .minimum_version_id = 1,
142 .needed = pre_2_10_vmstate_dummy_icp_needed,
143 .fields = (VMStateField[]) {
144 VMSTATE_UNUSED(4), /* uint32_t xirr */
145 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
146 VMSTATE_UNUSED(1), /* uint8_t mfrr */
147 VMSTATE_END_OF_LIST()
148 },
149 };
150
151 static void pre_2_10_vmstate_register_dummy_icp(int i)
152 {
153 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
154 (void *)(uintptr_t) i);
155 }
156
157 static void pre_2_10_vmstate_unregister_dummy_icp(int i)
158 {
159 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
160 (void *)(uintptr_t) i);
161 }
162
163 static inline int xics_max_server_number(void)
164 {
165 return DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), smp_threads);
166 }
167
168 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp)
169 {
170 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
171 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
172
173 if (kvm_enabled()) {
174 if (machine_kernel_irqchip_allowed(machine) &&
175 !xics_kvm_init(spapr, errp)) {
176 spapr->icp_type = TYPE_KVM_ICP;
177 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp);
178 }
179 if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
180 error_prepend(errp, "kernel_irqchip requested but unavailable: ");
181 return;
182 }
183 }
184
185 if (!spapr->ics) {
186 xics_spapr_init(spapr);
187 spapr->icp_type = TYPE_ICP;
188 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp);
189 if (!spapr->ics) {
190 return;
191 }
192 }
193
194 if (smc->pre_2_10_has_unused_icps) {
195 int i;
196
197 for (i = 0; i < xics_max_server_number(); i++) {
198 /* Dummy entries get deregistered when real ICPState objects
199 * are registered during CPU core hotplug.
200 */
201 pre_2_10_vmstate_register_dummy_icp(i);
202 }
203 }
204 }
205
206 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
207 int smt_threads)
208 {
209 int i, ret = 0;
210 uint32_t servers_prop[smt_threads];
211 uint32_t gservers_prop[smt_threads * 2];
212 int index = spapr_vcpu_id(cpu);
213
214 if (cpu->compat_pvr) {
215 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
216 if (ret < 0) {
217 return ret;
218 }
219 }
220
221 /* Build interrupt servers and gservers properties */
222 for (i = 0; i < smt_threads; i++) {
223 servers_prop[i] = cpu_to_be32(index + i);
224 /* Hack, direct the group queues back to cpu 0 */
225 gservers_prop[i*2] = cpu_to_be32(index + i);
226 gservers_prop[i*2 + 1] = 0;
227 }
228 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
229 servers_prop, sizeof(servers_prop));
230 if (ret < 0) {
231 return ret;
232 }
233 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
234 gservers_prop, sizeof(gservers_prop));
235
236 return ret;
237 }
238
239 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
240 {
241 int index = spapr_vcpu_id(cpu);
242 uint32_t associativity[] = {cpu_to_be32(0x5),
243 cpu_to_be32(0x0),
244 cpu_to_be32(0x0),
245 cpu_to_be32(0x0),
246 cpu_to_be32(cpu->node_id),
247 cpu_to_be32(index)};
248
249 /* Advertise NUMA via ibm,associativity */
250 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
251 sizeof(associativity));
252 }
253
254 /* Populate the "ibm,pa-features" property */
255 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset,
256 bool legacy_guest)
257 {
258 uint8_t pa_features_206[] = { 6, 0,
259 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
260 uint8_t pa_features_207[] = { 24, 0,
261 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
262 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
263 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
264 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
265 uint8_t pa_features_300[] = { 66, 0,
266 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
267 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
268 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
269 /* 6: DS207 */
270 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
271 /* 16: Vector */
272 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
273 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
274 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
275 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
276 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
277 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
278 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
279 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
280 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
281 /* 42: PM, 44: PC RA, 46: SC vec'd */
282 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
283 /* 48: SIMD, 50: QP BFP, 52: String */
284 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
285 /* 54: DecFP, 56: DecI, 58: SHA */
286 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
287 /* 60: NM atomic, 62: RNG */
288 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
289 };
290 uint8_t *pa_features;
291 size_t pa_size;
292
293 switch (POWERPC_MMU_VER(env->mmu_model)) {
294 case POWERPC_MMU_VER_2_06:
295 pa_features = pa_features_206;
296 pa_size = sizeof(pa_features_206);
297 break;
298 case POWERPC_MMU_VER_2_07:
299 pa_features = pa_features_207;
300 pa_size = sizeof(pa_features_207);
301 break;
302 case POWERPC_MMU_VER_3_00:
303 pa_features = pa_features_300;
304 pa_size = sizeof(pa_features_300);
305 break;
306 default:
307 return;
308 }
309
310 if (env->ci_large_pages) {
311 /*
312 * Note: we keep CI large pages off by default because a 64K capable
313 * guest provisioned with large pages might otherwise try to map a qemu
314 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
315 * even if that qemu runs on a 4k host.
316 * We dd this bit back here if we are confident this is not an issue
317 */
318 pa_features[3] |= 0x20;
319 }
320 if (kvmppc_has_cap_htm() && pa_size > 24) {
321 pa_features[24] |= 0x80; /* Transactional memory support */
322 }
323 if (legacy_guest && pa_size > 40) {
324 /* Workaround for broken kernels that attempt (guest) radix
325 * mode when they can't handle it, if they see the radix bit set
326 * in pa-features. So hide it from them. */
327 pa_features[40 + 2] &= ~0x80; /* Radix MMU */
328 }
329
330 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
331 }
332
333 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
334 {
335 int ret = 0, offset, cpus_offset;
336 CPUState *cs;
337 char cpu_model[32];
338 int smt = kvmppc_smt_threads();
339 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
340
341 CPU_FOREACH(cs) {
342 PowerPCCPU *cpu = POWERPC_CPU(cs);
343 CPUPPCState *env = &cpu->env;
344 DeviceClass *dc = DEVICE_GET_CLASS(cs);
345 int index = spapr_vcpu_id(cpu);
346 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
347
348 if ((index % smt) != 0) {
349 continue;
350 }
351
352 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
353
354 cpus_offset = fdt_path_offset(fdt, "/cpus");
355 if (cpus_offset < 0) {
356 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
357 if (cpus_offset < 0) {
358 return cpus_offset;
359 }
360 }
361 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
362 if (offset < 0) {
363 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
364 if (offset < 0) {
365 return offset;
366 }
367 }
368
369 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
370 pft_size_prop, sizeof(pft_size_prop));
371 if (ret < 0) {
372 return ret;
373 }
374
375 if (nb_numa_nodes > 1) {
376 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu);
377 if (ret < 0) {
378 return ret;
379 }
380 }
381
382 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
383 if (ret < 0) {
384 return ret;
385 }
386
387 spapr_populate_pa_features(env, fdt, offset,
388 spapr->cas_legacy_guest_workaround);
389 }
390 return ret;
391 }
392
393 static hwaddr spapr_node0_size(MachineState *machine)
394 {
395 if (nb_numa_nodes) {
396 int i;
397 for (i = 0; i < nb_numa_nodes; ++i) {
398 if (numa_info[i].node_mem) {
399 return MIN(pow2floor(numa_info[i].node_mem),
400 machine->ram_size);
401 }
402 }
403 }
404 return machine->ram_size;
405 }
406
407 static void add_str(GString *s, const gchar *s1)
408 {
409 g_string_append_len(s, s1, strlen(s1) + 1);
410 }
411
412 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
413 hwaddr size)
414 {
415 uint32_t associativity[] = {
416 cpu_to_be32(0x4), /* length */
417 cpu_to_be32(0x0), cpu_to_be32(0x0),
418 cpu_to_be32(0x0), cpu_to_be32(nodeid)
419 };
420 char mem_name[32];
421 uint64_t mem_reg_property[2];
422 int off;
423
424 mem_reg_property[0] = cpu_to_be64(start);
425 mem_reg_property[1] = cpu_to_be64(size);
426
427 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
428 off = fdt_add_subnode(fdt, 0, mem_name);
429 _FDT(off);
430 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
431 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
432 sizeof(mem_reg_property))));
433 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
434 sizeof(associativity))));
435 return off;
436 }
437
438 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
439 {
440 MachineState *machine = MACHINE(spapr);
441 hwaddr mem_start, node_size;
442 int i, nb_nodes = nb_numa_nodes;
443 NodeInfo *nodes = numa_info;
444 NodeInfo ramnode;
445
446 /* No NUMA nodes, assume there is just one node with whole RAM */
447 if (!nb_numa_nodes) {
448 nb_nodes = 1;
449 ramnode.node_mem = machine->ram_size;
450 nodes = &ramnode;
451 }
452
453 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
454 if (!nodes[i].node_mem) {
455 continue;
456 }
457 if (mem_start >= machine->ram_size) {
458 node_size = 0;
459 } else {
460 node_size = nodes[i].node_mem;
461 if (node_size > machine->ram_size - mem_start) {
462 node_size = machine->ram_size - mem_start;
463 }
464 }
465 if (!mem_start) {
466 /* ppc_spapr_init() checks for rma_size <= node0_size already */
467 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
468 mem_start += spapr->rma_size;
469 node_size -= spapr->rma_size;
470 }
471 for ( ; node_size; ) {
472 hwaddr sizetmp = pow2floor(node_size);
473
474 /* mem_start != 0 here */
475 if (ctzl(mem_start) < ctzl(sizetmp)) {
476 sizetmp = 1ULL << ctzl(mem_start);
477 }
478
479 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
480 node_size -= sizetmp;
481 mem_start += sizetmp;
482 }
483 }
484
485 return 0;
486 }
487
488 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
489 sPAPRMachineState *spapr)
490 {
491 PowerPCCPU *cpu = POWERPC_CPU(cs);
492 CPUPPCState *env = &cpu->env;
493 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
494 int index = spapr_vcpu_id(cpu);
495 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
496 0xffffffff, 0xffffffff};
497 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
498 : SPAPR_TIMEBASE_FREQ;
499 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
500 uint32_t page_sizes_prop[64];
501 size_t page_sizes_prop_size;
502 uint32_t vcpus_per_socket = smp_threads * smp_cores;
503 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
504 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
505 sPAPRDRConnector *drc;
506 int drc_index;
507 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
508 int i;
509
510 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
511 if (drc) {
512 drc_index = spapr_drc_index(drc);
513 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
514 }
515
516 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
517 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
518
519 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
520 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
521 env->dcache_line_size)));
522 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
523 env->dcache_line_size)));
524 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
525 env->icache_line_size)));
526 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
527 env->icache_line_size)));
528
529 if (pcc->l1_dcache_size) {
530 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
531 pcc->l1_dcache_size)));
532 } else {
533 warn_report("Unknown L1 dcache size for cpu");
534 }
535 if (pcc->l1_icache_size) {
536 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
537 pcc->l1_icache_size)));
538 } else {
539 warn_report("Unknown L1 icache size for cpu");
540 }
541
542 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
543 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
544 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
545 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
546 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
547 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
548
549 if (env->spr_cb[SPR_PURR].oea_read) {
550 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
551 }
552
553 if (env->mmu_model & POWERPC_MMU_1TSEG) {
554 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
555 segs, sizeof(segs))));
556 }
557
558 /* Advertise VMX/VSX (vector extensions) if available
559 * 0 / no property == no vector extensions
560 * 1 == VMX / Altivec available
561 * 2 == VSX available */
562 if (env->insns_flags & PPC_ALTIVEC) {
563 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
564
565 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
566 }
567
568 /* Advertise DFP (Decimal Floating Point) if available
569 * 0 / no property == no DFP
570 * 1 == DFP available */
571 if (env->insns_flags2 & PPC2_DFP) {
572 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
573 }
574
575 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
576 sizeof(page_sizes_prop));
577 if (page_sizes_prop_size) {
578 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
579 page_sizes_prop, page_sizes_prop_size)));
580 }
581
582 spapr_populate_pa_features(env, fdt, offset, false);
583
584 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
585 cs->cpu_index / vcpus_per_socket)));
586
587 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
588 pft_size_prop, sizeof(pft_size_prop))));
589
590 if (nb_numa_nodes > 1) {
591 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
592 }
593
594 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
595
596 if (pcc->radix_page_info) {
597 for (i = 0; i < pcc->radix_page_info->count; i++) {
598 radix_AP_encodings[i] =
599 cpu_to_be32(pcc->radix_page_info->entries[i]);
600 }
601 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
602 radix_AP_encodings,
603 pcc->radix_page_info->count *
604 sizeof(radix_AP_encodings[0]))));
605 }
606 }
607
608 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
609 {
610 CPUState *cs;
611 int cpus_offset;
612 char *nodename;
613 int smt = kvmppc_smt_threads();
614
615 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
616 _FDT(cpus_offset);
617 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
618 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
619
620 /*
621 * We walk the CPUs in reverse order to ensure that CPU DT nodes
622 * created by fdt_add_subnode() end up in the right order in FDT
623 * for the guest kernel the enumerate the CPUs correctly.
624 */
625 CPU_FOREACH_REVERSE(cs) {
626 PowerPCCPU *cpu = POWERPC_CPU(cs);
627 int index = spapr_vcpu_id(cpu);
628 DeviceClass *dc = DEVICE_GET_CLASS(cs);
629 int offset;
630
631 if ((index % smt) != 0) {
632 continue;
633 }
634
635 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
636 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
637 g_free(nodename);
638 _FDT(offset);
639 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
640 }
641
642 }
643
644 /*
645 * Adds ibm,dynamic-reconfiguration-memory node.
646 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
647 * of this device tree node.
648 */
649 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
650 {
651 MachineState *machine = MACHINE(spapr);
652 int ret, i, offset;
653 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
654 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
655 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
656 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
657 memory_region_size(&spapr->hotplug_memory.mr)) /
658 lmb_size;
659 uint32_t *int_buf, *cur_index, buf_len;
660 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
661
662 /*
663 * Don't create the node if there is no hotpluggable memory
664 */
665 if (machine->ram_size == machine->maxram_size) {
666 return 0;
667 }
668
669 /*
670 * Allocate enough buffer size to fit in ibm,dynamic-memory
671 * or ibm,associativity-lookup-arrays
672 */
673 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
674 * sizeof(uint32_t);
675 cur_index = int_buf = g_malloc0(buf_len);
676
677 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
678
679 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
680 sizeof(prop_lmb_size));
681 if (ret < 0) {
682 goto out;
683 }
684
685 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
686 if (ret < 0) {
687 goto out;
688 }
689
690 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
691 if (ret < 0) {
692 goto out;
693 }
694
695 /* ibm,dynamic-memory */
696 int_buf[0] = cpu_to_be32(nr_lmbs);
697 cur_index++;
698 for (i = 0; i < nr_lmbs; i++) {
699 uint64_t addr = i * lmb_size;
700 uint32_t *dynamic_memory = cur_index;
701
702 if (i >= hotplug_lmb_start) {
703 sPAPRDRConnector *drc;
704
705 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
706 g_assert(drc);
707
708 dynamic_memory[0] = cpu_to_be32(addr >> 32);
709 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
710 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
711 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
712 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
713 if (memory_region_present(get_system_memory(), addr)) {
714 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
715 } else {
716 dynamic_memory[5] = cpu_to_be32(0);
717 }
718 } else {
719 /*
720 * LMB information for RMA, boot time RAM and gap b/n RAM and
721 * hotplug memory region -- all these are marked as reserved
722 * and as having no valid DRC.
723 */
724 dynamic_memory[0] = cpu_to_be32(addr >> 32);
725 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
726 dynamic_memory[2] = cpu_to_be32(0);
727 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
728 dynamic_memory[4] = cpu_to_be32(-1);
729 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
730 SPAPR_LMB_FLAGS_DRC_INVALID);
731 }
732
733 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
734 }
735 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
736 if (ret < 0) {
737 goto out;
738 }
739
740 /* ibm,associativity-lookup-arrays */
741 cur_index = int_buf;
742 int_buf[0] = cpu_to_be32(nr_nodes);
743 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
744 cur_index += 2;
745 for (i = 0; i < nr_nodes; i++) {
746 uint32_t associativity[] = {
747 cpu_to_be32(0x0),
748 cpu_to_be32(0x0),
749 cpu_to_be32(0x0),
750 cpu_to_be32(i)
751 };
752 memcpy(cur_index, associativity, sizeof(associativity));
753 cur_index += 4;
754 }
755 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
756 (cur_index - int_buf) * sizeof(uint32_t));
757 out:
758 g_free(int_buf);
759 return ret;
760 }
761
762 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
763 sPAPROptionVector *ov5_updates)
764 {
765 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
766 int ret = 0, offset;
767
768 /* Generate ibm,dynamic-reconfiguration-memory node if required */
769 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
770 g_assert(smc->dr_lmb_enabled);
771 ret = spapr_populate_drconf_memory(spapr, fdt);
772 if (ret) {
773 goto out;
774 }
775 }
776
777 offset = fdt_path_offset(fdt, "/chosen");
778 if (offset < 0) {
779 offset = fdt_add_subnode(fdt, 0, "chosen");
780 if (offset < 0) {
781 return offset;
782 }
783 }
784 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
785 "ibm,architecture-vec-5");
786
787 out:
788 return ret;
789 }
790
791 static bool spapr_hotplugged_dev_before_cas(void)
792 {
793 Object *drc_container, *obj;
794 ObjectProperty *prop;
795 ObjectPropertyIterator iter;
796
797 drc_container = container_get(object_get_root(), "/dr-connector");
798 object_property_iter_init(&iter, drc_container);
799 while ((prop = object_property_iter_next(&iter))) {
800 if (!strstart(prop->type, "link<", NULL)) {
801 continue;
802 }
803 obj = object_property_get_link(drc_container, prop->name, NULL);
804 if (spapr_drc_needed(obj)) {
805 return true;
806 }
807 }
808 return false;
809 }
810
811 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
812 target_ulong addr, target_ulong size,
813 sPAPROptionVector *ov5_updates)
814 {
815 void *fdt, *fdt_skel;
816 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
817
818 if (spapr_hotplugged_dev_before_cas()) {
819 return 1;
820 }
821
822 if (size < sizeof(hdr) || size > FW_MAX_SIZE) {
823 error_report("SLOF provided an unexpected CAS buffer size "
824 TARGET_FMT_lu " (min: %zu, max: %u)",
825 size, sizeof(hdr), FW_MAX_SIZE);
826 exit(EXIT_FAILURE);
827 }
828
829 size -= sizeof(hdr);
830
831 /* Create skeleton */
832 fdt_skel = g_malloc0(size);
833 _FDT((fdt_create(fdt_skel, size)));
834 _FDT((fdt_begin_node(fdt_skel, "")));
835 _FDT((fdt_end_node(fdt_skel)));
836 _FDT((fdt_finish(fdt_skel)));
837 fdt = g_malloc0(size);
838 _FDT((fdt_open_into(fdt_skel, fdt, size)));
839 g_free(fdt_skel);
840
841 /* Fixup cpu nodes */
842 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
843
844 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
845 return -1;
846 }
847
848 /* Pack resulting tree */
849 _FDT((fdt_pack(fdt)));
850
851 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
852 trace_spapr_cas_failed(size);
853 return -1;
854 }
855
856 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
857 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
858 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
859 g_free(fdt);
860
861 return 0;
862 }
863
864 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
865 {
866 int rtas;
867 GString *hypertas = g_string_sized_new(256);
868 GString *qemu_hypertas = g_string_sized_new(256);
869 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
870 uint64_t max_hotplug_addr = spapr->hotplug_memory.base +
871 memory_region_size(&spapr->hotplug_memory.mr);
872 uint32_t lrdr_capacity[] = {
873 cpu_to_be32(max_hotplug_addr >> 32),
874 cpu_to_be32(max_hotplug_addr & 0xffffffff),
875 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
876 cpu_to_be32(max_cpus / smp_threads),
877 };
878
879 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
880
881 /* hypertas */
882 add_str(hypertas, "hcall-pft");
883 add_str(hypertas, "hcall-term");
884 add_str(hypertas, "hcall-dabr");
885 add_str(hypertas, "hcall-interrupt");
886 add_str(hypertas, "hcall-tce");
887 add_str(hypertas, "hcall-vio");
888 add_str(hypertas, "hcall-splpar");
889 add_str(hypertas, "hcall-bulk");
890 add_str(hypertas, "hcall-set-mode");
891 add_str(hypertas, "hcall-sprg0");
892 add_str(hypertas, "hcall-copy");
893 add_str(hypertas, "hcall-debug");
894 add_str(qemu_hypertas, "hcall-memop1");
895
896 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
897 add_str(hypertas, "hcall-multi-tce");
898 }
899
900 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
901 add_str(hypertas, "hcall-hpt-resize");
902 }
903
904 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
905 hypertas->str, hypertas->len));
906 g_string_free(hypertas, TRUE);
907 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
908 qemu_hypertas->str, qemu_hypertas->len));
909 g_string_free(qemu_hypertas, TRUE);
910
911 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
912 refpoints, sizeof(refpoints)));
913
914 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
915 RTAS_ERROR_LOG_MAX));
916 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
917 RTAS_EVENT_SCAN_RATE));
918
919 if (msi_nonbroken) {
920 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
921 }
922
923 /*
924 * According to PAPR, rtas ibm,os-term does not guarantee a return
925 * back to the guest cpu.
926 *
927 * While an additional ibm,extended-os-term property indicates
928 * that rtas call return will always occur. Set this property.
929 */
930 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
931
932 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
933 lrdr_capacity, sizeof(lrdr_capacity)));
934
935 spapr_dt_rtas_tokens(fdt, rtas);
936 }
937
938 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features
939 * that the guest may request and thus the valid values for bytes 24..26 of
940 * option vector 5: */
941 static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
942 {
943 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
944
945 char val[2 * 4] = {
946 23, 0x00, /* Xive mode, filled in below. */
947 24, 0x00, /* Hash/Radix, filled in below. */
948 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
949 26, 0x40, /* Radix options: GTSE == yes. */
950 };
951
952 if (kvm_enabled()) {
953 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
954 val[3] = 0x80; /* OV5_MMU_BOTH */
955 } else if (kvmppc_has_cap_mmu_radix()) {
956 val[3] = 0x40; /* OV5_MMU_RADIX_300 */
957 } else {
958 val[3] = 0x00; /* Hash */
959 }
960 } else {
961 if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) {
962 /* V3 MMU supports both hash and radix (with dynamic switching) */
963 val[3] = 0xC0;
964 } else {
965 /* Otherwise we can only do hash */
966 val[3] = 0x00;
967 }
968 }
969 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
970 val, sizeof(val)));
971 }
972
973 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
974 {
975 MachineState *machine = MACHINE(spapr);
976 int chosen;
977 const char *boot_device = machine->boot_order;
978 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
979 size_t cb = 0;
980 char *bootlist = get_boot_devices_list(&cb, true);
981
982 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
983
984 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
985 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
986 spapr->initrd_base));
987 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
988 spapr->initrd_base + spapr->initrd_size));
989
990 if (spapr->kernel_size) {
991 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
992 cpu_to_be64(spapr->kernel_size) };
993
994 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
995 &kprop, sizeof(kprop)));
996 if (spapr->kernel_le) {
997 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
998 }
999 }
1000 if (boot_menu) {
1001 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1002 }
1003 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1004 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1005 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1006
1007 if (cb && bootlist) {
1008 int i;
1009
1010 for (i = 0; i < cb; i++) {
1011 if (bootlist[i] == '\n') {
1012 bootlist[i] = ' ';
1013 }
1014 }
1015 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1016 }
1017
1018 if (boot_device && strlen(boot_device)) {
1019 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1020 }
1021
1022 if (!spapr->has_graphics && stdout_path) {
1023 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1024 }
1025
1026 spapr_dt_ov5_platform_support(fdt, chosen);
1027
1028 g_free(stdout_path);
1029 g_free(bootlist);
1030 }
1031
1032 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
1033 {
1034 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1035 * KVM to work under pHyp with some guest co-operation */
1036 int hypervisor;
1037 uint8_t hypercall[16];
1038
1039 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1040 /* indicate KVM hypercall interface */
1041 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1042 if (kvmppc_has_cap_fixup_hcalls()) {
1043 /*
1044 * Older KVM versions with older guest kernels were broken
1045 * with the magic page, don't allow the guest to map it.
1046 */
1047 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1048 sizeof(hypercall))) {
1049 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1050 hypercall, sizeof(hypercall)));
1051 }
1052 }
1053 }
1054
1055 static void *spapr_build_fdt(sPAPRMachineState *spapr,
1056 hwaddr rtas_addr,
1057 hwaddr rtas_size)
1058 {
1059 MachineState *machine = MACHINE(spapr);
1060 MachineClass *mc = MACHINE_GET_CLASS(machine);
1061 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1062 int ret;
1063 void *fdt;
1064 sPAPRPHBState *phb;
1065 char *buf;
1066
1067 fdt = g_malloc0(FDT_MAX_SIZE);
1068 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
1069
1070 /* Root node */
1071 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1072 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1073 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1074
1075 /*
1076 * Add info to guest to indentify which host is it being run on
1077 * and what is the uuid of the guest
1078 */
1079 if (kvmppc_get_host_model(&buf)) {
1080 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1081 g_free(buf);
1082 }
1083 if (kvmppc_get_host_serial(&buf)) {
1084 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1085 g_free(buf);
1086 }
1087
1088 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1089
1090 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1091 if (qemu_uuid_set) {
1092 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1093 }
1094 g_free(buf);
1095
1096 if (qemu_get_vm_name()) {
1097 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1098 qemu_get_vm_name()));
1099 }
1100
1101 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1102 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1103
1104 /* /interrupt controller */
1105 spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP);
1106
1107 ret = spapr_populate_memory(spapr, fdt);
1108 if (ret < 0) {
1109 error_report("couldn't setup memory nodes in fdt");
1110 exit(1);
1111 }
1112
1113 /* /vdevice */
1114 spapr_dt_vdevice(spapr->vio_bus, fdt);
1115
1116 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1117 ret = spapr_rng_populate_dt(fdt);
1118 if (ret < 0) {
1119 error_report("could not set up rng device in the fdt");
1120 exit(1);
1121 }
1122 }
1123
1124 QLIST_FOREACH(phb, &spapr->phbs, list) {
1125 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
1126 if (ret < 0) {
1127 error_report("couldn't setup PCI devices in fdt");
1128 exit(1);
1129 }
1130 }
1131
1132 /* cpus */
1133 spapr_populate_cpus_dt_node(fdt, spapr);
1134
1135 if (smc->dr_lmb_enabled) {
1136 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1137 }
1138
1139 if (mc->has_hotpluggable_cpus) {
1140 int offset = fdt_path_offset(fdt, "/cpus");
1141 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1142 SPAPR_DR_CONNECTOR_TYPE_CPU);
1143 if (ret < 0) {
1144 error_report("Couldn't set up CPU DR device tree properties");
1145 exit(1);
1146 }
1147 }
1148
1149 /* /event-sources */
1150 spapr_dt_events(spapr, fdt);
1151
1152 /* /rtas */
1153 spapr_dt_rtas(spapr, fdt);
1154
1155 /* /chosen */
1156 spapr_dt_chosen(spapr, fdt);
1157
1158 /* /hypervisor */
1159 if (kvm_enabled()) {
1160 spapr_dt_hypervisor(spapr, fdt);
1161 }
1162
1163 /* Build memory reserve map */
1164 if (spapr->kernel_size) {
1165 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1166 }
1167 if (spapr->initrd_size) {
1168 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1169 }
1170
1171 /* ibm,client-architecture-support updates */
1172 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1173 if (ret < 0) {
1174 error_report("couldn't setup CAS properties fdt");
1175 exit(1);
1176 }
1177
1178 return fdt;
1179 }
1180
1181 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1182 {
1183 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1184 }
1185
1186 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1187 PowerPCCPU *cpu)
1188 {
1189 CPUPPCState *env = &cpu->env;
1190
1191 /* The TCG path should also be holding the BQL at this point */
1192 g_assert(qemu_mutex_iothread_locked());
1193
1194 if (msr_pr) {
1195 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1196 env->gpr[3] = H_PRIVILEGE;
1197 } else {
1198 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1199 }
1200 }
1201
1202 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
1203 {
1204 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1205
1206 return spapr->patb_entry;
1207 }
1208
1209 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1210 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1211 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1212 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1213 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1214
1215 /*
1216 * Get the fd to access the kernel htab, re-opening it if necessary
1217 */
1218 static int get_htab_fd(sPAPRMachineState *spapr)
1219 {
1220 Error *local_err = NULL;
1221
1222 if (spapr->htab_fd >= 0) {
1223 return spapr->htab_fd;
1224 }
1225
1226 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1227 if (spapr->htab_fd < 0) {
1228 error_report_err(local_err);
1229 }
1230
1231 return spapr->htab_fd;
1232 }
1233
1234 void close_htab_fd(sPAPRMachineState *spapr)
1235 {
1236 if (spapr->htab_fd >= 0) {
1237 close(spapr->htab_fd);
1238 }
1239 spapr->htab_fd = -1;
1240 }
1241
1242 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1243 {
1244 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1245
1246 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1247 }
1248
1249 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1250 {
1251 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1252
1253 assert(kvm_enabled());
1254
1255 if (!spapr->htab) {
1256 return 0;
1257 }
1258
1259 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1260 }
1261
1262 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1263 hwaddr ptex, int n)
1264 {
1265 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1266 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1267
1268 if (!spapr->htab) {
1269 /*
1270 * HTAB is controlled by KVM. Fetch into temporary buffer
1271 */
1272 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1273 kvmppc_read_hptes(hptes, ptex, n);
1274 return hptes;
1275 }
1276
1277 /*
1278 * HTAB is controlled by QEMU. Just point to the internally
1279 * accessible PTEG.
1280 */
1281 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1282 }
1283
1284 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1285 const ppc_hash_pte64_t *hptes,
1286 hwaddr ptex, int n)
1287 {
1288 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1289
1290 if (!spapr->htab) {
1291 g_free((void *)hptes);
1292 }
1293
1294 /* Nothing to do for qemu managed HPT */
1295 }
1296
1297 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1298 uint64_t pte0, uint64_t pte1)
1299 {
1300 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1301 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1302
1303 if (!spapr->htab) {
1304 kvmppc_write_hpte(ptex, pte0, pte1);
1305 } else {
1306 stq_p(spapr->htab + offset, pte0);
1307 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1308 }
1309 }
1310
1311 int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1312 {
1313 int shift;
1314
1315 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1316 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1317 * that's much more than is needed for Linux guests */
1318 shift = ctz64(pow2ceil(ramsize)) - 7;
1319 shift = MAX(shift, 18); /* Minimum architected size */
1320 shift = MIN(shift, 46); /* Maximum architected size */
1321 return shift;
1322 }
1323
1324 void spapr_free_hpt(sPAPRMachineState *spapr)
1325 {
1326 g_free(spapr->htab);
1327 spapr->htab = NULL;
1328 spapr->htab_shift = 0;
1329 close_htab_fd(spapr);
1330 }
1331
1332 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1333 Error **errp)
1334 {
1335 long rc;
1336
1337 /* Clean up any HPT info from a previous boot */
1338 spapr_free_hpt(spapr);
1339
1340 rc = kvmppc_reset_htab(shift);
1341 if (rc < 0) {
1342 /* kernel-side HPT needed, but couldn't allocate one */
1343 error_setg_errno(errp, errno,
1344 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1345 shift);
1346 /* This is almost certainly fatal, but if the caller really
1347 * wants to carry on with shift == 0, it's welcome to try */
1348 } else if (rc > 0) {
1349 /* kernel-side HPT allocated */
1350 if (rc != shift) {
1351 error_setg(errp,
1352 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1353 shift, rc);
1354 }
1355
1356 spapr->htab_shift = shift;
1357 spapr->htab = NULL;
1358 } else {
1359 /* kernel-side HPT not needed, allocate in userspace instead */
1360 size_t size = 1ULL << shift;
1361 int i;
1362
1363 spapr->htab = qemu_memalign(size, size);
1364 if (!spapr->htab) {
1365 error_setg_errno(errp, errno,
1366 "Could not allocate HPT of order %d", shift);
1367 return;
1368 }
1369
1370 memset(spapr->htab, 0, size);
1371 spapr->htab_shift = shift;
1372
1373 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1374 DIRTY_HPTE(HPTE(spapr->htab, i));
1375 }
1376 }
1377 }
1378
1379 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr)
1380 {
1381 int hpt_shift;
1382
1383 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1384 || (spapr->cas_reboot
1385 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1386 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1387 } else {
1388 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->ram_size);
1389 }
1390 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1391
1392 if (spapr->vrma_adjust) {
1393 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)),
1394 spapr->htab_shift);
1395 }
1396 /* We're setting up a hash table, so that means we're not radix */
1397 spapr->patb_entry = 0;
1398 }
1399
1400 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1401 {
1402 bool matched = false;
1403
1404 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1405 matched = true;
1406 }
1407
1408 if (!matched) {
1409 error_report("Device %s is not supported by this machine yet.",
1410 qdev_fw_name(DEVICE(sbdev)));
1411 exit(1);
1412 }
1413 }
1414
1415 static void ppc_spapr_reset(void)
1416 {
1417 MachineState *machine = MACHINE(qdev_get_machine());
1418 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1419 PowerPCCPU *first_ppc_cpu;
1420 uint32_t rtas_limit;
1421 hwaddr rtas_addr, fdt_addr;
1422 void *fdt;
1423 int rc;
1424
1425 /* Check for unknown sysbus devices */
1426 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1427
1428 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) {
1429 /* If using KVM with radix mode available, VCPUs can be started
1430 * without a HPT because KVM will start them in radix mode.
1431 * Set the GR bit in PATB so that we know there is no HPT. */
1432 spapr->patb_entry = PATBE1_GR;
1433 } else {
1434 spapr_setup_hpt_and_vrma(spapr);
1435 }
1436
1437 qemu_devices_reset();
1438 spapr_clear_pending_events(spapr);
1439
1440 /*
1441 * We place the device tree and RTAS just below either the top of the RMA,
1442 * or just below 2GB, whichever is lowere, so that it can be
1443 * processed with 32-bit real mode code if necessary
1444 */
1445 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1446 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1447 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1448
1449 /* if this reset wasn't generated by CAS, we should reset our
1450 * negotiated options and start from scratch */
1451 if (!spapr->cas_reboot) {
1452 spapr_ovec_cleanup(spapr->ov5_cas);
1453 spapr->ov5_cas = spapr_ovec_new();
1454
1455 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
1456 }
1457
1458 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1459
1460 spapr_load_rtas(spapr, fdt, rtas_addr);
1461
1462 rc = fdt_pack(fdt);
1463
1464 /* Should only fail if we've built a corrupted tree */
1465 assert(rc == 0);
1466
1467 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1468 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1469 fdt_totalsize(fdt), FDT_MAX_SIZE);
1470 exit(1);
1471 }
1472
1473 /* Load the fdt */
1474 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1475 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1476 g_free(fdt);
1477
1478 /* Set up the entry state */
1479 first_ppc_cpu = POWERPC_CPU(first_cpu);
1480 first_ppc_cpu->env.gpr[3] = fdt_addr;
1481 first_ppc_cpu->env.gpr[5] = 0;
1482 first_cpu->halted = 0;
1483 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1484
1485 spapr->cas_reboot = false;
1486 }
1487
1488 static void spapr_create_nvram(sPAPRMachineState *spapr)
1489 {
1490 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1491 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1492
1493 if (dinfo) {
1494 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1495 &error_fatal);
1496 }
1497
1498 qdev_init_nofail(dev);
1499
1500 spapr->nvram = (struct sPAPRNVRAM *)dev;
1501 }
1502
1503 static void spapr_rtc_create(sPAPRMachineState *spapr)
1504 {
1505 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC);
1506 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc),
1507 &error_fatal);
1508 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1509 &error_fatal);
1510 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1511 "date", &error_fatal);
1512 }
1513
1514 /* Returns whether we want to use VGA or not */
1515 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1516 {
1517 switch (vga_interface_type) {
1518 case VGA_NONE:
1519 return false;
1520 case VGA_DEVICE:
1521 return true;
1522 case VGA_STD:
1523 case VGA_VIRTIO:
1524 return pci_vga_init(pci_bus) != NULL;
1525 default:
1526 error_setg(errp,
1527 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1528 return false;
1529 }
1530 }
1531
1532 static int spapr_post_load(void *opaque, int version_id)
1533 {
1534 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1535 int err = 0;
1536
1537 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
1538 CPUState *cs;
1539 CPU_FOREACH(cs) {
1540 PowerPCCPU *cpu = POWERPC_CPU(cs);
1541 icp_resend(ICP(cpu->intc));
1542 }
1543 }
1544
1545 /* In earlier versions, there was no separate qdev for the PAPR
1546 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1547 * So when migrating from those versions, poke the incoming offset
1548 * value into the RTC device */
1549 if (version_id < 3) {
1550 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1551 }
1552
1553 if (spapr->patb_entry) {
1554 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1555 bool radix = !!(spapr->patb_entry & PATBE1_GR);
1556 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1557
1558 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1559 if (err) {
1560 error_report("Process table config unsupported by the host");
1561 return -EINVAL;
1562 }
1563 }
1564
1565 return err;
1566 }
1567
1568 static bool version_before_3(void *opaque, int version_id)
1569 {
1570 return version_id < 3;
1571 }
1572
1573 static bool spapr_pending_events_needed(void *opaque)
1574 {
1575 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1576 return !QTAILQ_EMPTY(&spapr->pending_events);
1577 }
1578
1579 static const VMStateDescription vmstate_spapr_event_entry = {
1580 .name = "spapr_event_log_entry",
1581 .version_id = 1,
1582 .minimum_version_id = 1,
1583 .fields = (VMStateField[]) {
1584 VMSTATE_UINT32(summary, sPAPREventLogEntry),
1585 VMSTATE_UINT32(extended_length, sPAPREventLogEntry),
1586 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0,
1587 NULL, extended_length),
1588 VMSTATE_END_OF_LIST()
1589 },
1590 };
1591
1592 static const VMStateDescription vmstate_spapr_pending_events = {
1593 .name = "spapr_pending_events",
1594 .version_id = 1,
1595 .minimum_version_id = 1,
1596 .needed = spapr_pending_events_needed,
1597 .fields = (VMStateField[]) {
1598 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1,
1599 vmstate_spapr_event_entry, sPAPREventLogEntry, next),
1600 VMSTATE_END_OF_LIST()
1601 },
1602 };
1603
1604 static bool spapr_ov5_cas_needed(void *opaque)
1605 {
1606 sPAPRMachineState *spapr = opaque;
1607 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1608 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1609 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1610 bool cas_needed;
1611
1612 /* Prior to the introduction of sPAPROptionVector, we had two option
1613 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1614 * Both of these options encode machine topology into the device-tree
1615 * in such a way that the now-booted OS should still be able to interact
1616 * appropriately with QEMU regardless of what options were actually
1617 * negotiatied on the source side.
1618 *
1619 * As such, we can avoid migrating the CAS-negotiated options if these
1620 * are the only options available on the current machine/platform.
1621 * Since these are the only options available for pseries-2.7 and
1622 * earlier, this allows us to maintain old->new/new->old migration
1623 * compatibility.
1624 *
1625 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1626 * via default pseries-2.8 machines and explicit command-line parameters.
1627 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1628 * of the actual CAS-negotiated values to continue working properly. For
1629 * example, availability of memory unplug depends on knowing whether
1630 * OV5_HP_EVT was negotiated via CAS.
1631 *
1632 * Thus, for any cases where the set of available CAS-negotiatable
1633 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1634 * include the CAS-negotiated options in the migration stream.
1635 */
1636 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1637 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1638
1639 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1640 * the mask itself since in the future it's possible "legacy" bits may be
1641 * removed via machine options, which could generate a false positive
1642 * that breaks migration.
1643 */
1644 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1645 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1646
1647 spapr_ovec_cleanup(ov5_mask);
1648 spapr_ovec_cleanup(ov5_legacy);
1649 spapr_ovec_cleanup(ov5_removed);
1650
1651 return cas_needed;
1652 }
1653
1654 static const VMStateDescription vmstate_spapr_ov5_cas = {
1655 .name = "spapr_option_vector_ov5_cas",
1656 .version_id = 1,
1657 .minimum_version_id = 1,
1658 .needed = spapr_ov5_cas_needed,
1659 .fields = (VMStateField[]) {
1660 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1661 vmstate_spapr_ovec, sPAPROptionVector),
1662 VMSTATE_END_OF_LIST()
1663 },
1664 };
1665
1666 static bool spapr_patb_entry_needed(void *opaque)
1667 {
1668 sPAPRMachineState *spapr = opaque;
1669
1670 return !!spapr->patb_entry;
1671 }
1672
1673 static const VMStateDescription vmstate_spapr_patb_entry = {
1674 .name = "spapr_patb_entry",
1675 .version_id = 1,
1676 .minimum_version_id = 1,
1677 .needed = spapr_patb_entry_needed,
1678 .fields = (VMStateField[]) {
1679 VMSTATE_UINT64(patb_entry, sPAPRMachineState),
1680 VMSTATE_END_OF_LIST()
1681 },
1682 };
1683
1684 static const VMStateDescription vmstate_spapr = {
1685 .name = "spapr",
1686 .version_id = 3,
1687 .minimum_version_id = 1,
1688 .post_load = spapr_post_load,
1689 .fields = (VMStateField[]) {
1690 /* used to be @next_irq */
1691 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1692
1693 /* RTC offset */
1694 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1695
1696 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1697 VMSTATE_END_OF_LIST()
1698 },
1699 .subsections = (const VMStateDescription*[]) {
1700 &vmstate_spapr_ov5_cas,
1701 &vmstate_spapr_patb_entry,
1702 &vmstate_spapr_pending_events,
1703 NULL
1704 }
1705 };
1706
1707 static int htab_save_setup(QEMUFile *f, void *opaque)
1708 {
1709 sPAPRMachineState *spapr = opaque;
1710
1711 /* "Iteration" header */
1712 if (!spapr->htab_shift) {
1713 qemu_put_be32(f, -1);
1714 } else {
1715 qemu_put_be32(f, spapr->htab_shift);
1716 }
1717
1718 if (spapr->htab) {
1719 spapr->htab_save_index = 0;
1720 spapr->htab_first_pass = true;
1721 } else {
1722 if (spapr->htab_shift) {
1723 assert(kvm_enabled());
1724 }
1725 }
1726
1727
1728 return 0;
1729 }
1730
1731 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr,
1732 int chunkstart, int n_valid, int n_invalid)
1733 {
1734 qemu_put_be32(f, chunkstart);
1735 qemu_put_be16(f, n_valid);
1736 qemu_put_be16(f, n_invalid);
1737 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1738 HASH_PTE_SIZE_64 * n_valid);
1739 }
1740
1741 static void htab_save_end_marker(QEMUFile *f)
1742 {
1743 qemu_put_be32(f, 0);
1744 qemu_put_be16(f, 0);
1745 qemu_put_be16(f, 0);
1746 }
1747
1748 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1749 int64_t max_ns)
1750 {
1751 bool has_timeout = max_ns != -1;
1752 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1753 int index = spapr->htab_save_index;
1754 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1755
1756 assert(spapr->htab_first_pass);
1757
1758 do {
1759 int chunkstart;
1760
1761 /* Consume invalid HPTEs */
1762 while ((index < htabslots)
1763 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1764 CLEAN_HPTE(HPTE(spapr->htab, index));
1765 index++;
1766 }
1767
1768 /* Consume valid HPTEs */
1769 chunkstart = index;
1770 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1771 && HPTE_VALID(HPTE(spapr->htab, index))) {
1772 CLEAN_HPTE(HPTE(spapr->htab, index));
1773 index++;
1774 }
1775
1776 if (index > chunkstart) {
1777 int n_valid = index - chunkstart;
1778
1779 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
1780
1781 if (has_timeout &&
1782 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1783 break;
1784 }
1785 }
1786 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1787
1788 if (index >= htabslots) {
1789 assert(index == htabslots);
1790 index = 0;
1791 spapr->htab_first_pass = false;
1792 }
1793 spapr->htab_save_index = index;
1794 }
1795
1796 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1797 int64_t max_ns)
1798 {
1799 bool final = max_ns < 0;
1800 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1801 int examined = 0, sent = 0;
1802 int index = spapr->htab_save_index;
1803 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1804
1805 assert(!spapr->htab_first_pass);
1806
1807 do {
1808 int chunkstart, invalidstart;
1809
1810 /* Consume non-dirty HPTEs */
1811 while ((index < htabslots)
1812 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1813 index++;
1814 examined++;
1815 }
1816
1817 chunkstart = index;
1818 /* Consume valid dirty HPTEs */
1819 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1820 && HPTE_DIRTY(HPTE(spapr->htab, index))
1821 && HPTE_VALID(HPTE(spapr->htab, index))) {
1822 CLEAN_HPTE(HPTE(spapr->htab, index));
1823 index++;
1824 examined++;
1825 }
1826
1827 invalidstart = index;
1828 /* Consume invalid dirty HPTEs */
1829 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1830 && HPTE_DIRTY(HPTE(spapr->htab, index))
1831 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1832 CLEAN_HPTE(HPTE(spapr->htab, index));
1833 index++;
1834 examined++;
1835 }
1836
1837 if (index > chunkstart) {
1838 int n_valid = invalidstart - chunkstart;
1839 int n_invalid = index - invalidstart;
1840
1841 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
1842 sent += index - chunkstart;
1843
1844 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1845 break;
1846 }
1847 }
1848
1849 if (examined >= htabslots) {
1850 break;
1851 }
1852
1853 if (index >= htabslots) {
1854 assert(index == htabslots);
1855 index = 0;
1856 }
1857 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1858
1859 if (index >= htabslots) {
1860 assert(index == htabslots);
1861 index = 0;
1862 }
1863
1864 spapr->htab_save_index = index;
1865
1866 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1867 }
1868
1869 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1870 #define MAX_KVM_BUF_SIZE 2048
1871
1872 static int htab_save_iterate(QEMUFile *f, void *opaque)
1873 {
1874 sPAPRMachineState *spapr = opaque;
1875 int fd;
1876 int rc = 0;
1877
1878 /* Iteration header */
1879 if (!spapr->htab_shift) {
1880 qemu_put_be32(f, -1);
1881 return 1;
1882 } else {
1883 qemu_put_be32(f, 0);
1884 }
1885
1886 if (!spapr->htab) {
1887 assert(kvm_enabled());
1888
1889 fd = get_htab_fd(spapr);
1890 if (fd < 0) {
1891 return fd;
1892 }
1893
1894 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1895 if (rc < 0) {
1896 return rc;
1897 }
1898 } else if (spapr->htab_first_pass) {
1899 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1900 } else {
1901 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1902 }
1903
1904 htab_save_end_marker(f);
1905
1906 return rc;
1907 }
1908
1909 static int htab_save_complete(QEMUFile *f, void *opaque)
1910 {
1911 sPAPRMachineState *spapr = opaque;
1912 int fd;
1913
1914 /* Iteration header */
1915 if (!spapr->htab_shift) {
1916 qemu_put_be32(f, -1);
1917 return 0;
1918 } else {
1919 qemu_put_be32(f, 0);
1920 }
1921
1922 if (!spapr->htab) {
1923 int rc;
1924
1925 assert(kvm_enabled());
1926
1927 fd = get_htab_fd(spapr);
1928 if (fd < 0) {
1929 return fd;
1930 }
1931
1932 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1933 if (rc < 0) {
1934 return rc;
1935 }
1936 } else {
1937 if (spapr->htab_first_pass) {
1938 htab_save_first_pass(f, spapr, -1);
1939 }
1940 htab_save_later_pass(f, spapr, -1);
1941 }
1942
1943 /* End marker */
1944 htab_save_end_marker(f);
1945
1946 return 0;
1947 }
1948
1949 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1950 {
1951 sPAPRMachineState *spapr = opaque;
1952 uint32_t section_hdr;
1953 int fd = -1;
1954 Error *local_err = NULL;
1955
1956 if (version_id < 1 || version_id > 1) {
1957 error_report("htab_load() bad version");
1958 return -EINVAL;
1959 }
1960
1961 section_hdr = qemu_get_be32(f);
1962
1963 if (section_hdr == -1) {
1964 spapr_free_hpt(spapr);
1965 return 0;
1966 }
1967
1968 if (section_hdr) {
1969 /* First section gives the htab size */
1970 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1971 if (local_err) {
1972 error_report_err(local_err);
1973 return -EINVAL;
1974 }
1975 return 0;
1976 }
1977
1978 if (!spapr->htab) {
1979 assert(kvm_enabled());
1980
1981 fd = kvmppc_get_htab_fd(true, 0, &local_err);
1982 if (fd < 0) {
1983 error_report_err(local_err);
1984 return fd;
1985 }
1986 }
1987
1988 while (true) {
1989 uint32_t index;
1990 uint16_t n_valid, n_invalid;
1991
1992 index = qemu_get_be32(f);
1993 n_valid = qemu_get_be16(f);
1994 n_invalid = qemu_get_be16(f);
1995
1996 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1997 /* End of Stream */
1998 break;
1999 }
2000
2001 if ((index + n_valid + n_invalid) >
2002 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2003 /* Bad index in stream */
2004 error_report(
2005 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2006 index, n_valid, n_invalid, spapr->htab_shift);
2007 return -EINVAL;
2008 }
2009
2010 if (spapr->htab) {
2011 if (n_valid) {
2012 qemu_get_buffer(f, HPTE(spapr->htab, index),
2013 HASH_PTE_SIZE_64 * n_valid);
2014 }
2015 if (n_invalid) {
2016 memset(HPTE(spapr->htab, index + n_valid), 0,
2017 HASH_PTE_SIZE_64 * n_invalid);
2018 }
2019 } else {
2020 int rc;
2021
2022 assert(fd >= 0);
2023
2024 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2025 if (rc < 0) {
2026 return rc;
2027 }
2028 }
2029 }
2030
2031 if (!spapr->htab) {
2032 assert(fd >= 0);
2033 close(fd);
2034 }
2035
2036 return 0;
2037 }
2038
2039 static void htab_save_cleanup(void *opaque)
2040 {
2041 sPAPRMachineState *spapr = opaque;
2042
2043 close_htab_fd(spapr);
2044 }
2045
2046 static SaveVMHandlers savevm_htab_handlers = {
2047 .save_setup = htab_save_setup,
2048 .save_live_iterate = htab_save_iterate,
2049 .save_live_complete_precopy = htab_save_complete,
2050 .save_cleanup = htab_save_cleanup,
2051 .load_state = htab_load,
2052 };
2053
2054 static void spapr_boot_set(void *opaque, const char *boot_device,
2055 Error **errp)
2056 {
2057 MachineState *machine = MACHINE(opaque);
2058 machine->boot_order = g_strdup(boot_device);
2059 }
2060
2061 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
2062 {
2063 MachineState *machine = MACHINE(spapr);
2064 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2065 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2066 int i;
2067
2068 for (i = 0; i < nr_lmbs; i++) {
2069 uint64_t addr;
2070
2071 addr = i * lmb_size + spapr->hotplug_memory.base;
2072 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2073 addr / lmb_size);
2074 }
2075 }
2076
2077 /*
2078 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2079 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2080 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2081 */
2082 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2083 {
2084 int i;
2085
2086 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2087 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2088 " is not aligned to %llu MiB",
2089 machine->ram_size,
2090 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2091 return;
2092 }
2093
2094 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2095 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2096 " is not aligned to %llu MiB",
2097 machine->ram_size,
2098 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2099 return;
2100 }
2101
2102 for (i = 0; i < nb_numa_nodes; i++) {
2103 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2104 error_setg(errp,
2105 "Node %d memory size 0x%" PRIx64
2106 " is not aligned to %llu MiB",
2107 i, numa_info[i].node_mem,
2108 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2109 return;
2110 }
2111 }
2112 }
2113
2114 /* find cpu slot in machine->possible_cpus by core_id */
2115 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2116 {
2117 int index = id / smp_threads;
2118
2119 if (index >= ms->possible_cpus->len) {
2120 return NULL;
2121 }
2122 if (idx) {
2123 *idx = index;
2124 }
2125 return &ms->possible_cpus->cpus[index];
2126 }
2127
2128 static void spapr_init_cpus(sPAPRMachineState *spapr)
2129 {
2130 MachineState *machine = MACHINE(spapr);
2131 MachineClass *mc = MACHINE_GET_CLASS(machine);
2132 char *type = spapr_get_cpu_core_type(machine->cpu_model);
2133 int smt = kvmppc_smt_threads();
2134 const CPUArchIdList *possible_cpus;
2135 int boot_cores_nr = smp_cpus / smp_threads;
2136 int i;
2137
2138 if (!type) {
2139 error_report("Unable to find sPAPR CPU Core definition");
2140 exit(1);
2141 }
2142
2143 possible_cpus = mc->possible_cpu_arch_ids(machine);
2144 if (mc->has_hotpluggable_cpus) {
2145 if (smp_cpus % smp_threads) {
2146 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2147 smp_cpus, smp_threads);
2148 exit(1);
2149 }
2150 if (max_cpus % smp_threads) {
2151 error_report("max_cpus (%u) must be multiple of threads (%u)",
2152 max_cpus, smp_threads);
2153 exit(1);
2154 }
2155 } else {
2156 if (max_cpus != smp_cpus) {
2157 error_report("This machine version does not support CPU hotplug");
2158 exit(1);
2159 }
2160 boot_cores_nr = possible_cpus->len;
2161 }
2162
2163 for (i = 0; i < possible_cpus->len; i++) {
2164 int core_id = i * smp_threads;
2165
2166 if (mc->has_hotpluggable_cpus) {
2167 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2168 (core_id / smp_threads) * smt);
2169 }
2170
2171 if (i < boot_cores_nr) {
2172 Object *core = object_new(type);
2173 int nr_threads = smp_threads;
2174
2175 /* Handle the partially filled core for older machine types */
2176 if ((i + 1) * smp_threads >= smp_cpus) {
2177 nr_threads = smp_cpus - i * smp_threads;
2178 }
2179
2180 object_property_set_int(core, nr_threads, "nr-threads",
2181 &error_fatal);
2182 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2183 &error_fatal);
2184 object_property_set_bool(core, true, "realized", &error_fatal);
2185 }
2186 }
2187 g_free(type);
2188 }
2189
2190 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp)
2191 {
2192 Error *local_err = NULL;
2193 bool vsmt_user = !!spapr->vsmt;
2194 int kvm_smt = kvmppc_smt_threads();
2195 int ret;
2196
2197 if (!kvm_enabled() && (smp_threads > 1)) {
2198 error_setg(&local_err, "TCG cannot support more than 1 thread/core "
2199 "on a pseries machine");
2200 goto out;
2201 }
2202 if (!is_power_of_2(smp_threads)) {
2203 error_setg(&local_err, "Cannot support %d threads/core on a pseries "
2204 "machine because it must be a power of 2", smp_threads);
2205 goto out;
2206 }
2207
2208 /* Detemine the VSMT mode to use: */
2209 if (vsmt_user) {
2210 if (spapr->vsmt < smp_threads) {
2211 error_setg(&local_err, "Cannot support VSMT mode %d"
2212 " because it must be >= threads/core (%d)",
2213 spapr->vsmt, smp_threads);
2214 goto out;
2215 }
2216 /* In this case, spapr->vsmt has been set by the command line */
2217 } else {
2218 /* Choose a VSMT mode that may be higher than necessary but is
2219 * likely to be compatible with hosts that don't have VSMT. */
2220 spapr->vsmt = MAX(kvm_smt, smp_threads);
2221 }
2222
2223 /* KVM: If necessary, set the SMT mode: */
2224 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2225 ret = kvmppc_set_smt_threads(spapr->vsmt);
2226 if (ret) {
2227 error_setg(&local_err,
2228 "Failed to set KVM's VSMT mode to %d (errno %d)",
2229 spapr->vsmt, ret);
2230 if (!vsmt_user) {
2231 error_append_hint(&local_err, "On PPC, a VM with %d threads/"
2232 "core on a host with %d threads/core requires "
2233 " the use of VSMT mode %d.\n",
2234 smp_threads, kvm_smt, spapr->vsmt);
2235 }
2236 kvmppc_hint_smt_possible(&local_err);
2237 goto out;
2238 }
2239 }
2240 /* else TCG: nothing to do currently */
2241 out:
2242 error_propagate(errp, local_err);
2243 }
2244
2245 /* pSeries LPAR / sPAPR hardware init */
2246 static void ppc_spapr_init(MachineState *machine)
2247 {
2248 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2249 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2250 const char *kernel_filename = machine->kernel_filename;
2251 const char *initrd_filename = machine->initrd_filename;
2252 PCIHostState *phb;
2253 int i;
2254 MemoryRegion *sysmem = get_system_memory();
2255 MemoryRegion *ram = g_new(MemoryRegion, 1);
2256 MemoryRegion *rma_region;
2257 void *rma = NULL;
2258 hwaddr rma_alloc_size;
2259 hwaddr node0_size = spapr_node0_size(machine);
2260 long load_limit, fw_size;
2261 char *filename;
2262 Error *resize_hpt_err = NULL;
2263
2264 msi_nonbroken = true;
2265
2266 QLIST_INIT(&spapr->phbs);
2267 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2268
2269 /* Check HPT resizing availability */
2270 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2271 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2272 /*
2273 * If the user explicitly requested a mode we should either
2274 * supply it, or fail completely (which we do below). But if
2275 * it's not set explicitly, we reset our mode to something
2276 * that works
2277 */
2278 if (resize_hpt_err) {
2279 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2280 error_free(resize_hpt_err);
2281 resize_hpt_err = NULL;
2282 } else {
2283 spapr->resize_hpt = smc->resize_hpt_default;
2284 }
2285 }
2286
2287 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2288
2289 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2290 /*
2291 * User requested HPT resize, but this host can't supply it. Bail out
2292 */
2293 error_report_err(resize_hpt_err);
2294 exit(1);
2295 }
2296
2297 /* Allocate RMA if necessary */
2298 rma_alloc_size = kvmppc_alloc_rma(&rma);
2299
2300 if (rma_alloc_size == -1) {
2301 error_report("Unable to create RMA");
2302 exit(1);
2303 }
2304
2305 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
2306 spapr->rma_size = rma_alloc_size;
2307 } else {
2308 spapr->rma_size = node0_size;
2309
2310 /* With KVM, we don't actually know whether KVM supports an
2311 * unbounded RMA (PR KVM) or is limited by the hash table size
2312 * (HV KVM using VRMA), so we always assume the latter
2313 *
2314 * In that case, we also limit the initial allocations for RTAS
2315 * etc... to 256M since we have no way to know what the VRMA size
2316 * is going to be as it depends on the size of the hash table
2317 * isn't determined yet.
2318 */
2319 if (kvm_enabled()) {
2320 spapr->vrma_adjust = 1;
2321 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2322 }
2323
2324 /* Actually we don't support unbounded RMA anymore since we
2325 * added proper emulation of HV mode. The max we can get is
2326 * 16G which also happens to be what we configure for PAPR
2327 * mode so make sure we don't do anything bigger than that
2328 */
2329 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2330 }
2331
2332 if (spapr->rma_size > node0_size) {
2333 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2334 spapr->rma_size);
2335 exit(1);
2336 }
2337
2338 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2339 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2340
2341 /* Set up Interrupt Controller before we create the VCPUs */
2342 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal);
2343
2344 /* Set up containers for ibm,client-architecture-support negotiated options
2345 */
2346 spapr->ov5 = spapr_ovec_new();
2347 spapr->ov5_cas = spapr_ovec_new();
2348
2349 if (smc->dr_lmb_enabled) {
2350 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2351 spapr_validate_node_memory(machine, &error_fatal);
2352 }
2353
2354 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2355 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) {
2356 /* KVM and TCG always allow GTSE with radix... */
2357 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2358 }
2359 /* ... but not with hash (currently). */
2360
2361 /* advertise support for dedicated HP event source to guests */
2362 if (spapr->use_hotplug_event_source) {
2363 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2364 }
2365
2366 /* advertise support for HPT resizing */
2367 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2368 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2369 }
2370
2371 /* init CPUs */
2372 if (machine->cpu_model == NULL) {
2373 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu;
2374 }
2375
2376 cpu_parse_cpu_model(TYPE_POWERPC_CPU, machine->cpu_model);
2377
2378 spapr_set_vsmt_mode(spapr, &error_fatal);
2379
2380 spapr_init_cpus(spapr);
2381
2382 if (kvm_enabled()) {
2383 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2384 kvmppc_enable_logical_ci_hcalls();
2385 kvmppc_enable_set_mode_hcall();
2386
2387 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2388 kvmppc_enable_clear_ref_mod_hcalls();
2389 }
2390
2391 /* allocate RAM */
2392 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2393 machine->ram_size);
2394 memory_region_add_subregion(sysmem, 0, ram);
2395
2396 if (rma_alloc_size && rma) {
2397 rma_region = g_new(MemoryRegion, 1);
2398 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
2399 rma_alloc_size, rma);
2400 vmstate_register_ram_global(rma_region);
2401 memory_region_add_subregion(sysmem, 0, rma_region);
2402 }
2403
2404 /* initialize hotplug memory address space */
2405 if (machine->ram_size < machine->maxram_size) {
2406 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
2407 /*
2408 * Limit the number of hotpluggable memory slots to half the number
2409 * slots that KVM supports, leaving the other half for PCI and other
2410 * devices. However ensure that number of slots doesn't drop below 32.
2411 */
2412 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2413 SPAPR_MAX_RAM_SLOTS;
2414
2415 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2416 max_memslots = SPAPR_MAX_RAM_SLOTS;
2417 }
2418 if (machine->ram_slots > max_memslots) {
2419 error_report("Specified number of memory slots %"
2420 PRIu64" exceeds max supported %d",
2421 machine->ram_slots, max_memslots);
2422 exit(1);
2423 }
2424
2425 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
2426 SPAPR_HOTPLUG_MEM_ALIGN);
2427 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
2428 "hotplug-memory", hotplug_mem_size);
2429 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
2430 &spapr->hotplug_memory.mr);
2431 }
2432
2433 if (smc->dr_lmb_enabled) {
2434 spapr_create_lmb_dr_connectors(spapr);
2435 }
2436
2437 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2438 if (!filename) {
2439 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2440 exit(1);
2441 }
2442 spapr->rtas_size = get_image_size(filename);
2443 if (spapr->rtas_size < 0) {
2444 error_report("Could not get size of LPAR rtas '%s'", filename);
2445 exit(1);
2446 }
2447 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2448 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2449 error_report("Could not load LPAR rtas '%s'", filename);
2450 exit(1);
2451 }
2452 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2453 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2454 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2455 exit(1);
2456 }
2457 g_free(filename);
2458
2459 /* Set up RTAS event infrastructure */
2460 spapr_events_init(spapr);
2461
2462 /* Set up the RTC RTAS interfaces */
2463 spapr_rtc_create(spapr);
2464
2465 /* Set up VIO bus */
2466 spapr->vio_bus = spapr_vio_bus_init();
2467
2468 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
2469 if (serial_hds[i]) {
2470 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
2471 }
2472 }
2473
2474 /* We always have at least the nvram device on VIO */
2475 spapr_create_nvram(spapr);
2476
2477 /* Set up PCI */
2478 spapr_pci_rtas_init();
2479
2480 phb = spapr_create_phb(spapr, 0);
2481
2482 for (i = 0; i < nb_nics; i++) {
2483 NICInfo *nd = &nd_table[i];
2484
2485 if (!nd->model) {
2486 nd->model = g_strdup("ibmveth");
2487 }
2488
2489 if (strcmp(nd->model, "ibmveth") == 0) {
2490 spapr_vlan_create(spapr->vio_bus, nd);
2491 } else {
2492 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2493 }
2494 }
2495
2496 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2497 spapr_vscsi_create(spapr->vio_bus);
2498 }
2499
2500 /* Graphics */
2501 if (spapr_vga_init(phb->bus, &error_fatal)) {
2502 spapr->has_graphics = true;
2503 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2504 }
2505
2506 if (machine->usb) {
2507 if (smc->use_ohci_by_default) {
2508 pci_create_simple(phb->bus, -1, "pci-ohci");
2509 } else {
2510 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2511 }
2512
2513 if (spapr->has_graphics) {
2514 USBBus *usb_bus = usb_bus_find(-1);
2515
2516 usb_create_simple(usb_bus, "usb-kbd");
2517 usb_create_simple(usb_bus, "usb-mouse");
2518 }
2519 }
2520
2521 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
2522 error_report(
2523 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2524 MIN_RMA_SLOF);
2525 exit(1);
2526 }
2527
2528 if (kernel_filename) {
2529 uint64_t lowaddr = 0;
2530
2531 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2532 NULL, NULL, &lowaddr, NULL, 1,
2533 PPC_ELF_MACHINE, 0, 0);
2534 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2535 spapr->kernel_size = load_elf(kernel_filename,
2536 translate_kernel_address, NULL, NULL,
2537 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2538 0, 0);
2539 spapr->kernel_le = spapr->kernel_size > 0;
2540 }
2541 if (spapr->kernel_size < 0) {
2542 error_report("error loading %s: %s", kernel_filename,
2543 load_elf_strerror(spapr->kernel_size));
2544 exit(1);
2545 }
2546
2547 /* load initrd */
2548 if (initrd_filename) {
2549 /* Try to locate the initrd in the gap between the kernel
2550 * and the firmware. Add a bit of space just in case
2551 */
2552 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2553 + 0x1ffff) & ~0xffff;
2554 spapr->initrd_size = load_image_targphys(initrd_filename,
2555 spapr->initrd_base,
2556 load_limit
2557 - spapr->initrd_base);
2558 if (spapr->initrd_size < 0) {
2559 error_report("could not load initial ram disk '%s'",
2560 initrd_filename);
2561 exit(1);
2562 }
2563 }
2564 }
2565
2566 if (bios_name == NULL) {
2567 bios_name = FW_FILE_NAME;
2568 }
2569 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2570 if (!filename) {
2571 error_report("Could not find LPAR firmware '%s'", bios_name);
2572 exit(1);
2573 }
2574 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2575 if (fw_size <= 0) {
2576 error_report("Could not load LPAR firmware '%s'", filename);
2577 exit(1);
2578 }
2579 g_free(filename);
2580
2581 /* FIXME: Should register things through the MachineState's qdev
2582 * interface, this is a legacy from the sPAPREnvironment structure
2583 * which predated MachineState but had a similar function */
2584 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2585 register_savevm_live(NULL, "spapr/htab", -1, 1,
2586 &savevm_htab_handlers, spapr);
2587
2588 qemu_register_boot_set(spapr_boot_set, spapr);
2589
2590 if (kvm_enabled()) {
2591 /* to stop and start vmclock */
2592 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2593 &spapr->tb);
2594
2595 kvmppc_spapr_enable_inkernel_multitce();
2596 }
2597 }
2598
2599 static int spapr_kvm_type(const char *vm_type)
2600 {
2601 if (!vm_type) {
2602 return 0;
2603 }
2604
2605 if (!strcmp(vm_type, "HV")) {
2606 return 1;
2607 }
2608
2609 if (!strcmp(vm_type, "PR")) {
2610 return 2;
2611 }
2612
2613 error_report("Unknown kvm-type specified '%s'", vm_type);
2614 exit(1);
2615 }
2616
2617 /*
2618 * Implementation of an interface to adjust firmware path
2619 * for the bootindex property handling.
2620 */
2621 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2622 DeviceState *dev)
2623 {
2624 #define CAST(type, obj, name) \
2625 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2626 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2627 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2628 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
2629
2630 if (d) {
2631 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2632 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2633 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2634
2635 if (spapr) {
2636 /*
2637 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2638 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2639 * in the top 16 bits of the 64-bit LUN
2640 */
2641 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2642 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2643 (uint64_t)id << 48);
2644 } else if (virtio) {
2645 /*
2646 * We use SRP luns of the form 01000000 | (target << 8) | lun
2647 * in the top 32 bits of the 64-bit LUN
2648 * Note: the quote above is from SLOF and it is wrong,
2649 * the actual binding is:
2650 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2651 */
2652 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2653 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2654 (uint64_t)id << 32);
2655 } else if (usb) {
2656 /*
2657 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2658 * in the top 32 bits of the 64-bit LUN
2659 */
2660 unsigned usb_port = atoi(usb->port->path);
2661 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2662 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2663 (uint64_t)id << 32);
2664 }
2665 }
2666
2667 /*
2668 * SLOF probes the USB devices, and if it recognizes that the device is a
2669 * storage device, it changes its name to "storage" instead of "usb-host",
2670 * and additionally adds a child node for the SCSI LUN, so the correct
2671 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
2672 */
2673 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
2674 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
2675 if (usb_host_dev_is_scsi_storage(usbdev)) {
2676 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
2677 }
2678 }
2679
2680 if (phb) {
2681 /* Replace "pci" with "pci@800000020000000" */
2682 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2683 }
2684
2685 if (vsc) {
2686 /* Same logic as virtio above */
2687 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
2688 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
2689 }
2690
2691 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
2692 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
2693 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
2694 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
2695 }
2696
2697 return NULL;
2698 }
2699
2700 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2701 {
2702 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2703
2704 return g_strdup(spapr->kvm_type);
2705 }
2706
2707 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2708 {
2709 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2710
2711 g_free(spapr->kvm_type);
2712 spapr->kvm_type = g_strdup(value);
2713 }
2714
2715 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2716 {
2717 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2718
2719 return spapr->use_hotplug_event_source;
2720 }
2721
2722 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2723 Error **errp)
2724 {
2725 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2726
2727 spapr->use_hotplug_event_source = value;
2728 }
2729
2730 static char *spapr_get_resize_hpt(Object *obj, Error **errp)
2731 {
2732 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2733
2734 switch (spapr->resize_hpt) {
2735 case SPAPR_RESIZE_HPT_DEFAULT:
2736 return g_strdup("default");
2737 case SPAPR_RESIZE_HPT_DISABLED:
2738 return g_strdup("disabled");
2739 case SPAPR_RESIZE_HPT_ENABLED:
2740 return g_strdup("enabled");
2741 case SPAPR_RESIZE_HPT_REQUIRED:
2742 return g_strdup("required");
2743 }
2744 g_assert_not_reached();
2745 }
2746
2747 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
2748 {
2749 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2750
2751 if (strcmp(value, "default") == 0) {
2752 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
2753 } else if (strcmp(value, "disabled") == 0) {
2754 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2755 } else if (strcmp(value, "enabled") == 0) {
2756 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
2757 } else if (strcmp(value, "required") == 0) {
2758 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
2759 } else {
2760 error_setg(errp, "Bad value for \"resize-hpt\" property");
2761 }
2762 }
2763
2764 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
2765 void *opaque, Error **errp)
2766 {
2767 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
2768 }
2769
2770 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
2771 void *opaque, Error **errp)
2772 {
2773 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
2774 }
2775
2776 static void spapr_machine_initfn(Object *obj)
2777 {
2778 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2779
2780 spapr->htab_fd = -1;
2781 spapr->use_hotplug_event_source = true;
2782 object_property_add_str(obj, "kvm-type",
2783 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2784 object_property_set_description(obj, "kvm-type",
2785 "Specifies the KVM virtualization mode (HV, PR)",
2786 NULL);
2787 object_property_add_bool(obj, "modern-hotplug-events",
2788 spapr_get_modern_hotplug_events,
2789 spapr_set_modern_hotplug_events,
2790 NULL);
2791 object_property_set_description(obj, "modern-hotplug-events",
2792 "Use dedicated hotplug event mechanism in"
2793 " place of standard EPOW events when possible"
2794 " (required for memory hot-unplug support)",
2795 NULL);
2796
2797 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
2798 "Maximum permitted CPU compatibility mode",
2799 &error_fatal);
2800
2801 object_property_add_str(obj, "resize-hpt",
2802 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
2803 object_property_set_description(obj, "resize-hpt",
2804 "Resizing of the Hash Page Table (enabled, disabled, required)",
2805 NULL);
2806 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt,
2807 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort);
2808 object_property_set_description(obj, "vsmt",
2809 "Virtual SMT: KVM behaves as if this were"
2810 " the host's SMT mode", &error_abort);
2811 }
2812
2813 static void spapr_machine_finalizefn(Object *obj)
2814 {
2815 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2816
2817 g_free(spapr->kvm_type);
2818 }
2819
2820 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
2821 {
2822 cpu_synchronize_state(cs);
2823 ppc_cpu_do_system_reset(cs);
2824 }
2825
2826 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2827 {
2828 CPUState *cs;
2829
2830 CPU_FOREACH(cs) {
2831 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
2832 }
2833 }
2834
2835 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2836 uint32_t node, bool dedicated_hp_event_source,
2837 Error **errp)
2838 {
2839 sPAPRDRConnector *drc;
2840 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2841 int i, fdt_offset, fdt_size;
2842 void *fdt;
2843 uint64_t addr = addr_start;
2844 bool hotplugged = spapr_drc_hotplugged(dev);
2845 Error *local_err = NULL;
2846
2847 for (i = 0; i < nr_lmbs; i++) {
2848 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2849 addr / SPAPR_MEMORY_BLOCK_SIZE);
2850 g_assert(drc);
2851
2852 fdt = create_device_tree(&fdt_size);
2853 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2854 SPAPR_MEMORY_BLOCK_SIZE);
2855
2856 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
2857 if (local_err) {
2858 while (addr > addr_start) {
2859 addr -= SPAPR_MEMORY_BLOCK_SIZE;
2860 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2861 addr / SPAPR_MEMORY_BLOCK_SIZE);
2862 spapr_drc_detach(drc);
2863 }
2864 g_free(fdt);
2865 error_propagate(errp, local_err);
2866 return;
2867 }
2868 if (!hotplugged) {
2869 spapr_drc_reset(drc);
2870 }
2871 addr += SPAPR_MEMORY_BLOCK_SIZE;
2872 }
2873 /* send hotplug notification to the
2874 * guest only in case of hotplugged memory
2875 */
2876 if (hotplugged) {
2877 if (dedicated_hp_event_source) {
2878 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2879 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2880 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2881 nr_lmbs,
2882 spapr_drc_index(drc));
2883 } else {
2884 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
2885 nr_lmbs);
2886 }
2887 }
2888 }
2889
2890 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2891 uint32_t node, Error **errp)
2892 {
2893 Error *local_err = NULL;
2894 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2895 PCDIMMDevice *dimm = PC_DIMM(dev);
2896 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2897 MemoryRegion *mr;
2898 uint64_t align, size, addr;
2899
2900 mr = ddc->get_memory_region(dimm, &local_err);
2901 if (local_err) {
2902 goto out;
2903 }
2904 align = memory_region_get_alignment(mr);
2905 size = memory_region_size(mr);
2906
2907 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2908 if (local_err) {
2909 goto out;
2910 }
2911
2912 addr = object_property_get_uint(OBJECT(dimm),
2913 PC_DIMM_ADDR_PROP, &local_err);
2914 if (local_err) {
2915 goto out_unplug;
2916 }
2917
2918 spapr_add_lmbs(dev, addr, size, node,
2919 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
2920 &local_err);
2921 if (local_err) {
2922 goto out_unplug;
2923 }
2924
2925 return;
2926
2927 out_unplug:
2928 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2929 out:
2930 error_propagate(errp, local_err);
2931 }
2932
2933 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2934 Error **errp)
2935 {
2936 PCDIMMDevice *dimm = PC_DIMM(dev);
2937 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2938 MemoryRegion *mr;
2939 uint64_t size;
2940 char *mem_dev;
2941
2942 mr = ddc->get_memory_region(dimm, errp);
2943 if (!mr) {
2944 return;
2945 }
2946 size = memory_region_size(mr);
2947
2948 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2949 error_setg(errp, "Hotplugged memory size must be a multiple of "
2950 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2951 return;
2952 }
2953
2954 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL);
2955 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) {
2956 error_setg(errp, "Memory backend has bad page size. "
2957 "Use 'memory-backend-file' with correct mem-path.");
2958 goto out;
2959 }
2960
2961 out:
2962 g_free(mem_dev);
2963 }
2964
2965 struct sPAPRDIMMState {
2966 PCDIMMDevice *dimm;
2967 uint32_t nr_lmbs;
2968 QTAILQ_ENTRY(sPAPRDIMMState) next;
2969 };
2970
2971 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s,
2972 PCDIMMDevice *dimm)
2973 {
2974 sPAPRDIMMState *dimm_state = NULL;
2975
2976 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
2977 if (dimm_state->dimm == dimm) {
2978 break;
2979 }
2980 }
2981 return dimm_state;
2982 }
2983
2984 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr,
2985 uint32_t nr_lmbs,
2986 PCDIMMDevice *dimm)
2987 {
2988 sPAPRDIMMState *ds = NULL;
2989
2990 /*
2991 * If this request is for a DIMM whose removal had failed earlier
2992 * (due to guest's refusal to remove the LMBs), we would have this
2993 * dimm already in the pending_dimm_unplugs list. In that
2994 * case don't add again.
2995 */
2996 ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
2997 if (!ds) {
2998 ds = g_malloc0(sizeof(sPAPRDIMMState));
2999 ds->nr_lmbs = nr_lmbs;
3000 ds->dimm = dimm;
3001 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
3002 }
3003 return ds;
3004 }
3005
3006 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr,
3007 sPAPRDIMMState *dimm_state)
3008 {
3009 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
3010 g_free(dimm_state);
3011 }
3012
3013 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms,
3014 PCDIMMDevice *dimm)
3015 {
3016 sPAPRDRConnector *drc;
3017 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3018 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
3019 uint64_t size = memory_region_size(mr);
3020 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3021 uint32_t avail_lmbs = 0;
3022 uint64_t addr_start, addr;
3023 int i;
3024
3025 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3026 &error_abort);
3027
3028 addr = addr_start;
3029 for (i = 0; i < nr_lmbs; i++) {
3030 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3031 addr / SPAPR_MEMORY_BLOCK_SIZE);
3032 g_assert(drc);
3033 if (drc->dev) {
3034 avail_lmbs++;
3035 }
3036 addr += SPAPR_MEMORY_BLOCK_SIZE;
3037 }
3038
3039 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
3040 }
3041
3042 /* Callback to be called during DRC release. */
3043 void spapr_lmb_release(DeviceState *dev)
3044 {
3045 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev));
3046 PCDIMMDevice *dimm = PC_DIMM(dev);
3047 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3048 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
3049 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3050
3051 /* This information will get lost if a migration occurs
3052 * during the unplug process. In this case recover it. */
3053 if (ds == NULL) {
3054 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
3055 g_assert(ds);
3056 /* The DRC being examined by the caller at least must be counted */
3057 g_assert(ds->nr_lmbs);
3058 }
3059
3060 if (--ds->nr_lmbs) {
3061 return;
3062 }
3063
3064 /*
3065 * Now that all the LMBs have been removed by the guest, call the
3066 * pc-dimm unplug handler to cleanup up the pc-dimm device.
3067 */
3068 pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr);
3069 object_unparent(OBJECT(dev));
3070 spapr_pending_dimm_unplugs_remove(spapr, ds);
3071 }
3072
3073 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3074 DeviceState *dev, Error **errp)
3075 {
3076 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3077 Error *local_err = NULL;
3078 PCDIMMDevice *dimm = PC_DIMM(dev);
3079 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3080 MemoryRegion *mr;
3081 uint32_t nr_lmbs;
3082 uint64_t size, addr_start, addr;
3083 int i;
3084 sPAPRDRConnector *drc;
3085
3086 mr = ddc->get_memory_region(dimm, &local_err);
3087 if (local_err) {
3088 goto out;
3089 }
3090 size = memory_region_size(mr);
3091 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3092
3093 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3094 &local_err);
3095 if (local_err) {
3096 goto out;
3097 }
3098
3099 /*
3100 * An existing pending dimm state for this DIMM means that there is an
3101 * unplug operation in progress, waiting for the spapr_lmb_release
3102 * callback to complete the job (BQL can't cover that far). In this case,
3103 * bail out to avoid detaching DRCs that were already released.
3104 */
3105 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) {
3106 error_setg(&local_err,
3107 "Memory unplug already in progress for device %s",
3108 dev->id);
3109 goto out;
3110 }
3111
3112 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
3113
3114 addr = addr_start;
3115 for (i = 0; i < nr_lmbs; i++) {
3116 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3117 addr / SPAPR_MEMORY_BLOCK_SIZE);
3118 g_assert(drc);
3119
3120 spapr_drc_detach(drc);
3121 addr += SPAPR_MEMORY_BLOCK_SIZE;
3122 }
3123
3124 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3125 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3126 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3127 nr_lmbs, spapr_drc_index(drc));
3128 out:
3129 error_propagate(errp, local_err);
3130 }
3131
3132 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
3133 sPAPRMachineState *spapr)
3134 {
3135 PowerPCCPU *cpu = POWERPC_CPU(cs);
3136 DeviceClass *dc = DEVICE_GET_CLASS(cs);
3137 int id = spapr_vcpu_id(cpu);
3138 void *fdt;
3139 int offset, fdt_size;
3140 char *nodename;
3141
3142 fdt = create_device_tree(&fdt_size);
3143 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3144 offset = fdt_add_subnode(fdt, 0, nodename);
3145
3146 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
3147 g_free(nodename);
3148
3149 *fdt_offset = offset;
3150 return fdt;
3151 }
3152
3153 /* Callback to be called during DRC release. */
3154 void spapr_core_release(DeviceState *dev)
3155 {
3156 MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev));
3157 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3158 CPUCore *cc = CPU_CORE(dev);
3159 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3160
3161 if (smc->pre_2_10_has_unused_icps) {
3162 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3163 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc));
3164 size_t size = object_type_get_instance_size(scc->cpu_type);
3165 int i;
3166
3167 for (i = 0; i < cc->nr_threads; i++) {
3168 CPUState *cs = CPU(sc->threads + i * size);
3169
3170 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3171 }
3172 }
3173
3174 assert(core_slot);
3175 core_slot->cpu = NULL;
3176 object_unparent(OBJECT(dev));
3177 }
3178
3179 static
3180 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3181 Error **errp)
3182 {
3183 int index;
3184 sPAPRDRConnector *drc;
3185 CPUCore *cc = CPU_CORE(dev);
3186 int smt = kvmppc_smt_threads();
3187
3188 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3189 error_setg(errp, "Unable to find CPU core with core-id: %d",
3190 cc->core_id);
3191 return;
3192 }
3193 if (index == 0) {
3194 error_setg(errp, "Boot CPU core may not be unplugged");
3195 return;
3196 }
3197
3198 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt);
3199 g_assert(drc);
3200
3201 spapr_drc_detach(drc);
3202
3203 spapr_hotplug_req_remove_by_index(drc);
3204 }
3205
3206 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3207 Error **errp)
3208 {
3209 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3210 MachineClass *mc = MACHINE_GET_CLASS(spapr);
3211 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3212 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3213 CPUCore *cc = CPU_CORE(dev);
3214 CPUState *cs = CPU(core->threads);
3215 sPAPRDRConnector *drc;
3216 Error *local_err = NULL;
3217 int smt = kvmppc_smt_threads();
3218 CPUArchId *core_slot;
3219 int index;
3220 bool hotplugged = spapr_drc_hotplugged(dev);
3221
3222 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3223 if (!core_slot) {
3224 error_setg(errp, "Unable to find CPU core with core-id: %d",
3225 cc->core_id);
3226 return;
3227 }
3228 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt);
3229
3230 g_assert(drc || !mc->has_hotpluggable_cpus);
3231
3232 if (drc) {
3233 void *fdt;
3234 int fdt_offset;
3235
3236 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
3237
3238 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
3239 if (local_err) {
3240 g_free(fdt);
3241 error_propagate(errp, local_err);
3242 return;
3243 }
3244
3245 if (hotplugged) {
3246 /*
3247 * Send hotplug notification interrupt to the guest only
3248 * in case of hotplugged CPUs.
3249 */
3250 spapr_hotplug_req_add_by_index(drc);
3251 } else {
3252 spapr_drc_reset(drc);
3253 }
3254 }
3255
3256 core_slot->cpu = OBJECT(dev);
3257
3258 if (smc->pre_2_10_has_unused_icps) {
3259 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc));
3260 size_t size = object_type_get_instance_size(scc->cpu_type);
3261 int i;
3262
3263 for (i = 0; i < cc->nr_threads; i++) {
3264 sPAPRCPUCore *sc = SPAPR_CPU_CORE(dev);
3265 void *obj = sc->threads + i * size;
3266
3267 cs = CPU(obj);
3268 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3269 }
3270 }
3271 }
3272
3273 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3274 Error **errp)
3275 {
3276 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3277 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3278 Error *local_err = NULL;
3279 CPUCore *cc = CPU_CORE(dev);
3280 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
3281 const char *type = object_get_typename(OBJECT(dev));
3282 CPUArchId *core_slot;
3283 int index;
3284
3285 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3286 error_setg(&local_err, "CPU hotplug not supported for this machine");
3287 goto out;
3288 }
3289
3290 if (strcmp(base_core_type, type)) {
3291 error_setg(&local_err, "CPU core type should be %s", base_core_type);
3292 goto out;
3293 }
3294
3295 if (cc->core_id % smp_threads) {
3296 error_setg(&local_err, "invalid core id %d", cc->core_id);
3297 goto out;
3298 }
3299
3300 /*
3301 * In general we should have homogeneous threads-per-core, but old
3302 * (pre hotplug support) machine types allow the last core to have
3303 * reduced threads as a compatibility hack for when we allowed
3304 * total vcpus not a multiple of threads-per-core.
3305 */
3306 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3307 error_setg(&local_err, "invalid nr-threads %d, must be %d",
3308 cc->nr_threads, smp_threads);
3309 goto out;
3310 }
3311
3312 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3313 if (!core_slot) {
3314 error_setg(&local_err, "core id %d out of range", cc->core_id);
3315 goto out;
3316 }
3317
3318 if (core_slot->cpu) {
3319 error_setg(&local_err, "core %d already populated", cc->core_id);
3320 goto out;
3321 }
3322
3323 numa_cpu_pre_plug(core_slot, dev, &local_err);
3324
3325 out:
3326 g_free(base_core_type);
3327 error_propagate(errp, local_err);
3328 }
3329
3330 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
3331 DeviceState *dev, Error **errp)
3332 {
3333 MachineState *ms = MACHINE(hotplug_dev);
3334 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3335
3336 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3337 int node;
3338
3339 if (!smc->dr_lmb_enabled) {
3340 error_setg(errp, "Memory hotplug not supported for this machine");
3341 return;
3342 }
3343 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
3344 if (*errp) {
3345 return;
3346 }
3347 if (node < 0 || node >= MAX_NODES) {
3348 error_setg(errp, "Invaild node %d", node);
3349 return;
3350 }
3351
3352 /*
3353 * Currently PowerPC kernel doesn't allow hot-adding memory to
3354 * memory-less node, but instead will silently add the memory
3355 * to the first node that has some memory. This causes two
3356 * unexpected behaviours for the user.
3357 *
3358 * - Memory gets hotplugged to a different node than what the user
3359 * specified.
3360 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
3361 * to memory-less node, a reboot will set things accordingly
3362 * and the previously hotplugged memory now ends in the right node.
3363 * This appears as if some memory moved from one node to another.
3364 *
3365 * So until kernel starts supporting memory hotplug to memory-less
3366 * nodes, just prevent such attempts upfront in QEMU.
3367 */
3368 if (nb_numa_nodes && !numa_info[node].node_mem) {
3369 error_setg(errp, "Can't hotplug memory to memory-less node %d",
3370 node);
3371 return;
3372 }
3373
3374 spapr_memory_plug(hotplug_dev, dev, node, errp);
3375 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3376 spapr_core_plug(hotplug_dev, dev, errp);
3377 }
3378 }
3379
3380 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
3381 DeviceState *dev, Error **errp)
3382 {
3383 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev));
3384 MachineClass *mc = MACHINE_GET_CLASS(sms);
3385
3386 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3387 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
3388 spapr_memory_unplug_request(hotplug_dev, dev, errp);
3389 } else {
3390 /* NOTE: this means there is a window after guest reset, prior to
3391 * CAS negotiation, where unplug requests will fail due to the
3392 * capability not being detected yet. This is a bit different than
3393 * the case with PCI unplug, where the events will be queued and
3394 * eventually handled by the guest after boot
3395 */
3396 error_setg(errp, "Memory hot unplug not supported for this guest");
3397 }
3398 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3399 if (!mc->has_hotpluggable_cpus) {
3400 error_setg(errp, "CPU hot unplug not supported on this machine");
3401 return;
3402 }
3403 spapr_core_unplug_request(hotplug_dev, dev, errp);
3404 }
3405 }
3406
3407 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
3408 DeviceState *dev, Error **errp)
3409 {
3410 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3411 spapr_memory_pre_plug(hotplug_dev, dev, errp);
3412 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3413 spapr_core_pre_plug(hotplug_dev, dev, errp);
3414 }
3415 }
3416
3417 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
3418 DeviceState *dev)
3419 {
3420 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
3421 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3422 return HOTPLUG_HANDLER(machine);
3423 }
3424 return NULL;
3425 }
3426
3427 static CpuInstanceProperties
3428 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
3429 {
3430 CPUArchId *core_slot;
3431 MachineClass *mc = MACHINE_GET_CLASS(machine);
3432
3433 /* make sure possible_cpu are intialized */
3434 mc->possible_cpu_arch_ids(machine);
3435 /* get CPU core slot containing thread that matches cpu_index */
3436 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
3437 assert(core_slot);
3438 return core_slot->props;
3439 }
3440
3441 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
3442 {
3443 return idx / smp_cores % nb_numa_nodes;
3444 }
3445
3446 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
3447 {
3448 int i;
3449 int spapr_max_cores = max_cpus / smp_threads;
3450 MachineClass *mc = MACHINE_GET_CLASS(machine);
3451
3452 if (!mc->has_hotpluggable_cpus) {
3453 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
3454 }
3455 if (machine->possible_cpus) {
3456 assert(machine->possible_cpus->len == spapr_max_cores);
3457 return machine->possible_cpus;
3458 }
3459
3460 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
3461 sizeof(CPUArchId) * spapr_max_cores);
3462 machine->possible_cpus->len = spapr_max_cores;
3463 for (i = 0; i < machine->possible_cpus->len; i++) {
3464 int core_id = i * smp_threads;
3465
3466 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
3467 machine->possible_cpus->cpus[i].arch_id = core_id;
3468 machine->possible_cpus->cpus[i].props.has_core_id = true;
3469 machine->possible_cpus->cpus[i].props.core_id = core_id;
3470 }
3471 return machine->possible_cpus;
3472 }
3473
3474 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
3475 uint64_t *buid, hwaddr *pio,
3476 hwaddr *mmio32, hwaddr *mmio64,
3477 unsigned n_dma, uint32_t *liobns, Error **errp)
3478 {
3479 /*
3480 * New-style PHB window placement.
3481 *
3482 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
3483 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
3484 * windows.
3485 *
3486 * Some guest kernels can't work with MMIO windows above 1<<46
3487 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
3488 *
3489 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
3490 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
3491 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
3492 * 1TiB 64-bit MMIO windows for each PHB.
3493 */
3494 const uint64_t base_buid = 0x800000020000000ULL;
3495 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3496 SPAPR_PCI_MEM64_WIN_SIZE - 1)
3497 int i;
3498
3499 /* Sanity check natural alignments */
3500 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3501 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3502 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
3503 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
3504 /* Sanity check bounds */
3505 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
3506 SPAPR_PCI_MEM32_WIN_SIZE);
3507 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
3508 SPAPR_PCI_MEM64_WIN_SIZE);
3509
3510 if (index >= SPAPR_MAX_PHBS) {
3511 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
3512 SPAPR_MAX_PHBS - 1);
3513 return;
3514 }
3515
3516 *buid = base_buid + index;
3517 for (i = 0; i < n_dma; ++i) {
3518 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3519 }
3520
3521 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
3522 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
3523 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
3524 }
3525
3526 static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
3527 {
3528 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3529
3530 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
3531 }
3532
3533 static void spapr_ics_resend(XICSFabric *dev)
3534 {
3535 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3536
3537 ics_resend(spapr->ics);
3538 }
3539
3540 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
3541 {
3542 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
3543
3544 return cpu ? ICP(cpu->intc) : NULL;
3545 }
3546
3547 static void spapr_pic_print_info(InterruptStatsProvider *obj,
3548 Monitor *mon)
3549 {
3550 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3551 CPUState *cs;
3552
3553 CPU_FOREACH(cs) {
3554 PowerPCCPU *cpu = POWERPC_CPU(cs);
3555
3556 icp_pic_print_info(ICP(cpu->intc), mon);
3557 }
3558
3559 ics_pic_print_info(spapr->ics, mon);
3560 }
3561
3562 int spapr_vcpu_id(PowerPCCPU *cpu)
3563 {
3564 CPUState *cs = CPU(cpu);
3565
3566 if (kvm_enabled()) {
3567 return kvm_arch_vcpu_id(cs);
3568 } else {
3569 return cs->cpu_index;
3570 }
3571 }
3572
3573 PowerPCCPU *spapr_find_cpu(int vcpu_id)
3574 {
3575 CPUState *cs;
3576
3577 CPU_FOREACH(cs) {
3578 PowerPCCPU *cpu = POWERPC_CPU(cs);
3579
3580 if (spapr_vcpu_id(cpu) == vcpu_id) {
3581 return cpu;
3582 }
3583 }
3584
3585 return NULL;
3586 }
3587
3588 static void spapr_machine_class_init(ObjectClass *oc, void *data)
3589 {
3590 MachineClass *mc = MACHINE_CLASS(oc);
3591 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
3592 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
3593 NMIClass *nc = NMI_CLASS(oc);
3594 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3595 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
3596 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
3597 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
3598
3599 mc->desc = "pSeries Logical Partition (PAPR compliant)";
3600
3601 /*
3602 * We set up the default / latest behaviour here. The class_init
3603 * functions for the specific versioned machine types can override
3604 * these details for backwards compatibility
3605 */
3606 mc->init = ppc_spapr_init;
3607 mc->reset = ppc_spapr_reset;
3608 mc->block_default_type = IF_SCSI;
3609 mc->max_cpus = 1024;
3610 mc->no_parallel = 1;
3611 mc->default_boot_order = "";
3612 mc->default_ram_size = 512 * M_BYTE;
3613 mc->kvm_type = spapr_kvm_type;
3614 mc->has_dynamic_sysbus = true;
3615 mc->pci_allow_0_address = true;
3616 mc->get_hotplug_handler = spapr_get_hotplug_handler;
3617 hc->pre_plug = spapr_machine_device_pre_plug;
3618 hc->plug = spapr_machine_device_plug;
3619 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
3620 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id;
3621 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
3622 hc->unplug_request = spapr_machine_device_unplug_request;
3623
3624 smc->dr_lmb_enabled = true;
3625 smc->tcg_default_cpu = "POWER8";
3626 mc->has_hotpluggable_cpus = true;
3627 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
3628 fwc->get_dev_path = spapr_get_fw_dev_path;
3629 nc->nmi_monitor_handler = spapr_nmi;
3630 smc->phb_placement = spapr_phb_placement;
3631 vhc->hypercall = emulate_spapr_hypercall;
3632 vhc->hpt_mask = spapr_hpt_mask;
3633 vhc->map_hptes = spapr_map_hptes;
3634 vhc->unmap_hptes = spapr_unmap_hptes;
3635 vhc->store_hpte = spapr_store_hpte;
3636 vhc->get_patbe = spapr_get_patbe;
3637 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr;
3638 xic->ics_get = spapr_ics_get;
3639 xic->ics_resend = spapr_ics_resend;
3640 xic->icp_get = spapr_icp_get;
3641 ispc->print_info = spapr_pic_print_info;
3642 /* Force NUMA node memory size to be a multiple of
3643 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
3644 * in which LMBs are represented and hot-added
3645 */
3646 mc->numa_mem_align_shift = 28;
3647 }
3648
3649 static const TypeInfo spapr_machine_info = {
3650 .name = TYPE_SPAPR_MACHINE,
3651 .parent = TYPE_MACHINE,
3652 .abstract = true,
3653 .instance_size = sizeof(sPAPRMachineState),
3654 .instance_init = spapr_machine_initfn,
3655 .instance_finalize = spapr_machine_finalizefn,
3656 .class_size = sizeof(sPAPRMachineClass),
3657 .class_init = spapr_machine_class_init,
3658 .interfaces = (InterfaceInfo[]) {
3659 { TYPE_FW_PATH_PROVIDER },
3660 { TYPE_NMI },
3661 { TYPE_HOTPLUG_HANDLER },
3662 { TYPE_PPC_VIRTUAL_HYPERVISOR },
3663 { TYPE_XICS_FABRIC },
3664 { TYPE_INTERRUPT_STATS_PROVIDER },
3665 { }
3666 },
3667 };
3668
3669 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
3670 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
3671 void *data) \
3672 { \
3673 MachineClass *mc = MACHINE_CLASS(oc); \
3674 spapr_machine_##suffix##_class_options(mc); \
3675 if (latest) { \
3676 mc->alias = "pseries"; \
3677 mc->is_default = 1; \
3678 } \
3679 } \
3680 static void spapr_machine_##suffix##_instance_init(Object *obj) \
3681 { \
3682 MachineState *machine = MACHINE(obj); \
3683 spapr_machine_##suffix##_instance_options(machine); \
3684 } \
3685 static const TypeInfo spapr_machine_##suffix##_info = { \
3686 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
3687 .parent = TYPE_SPAPR_MACHINE, \
3688 .class_init = spapr_machine_##suffix##_class_init, \
3689 .instance_init = spapr_machine_##suffix##_instance_init, \
3690 }; \
3691 static void spapr_machine_register_##suffix(void) \
3692 { \
3693 type_register(&spapr_machine_##suffix##_info); \
3694 } \
3695 type_init(spapr_machine_register_##suffix)
3696
3697 /*
3698 * pseries-2.11
3699 */
3700 static void spapr_machine_2_11_instance_options(MachineState *machine)
3701 {
3702 }
3703
3704 static void spapr_machine_2_11_class_options(MachineClass *mc)
3705 {
3706 /* Defaults for the latest behaviour inherited from the base class */
3707 }
3708
3709 DEFINE_SPAPR_MACHINE(2_11, "2.11", true);
3710
3711 /*
3712 * pseries-2.10
3713 */
3714 #define SPAPR_COMPAT_2_10 \
3715 HW_COMPAT_2_10 \
3716
3717 static void spapr_machine_2_10_instance_options(MachineState *machine)
3718 {
3719 }
3720
3721 static void spapr_machine_2_10_class_options(MachineClass *mc)
3722 {
3723 spapr_machine_2_11_class_options(mc);
3724 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10);
3725 }
3726
3727 DEFINE_SPAPR_MACHINE(2_10, "2.10", false);
3728
3729 /*
3730 * pseries-2.9
3731 */
3732 #define SPAPR_COMPAT_2_9 \
3733 HW_COMPAT_2_9 \
3734 { \
3735 .driver = TYPE_POWERPC_CPU, \
3736 .property = "pre-2.10-migration", \
3737 .value = "on", \
3738 }, \
3739
3740 static void spapr_machine_2_9_instance_options(MachineState *machine)
3741 {
3742 spapr_machine_2_10_instance_options(machine);
3743 }
3744
3745 static void spapr_machine_2_9_class_options(MachineClass *mc)
3746 {
3747 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3748
3749 spapr_machine_2_10_class_options(mc);
3750 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9);
3751 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
3752 smc->pre_2_10_has_unused_icps = true;
3753 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
3754 }
3755
3756 DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
3757
3758 /*
3759 * pseries-2.8
3760 */
3761 #define SPAPR_COMPAT_2_8 \
3762 HW_COMPAT_2_8 \
3763 { \
3764 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3765 .property = "pcie-extended-configuration-space", \
3766 .value = "off", \
3767 },
3768
3769 static void spapr_machine_2_8_instance_options(MachineState *machine)
3770 {
3771 spapr_machine_2_9_instance_options(machine);
3772 }
3773
3774 static void spapr_machine_2_8_class_options(MachineClass *mc)
3775 {
3776 spapr_machine_2_9_class_options(mc);
3777 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
3778 mc->numa_mem_align_shift = 23;
3779 }
3780
3781 DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
3782
3783 /*
3784 * pseries-2.7
3785 */
3786 #define SPAPR_COMPAT_2_7 \
3787 HW_COMPAT_2_7 \
3788 { \
3789 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3790 .property = "mem_win_size", \
3791 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
3792 }, \
3793 { \
3794 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3795 .property = "mem64_win_size", \
3796 .value = "0", \
3797 }, \
3798 { \
3799 .driver = TYPE_POWERPC_CPU, \
3800 .property = "pre-2.8-migration", \
3801 .value = "on", \
3802 }, \
3803 { \
3804 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3805 .property = "pre-2.8-migration", \
3806 .value = "on", \
3807 },
3808
3809 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
3810 uint64_t *buid, hwaddr *pio,
3811 hwaddr *mmio32, hwaddr *mmio64,
3812 unsigned n_dma, uint32_t *liobns, Error **errp)
3813 {
3814 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
3815 const uint64_t base_buid = 0x800000020000000ULL;
3816 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
3817 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
3818 const hwaddr pio_offset = 0x80000000; /* 2 GiB */
3819 const uint32_t max_index = 255;
3820 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
3821
3822 uint64_t ram_top = MACHINE(spapr)->ram_size;
3823 hwaddr phb0_base, phb_base;
3824 int i;
3825
3826 /* Do we have hotpluggable memory? */
3827 if (MACHINE(spapr)->maxram_size > ram_top) {
3828 /* Can't just use maxram_size, because there may be an
3829 * alignment gap between normal and hotpluggable memory
3830 * regions */
3831 ram_top = spapr->hotplug_memory.base +
3832 memory_region_size(&spapr->hotplug_memory.mr);
3833 }
3834
3835 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
3836
3837 if (index > max_index) {
3838 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
3839 max_index);
3840 return;
3841 }
3842
3843 *buid = base_buid + index;
3844 for (i = 0; i < n_dma; ++i) {
3845 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3846 }
3847
3848 phb_base = phb0_base + index * phb_spacing;
3849 *pio = phb_base + pio_offset;
3850 *mmio32 = phb_base + mmio_offset;
3851 /*
3852 * We don't set the 64-bit MMIO window, relying on the PHB's
3853 * fallback behaviour of automatically splitting a large "32-bit"
3854 * window into contiguous 32-bit and 64-bit windows
3855 */
3856 }
3857
3858 static void spapr_machine_2_7_instance_options(MachineState *machine)
3859 {
3860 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
3861
3862 spapr_machine_2_8_instance_options(machine);
3863 spapr->use_hotplug_event_source = false;
3864 }
3865
3866 static void spapr_machine_2_7_class_options(MachineClass *mc)
3867 {
3868 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3869
3870 spapr_machine_2_8_class_options(mc);
3871 smc->tcg_default_cpu = "POWER7";
3872 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
3873 smc->phb_placement = phb_placement_2_7;
3874 }
3875
3876 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
3877
3878 /*
3879 * pseries-2.6
3880 */
3881 #define SPAPR_COMPAT_2_6 \
3882 HW_COMPAT_2_6 \
3883 { \
3884 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3885 .property = "ddw",\
3886 .value = stringify(off),\
3887 },
3888
3889 static void spapr_machine_2_6_instance_options(MachineState *machine)
3890 {
3891 spapr_machine_2_7_instance_options(machine);
3892 }
3893
3894 static void spapr_machine_2_6_class_options(MachineClass *mc)
3895 {
3896 spapr_machine_2_7_class_options(mc);
3897 mc->has_hotpluggable_cpus = false;
3898 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
3899 }
3900
3901 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
3902
3903 /*
3904 * pseries-2.5
3905 */
3906 #define SPAPR_COMPAT_2_5 \
3907 HW_COMPAT_2_5 \
3908 { \
3909 .driver = "spapr-vlan", \
3910 .property = "use-rx-buffer-pools", \
3911 .value = "off", \
3912 },
3913
3914 static void spapr_machine_2_5_instance_options(MachineState *machine)
3915 {
3916 spapr_machine_2_6_instance_options(machine);
3917 }
3918
3919 static void spapr_machine_2_5_class_options(MachineClass *mc)
3920 {
3921 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3922
3923 spapr_machine_2_6_class_options(mc);
3924 smc->use_ohci_by_default = true;
3925 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
3926 }
3927
3928 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
3929
3930 /*
3931 * pseries-2.4
3932 */
3933 #define SPAPR_COMPAT_2_4 \
3934 HW_COMPAT_2_4
3935
3936 static void spapr_machine_2_4_instance_options(MachineState *machine)
3937 {
3938 spapr_machine_2_5_instance_options(machine);
3939 }
3940
3941 static void spapr_machine_2_4_class_options(MachineClass *mc)
3942 {
3943 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3944
3945 spapr_machine_2_5_class_options(mc);
3946 smc->dr_lmb_enabled = false;
3947 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
3948 }
3949
3950 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
3951
3952 /*
3953 * pseries-2.3
3954 */
3955 #define SPAPR_COMPAT_2_3 \
3956 HW_COMPAT_2_3 \
3957 {\
3958 .driver = "spapr-pci-host-bridge",\
3959 .property = "dynamic-reconfiguration",\
3960 .value = "off",\
3961 },
3962
3963 static void spapr_machine_2_3_instance_options(MachineState *machine)
3964 {
3965 spapr_machine_2_4_instance_options(machine);
3966 }
3967
3968 static void spapr_machine_2_3_class_options(MachineClass *mc)
3969 {
3970 spapr_machine_2_4_class_options(mc);
3971 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
3972 }
3973 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
3974
3975 /*
3976 * pseries-2.2
3977 */
3978
3979 #define SPAPR_COMPAT_2_2 \
3980 HW_COMPAT_2_2 \
3981 {\
3982 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3983 .property = "mem_win_size",\
3984 .value = "0x20000000",\
3985 },
3986
3987 static void spapr_machine_2_2_instance_options(MachineState *machine)
3988 {
3989 spapr_machine_2_3_instance_options(machine);
3990 machine->suppress_vmdesc = true;
3991 }
3992
3993 static void spapr_machine_2_2_class_options(MachineClass *mc)
3994 {
3995 spapr_machine_2_3_class_options(mc);
3996 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
3997 }
3998 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
3999
4000 /*
4001 * pseries-2.1
4002 */
4003 #define SPAPR_COMPAT_2_1 \
4004 HW_COMPAT_2_1
4005
4006 static void spapr_machine_2_1_instance_options(MachineState *machine)
4007 {
4008 spapr_machine_2_2_instance_options(machine);
4009 }
4010
4011 static void spapr_machine_2_1_class_options(MachineClass *mc)
4012 {
4013 spapr_machine_2_2_class_options(mc);
4014 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
4015 }
4016 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
4017
4018 static void spapr_machine_register_types(void)
4019 {
4020 type_register_static(&spapr_machine_info);
4021 }
4022
4023 type_init(spapr_machine_register_types)
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