2 * QEMU PowerMac emulation shared definitions and prototypes
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #include "exec/memory.h"
30 #include "hw/sysbus.h"
31 #include "hw/ide/internal.h"
32 #include "hw/input/adb.h"
34 /* SMP is not enabled, for now */
37 #define BIOS_SIZE (1024 * 1024)
38 #define NVRAM_SIZE 0x2000
39 #define PROM_FILENAME "openbios-ppc"
40 #define PROM_ADDR 0xfff00000
42 #define KERNEL_LOAD_ADDR 0x01000000
43 #define KERNEL_GAP 0x00100000
45 #define ESCC_CLOCK 3686400
48 #define TYPE_CUDA "cuda"
49 #define CUDA(obj) OBJECT_CHECK(CUDAState, (obj), TYPE_CUDA)
53 * @counter_value: counter value at load time
55 typedef struct CUDATimer
{
58 uint16_t counter_value
;
60 int64_t next_irq_time
;
69 * @dirb: B-side direction (1=output)
70 * @dira: A-side direction (1=output)
72 * @acr: Auxiliary control register
73 * @pcr: Peripheral control register
74 * @ifr: Interrupt flag register
75 * @ier: Interrupt enable register
76 * @anh: A-side data, no handshake
77 * @last_b: last value of B register
78 * @last_acr: last value of ACR register
80 typedef struct CUDAState
{
82 SysBusDevice parent_obj
;
101 uint32_t tick_offset
;
107 /* MacOS 9 is racy and requires a delay upon setting the SR_INT bit */
108 QEMUTimer
*sr_delay_timer
;
115 uint16_t adb_poll_mask
;
116 uint8_t autopoll_rate_ms
;
118 uint8_t data_in
[128];
119 uint8_t data_out
[16];
120 QEMUTimer
*adb_poll_timer
;
124 #define TYPE_OLDWORLD_MACIO "macio-oldworld"
125 #define TYPE_NEWWORLD_MACIO "macio-newworld"
127 #define TYPE_MACIO_IDE "macio-ide"
128 #define MACIO_IDE(obj) OBJECT_CHECK(MACIOIDEState, (obj), TYPE_MACIO_IDE)
130 typedef struct MACIOIDEState
{
132 SysBusDevice parent_obj
;
135 qemu_irq real_ide_irq
;
136 qemu_irq real_dma_irq
;
149 void macio_ide_init_drives(MACIOIDEState
*ide
, DriveInfo
**hd_table
);
150 void macio_ide_register_dma(MACIOIDEState
*ide
);
152 void macio_init(PCIDevice
*dev
,
153 MemoryRegion
*pic_mem
,
154 MemoryRegion
*escc_mem
);
157 qemu_irq
*heathrow_pic_init(MemoryRegion
**pmem
,
158 int nb_cpus
, qemu_irq
**irqs
);
161 #define TYPE_GRACKLE_PCI_HOST_BRIDGE "grackle-pcihost"
162 PCIBus
*pci_grackle_init(uint32_t base
, qemu_irq
*pic
,
163 MemoryRegion
*address_space_mem
,
164 MemoryRegion
*address_space_io
);
167 PCIBus
*pci_pmac_init(qemu_irq
*pic
,
168 MemoryRegion
*address_space_mem
,
169 MemoryRegion
*address_space_io
);
170 PCIBus
*pci_pmac_u3_init(qemu_irq
*pic
,
171 MemoryRegion
*address_space_mem
,
172 MemoryRegion
*address_space_io
);
175 #define TYPE_MACIO_NVRAM "macio-nvram"
176 #define MACIO_NVRAM(obj) \
177 OBJECT_CHECK(MacIONVRAMState, (obj), TYPE_MACIO_NVRAM)
179 typedef struct MacIONVRAMState
{
181 SysBusDevice parent_obj
;
191 void pmac_format_nvram_partition (MacIONVRAMState
*nvr
, int len
);
192 #endif /* PPC_MAC_H */