?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
seabios: turn off CONFIG_ATA_DMA
[qemu/kevin.git] / hw / ppc / pnv.c
blob8be4d4cbf78531797ffe0ec15e1c5a254377230b
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qapi/error.h"
23 #include "sysemu/sysemu.h"
24 #include "sysemu/numa.h"
25 #include "sysemu/cpus.h"
26 #include "hw/hw.h"
27 #include "target/ppc/cpu.h"
28 #include "qemu/log.h"
29 #include "hw/ppc/fdt.h"
30 #include "hw/ppc/ppc.h"
31 #include "hw/ppc/pnv.h"
32 #include "hw/ppc/pnv_core.h"
33 #include "hw/loader.h"
34 #include "exec/address-spaces.h"
35 #include "qapi/visitor.h"
36 #include "monitor/monitor.h"
37 #include "hw/intc/intc.h"
38 #include "hw/ipmi/ipmi.h"
39 #include "target/ppc/mmu-hash64.h"
40
41 #include "hw/ppc/xics.h"
42 #include "hw/ppc/pnv_xscom.h"
43
44 #include "hw/isa/isa.h"
45 #include "hw/char/serial.h"
46 #include "hw/timer/mc146818rtc.h"
47
48 #include <libfdt.h>
49
50 #define FDT_MAX_SIZE (1 * MiB)
51
52 #define FW_FILE_NAME "skiboot.lid"
53 #define FW_LOAD_ADDR 0x0
54 #define FW_MAX_SIZE (4 * MiB)
55
56 #define KERNEL_LOAD_ADDR 0x20000000
57 #define KERNEL_MAX_SIZE (256 * MiB)
58 #define INITRD_LOAD_ADDR 0x60000000
59 #define INITRD_MAX_SIZE (256 * MiB)
60
61 static const char *pnv_chip_core_typename(const PnvChip *o)
62 {
63 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
64 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
65 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
66 const char *core_type = object_class_get_name(object_class_by_name(s));
67 g_free(s);
68 return core_type;
69 }
70
71 /*
72 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
73 * 4 * 4 sockets * 12 cores * 8 threads = 1536
74 * Let's make it 2^11
75 */
76 #define MAX_CPUS 2048
77
78 /*
79 * Memory nodes are created by hostboot, one for each range of memory
80 * that has a different "affinity". In practice, it means one range
81 * per chip.
82 */
83 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
84 {
85 char *mem_name;
86 uint64_t mem_reg_property[2];
87 int off;
88
89 mem_reg_property[0] = cpu_to_be64(start);
90 mem_reg_property[1] = cpu_to_be64(size);
91
92 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
93 off = fdt_add_subnode(fdt, 0, mem_name);
94 g_free(mem_name);
95
96 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
97 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
98 sizeof(mem_reg_property))));
99 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
100 }
101
102 static int get_cpus_node(void *fdt)
103 {
104 int cpus_offset = fdt_path_offset(fdt, "/cpus");
105
106 if (cpus_offset < 0) {
107 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
108 if (cpus_offset) {
109 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
110 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
111 }
112 }
113 _FDT(cpus_offset);
114 return cpus_offset;
115 }
116
117 /*
118 * The PowerNV cores (and threads) need to use real HW ids and not an
119 * incremental index like it has been done on other platforms. This HW
120 * id is stored in the CPU PIR, it is used to create cpu nodes in the
121 * device tree, used in XSCOM to address cores and in interrupt
122 * servers.
123 */
124 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
125 {
126 PowerPCCPU *cpu = pc->threads[0];
127 CPUState *cs = CPU(cpu);
128 DeviceClass *dc = DEVICE_GET_CLASS(cs);
129 int smt_threads = CPU_CORE(pc)->nr_threads;
130 CPUPPCState *env = &cpu->env;
131 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
132 uint32_t servers_prop[smt_threads];
133 int i;
134 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
135 0xffffffff, 0xffffffff};
136 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
137 uint32_t cpufreq = 1000000000;
138 uint32_t page_sizes_prop[64];
139 size_t page_sizes_prop_size;
140 const uint8_t pa_features[] = { 24, 0,
141 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
142 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
143 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
144 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
145 int offset;
146 char *nodename;
147 int cpus_offset = get_cpus_node(fdt);
148
149 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
150 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
151 _FDT(offset);
152 g_free(nodename);
153
154 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
155
156 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
157 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
158 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
159
160 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
161 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
162 env->dcache_line_size)));
163 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
164 env->dcache_line_size)));
165 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
166 env->icache_line_size)));
167 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
168 env->icache_line_size)));
169
170 if (pcc->l1_dcache_size) {
171 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
172 pcc->l1_dcache_size)));
173 } else {
174 warn_report("Unknown L1 dcache size for cpu");
175 }
176 if (pcc->l1_icache_size) {
177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
178 pcc->l1_icache_size)));
179 } else {
180 warn_report("Unknown L1 icache size for cpu");
181 }
182
183 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
184 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
185 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
186 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
187 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
188
189 if (env->spr_cb[SPR_PURR].oea_read) {
190 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
191 }
192
193 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
194 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
195 segs, sizeof(segs))));
196 }
197
198 /* Advertise VMX/VSX (vector extensions) if available
199 * 0 / no property == no vector extensions
200 * 1 == VMX / Altivec available
201 * 2 == VSX available */
202 if (env->insns_flags & PPC_ALTIVEC) {
203 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
204
205 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
206 }
207
208 /* Advertise DFP (Decimal Floating Point) if available
209 * 0 / no property == no DFP
210 * 1 == DFP available */
211 if (env->insns_flags2 & PPC2_DFP) {
212 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
213 }
214
215 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
216 sizeof(page_sizes_prop));
217 if (page_sizes_prop_size) {
218 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
219 page_sizes_prop, page_sizes_prop_size)));
220 }
221
222 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
223 pa_features, sizeof(pa_features))));
224
225 /* Build interrupt servers properties */
226 for (i = 0; i < smt_threads; i++) {
227 servers_prop[i] = cpu_to_be32(pc->pir + i);
228 }
229 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
230 servers_prop, sizeof(servers_prop))));
231 }
232
233 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
234 uint32_t nr_threads)
235 {
236 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
237 char *name;
238 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
239 uint32_t irange[2], i, rsize;
240 uint64_t *reg;
241 int offset;
242
243 irange[0] = cpu_to_be32(pir);
244 irange[1] = cpu_to_be32(nr_threads);
245
246 rsize = sizeof(uint64_t) * 2 * nr_threads;
247 reg = g_malloc(rsize);
248 for (i = 0; i < nr_threads; i++) {
249 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
250 reg[i * 2 + 1] = cpu_to_be64(0x1000);
251 }
252
253 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
254 offset = fdt_add_subnode(fdt, 0, name);
255 _FDT(offset);
256 g_free(name);
257
258 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
259 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
260 _FDT((fdt_setprop_string(fdt, offset, "device_type",
261 "PowerPC-External-Interrupt-Presentation")));
262 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
263 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
264 irange, sizeof(irange))));
265 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
266 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
267 g_free(reg);
268 }
269
270 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
271 {
272 const char *typename = pnv_chip_core_typename(chip);
273 size_t typesize = object_type_get_instance_size(typename);
274 int i;
275
276 pnv_dt_xscom(chip, fdt, 0);
277
278 for (i = 0; i < chip->nr_cores; i++) {
279 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
280
281 pnv_dt_core(chip, pnv_core, fdt);
282
283 /* Interrupt Control Presenters (ICP). One per core. */
284 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
285 }
286
287 if (chip->ram_size) {
288 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
289 }
290 }
291
292 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
293 {
294 const char *typename = pnv_chip_core_typename(chip);
295 size_t typesize = object_type_get_instance_size(typename);
296 int i;
297
298 pnv_dt_xscom(chip, fdt, 0);
299
300 for (i = 0; i < chip->nr_cores; i++) {
301 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
302
303 pnv_dt_core(chip, pnv_core, fdt);
304 }
305
306 if (chip->ram_size) {
307 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
308 }
309
310 pnv_dt_lpc(chip, fdt, 0);
311 }
312
313 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
314 {
315 uint32_t io_base = d->ioport_id;
316 uint32_t io_regs[] = {
317 cpu_to_be32(1),
318 cpu_to_be32(io_base),
319 cpu_to_be32(2)
320 };
321 char *name;
322 int node;
323
324 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
325 node = fdt_add_subnode(fdt, lpc_off, name);
326 _FDT(node);
327 g_free(name);
328
329 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
330 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
331 }
332
333 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
334 {
335 const char compatible[] = "ns16550\0pnpPNP,501";
336 uint32_t io_base = d->ioport_id;
337 uint32_t io_regs[] = {
338 cpu_to_be32(1),
339 cpu_to_be32(io_base),
340 cpu_to_be32(8)
341 };
342 char *name;
343 int node;
344
345 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
346 node = fdt_add_subnode(fdt, lpc_off, name);
347 _FDT(node);
348 g_free(name);
349
350 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
351 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
352 sizeof(compatible))));
353
354 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
355 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
356 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
357 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
358 fdt_get_phandle(fdt, lpc_off))));
359
360 /* This is needed by Linux */
361 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
362 }
363
364 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
365 {
366 const char compatible[] = "bt\0ipmi-bt";
367 uint32_t io_base;
368 uint32_t io_regs[] = {
369 cpu_to_be32(1),
370 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
371 cpu_to_be32(3)
372 };
373 uint32_t irq;
374 char *name;
375 int node;
376
377 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
378 io_regs[1] = cpu_to_be32(io_base);
379
380 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
381
382 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
383 node = fdt_add_subnode(fdt, lpc_off, name);
384 _FDT(node);
385 g_free(name);
386
387 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
388 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
389 sizeof(compatible))));
390
391 /* Mark it as reserved to avoid Linux trying to claim it */
392 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
393 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
394 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
395 fdt_get_phandle(fdt, lpc_off))));
396 }
397
398 typedef struct ForeachPopulateArgs {
399 void *fdt;
400 int offset;
401 } ForeachPopulateArgs;
402
403 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
404 {
405 ForeachPopulateArgs *args = opaque;
406 ISADevice *d = ISA_DEVICE(dev);
407
408 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
409 pnv_dt_rtc(d, args->fdt, args->offset);
410 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
411 pnv_dt_serial(d, args->fdt, args->offset);
412 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
413 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
414 } else {
415 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
416 d->ioport_id);
417 }
418
419 return 0;
420 }
421
422 /* The default LPC bus of a multichip system is on chip 0. It's
423 * recognized by the firmware (skiboot) using a "primary" property.
424 */
425 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
426 {
427 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
428 ForeachPopulateArgs args = {
429 .fdt = fdt,
430 .offset = isa_offset,
431 };
432
433 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
434
435 /* ISA devices are not necessarily parented to the ISA bus so we
436 * can not use object_child_foreach() */
437 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
438 &args);
439 }
440
441 static void pnv_dt_power_mgt(void *fdt)
442 {
443 int off;
444
445 off = fdt_add_subnode(fdt, 0, "ibm,opal");
446 off = fdt_add_subnode(fdt, off, "power-mgt");
447
448 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
449 }
450
451 static void *pnv_dt_create(MachineState *machine)
452 {
453 const char plat_compat[] = "qemu,powernv\0ibm,powernv";
454 PnvMachineState *pnv = PNV_MACHINE(machine);
455 void *fdt;
456 char *buf;
457 int off;
458 int i;
459
460 fdt = g_malloc0(FDT_MAX_SIZE);
461 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
462
463 /* Root node */
464 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
465 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
466 _FDT((fdt_setprop_string(fdt, 0, "model",
467 "IBM PowerNV (emulated by qemu)")));
468 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat,
469 sizeof(plat_compat))));
470
471 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
472 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
473 if (qemu_uuid_set) {
474 _FDT((fdt_property_string(fdt, "system-id", buf)));
475 }
476 g_free(buf);
477
478 off = fdt_add_subnode(fdt, 0, "chosen");
479 if (machine->kernel_cmdline) {
480 _FDT((fdt_setprop_string(fdt, off, "bootargs",
481 machine->kernel_cmdline)));
482 }
483
484 if (pnv->initrd_size) {
485 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
486 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
487
488 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
489 &start_prop, sizeof(start_prop))));
490 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
491 &end_prop, sizeof(end_prop))));
492 }
493
494 /* Populate device tree for each chip */
495 for (i = 0; i < pnv->num_chips; i++) {
496 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
497 }
498
499 /* Populate ISA devices on chip 0 */
500 pnv_dt_isa(pnv, fdt);
501
502 if (pnv->bmc) {
503 pnv_dt_bmc_sensors(pnv->bmc, fdt);
504 }
505
506 /* Create an extra node for power management on Power9 */
507 if (pnv_is_power9(pnv)) {
508 pnv_dt_power_mgt(fdt);
509 }
510
511 return fdt;
512 }
513
514 static void pnv_powerdown_notify(Notifier *n, void *opaque)
515 {
516 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
517
518 if (pnv->bmc) {
519 pnv_bmc_powerdown(pnv->bmc);
520 }
521 }
522
523 static void pnv_reset(void)
524 {
525 MachineState *machine = MACHINE(qdev_get_machine());
526 PnvMachineState *pnv = PNV_MACHINE(machine);
527 void *fdt;
528 Object *obj;
529
530 qemu_devices_reset();
531
532 /* OpenPOWER systems have a BMC, which can be defined on the
533 * command line with:
534 *
535 * -device ipmi-bmc-sim,id=bmc0
536 *
537 * This is the internal simulator but it could also be an external
538 * BMC.
539 */
540 obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL);
541 if (obj) {
542 pnv->bmc = IPMI_BMC(obj);
543 }
544
545 fdt = pnv_dt_create(machine);
546
547 /* Pack resulting tree */
548 _FDT((fdt_pack(fdt)));
549
550 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
551 }
552
553 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
554 {
555 Pnv8Chip *chip8 = PNV8_CHIP(chip);
556 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
557 }
558
559 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
560 {
561 Pnv8Chip *chip8 = PNV8_CHIP(chip);
562 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
563 }
564
565 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
566 {
567 Pnv9Chip *chip9 = PNV9_CHIP(chip);
568 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
569 }
570
571 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
572 {
573 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
574 }
575
576 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
577 {
578 Pnv8Chip *chip8 = PNV8_CHIP(chip);
579
580 ics_pic_print_info(&chip8->psi.ics, mon);
581 }
582
583 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
584 {
585 Pnv9Chip *chip9 = PNV9_CHIP(chip);
586
587 pnv_xive_pic_print_info(&chip9->xive, mon);
588 pnv_psi_pic_print_info(&chip9->psi, mon);
589 }
590
591 static void pnv_init(MachineState *machine)
592 {
593 PnvMachineState *pnv = PNV_MACHINE(machine);
594 MemoryRegion *ram;
595 char *fw_filename;
596 long fw_size;
597 int i;
598 char *chip_typename;
599
600 /* allocate RAM */
601 if (machine->ram_size < (1 * GiB)) {
602 warn_report("skiboot may not work with < 1GB of RAM");
603 }
604
605 ram = g_new(MemoryRegion, 1);
606 memory_region_allocate_system_memory(ram, NULL, "pnv.ram",
607 machine->ram_size);
608 memory_region_add_subregion(get_system_memory(), 0, ram);
609
610 /* load skiboot firmware */
611 if (bios_name == NULL) {
612 bios_name = FW_FILE_NAME;
613 }
614
615 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
616 if (!fw_filename) {
617 error_report("Could not find OPAL firmware '%s'", bios_name);
618 exit(1);
619 }
620
621 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
622 if (fw_size < 0) {
623 error_report("Could not load OPAL firmware '%s'", fw_filename);
624 exit(1);
625 }
626 g_free(fw_filename);
627
628 /* load kernel */
629 if (machine->kernel_filename) {
630 long kernel_size;
631
632 kernel_size = load_image_targphys(machine->kernel_filename,
633 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
634 if (kernel_size < 0) {
635 error_report("Could not load kernel '%s'",
636 machine->kernel_filename);
637 exit(1);
638 }
639 }
640
641 /* load initrd */
642 if (machine->initrd_filename) {
643 pnv->initrd_base = INITRD_LOAD_ADDR;
644 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
645 pnv->initrd_base, INITRD_MAX_SIZE);
646 if (pnv->initrd_size < 0) {
647 error_report("Could not load initial ram disk '%s'",
648 machine->initrd_filename);
649 exit(1);
650 }
651 }
652
653 /* Create the processor chips */
654 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
655 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
656 i, machine->cpu_type);
657 if (!object_class_by_name(chip_typename)) {
658 error_report("invalid CPU model '%.*s' for %s machine",
659 i, machine->cpu_type, MACHINE_GET_CLASS(machine)->name);
660 exit(1);
661 }
662
663 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
664 for (i = 0; i < pnv->num_chips; i++) {
665 char chip_name[32];
666 Object *chip = object_new(chip_typename);
667
668 pnv->chips[i] = PNV_CHIP(chip);
669
670 /* TODO: put all the memory in one node on chip 0 until we find a
671 * way to specify different ranges for each chip
672 */
673 if (i == 0) {
674 object_property_set_int(chip, machine->ram_size, "ram-size",
675 &error_fatal);
676 }
677
678 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
679 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
680 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
681 &error_fatal);
682 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal);
683 object_property_set_bool(chip, true, "realized", &error_fatal);
684 }
685 g_free(chip_typename);
686
687 /* Instantiate ISA bus on chip 0 */
688 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
689
690 /* Create serial port */
691 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
692
693 /* Create an RTC ISA device too */
694 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
695
696 /* OpenPOWER systems use a IPMI SEL Event message to notify the
697 * host to powerdown */
698 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
699 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
700 }
701
702 /*
703 * 0:21 Reserved - Read as zeros
704 * 22:24 Chip ID
705 * 25:28 Core number
706 * 29:31 Thread ID
707 */
708 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
709 {
710 return (chip->chip_id << 7) | (core_id << 3);
711 }
712
713 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
714 Error **errp)
715 {
716 Error *local_err = NULL;
717 Object *obj;
718 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
719
720 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()),
721 &local_err);
722 if (local_err) {
723 error_propagate(errp, local_err);
724 return;
725 }
726
727 pnv_cpu->intc = obj;
728 }
729
730 /*
731 * 0:48 Reserved - Read as zeroes
732 * 49:52 Node ID
733 * 53:55 Chip ID
734 * 56 Reserved - Read as zero
735 * 57:61 Core number
736 * 62:63 Thread ID
737 *
738 * We only care about the lower bits. uint32_t is fine for the moment.
739 */
740 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
741 {
742 return (chip->chip_id << 8) | (core_id << 2);
743 }
744
745 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
746 Error **errp)
747 {
748 Pnv9Chip *chip9 = PNV9_CHIP(chip);
749 Error *local_err = NULL;
750 Object *obj;
751 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
752
753 /*
754 * The core creates its interrupt presenter but the XIVE interrupt
755 * controller object is initialized afterwards. Hopefully, it's
756 * only used at runtime.
757 */
758 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), errp);
759 if (local_err) {
760 error_propagate(errp, local_err);
761 return;
762 }
763
764 pnv_cpu->intc = obj;
765 }
766
767 /* Allowed core identifiers on a POWER8 Processor Chip :
768 *
769 * <EX0 reserved>
770 * EX1 - Venice only
771 * EX2 - Venice only
772 * EX3 - Venice only
773 * EX4
774 * EX5
775 * EX6
776 * <EX7,8 reserved> <reserved>
777 * EX9 - Venice only
778 * EX10 - Venice only
779 * EX11 - Venice only
780 * EX12
781 * EX13
782 * EX14
783 * <EX15 reserved>
784 */
785 #define POWER8E_CORE_MASK (0x7070ull)
786 #define POWER8_CORE_MASK (0x7e7eull)
787
788 /*
789 * POWER9 has 24 cores, ids starting at 0x0
790 */
791 #define POWER9_CORE_MASK (0xffffffffffffffull)
792
793 static void pnv_chip_power8_instance_init(Object *obj)
794 {
795 Pnv8Chip *chip8 = PNV8_CHIP(obj);
796
797 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi),
798 TYPE_PNV8_PSI, &error_abort, NULL);
799 object_property_add_const_link(OBJECT(&chip8->psi), "xics",
800 OBJECT(qdev_get_machine()), &error_abort);
801
802 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc),
803 TYPE_PNV8_LPC, &error_abort, NULL);
804 object_property_add_const_link(OBJECT(&chip8->lpc), "psi",
805 OBJECT(&chip8->psi), &error_abort);
806
807 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
808 TYPE_PNV8_OCC, &error_abort, NULL);
809 object_property_add_const_link(OBJECT(&chip8->occ), "psi",
810 OBJECT(&chip8->psi), &error_abort);
811 }
812
813 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
814 {
815 PnvChip *chip = PNV_CHIP(chip8);
816 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
817 const char *typename = pnv_chip_core_typename(chip);
818 size_t typesize = object_type_get_instance_size(typename);
819 int i, j;
820 char *name;
821 XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
822
823 name = g_strdup_printf("icp-%x", chip->chip_id);
824 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
825 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
826 g_free(name);
827
828 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
829
830 /* Map the ICP registers for each thread */
831 for (i = 0; i < chip->nr_cores; i++) {
832 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
833 int core_hwid = CPU_CORE(pnv_core)->core_id;
834
835 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
836 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
837 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir));
838
839 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
840 &icp->mmio);
841 }
842 }
843 }
844
845 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
846 {
847 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
848 PnvChip *chip = PNV_CHIP(dev);
849 Pnv8Chip *chip8 = PNV8_CHIP(dev);
850 Pnv8Psi *psi8 = &chip8->psi;
851 Error *local_err = NULL;
852
853 pcc->parent_realize(dev, &local_err);
854 if (local_err) {
855 error_propagate(errp, local_err);
856 return;
857 }
858
859 /* Processor Service Interface (PSI) Host Bridge */
860 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
861 "bar", &error_fatal);
862 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
863 if (local_err) {
864 error_propagate(errp, local_err);
865 return;
866 }
867 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
868 &PNV_PSI(psi8)->xscom_regs);
869
870 /* Create LPC controller */
871 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized",
872 &error_fatal);
873 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
874
875 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
876 (uint64_t) PNV_XSCOM_BASE(chip),
877 PNV_XSCOM_LPC_BASE);
878
879 /* Interrupt Management Area. This is the memory region holding
880 * all the Interrupt Control Presenter (ICP) registers */
881 pnv_chip_icp_realize(chip8, &local_err);
882 if (local_err) {
883 error_propagate(errp, local_err);
884 return;
885 }
886
887 /* Create the simplified OCC model */
888 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err);
889 if (local_err) {
890 error_propagate(errp, local_err);
891 return;
892 }
893 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
894 }
895
896 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
897 {
898 DeviceClass *dc = DEVICE_CLASS(klass);
899 PnvChipClass *k = PNV_CHIP_CLASS(klass);
900
901 k->chip_type = PNV_CHIP_POWER8E;
902 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
903 k->cores_mask = POWER8E_CORE_MASK;
904 k->core_pir = pnv_chip_core_pir_p8;
905 k->intc_create = pnv_chip_power8_intc_create;
906 k->isa_create = pnv_chip_power8_isa_create;
907 k->dt_populate = pnv_chip_power8_dt_populate;
908 k->pic_print_info = pnv_chip_power8_pic_print_info;
909 k->xscom_base = 0x003fc0000000000ull;
910 dc->desc = "PowerNV Chip POWER8E";
911
912 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
913 &k->parent_realize);
914 }
915
916 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
917 {
918 DeviceClass *dc = DEVICE_CLASS(klass);
919 PnvChipClass *k = PNV_CHIP_CLASS(klass);
920
921 k->chip_type = PNV_CHIP_POWER8;
922 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
923 k->cores_mask = POWER8_CORE_MASK;
924 k->core_pir = pnv_chip_core_pir_p8;
925 k->intc_create = pnv_chip_power8_intc_create;
926 k->isa_create = pnv_chip_power8_isa_create;
927 k->dt_populate = pnv_chip_power8_dt_populate;
928 k->pic_print_info = pnv_chip_power8_pic_print_info;
929 k->xscom_base = 0x003fc0000000000ull;
930 dc->desc = "PowerNV Chip POWER8";
931
932 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
933 &k->parent_realize);
934 }
935
936 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
937 {
938 DeviceClass *dc = DEVICE_CLASS(klass);
939 PnvChipClass *k = PNV_CHIP_CLASS(klass);
940
941 k->chip_type = PNV_CHIP_POWER8NVL;
942 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
943 k->cores_mask = POWER8_CORE_MASK;
944 k->core_pir = pnv_chip_core_pir_p8;
945 k->intc_create = pnv_chip_power8_intc_create;
946 k->isa_create = pnv_chip_power8nvl_isa_create;
947 k->dt_populate = pnv_chip_power8_dt_populate;
948 k->pic_print_info = pnv_chip_power8_pic_print_info;
949 k->xscom_base = 0x003fc0000000000ull;
950 dc->desc = "PowerNV Chip POWER8NVL";
951
952 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
953 &k->parent_realize);
954 }
955
956 static void pnv_chip_power9_instance_init(Object *obj)
957 {
958 Pnv9Chip *chip9 = PNV9_CHIP(obj);
959
960 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive),
961 TYPE_PNV_XIVE, &error_abort, NULL);
962 object_property_add_const_link(OBJECT(&chip9->xive), "chip", obj,
963 &error_abort);
964
965 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi),
966 TYPE_PNV9_PSI, &error_abort, NULL);
967 object_property_add_const_link(OBJECT(&chip9->psi), "chip", obj,
968 &error_abort);
969
970 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc),
971 TYPE_PNV9_LPC, &error_abort, NULL);
972 object_property_add_const_link(OBJECT(&chip9->lpc), "psi",
973 OBJECT(&chip9->psi), &error_abort);
974
975 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ),
976 TYPE_PNV9_OCC, &error_abort, NULL);
977 object_property_add_const_link(OBJECT(&chip9->occ), "psi",
978 OBJECT(&chip9->psi), &error_abort);
979 }
980
981 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
982 {
983 PnvChip *chip = PNV_CHIP(chip9);
984 const char *typename = pnv_chip_core_typename(chip);
985 size_t typesize = object_type_get_instance_size(typename);
986 int i;
987
988 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
989 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
990
991 for (i = 0; i < chip9->nr_quads; i++) {
992 char eq_name[32];
993 PnvQuad *eq = &chip9->quads[i];
994 PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize);
995 int core_id = CPU_CORE(pnv_core)->core_id;
996
997 object_initialize(eq, sizeof(*eq), TYPE_PNV_QUAD);
998 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
999
1000 object_property_add_child(OBJECT(chip), eq_name, OBJECT(eq),
1001 &error_fatal);
1002 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal);
1003 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal);
1004 object_unref(OBJECT(eq));
1005
1006 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id),
1007 &eq->xscom_regs);
1008 }
1009 }
1010
1011 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1012 {
1013 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1014 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1015 PnvChip *chip = PNV_CHIP(dev);
1016 Pnv9Psi *psi9 = &chip9->psi;
1017 Error *local_err = NULL;
1018
1019 pcc->parent_realize(dev, &local_err);
1020 if (local_err) {
1021 error_propagate(errp, local_err);
1022 return;
1023 }
1024
1025 pnv_chip_quad_realize(chip9, &local_err);
1026 if (local_err) {
1027 error_propagate(errp, local_err);
1028 return;
1029 }
1030
1031 /* XIVE interrupt controller (POWER9) */
1032 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip),
1033 "ic-bar", &error_fatal);
1034 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip),
1035 "vc-bar", &error_fatal);
1036 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip),
1037 "pc-bar", &error_fatal);
1038 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip),
1039 "tm-bar", &error_fatal);
1040 object_property_set_bool(OBJECT(&chip9->xive), true, "realized",
1041 &local_err);
1042 if (local_err) {
1043 error_propagate(errp, local_err);
1044 return;
1045 }
1046 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1047 &chip9->xive.xscom_regs);
1048
1049 /* Processor Service Interface (PSI) Host Bridge */
1050 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip),
1051 "bar", &error_fatal);
1052 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err);
1053 if (local_err) {
1054 error_propagate(errp, local_err);
1055 return;
1056 }
1057 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1058 &PNV_PSI(psi9)->xscom_regs);
1059
1060 /* LPC */
1061 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err);
1062 if (local_err) {
1063 error_propagate(errp, local_err);
1064 return;
1065 }
1066 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1067 &chip9->lpc.xscom_regs);
1068
1069 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1070 (uint64_t) PNV9_LPCM_BASE(chip));
1071
1072 /* Create the simplified OCC model */
1073 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err);
1074 if (local_err) {
1075 error_propagate(errp, local_err);
1076 return;
1077 }
1078 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1079 }
1080
1081 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1082 {
1083 DeviceClass *dc = DEVICE_CLASS(klass);
1084 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1085
1086 k->chip_type = PNV_CHIP_POWER9;
1087 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
1088 k->cores_mask = POWER9_CORE_MASK;
1089 k->core_pir = pnv_chip_core_pir_p9;
1090 k->intc_create = pnv_chip_power9_intc_create;
1091 k->isa_create = pnv_chip_power9_isa_create;
1092 k->dt_populate = pnv_chip_power9_dt_populate;
1093 k->pic_print_info = pnv_chip_power9_pic_print_info;
1094 k->xscom_base = 0x00603fc00000000ull;
1095 dc->desc = "PowerNV Chip POWER9";
1096
1097 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1098 &k->parent_realize);
1099 }
1100
1101 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1102 {
1103 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1104 int cores_max;
1105
1106 /*
1107 * No custom mask for this chip, let's use the default one from *
1108 * the chip class
1109 */
1110 if (!chip->cores_mask) {
1111 chip->cores_mask = pcc->cores_mask;
1112 }
1113
1114 /* filter alien core ids ! some are reserved */
1115 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1116 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1117 chip->cores_mask);
1118 return;
1119 }
1120 chip->cores_mask &= pcc->cores_mask;
1121
1122 /* now that we have a sane layout, let check the number of cores */
1123 cores_max = ctpop64(chip->cores_mask);
1124 if (chip->nr_cores > cores_max) {
1125 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1126 cores_max);
1127 return;
1128 }
1129 }
1130
1131 static void pnv_chip_instance_init(Object *obj)
1132 {
1133 PNV_CHIP(obj)->xscom_base = PNV_CHIP_GET_CLASS(obj)->xscom_base;
1134 }
1135
1136 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
1137 {
1138 Error *error = NULL;
1139 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1140 const char *typename = pnv_chip_core_typename(chip);
1141 size_t typesize = object_type_get_instance_size(typename);
1142 int i, core_hwid;
1143
1144 if (!object_class_by_name(typename)) {
1145 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1146 return;
1147 }
1148
1149 /* Cores */
1150 pnv_chip_core_sanitize(chip, &error);
1151 if (error) {
1152 error_propagate(errp, error);
1153 return;
1154 }
1155
1156 chip->cores = g_malloc0(typesize * chip->nr_cores);
1157
1158 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1159 && (i < chip->nr_cores); core_hwid++) {
1160 char core_name[32];
1161 void *pnv_core = chip->cores + i * typesize;
1162 uint64_t xscom_core_base;
1163
1164 if (!(chip->cores_mask & (1ull << core_hwid))) {
1165 continue;
1166 }
1167
1168 object_initialize(pnv_core, typesize, typename);
1169 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
1170 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
1171 &error_fatal);
1172 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads",
1173 &error_fatal);
1174 object_property_set_int(OBJECT(pnv_core), core_hwid,
1175 CPU_CORE_PROP_CORE_ID, &error_fatal);
1176 object_property_set_int(OBJECT(pnv_core),
1177 pcc->core_pir(chip, core_hwid),
1178 "pir", &error_fatal);
1179 object_property_add_const_link(OBJECT(pnv_core), "chip",
1180 OBJECT(chip), &error_fatal);
1181 object_property_set_bool(OBJECT(pnv_core), true, "realized",
1182 &error_fatal);
1183 object_unref(OBJECT(pnv_core));
1184
1185 /* Each core has an XSCOM MMIO region */
1186 if (!pnv_chip_is_power9(chip)) {
1187 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid);
1188 } else {
1189 xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid);
1190 }
1191
1192 pnv_xscom_add_subregion(chip, xscom_core_base,
1193 &PNV_CORE(pnv_core)->xscom_regs);
1194 i++;
1195 }
1196 }
1197
1198 static void pnv_chip_realize(DeviceState *dev, Error **errp)
1199 {
1200 PnvChip *chip = PNV_CHIP(dev);
1201 Error *error = NULL;
1202
1203 /* XSCOM bridge */
1204 pnv_xscom_realize(chip, &error);
1205 if (error) {
1206 error_propagate(errp, error);
1207 return;
1208 }
1209 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1210
1211 /* Cores */
1212 pnv_chip_core_realize(chip, &error);
1213 if (error) {
1214 error_propagate(errp, error);
1215 return;
1216 }
1217 }
1218
1219 static Property pnv_chip_properties[] = {
1220 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1221 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1222 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
1223 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1224 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
1225 DEFINE_PROP_END_OF_LIST(),
1226 };
1227
1228 static void pnv_chip_class_init(ObjectClass *klass, void *data)
1229 {
1230 DeviceClass *dc = DEVICE_CLASS(klass);
1231
1232 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
1233 dc->realize = pnv_chip_realize;
1234 dc->props = pnv_chip_properties;
1235 dc->desc = "PowerNV Chip";
1236 }
1237
1238 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1239 {
1240 PnvMachineState *pnv = PNV_MACHINE(xi);
1241 int i;
1242
1243 for (i = 0; i < pnv->num_chips; i++) {
1244 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1245
1246 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1247 return &chip8->psi.ics;
1248 }
1249 }
1250 return NULL;
1251 }
1252
1253 static void pnv_ics_resend(XICSFabric *xi)
1254 {
1255 PnvMachineState *pnv = PNV_MACHINE(xi);
1256 int i;
1257
1258 for (i = 0; i < pnv->num_chips; i++) {
1259 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1260 ics_resend(&chip8->psi.ics);
1261 }
1262 }
1263
1264 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1265 {
1266 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1267
1268 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
1269 }
1270
1271 static void pnv_pic_print_info(InterruptStatsProvider *obj,
1272 Monitor *mon)
1273 {
1274 PnvMachineState *pnv = PNV_MACHINE(obj);
1275 int i;
1276 CPUState *cs;
1277
1278 CPU_FOREACH(cs) {
1279 PowerPCCPU *cpu = POWERPC_CPU(cs);
1280
1281 if (pnv_chip_is_power9(pnv->chips[0])) {
1282 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1283 } else {
1284 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
1285 }
1286 }
1287
1288 for (i = 0; i < pnv->num_chips; i++) {
1289 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
1290 }
1291 }
1292
1293 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
1294 void *opaque, Error **errp)
1295 {
1296 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp);
1297 }
1298
1299 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
1300 void *opaque, Error **errp)
1301 {
1302 PnvMachineState *pnv = PNV_MACHINE(obj);
1303 uint32_t num_chips;
1304 Error *local_err = NULL;
1305
1306 visit_type_uint32(v, name, &num_chips, &local_err);
1307 if (local_err) {
1308 error_propagate(errp, local_err);
1309 return;
1310 }
1311
1312 /*
1313 * TODO: should we decide on how many chips we can create based
1314 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1315 */
1316 if (!is_power_of_2(num_chips) || num_chips > 4) {
1317 error_setg(errp, "invalid number of chips: '%d'", num_chips);
1318 return;
1319 }
1320
1321 pnv->num_chips = num_chips;
1322 }
1323
1324 static void pnv_machine_instance_init(Object *obj)
1325 {
1326 PnvMachineState *pnv = PNV_MACHINE(obj);
1327 pnv->num_chips = 1;
1328 }
1329
1330 static void pnv_machine_class_props_init(ObjectClass *oc)
1331 {
1332 object_class_property_add(oc, "num-chips", "uint32",
1333 pnv_get_num_chips, pnv_set_num_chips,
1334 NULL, NULL, NULL);
1335 object_class_property_set_description(oc, "num-chips",
1336 "Specifies the number of processor chips",
1337 NULL);
1338 }
1339
1340 static void pnv_machine_class_init(ObjectClass *oc, void *data)
1341 {
1342 MachineClass *mc = MACHINE_CLASS(oc);
1343 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
1344 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
1345
1346 mc->desc = "IBM PowerNV (Non-Virtualized)";
1347 mc->init = pnv_init;
1348 mc->reset = pnv_reset;
1349 mc->max_cpus = MAX_CPUS;
1350 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
1351 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
1352 * storage */
1353 mc->no_parallel = 1;
1354 mc->default_boot_order = NULL;
1355 mc->default_ram_size = 1 * GiB;
1356 xic->icp_get = pnv_icp_get;
1357 xic->ics_get = pnv_ics_get;
1358 xic->ics_resend = pnv_ics_resend;
1359 ispc->print_info = pnv_pic_print_info;
1360
1361 pnv_machine_class_props_init(oc);
1362 }
1363
1364 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
1365 { \
1366 .name = type, \
1367 .class_init = class_initfn, \
1368 .parent = TYPE_PNV8_CHIP, \
1369 }
1370
1371 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
1372 { \
1373 .name = type, \
1374 .class_init = class_initfn, \
1375 .parent = TYPE_PNV9_CHIP, \
1376 }
1377
1378 static const TypeInfo types[] = {
1379 {
1380 .name = TYPE_PNV_MACHINE,
1381 .parent = TYPE_MACHINE,
1382 .instance_size = sizeof(PnvMachineState),
1383 .instance_init = pnv_machine_instance_init,
1384 .class_init = pnv_machine_class_init,
1385 .interfaces = (InterfaceInfo[]) {
1386 { TYPE_XICS_FABRIC },
1387 { TYPE_INTERRUPT_STATS_PROVIDER },
1388 { },
1389 },
1390 },
1391 {
1392 .name = TYPE_PNV_CHIP,
1393 .parent = TYPE_SYS_BUS_DEVICE,
1394 .class_init = pnv_chip_class_init,
1395 .instance_init = pnv_chip_instance_init,
1396 .instance_size = sizeof(PnvChip),
1397 .class_size = sizeof(PnvChipClass),
1398 .abstract = true,
1399 },
1400
1401 /*
1402 * P9 chip and variants
1403 */
1404 {
1405 .name = TYPE_PNV9_CHIP,
1406 .parent = TYPE_PNV_CHIP,
1407 .instance_init = pnv_chip_power9_instance_init,
1408 .instance_size = sizeof(Pnv9Chip),
1409 },
1410 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
1411
1412 /*
1413 * P8 chip and variants
1414 */
1415 {
1416 .name = TYPE_PNV8_CHIP,
1417 .parent = TYPE_PNV_CHIP,
1418 .instance_init = pnv_chip_power8_instance_init,
1419 .instance_size = sizeof(Pnv8Chip),
1420 },
1421 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
1422 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
1423 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
1424 pnv_chip_power8nvl_class_init),
1425 };
1426
1427 DEFINE_TYPES(types)
Random patches