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target-ppc: add cnttzw[.] instruction
[qemu/kevin.git] / target-ppc / translate.c
blobb24845344e6868b7f864a1cdcc252454516ab43f
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91 tcg_ctx.tcg_env = cpu_env;
92
93 p = cpu_reg_names;
94 cpu_reg_names_size = sizeof(cpu_reg_names);
95
96 for (i = 0; i < 8; i++) {
97 snprintf(p, cpu_reg_names_size, "crf%d", i);
98 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
99 offsetof(CPUPPCState, crf[i]), p);
100 p += 5;
101 cpu_reg_names_size -= 5;
102 }
103
104 for (i = 0; i < 32; i++) {
105 snprintf(p, cpu_reg_names_size, "r%d", i);
106 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gpr[i]), p);
108 p += (i < 10) ? 3 : 4;
109 cpu_reg_names_size -= (i < 10) ? 3 : 4;
110 snprintf(p, cpu_reg_names_size, "r%dH", i);
111 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUPPCState, gprh[i]), p);
113 p += (i < 10) ? 4 : 5;
114 cpu_reg_names_size -= (i < 10) ? 4 : 5;
115
116 snprintf(p, cpu_reg_names_size, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
118 offsetof(CPUPPCState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120 cpu_reg_names_size -= (i < 10) ? 4 : 5;
121
122 snprintf(p, cpu_reg_names_size, "avr%dH", i);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
125 offsetof(CPUPPCState, avr[i].u64[0]), p);
126 #else
127 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
128 offsetof(CPUPPCState, avr[i].u64[1]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 cpu_reg_names_size -= (i < 10) ? 6 : 7;
132
133 snprintf(p, cpu_reg_names_size, "avr%dL", i);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
136 offsetof(CPUPPCState, avr[i].u64[1]), p);
137 #else
138 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
139 offsetof(CPUPPCState, avr[i].u64[0]), p);
140 #endif
141 p += (i < 10) ? 6 : 7;
142 cpu_reg_names_size -= (i < 10) ? 6 : 7;
143 snprintf(p, cpu_reg_names_size, "vsr%d", i);
144 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
145 offsetof(CPUPPCState, vsr[i]), p);
146 p += (i < 10) ? 5 : 6;
147 cpu_reg_names_size -= (i < 10) ? 5 : 6;
148 }
149
150 cpu_nip = tcg_global_mem_new(cpu_env,
151 offsetof(CPUPPCState, nip), "nip");
152
153 cpu_msr = tcg_global_mem_new(cpu_env,
154 offsetof(CPUPPCState, msr), "msr");
155
156 cpu_ctr = tcg_global_mem_new(cpu_env,
157 offsetof(CPUPPCState, ctr), "ctr");
158
159 cpu_lr = tcg_global_mem_new(cpu_env,
160 offsetof(CPUPPCState, lr), "lr");
161
162 #if defined(TARGET_PPC64)
163 cpu_cfar = tcg_global_mem_new(cpu_env,
164 offsetof(CPUPPCState, cfar), "cfar");
165 #endif
166
167 cpu_xer = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, xer), "xer");
169 cpu_so = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, so), "SO");
171 cpu_ov = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ov), "OV");
173 cpu_ca = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ca), "CA");
175
176 cpu_reserve = tcg_global_mem_new(cpu_env,
177 offsetof(CPUPPCState, reserve_addr),
178 "reserve_addr");
179
180 cpu_fpscr = tcg_global_mem_new(cpu_env,
181 offsetof(CPUPPCState, fpscr), "fpscr");
182
183 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
184 offsetof(CPUPPCState, access_type), "access_type");
185
186 done_init = 1;
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 struct TranslationBlock *tb;
192 target_ulong nip;
193 uint32_t opcode;
194 uint32_t exception;
195 /* Routine used to access memory */
196 bool pr, hv, dr, le_mode;
197 bool lazy_tlb_flush;
198 int mem_idx;
199 int access_type;
200 /* Translation flags */
201 TCGMemOp default_tcg_memop_mask;
202 #if defined(TARGET_PPC64)
203 bool sf_mode;
204 bool has_cfar;
205 #endif
206 bool fpu_enabled;
207 bool altivec_enabled;
208 bool vsx_enabled;
209 bool spe_enabled;
210 bool tm_enabled;
211 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
212 int singlestep_enabled;
213 uint64_t insns_flags;
214 uint64_t insns_flags2;
215 };
216
217 /* Return true iff byteswap is needed in a scalar memop */
218 static inline bool need_byteswap(const DisasContext *ctx)
219 {
220 #if defined(TARGET_WORDS_BIGENDIAN)
221 return ctx->le_mode;
222 #else
223 return !ctx->le_mode;
224 #endif
225 }
226
227 /* True when active word size < size of target_long. */
228 #ifdef TARGET_PPC64
229 # define NARROW_MODE(C) (!(C)->sf_mode)
230 #else
231 # define NARROW_MODE(C) 0
232 #endif
233
234 struct opc_handler_t {
235 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
236 uint32_t inval1;
237 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
238 uint32_t inval2;
239 /* instruction type */
240 uint64_t type;
241 /* extended instruction type */
242 uint64_t type2;
243 /* handler */
244 void (*handler)(DisasContext *ctx);
245 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
246 const char *oname;
247 #endif
248 #if defined(DO_PPC_STATISTICS)
249 uint64_t count;
250 #endif
251 };
252
253 static inline void gen_reset_fpstatus(void)
254 {
255 gen_helper_reset_fpstatus(cpu_env);
256 }
257
258 static inline void gen_compute_fprf(TCGv_i64 arg)
259 {
260 gen_helper_compute_fprf(cpu_env, arg);
261 gen_helper_float_check_status(cpu_env);
262 }
263
264 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
265 {
266 if (ctx->access_type != access_type) {
267 tcg_gen_movi_i32(cpu_access_type, access_type);
268 ctx->access_type = access_type;
269 }
270 }
271
272 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
273 {
274 if (NARROW_MODE(ctx)) {
275 nip = (uint32_t)nip;
276 }
277 tcg_gen_movi_tl(cpu_nip, nip);
278 }
279
280 void gen_update_current_nip(void *opaque)
281 {
282 DisasContext *ctx = opaque;
283
284 tcg_gen_movi_tl(cpu_nip, ctx->nip);
285 }
286
287 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
288 {
289 TCGv_i32 t0, t1;
290 if (ctx->exception == POWERPC_EXCP_NONE) {
291 gen_update_nip(ctx, ctx->nip);
292 }
293 t0 = tcg_const_i32(excp);
294 t1 = tcg_const_i32(error);
295 gen_helper_raise_exception_err(cpu_env, t0, t1);
296 tcg_temp_free_i32(t0);
297 tcg_temp_free_i32(t1);
298 ctx->exception = (excp);
299 }
300
301 static void gen_exception(DisasContext *ctx, uint32_t excp)
302 {
303 TCGv_i32 t0;
304 if (ctx->exception == POWERPC_EXCP_NONE) {
305 gen_update_nip(ctx, ctx->nip);
306 }
307 t0 = tcg_const_i32(excp);
308 gen_helper_raise_exception(cpu_env, t0);
309 tcg_temp_free_i32(t0);
310 ctx->exception = (excp);
311 }
312
313 static void gen_debug_exception(DisasContext *ctx)
314 {
315 TCGv_i32 t0;
316
317 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
318 (ctx->exception != POWERPC_EXCP_SYNC)) {
319 gen_update_nip(ctx, ctx->nip);
320 }
321 t0 = tcg_const_i32(EXCP_DEBUG);
322 gen_helper_raise_exception(cpu_env, t0);
323 tcg_temp_free_i32(t0);
324 }
325
326 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
327 {
328 /* Will be converted to program check if needed */
329 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
330 }
331
332 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
333 {
334 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
335 }
336
337 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
338 {
339 /* Will be converted to program check if needed */
340 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
341 }
342
343 /* Stop translation */
344 static inline void gen_stop_exception(DisasContext *ctx)
345 {
346 gen_update_nip(ctx, ctx->nip);
347 ctx->exception = POWERPC_EXCP_STOP;
348 }
349
350 #ifndef CONFIG_USER_ONLY
351 /* No need to update nip here, as execution flow will change */
352 static inline void gen_sync_exception(DisasContext *ctx)
353 {
354 ctx->exception = POWERPC_EXCP_SYNC;
355 }
356 #endif
357
358 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
359 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
360
361 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
362 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
363
364 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
365 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
366
367 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
368 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
369
370 typedef struct opcode_t {
371 unsigned char opc1, opc2, opc3;
372 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
373 unsigned char pad[5];
374 #else
375 unsigned char pad[1];
376 #endif
377 opc_handler_t handler;
378 const char *oname;
379 } opcode_t;
380
381 /* Helpers for priv. check */
382 #define GEN_PRIV \
383 do { \
384 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
385 } while (0)
386
387 #if defined(CONFIG_USER_ONLY)
388 #define CHK_HV GEN_PRIV
389 #define CHK_SV GEN_PRIV
390 #define CHK_HVRM GEN_PRIV
391 #else
392 #define CHK_HV \
393 do { \
394 if (unlikely(ctx->pr || !ctx->hv)) { \
395 GEN_PRIV; \
396 } \
397 } while (0)
398 #define CHK_SV \
399 do { \
400 if (unlikely(ctx->pr)) { \
401 GEN_PRIV; \
402 } \
403 } while (0)
404 #define CHK_HVRM \
405 do { \
406 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
407 GEN_PRIV; \
408 } \
409 } while (0)
410 #endif
411
412 #define CHK_NONE
413
414
415 /*****************************************************************************/
416 /*** Instruction decoding ***/
417 #define EXTRACT_HELPER(name, shift, nb) \
418 static inline uint32_t name(uint32_t opcode) \
419 { \
420 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
421 }
422
423 #define EXTRACT_SHELPER(name, shift, nb) \
424 static inline int32_t name(uint32_t opcode) \
425 { \
426 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
427 }
428
429 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
430 static inline uint32_t name(uint32_t opcode) \
431 { \
432 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
433 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
434 }
435
436 #define EXTRACT_HELPER_DXFORM(name, \
437 d0_bits, shift_op_d0, shift_d0, \
438 d1_bits, shift_op_d1, shift_d1, \
439 d2_bits, shift_op_d2, shift_d2) \
440 static inline int16_t name(uint32_t opcode) \
441 { \
442 return \
443 (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
444 (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
445 (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
446 }
447
448
449 /* Opcode part 1 */
450 EXTRACT_HELPER(opc1, 26, 6);
451 /* Opcode part 2 */
452 EXTRACT_HELPER(opc2, 1, 5);
453 /* Opcode part 3 */
454 EXTRACT_HELPER(opc3, 6, 5);
455 /* Update Cr0 flags */
456 EXTRACT_HELPER(Rc, 0, 1);
457 /* Update Cr6 flags (Altivec) */
458 EXTRACT_HELPER(Rc21, 10, 1);
459 /* Destination */
460 EXTRACT_HELPER(rD, 21, 5);
461 /* Source */
462 EXTRACT_HELPER(rS, 21, 5);
463 /* First operand */
464 EXTRACT_HELPER(rA, 16, 5);
465 /* Second operand */
466 EXTRACT_HELPER(rB, 11, 5);
467 /* Third operand */
468 EXTRACT_HELPER(rC, 6, 5);
469 /*** Get CRn ***/
470 EXTRACT_HELPER(crfD, 23, 3);
471 EXTRACT_HELPER(crfS, 18, 3);
472 EXTRACT_HELPER(crbD, 21, 5);
473 EXTRACT_HELPER(crbA, 16, 5);
474 EXTRACT_HELPER(crbB, 11, 5);
475 /* SPR / TBL */
476 EXTRACT_HELPER(_SPR, 11, 10);
477 static inline uint32_t SPR(uint32_t opcode)
478 {
479 uint32_t sprn = _SPR(opcode);
480
481 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
482 }
483 /*** Get constants ***/
484 /* 16 bits signed immediate value */
485 EXTRACT_SHELPER(SIMM, 0, 16);
486 /* 16 bits unsigned immediate value */
487 EXTRACT_HELPER(UIMM, 0, 16);
488 /* 5 bits signed immediate value */
489 EXTRACT_HELPER(SIMM5, 16, 5);
490 /* 5 bits signed immediate value */
491 EXTRACT_HELPER(UIMM5, 16, 5);
492 /* Bit count */
493 EXTRACT_HELPER(NB, 11, 5);
494 /* Shift count */
495 EXTRACT_HELPER(SH, 11, 5);
496 /* Vector shift count */
497 EXTRACT_HELPER(VSH, 6, 4);
498 /* Mask start */
499 EXTRACT_HELPER(MB, 6, 5);
500 /* Mask end */
501 EXTRACT_HELPER(ME, 1, 5);
502 /* Trap operand */
503 EXTRACT_HELPER(TO, 21, 5);
504
505 EXTRACT_HELPER(CRM, 12, 8);
506
507 #ifndef CONFIG_USER_ONLY
508 EXTRACT_HELPER(SR, 16, 4);
509 #endif
510
511 /* mtfsf/mtfsfi */
512 EXTRACT_HELPER(FPBF, 23, 3);
513 EXTRACT_HELPER(FPIMM, 12, 4);
514 EXTRACT_HELPER(FPL, 25, 1);
515 EXTRACT_HELPER(FPFLM, 17, 8);
516 EXTRACT_HELPER(FPW, 16, 1);
517
518 /* addpcis */
519 EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
520
521 /*** Jump target decoding ***/
522 /* Immediate address */
523 static inline target_ulong LI(uint32_t opcode)
524 {
525 return (opcode >> 0) & 0x03FFFFFC;
526 }
527
528 static inline uint32_t BD(uint32_t opcode)
529 {
530 return (opcode >> 0) & 0xFFFC;
531 }
532
533 EXTRACT_HELPER(BO, 21, 5);
534 EXTRACT_HELPER(BI, 16, 5);
535 /* Absolute/relative address */
536 EXTRACT_HELPER(AA, 1, 1);
537 /* Link */
538 EXTRACT_HELPER(LK, 0, 1);
539
540 /* DFP Z22-form */
541 EXTRACT_HELPER(DCM, 10, 6)
542
543 /* DFP Z23-form */
544 EXTRACT_HELPER(RMC, 9, 2)
545
546 /* Create a mask between <start> and <end> bits */
547 static inline target_ulong MASK(uint32_t start, uint32_t end)
548 {
549 target_ulong ret;
550
551 #if defined(TARGET_PPC64)
552 if (likely(start == 0)) {
553 ret = UINT64_MAX << (63 - end);
554 } else if (likely(end == 63)) {
555 ret = UINT64_MAX >> start;
556 }
557 #else
558 if (likely(start == 0)) {
559 ret = UINT32_MAX << (31 - end);
560 } else if (likely(end == 31)) {
561 ret = UINT32_MAX >> start;
562 }
563 #endif
564 else {
565 ret = (((target_ulong)(-1ULL)) >> (start)) ^
566 (((target_ulong)(-1ULL) >> (end)) >> 1);
567 if (unlikely(start > end))
568 return ~ret;
569 }
570
571 return ret;
572 }
573
574 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
575 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
576 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
577 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
578 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
579 EXTRACT_HELPER(DM, 8, 2);
580 EXTRACT_HELPER(UIM, 16, 2);
581 EXTRACT_HELPER(SHW, 8, 2);
582 EXTRACT_HELPER(SP, 19, 2);
583 /*****************************************************************************/
584 /* PowerPC instructions table */
585
586 #if defined(DO_PPC_STATISTICS)
587 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
588 { \
589 .opc1 = op1, \
590 .opc2 = op2, \
591 .opc3 = op3, \
592 .pad = { 0, }, \
593 .handler = { \
594 .inval1 = invl, \
595 .type = _typ, \
596 .type2 = _typ2, \
597 .handler = &gen_##name, \
598 .oname = stringify(name), \
599 }, \
600 .oname = stringify(name), \
601 }
602 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
603 { \
604 .opc1 = op1, \
605 .opc2 = op2, \
606 .opc3 = op3, \
607 .pad = { 0, }, \
608 .handler = { \
609 .inval1 = invl1, \
610 .inval2 = invl2, \
611 .type = _typ, \
612 .type2 = _typ2, \
613 .handler = &gen_##name, \
614 .oname = stringify(name), \
615 }, \
616 .oname = stringify(name), \
617 }
618 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
619 { \
620 .opc1 = op1, \
621 .opc2 = op2, \
622 .opc3 = op3, \
623 .pad = { 0, }, \
624 .handler = { \
625 .inval1 = invl, \
626 .type = _typ, \
627 .type2 = _typ2, \
628 .handler = &gen_##name, \
629 .oname = onam, \
630 }, \
631 .oname = onam, \
632 }
633 #else
634 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
635 { \
636 .opc1 = op1, \
637 .opc2 = op2, \
638 .opc3 = op3, \
639 .pad = { 0, }, \
640 .handler = { \
641 .inval1 = invl, \
642 .type = _typ, \
643 .type2 = _typ2, \
644 .handler = &gen_##name, \
645 }, \
646 .oname = stringify(name), \
647 }
648 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
649 { \
650 .opc1 = op1, \
651 .opc2 = op2, \
652 .opc3 = op3, \
653 .pad = { 0, }, \
654 .handler = { \
655 .inval1 = invl1, \
656 .inval2 = invl2, \
657 .type = _typ, \
658 .type2 = _typ2, \
659 .handler = &gen_##name, \
660 }, \
661 .oname = stringify(name), \
662 }
663 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
664 { \
665 .opc1 = op1, \
666 .opc2 = op2, \
667 .opc3 = op3, \
668 .pad = { 0, }, \
669 .handler = { \
670 .inval1 = invl, \
671 .type = _typ, \
672 .type2 = _typ2, \
673 .handler = &gen_##name, \
674 }, \
675 .oname = onam, \
676 }
677 #endif
678
679 /* SPR load/store helpers */
680 static inline void gen_load_spr(TCGv t, int reg)
681 {
682 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
683 }
684
685 static inline void gen_store_spr(int reg, TCGv t)
686 {
687 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
688 }
689
690 /* Invalid instruction */
691 static void gen_invalid(DisasContext *ctx)
692 {
693 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
694 }
695
696 static opc_handler_t invalid_handler = {
697 .inval1 = 0xFFFFFFFF,
698 .inval2 = 0xFFFFFFFF,
699 .type = PPC_NONE,
700 .type2 = PPC_NONE,
701 .handler = gen_invalid,
702 };
703
704 /*** Integer comparison ***/
705
706 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
707 {
708 TCGv t0 = tcg_temp_new();
709 TCGv_i32 t1 = tcg_temp_new_i32();
710
711 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
712
713 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
714 tcg_gen_trunc_tl_i32(t1, t0);
715 tcg_gen_shli_i32(t1, t1, CRF_LT);
716 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
717
718 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
719 tcg_gen_trunc_tl_i32(t1, t0);
720 tcg_gen_shli_i32(t1, t1, CRF_GT);
721 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
722
723 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
724 tcg_gen_trunc_tl_i32(t1, t0);
725 tcg_gen_shli_i32(t1, t1, CRF_EQ);
726 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
727
728 tcg_temp_free(t0);
729 tcg_temp_free_i32(t1);
730 }
731
732 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
733 {
734 TCGv t0 = tcg_const_tl(arg1);
735 gen_op_cmp(arg0, t0, s, crf);
736 tcg_temp_free(t0);
737 }
738
739 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
740 {
741 TCGv t0, t1;
742 t0 = tcg_temp_new();
743 t1 = tcg_temp_new();
744 if (s) {
745 tcg_gen_ext32s_tl(t0, arg0);
746 tcg_gen_ext32s_tl(t1, arg1);
747 } else {
748 tcg_gen_ext32u_tl(t0, arg0);
749 tcg_gen_ext32u_tl(t1, arg1);
750 }
751 gen_op_cmp(t0, t1, s, crf);
752 tcg_temp_free(t1);
753 tcg_temp_free(t0);
754 }
755
756 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
757 {
758 TCGv t0 = tcg_const_tl(arg1);
759 gen_op_cmp32(arg0, t0, s, crf);
760 tcg_temp_free(t0);
761 }
762
763 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
764 {
765 if (NARROW_MODE(ctx)) {
766 gen_op_cmpi32(reg, 0, 1, 0);
767 } else {
768 gen_op_cmpi(reg, 0, 1, 0);
769 }
770 }
771
772 /* cmp */
773 static void gen_cmp(DisasContext *ctx)
774 {
775 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
776 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
777 1, crfD(ctx->opcode));
778 } else {
779 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
780 1, crfD(ctx->opcode));
781 }
782 }
783
784 /* cmpi */
785 static void gen_cmpi(DisasContext *ctx)
786 {
787 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
788 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
789 1, crfD(ctx->opcode));
790 } else {
791 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
792 1, crfD(ctx->opcode));
793 }
794 }
795
796 /* cmpl */
797 static void gen_cmpl(DisasContext *ctx)
798 {
799 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
800 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
801 0, crfD(ctx->opcode));
802 } else {
803 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
804 0, crfD(ctx->opcode));
805 }
806 }
807
808 /* cmpli */
809 static void gen_cmpli(DisasContext *ctx)
810 {
811 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
812 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
813 0, crfD(ctx->opcode));
814 } else {
815 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
816 0, crfD(ctx->opcode));
817 }
818 }
819
820 /* cmprb - range comparison: isupper, isaplha, islower*/
821 static void gen_cmprb(DisasContext *ctx)
822 {
823 TCGv_i32 src1 = tcg_temp_new_i32();
824 TCGv_i32 src2 = tcg_temp_new_i32();
825 TCGv_i32 src2lo = tcg_temp_new_i32();
826 TCGv_i32 src2hi = tcg_temp_new_i32();
827 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
828
829 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
830 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
831
832 tcg_gen_andi_i32(src1, src1, 0xFF);
833 tcg_gen_ext8u_i32(src2lo, src2);
834 tcg_gen_shri_i32(src2, src2, 8);
835 tcg_gen_ext8u_i32(src2hi, src2);
836
837 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
838 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
839 tcg_gen_and_i32(crf, src2lo, src2hi);
840
841 if (ctx->opcode & 0x00200000) {
842 tcg_gen_shri_i32(src2, src2, 8);
843 tcg_gen_ext8u_i32(src2lo, src2);
844 tcg_gen_shri_i32(src2, src2, 8);
845 tcg_gen_ext8u_i32(src2hi, src2);
846 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
847 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
848 tcg_gen_and_i32(src2lo, src2lo, src2hi);
849 tcg_gen_or_i32(crf, crf, src2lo);
850 }
851 tcg_gen_shli_i32(crf, crf, CRF_GT);
852 tcg_temp_free_i32(src1);
853 tcg_temp_free_i32(src2);
854 tcg_temp_free_i32(src2lo);
855 tcg_temp_free_i32(src2hi);
856 }
857
858 /* isel (PowerPC 2.03 specification) */
859 static void gen_isel(DisasContext *ctx)
860 {
861 uint32_t bi = rC(ctx->opcode);
862 uint32_t mask = 0x08 >> (bi & 0x03);
863 TCGv t0 = tcg_temp_new();
864 TCGv zr;
865
866 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
867 tcg_gen_andi_tl(t0, t0, mask);
868
869 zr = tcg_const_tl(0);
870 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
871 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
872 cpu_gpr[rB(ctx->opcode)]);
873 tcg_temp_free(zr);
874 tcg_temp_free(t0);
875 }
876
877 /* cmpb: PowerPC 2.05 specification */
878 static void gen_cmpb(DisasContext *ctx)
879 {
880 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
881 cpu_gpr[rB(ctx->opcode)]);
882 }
883
884 /*** Integer arithmetic ***/
885
886 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
887 TCGv arg1, TCGv arg2, int sub)
888 {
889 TCGv t0 = tcg_temp_new();
890
891 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
892 tcg_gen_xor_tl(t0, arg1, arg2);
893 if (sub) {
894 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
895 } else {
896 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
897 }
898 tcg_temp_free(t0);
899 if (NARROW_MODE(ctx)) {
900 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
901 }
902 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
903 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
904 }
905
906 /* Common add function */
907 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
908 TCGv arg2, bool add_ca, bool compute_ca,
909 bool compute_ov, bool compute_rc0)
910 {
911 TCGv t0 = ret;
912
913 if (compute_ca || compute_ov) {
914 t0 = tcg_temp_new();
915 }
916
917 if (compute_ca) {
918 if (NARROW_MODE(ctx)) {
919 /* Caution: a non-obvious corner case of the spec is that we
920 must produce the *entire* 64-bit addition, but produce the
921 carry into bit 32. */
922 TCGv t1 = tcg_temp_new();
923 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
924 tcg_gen_add_tl(t0, arg1, arg2);
925 if (add_ca) {
926 tcg_gen_add_tl(t0, t0, cpu_ca);
927 }
928 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
929 tcg_temp_free(t1);
930 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
931 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
932 } else {
933 TCGv zero = tcg_const_tl(0);
934 if (add_ca) {
935 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
936 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
937 } else {
938 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
939 }
940 tcg_temp_free(zero);
941 }
942 } else {
943 tcg_gen_add_tl(t0, arg1, arg2);
944 if (add_ca) {
945 tcg_gen_add_tl(t0, t0, cpu_ca);
946 }
947 }
948
949 if (compute_ov) {
950 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
951 }
952 if (unlikely(compute_rc0)) {
953 gen_set_Rc0(ctx, t0);
954 }
955
956 if (!TCGV_EQUAL(t0, ret)) {
957 tcg_gen_mov_tl(ret, t0);
958 tcg_temp_free(t0);
959 }
960 }
961 /* Add functions with two operands */
962 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
963 static void glue(gen_, name)(DisasContext *ctx) \
964 { \
965 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
966 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
967 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
968 }
969 /* Add functions with one operand and one immediate */
970 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
971 add_ca, compute_ca, compute_ov) \
972 static void glue(gen_, name)(DisasContext *ctx) \
973 { \
974 TCGv t0 = tcg_const_tl(const_val); \
975 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
976 cpu_gpr[rA(ctx->opcode)], t0, \
977 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
978 tcg_temp_free(t0); \
979 }
980
981 /* add add. addo addo. */
982 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
983 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
984 /* addc addc. addco addco. */
985 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
986 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
987 /* adde adde. addeo addeo. */
988 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
989 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
990 /* addme addme. addmeo addmeo. */
991 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
992 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
993 /* addze addze. addzeo addzeo.*/
994 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
995 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
996 /* addi */
997 static void gen_addi(DisasContext *ctx)
998 {
999 target_long simm = SIMM(ctx->opcode);
1000
1001 if (rA(ctx->opcode) == 0) {
1002 /* li case */
1003 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1004 } else {
1005 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1006 cpu_gpr[rA(ctx->opcode)], simm);
1007 }
1008 }
1009 /* addic addic.*/
1010 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1011 {
1012 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1013 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1014 c, 0, 1, 0, compute_rc0);
1015 tcg_temp_free(c);
1016 }
1017
1018 static void gen_addic(DisasContext *ctx)
1019 {
1020 gen_op_addic(ctx, 0);
1021 }
1022
1023 static void gen_addic_(DisasContext *ctx)
1024 {
1025 gen_op_addic(ctx, 1);
1026 }
1027
1028 /* addis */
1029 static void gen_addis(DisasContext *ctx)
1030 {
1031 target_long simm = SIMM(ctx->opcode);
1032
1033 if (rA(ctx->opcode) == 0) {
1034 /* lis case */
1035 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1036 } else {
1037 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1038 cpu_gpr[rA(ctx->opcode)], simm << 16);
1039 }
1040 }
1041
1042 /* addpcis */
1043 static void gen_addpcis(DisasContext *ctx)
1044 {
1045 target_long d = DX(ctx->opcode);
1046
1047 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
1048 }
1049
1050 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1051 TCGv arg2, int sign, int compute_ov)
1052 {
1053 TCGLabel *l1 = gen_new_label();
1054 TCGLabel *l2 = gen_new_label();
1055 TCGv_i32 t0 = tcg_temp_local_new_i32();
1056 TCGv_i32 t1 = tcg_temp_local_new_i32();
1057
1058 tcg_gen_trunc_tl_i32(t0, arg1);
1059 tcg_gen_trunc_tl_i32(t1, arg2);
1060 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1061 if (sign) {
1062 TCGLabel *l3 = gen_new_label();
1063 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1064 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1065 gen_set_label(l3);
1066 tcg_gen_div_i32(t0, t0, t1);
1067 } else {
1068 tcg_gen_divu_i32(t0, t0, t1);
1069 }
1070 if (compute_ov) {
1071 tcg_gen_movi_tl(cpu_ov, 0);
1072 }
1073 tcg_gen_br(l2);
1074 gen_set_label(l1);
1075 if (sign) {
1076 tcg_gen_sari_i32(t0, t0, 31);
1077 } else {
1078 tcg_gen_movi_i32(t0, 0);
1079 }
1080 if (compute_ov) {
1081 tcg_gen_movi_tl(cpu_ov, 1);
1082 tcg_gen_movi_tl(cpu_so, 1);
1083 }
1084 gen_set_label(l2);
1085 tcg_gen_extu_i32_tl(ret, t0);
1086 tcg_temp_free_i32(t0);
1087 tcg_temp_free_i32(t1);
1088 if (unlikely(Rc(ctx->opcode) != 0))
1089 gen_set_Rc0(ctx, ret);
1090 }
1091 /* Div functions */
1092 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1093 static void glue(gen_, name)(DisasContext *ctx) \
1094 { \
1095 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1096 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1097 sign, compute_ov); \
1098 }
1099 /* divwu divwu. divwuo divwuo. */
1100 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1101 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1102 /* divw divw. divwo divwo. */
1103 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1104 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1105
1106 /* div[wd]eu[o][.] */
1107 #define GEN_DIVE(name, hlpr, compute_ov) \
1108 static void gen_##name(DisasContext *ctx) \
1109 { \
1110 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1111 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1112 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1113 tcg_temp_free_i32(t0); \
1114 if (unlikely(Rc(ctx->opcode) != 0)) { \
1115 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1116 } \
1117 }
1118
1119 GEN_DIVE(divweu, divweu, 0);
1120 GEN_DIVE(divweuo, divweu, 1);
1121 GEN_DIVE(divwe, divwe, 0);
1122 GEN_DIVE(divweo, divwe, 1);
1123
1124 #if defined(TARGET_PPC64)
1125 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1126 TCGv arg2, int sign, int compute_ov)
1127 {
1128 TCGLabel *l1 = gen_new_label();
1129 TCGLabel *l2 = gen_new_label();
1130
1131 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1132 if (sign) {
1133 TCGLabel *l3 = gen_new_label();
1134 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1135 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1136 gen_set_label(l3);
1137 tcg_gen_div_i64(ret, arg1, arg2);
1138 } else {
1139 tcg_gen_divu_i64(ret, arg1, arg2);
1140 }
1141 if (compute_ov) {
1142 tcg_gen_movi_tl(cpu_ov, 0);
1143 }
1144 tcg_gen_br(l2);
1145 gen_set_label(l1);
1146 if (sign) {
1147 tcg_gen_sari_i64(ret, arg1, 63);
1148 } else {
1149 tcg_gen_movi_i64(ret, 0);
1150 }
1151 if (compute_ov) {
1152 tcg_gen_movi_tl(cpu_ov, 1);
1153 tcg_gen_movi_tl(cpu_so, 1);
1154 }
1155 gen_set_label(l2);
1156 if (unlikely(Rc(ctx->opcode) != 0))
1157 gen_set_Rc0(ctx, ret);
1158 }
1159 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1160 static void glue(gen_, name)(DisasContext *ctx) \
1161 { \
1162 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1163 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1164 sign, compute_ov); \
1165 }
1166 /* divwu divwu. divwuo divwuo. */
1167 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1168 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1169 /* divw divw. divwo divwo. */
1170 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1171 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1172
1173 GEN_DIVE(divdeu, divdeu, 0);
1174 GEN_DIVE(divdeuo, divdeu, 1);
1175 GEN_DIVE(divde, divde, 0);
1176 GEN_DIVE(divdeo, divde, 1);
1177 #endif
1178
1179 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1180 TCGv arg2, int sign)
1181 {
1182 TCGv_i32 t0 = tcg_temp_new_i32();
1183 TCGv_i32 t1 = tcg_temp_new_i32();
1184
1185 tcg_gen_trunc_tl_i32(t0, arg1);
1186 tcg_gen_trunc_tl_i32(t1, arg2);
1187 if (sign) {
1188 TCGv_i32 t2 = tcg_temp_new_i32();
1189 TCGv_i32 t3 = tcg_temp_new_i32();
1190 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1191 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1192 tcg_gen_and_i32(t2, t2, t3);
1193 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1194 tcg_gen_or_i32(t2, t2, t3);
1195 tcg_gen_movi_i32(t3, 0);
1196 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1197 tcg_gen_rem_i32(t3, t0, t1);
1198 tcg_gen_ext_i32_tl(ret, t3);
1199 tcg_temp_free_i32(t2);
1200 tcg_temp_free_i32(t3);
1201 } else {
1202 TCGv_i32 t2 = tcg_const_i32(1);
1203 TCGv_i32 t3 = tcg_const_i32(0);
1204 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1205 tcg_gen_remu_i32(t3, t0, t1);
1206 tcg_gen_extu_i32_tl(ret, t3);
1207 tcg_temp_free_i32(t2);
1208 tcg_temp_free_i32(t3);
1209 }
1210 tcg_temp_free_i32(t0);
1211 tcg_temp_free_i32(t1);
1212 }
1213
1214 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1215 static void glue(gen_, name)(DisasContext *ctx) \
1216 { \
1217 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1218 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1219 sign); \
1220 }
1221
1222 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1223 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1224
1225 #if defined(TARGET_PPC64)
1226 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1227 TCGv arg2, int sign)
1228 {
1229 TCGv_i64 t0 = tcg_temp_new_i64();
1230 TCGv_i64 t1 = tcg_temp_new_i64();
1231
1232 tcg_gen_mov_i64(t0, arg1);
1233 tcg_gen_mov_i64(t1, arg2);
1234 if (sign) {
1235 TCGv_i64 t2 = tcg_temp_new_i64();
1236 TCGv_i64 t3 = tcg_temp_new_i64();
1237 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1238 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1239 tcg_gen_and_i64(t2, t2, t3);
1240 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1241 tcg_gen_or_i64(t2, t2, t3);
1242 tcg_gen_movi_i64(t3, 0);
1243 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1244 tcg_gen_rem_i64(ret, t0, t1);
1245 tcg_temp_free_i64(t2);
1246 tcg_temp_free_i64(t3);
1247 } else {
1248 TCGv_i64 t2 = tcg_const_i64(1);
1249 TCGv_i64 t3 = tcg_const_i64(0);
1250 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1251 tcg_gen_remu_i64(ret, t0, t1);
1252 tcg_temp_free_i64(t2);
1253 tcg_temp_free_i64(t3);
1254 }
1255 tcg_temp_free_i64(t0);
1256 tcg_temp_free_i64(t1);
1257 }
1258
1259 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1260 static void glue(gen_, name)(DisasContext *ctx) \
1261 { \
1262 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1263 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1264 sign); \
1265 }
1266
1267 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1268 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1269 #endif
1270
1271 /* mulhw mulhw. */
1272 static void gen_mulhw(DisasContext *ctx)
1273 {
1274 TCGv_i32 t0 = tcg_temp_new_i32();
1275 TCGv_i32 t1 = tcg_temp_new_i32();
1276
1277 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1278 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1279 tcg_gen_muls2_i32(t0, t1, t0, t1);
1280 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1281 tcg_temp_free_i32(t0);
1282 tcg_temp_free_i32(t1);
1283 if (unlikely(Rc(ctx->opcode) != 0))
1284 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1285 }
1286
1287 /* mulhwu mulhwu. */
1288 static void gen_mulhwu(DisasContext *ctx)
1289 {
1290 TCGv_i32 t0 = tcg_temp_new_i32();
1291 TCGv_i32 t1 = tcg_temp_new_i32();
1292
1293 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1294 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1295 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1296 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1297 tcg_temp_free_i32(t0);
1298 tcg_temp_free_i32(t1);
1299 if (unlikely(Rc(ctx->opcode) != 0))
1300 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1301 }
1302
1303 /* mullw mullw. */
1304 static void gen_mullw(DisasContext *ctx)
1305 {
1306 #if defined(TARGET_PPC64)
1307 TCGv_i64 t0, t1;
1308 t0 = tcg_temp_new_i64();
1309 t1 = tcg_temp_new_i64();
1310 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1311 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1312 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1313 tcg_temp_free(t0);
1314 tcg_temp_free(t1);
1315 #else
1316 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1317 cpu_gpr[rB(ctx->opcode)]);
1318 #endif
1319 if (unlikely(Rc(ctx->opcode) != 0))
1320 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1321 }
1322
1323 /* mullwo mullwo. */
1324 static void gen_mullwo(DisasContext *ctx)
1325 {
1326 TCGv_i32 t0 = tcg_temp_new_i32();
1327 TCGv_i32 t1 = tcg_temp_new_i32();
1328
1329 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1330 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1331 tcg_gen_muls2_i32(t0, t1, t0, t1);
1332 #if defined(TARGET_PPC64)
1333 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1334 #else
1335 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1336 #endif
1337
1338 tcg_gen_sari_i32(t0, t0, 31);
1339 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1340 tcg_gen_extu_i32_tl(cpu_ov, t0);
1341 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1342
1343 tcg_temp_free_i32(t0);
1344 tcg_temp_free_i32(t1);
1345 if (unlikely(Rc(ctx->opcode) != 0))
1346 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1347 }
1348
1349 /* mulli */
1350 static void gen_mulli(DisasContext *ctx)
1351 {
1352 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1353 SIMM(ctx->opcode));
1354 }
1355
1356 #if defined(TARGET_PPC64)
1357 /* mulhd mulhd. */
1358 static void gen_mulhd(DisasContext *ctx)
1359 {
1360 TCGv lo = tcg_temp_new();
1361 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1362 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1363 tcg_temp_free(lo);
1364 if (unlikely(Rc(ctx->opcode) != 0)) {
1365 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1366 }
1367 }
1368
1369 /* mulhdu mulhdu. */
1370 static void gen_mulhdu(DisasContext *ctx)
1371 {
1372 TCGv lo = tcg_temp_new();
1373 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1374 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1375 tcg_temp_free(lo);
1376 if (unlikely(Rc(ctx->opcode) != 0)) {
1377 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1378 }
1379 }
1380
1381 /* mulld mulld. */
1382 static void gen_mulld(DisasContext *ctx)
1383 {
1384 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1385 cpu_gpr[rB(ctx->opcode)]);
1386 if (unlikely(Rc(ctx->opcode) != 0))
1387 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1388 }
1389
1390 /* mulldo mulldo. */
1391 static void gen_mulldo(DisasContext *ctx)
1392 {
1393 TCGv_i64 t0 = tcg_temp_new_i64();
1394 TCGv_i64 t1 = tcg_temp_new_i64();
1395
1396 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1397 cpu_gpr[rB(ctx->opcode)]);
1398 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1399
1400 tcg_gen_sari_i64(t0, t0, 63);
1401 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1402 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1403
1404 tcg_temp_free_i64(t0);
1405 tcg_temp_free_i64(t1);
1406
1407 if (unlikely(Rc(ctx->opcode) != 0)) {
1408 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1409 }
1410 }
1411 #endif
1412
1413 /* Common subf function */
1414 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1415 TCGv arg2, bool add_ca, bool compute_ca,
1416 bool compute_ov, bool compute_rc0)
1417 {
1418 TCGv t0 = ret;
1419
1420 if (compute_ca || compute_ov) {
1421 t0 = tcg_temp_new();
1422 }
1423
1424 if (compute_ca) {
1425 /* dest = ~arg1 + arg2 [+ ca]. */
1426 if (NARROW_MODE(ctx)) {
1427 /* Caution: a non-obvious corner case of the spec is that we
1428 must produce the *entire* 64-bit addition, but produce the
1429 carry into bit 32. */
1430 TCGv inv1 = tcg_temp_new();
1431 TCGv t1 = tcg_temp_new();
1432 tcg_gen_not_tl(inv1, arg1);
1433 if (add_ca) {
1434 tcg_gen_add_tl(t0, arg2, cpu_ca);
1435 } else {
1436 tcg_gen_addi_tl(t0, arg2, 1);
1437 }
1438 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1439 tcg_gen_add_tl(t0, t0, inv1);
1440 tcg_temp_free(inv1);
1441 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1442 tcg_temp_free(t1);
1443 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1444 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1445 } else if (add_ca) {
1446 TCGv zero, inv1 = tcg_temp_new();
1447 tcg_gen_not_tl(inv1, arg1);
1448 zero = tcg_const_tl(0);
1449 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1450 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1451 tcg_temp_free(zero);
1452 tcg_temp_free(inv1);
1453 } else {
1454 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1455 tcg_gen_sub_tl(t0, arg2, arg1);
1456 }
1457 } else if (add_ca) {
1458 /* Since we're ignoring carry-out, we can simplify the
1459 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1460 tcg_gen_sub_tl(t0, arg2, arg1);
1461 tcg_gen_add_tl(t0, t0, cpu_ca);
1462 tcg_gen_subi_tl(t0, t0, 1);
1463 } else {
1464 tcg_gen_sub_tl(t0, arg2, arg1);
1465 }
1466
1467 if (compute_ov) {
1468 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1469 }
1470 if (unlikely(compute_rc0)) {
1471 gen_set_Rc0(ctx, t0);
1472 }
1473
1474 if (!TCGV_EQUAL(t0, ret)) {
1475 tcg_gen_mov_tl(ret, t0);
1476 tcg_temp_free(t0);
1477 }
1478 }
1479 /* Sub functions with Two operands functions */
1480 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1481 static void glue(gen_, name)(DisasContext *ctx) \
1482 { \
1483 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1484 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1485 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1486 }
1487 /* Sub functions with one operand and one immediate */
1488 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1489 add_ca, compute_ca, compute_ov) \
1490 static void glue(gen_, name)(DisasContext *ctx) \
1491 { \
1492 TCGv t0 = tcg_const_tl(const_val); \
1493 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1494 cpu_gpr[rA(ctx->opcode)], t0, \
1495 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1496 tcg_temp_free(t0); \
1497 }
1498 /* subf subf. subfo subfo. */
1499 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1500 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1501 /* subfc subfc. subfco subfco. */
1502 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1503 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1504 /* subfe subfe. subfeo subfo. */
1505 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1506 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1507 /* subfme subfme. subfmeo subfmeo. */
1508 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1509 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1510 /* subfze subfze. subfzeo subfzeo.*/
1511 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1512 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1513
1514 /* subfic */
1515 static void gen_subfic(DisasContext *ctx)
1516 {
1517 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1518 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1519 c, 0, 1, 0, 0);
1520 tcg_temp_free(c);
1521 }
1522
1523 /* neg neg. nego nego. */
1524 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1525 {
1526 TCGv zero = tcg_const_tl(0);
1527 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1528 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1529 tcg_temp_free(zero);
1530 }
1531
1532 static void gen_neg(DisasContext *ctx)
1533 {
1534 gen_op_arith_neg(ctx, 0);
1535 }
1536
1537 static void gen_nego(DisasContext *ctx)
1538 {
1539 gen_op_arith_neg(ctx, 1);
1540 }
1541
1542 /*** Integer logical ***/
1543 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1544 static void glue(gen_, name)(DisasContext *ctx) \
1545 { \
1546 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1547 cpu_gpr[rB(ctx->opcode)]); \
1548 if (unlikely(Rc(ctx->opcode) != 0)) \
1549 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1550 }
1551
1552 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1553 static void glue(gen_, name)(DisasContext *ctx) \
1554 { \
1555 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1556 if (unlikely(Rc(ctx->opcode) != 0)) \
1557 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1558 }
1559
1560 /* and & and. */
1561 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1562 /* andc & andc. */
1563 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1564
1565 /* andi. */
1566 static void gen_andi_(DisasContext *ctx)
1567 {
1568 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1569 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1570 }
1571
1572 /* andis. */
1573 static void gen_andis_(DisasContext *ctx)
1574 {
1575 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1576 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1577 }
1578
1579 /* cntlzw */
1580 static void gen_cntlzw(DisasContext *ctx)
1581 {
1582 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1583 if (unlikely(Rc(ctx->opcode) != 0))
1584 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1585 }
1586
1587 /* cnttzw */
1588 static void gen_cnttzw(DisasContext *ctx)
1589 {
1590 gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1591 if (unlikely(Rc(ctx->opcode) != 0)) {
1592 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1593 }
1594 }
1595
1596 /* eqv & eqv. */
1597 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1598 /* extsb & extsb. */
1599 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1600 /* extsh & extsh. */
1601 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1602 /* nand & nand. */
1603 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1604 /* nor & nor. */
1605 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1606
1607 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1608 static void gen_pause(DisasContext *ctx)
1609 {
1610 TCGv_i32 t0 = tcg_const_i32(0);
1611 tcg_gen_st_i32(t0, cpu_env,
1612 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1613 tcg_temp_free_i32(t0);
1614
1615 /* Stop translation, this gives other CPUs a chance to run */
1616 gen_exception_err(ctx, EXCP_HLT, 1);
1617 }
1618 #endif /* defined(TARGET_PPC64) */
1619
1620 /* or & or. */
1621 static void gen_or(DisasContext *ctx)
1622 {
1623 int rs, ra, rb;
1624
1625 rs = rS(ctx->opcode);
1626 ra = rA(ctx->opcode);
1627 rb = rB(ctx->opcode);
1628 /* Optimisation for mr. ri case */
1629 if (rs != ra || rs != rb) {
1630 if (rs != rb)
1631 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1632 else
1633 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1634 if (unlikely(Rc(ctx->opcode) != 0))
1635 gen_set_Rc0(ctx, cpu_gpr[ra]);
1636 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1637 gen_set_Rc0(ctx, cpu_gpr[rs]);
1638 #if defined(TARGET_PPC64)
1639 } else if (rs != 0) { /* 0 is nop */
1640 int prio = 0;
1641
1642 switch (rs) {
1643 case 1:
1644 /* Set process priority to low */
1645 prio = 2;
1646 break;
1647 case 6:
1648 /* Set process priority to medium-low */
1649 prio = 3;
1650 break;
1651 case 2:
1652 /* Set process priority to normal */
1653 prio = 4;
1654 break;
1655 #if !defined(CONFIG_USER_ONLY)
1656 case 31:
1657 if (!ctx->pr) {
1658 /* Set process priority to very low */
1659 prio = 1;
1660 }
1661 break;
1662 case 5:
1663 if (!ctx->pr) {
1664 /* Set process priority to medium-hight */
1665 prio = 5;
1666 }
1667 break;
1668 case 3:
1669 if (!ctx->pr) {
1670 /* Set process priority to high */
1671 prio = 6;
1672 }
1673 break;
1674 case 7:
1675 if (ctx->hv && !ctx->pr) {
1676 /* Set process priority to very high */
1677 prio = 7;
1678 }
1679 break;
1680 #endif
1681 default:
1682 break;
1683 }
1684 if (prio) {
1685 TCGv t0 = tcg_temp_new();
1686 gen_load_spr(t0, SPR_PPR);
1687 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1688 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1689 gen_store_spr(SPR_PPR, t0);
1690 tcg_temp_free(t0);
1691 }
1692 #if !defined(CONFIG_USER_ONLY)
1693 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1694 * CPU and the kernel hangs. This applies to all encodings other
1695 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1696 * and all currently undefined.
1697 */
1698 gen_pause(ctx);
1699 #endif
1700 #endif
1701 }
1702 }
1703 /* orc & orc. */
1704 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1705
1706 /* xor & xor. */
1707 static void gen_xor(DisasContext *ctx)
1708 {
1709 /* Optimisation for "set to zero" case */
1710 if (rS(ctx->opcode) != rB(ctx->opcode))
1711 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1712 else
1713 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1714 if (unlikely(Rc(ctx->opcode) != 0))
1715 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1716 }
1717
1718 /* ori */
1719 static void gen_ori(DisasContext *ctx)
1720 {
1721 target_ulong uimm = UIMM(ctx->opcode);
1722
1723 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1724 return;
1725 }
1726 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1727 }
1728
1729 /* oris */
1730 static void gen_oris(DisasContext *ctx)
1731 {
1732 target_ulong uimm = UIMM(ctx->opcode);
1733
1734 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1735 /* NOP */
1736 return;
1737 }
1738 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1739 }
1740
1741 /* xori */
1742 static void gen_xori(DisasContext *ctx)
1743 {
1744 target_ulong uimm = UIMM(ctx->opcode);
1745
1746 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1747 /* NOP */
1748 return;
1749 }
1750 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1751 }
1752
1753 /* xoris */
1754 static void gen_xoris(DisasContext *ctx)
1755 {
1756 target_ulong uimm = UIMM(ctx->opcode);
1757
1758 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1759 /* NOP */
1760 return;
1761 }
1762 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1763 }
1764
1765 /* popcntb : PowerPC 2.03 specification */
1766 static void gen_popcntb(DisasContext *ctx)
1767 {
1768 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1769 }
1770
1771 static void gen_popcntw(DisasContext *ctx)
1772 {
1773 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1774 }
1775
1776 #if defined(TARGET_PPC64)
1777 /* popcntd: PowerPC 2.06 specification */
1778 static void gen_popcntd(DisasContext *ctx)
1779 {
1780 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1781 }
1782 #endif
1783
1784 /* prtyw: PowerPC 2.05 specification */
1785 static void gen_prtyw(DisasContext *ctx)
1786 {
1787 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1788 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1789 TCGv t0 = tcg_temp_new();
1790 tcg_gen_shri_tl(t0, rs, 16);
1791 tcg_gen_xor_tl(ra, rs, t0);
1792 tcg_gen_shri_tl(t0, ra, 8);
1793 tcg_gen_xor_tl(ra, ra, t0);
1794 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1795 tcg_temp_free(t0);
1796 }
1797
1798 #if defined(TARGET_PPC64)
1799 /* prtyd: PowerPC 2.05 specification */
1800 static void gen_prtyd(DisasContext *ctx)
1801 {
1802 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1803 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1804 TCGv t0 = tcg_temp_new();
1805 tcg_gen_shri_tl(t0, rs, 32);
1806 tcg_gen_xor_tl(ra, rs, t0);
1807 tcg_gen_shri_tl(t0, ra, 16);
1808 tcg_gen_xor_tl(ra, ra, t0);
1809 tcg_gen_shri_tl(t0, ra, 8);
1810 tcg_gen_xor_tl(ra, ra, t0);
1811 tcg_gen_andi_tl(ra, ra, 1);
1812 tcg_temp_free(t0);
1813 }
1814 #endif
1815
1816 #if defined(TARGET_PPC64)
1817 /* bpermd */
1818 static void gen_bpermd(DisasContext *ctx)
1819 {
1820 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1821 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1822 }
1823 #endif
1824
1825 #if defined(TARGET_PPC64)
1826 /* extsw & extsw. */
1827 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1828
1829 /* cntlzd */
1830 static void gen_cntlzd(DisasContext *ctx)
1831 {
1832 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1833 if (unlikely(Rc(ctx->opcode) != 0))
1834 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1835 }
1836
1837 /* cnttzd */
1838 static void gen_cnttzd(DisasContext *ctx)
1839 {
1840 gen_helper_cnttzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1841 if (unlikely(Rc(ctx->opcode) != 0)) {
1842 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1843 }
1844 }
1845 #endif
1846
1847 /*** Integer rotate ***/
1848
1849 /* rlwimi & rlwimi. */
1850 static void gen_rlwimi(DisasContext *ctx)
1851 {
1852 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1853 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1854 uint32_t sh = SH(ctx->opcode);
1855 uint32_t mb = MB(ctx->opcode);
1856 uint32_t me = ME(ctx->opcode);
1857
1858 if (sh == (31-me) && mb <= me) {
1859 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1860 } else {
1861 target_ulong mask;
1862 TCGv t1;
1863
1864 #if defined(TARGET_PPC64)
1865 mb += 32;
1866 me += 32;
1867 #endif
1868 mask = MASK(mb, me);
1869
1870 t1 = tcg_temp_new();
1871 if (mask <= 0xffffffffu) {
1872 TCGv_i32 t0 = tcg_temp_new_i32();
1873 tcg_gen_trunc_tl_i32(t0, t_rs);
1874 tcg_gen_rotli_i32(t0, t0, sh);
1875 tcg_gen_extu_i32_tl(t1, t0);
1876 tcg_temp_free_i32(t0);
1877 } else {
1878 #if defined(TARGET_PPC64)
1879 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1880 tcg_gen_rotli_i64(t1, t1, sh);
1881 #else
1882 g_assert_not_reached();
1883 #endif
1884 }
1885
1886 tcg_gen_andi_tl(t1, t1, mask);
1887 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1888 tcg_gen_or_tl(t_ra, t_ra, t1);
1889 tcg_temp_free(t1);
1890 }
1891 if (unlikely(Rc(ctx->opcode) != 0)) {
1892 gen_set_Rc0(ctx, t_ra);
1893 }
1894 }
1895
1896 /* rlwinm & rlwinm. */
1897 static void gen_rlwinm(DisasContext *ctx)
1898 {
1899 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1900 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1901 uint32_t sh = SH(ctx->opcode);
1902 uint32_t mb = MB(ctx->opcode);
1903 uint32_t me = ME(ctx->opcode);
1904
1905 if (mb == 0 && me == (31 - sh)) {
1906 tcg_gen_shli_tl(t_ra, t_rs, sh);
1907 tcg_gen_ext32u_tl(t_ra, t_ra);
1908 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1909 tcg_gen_ext32u_tl(t_ra, t_rs);
1910 tcg_gen_shri_tl(t_ra, t_ra, mb);
1911 } else {
1912 target_ulong mask;
1913 #if defined(TARGET_PPC64)
1914 mb += 32;
1915 me += 32;
1916 #endif
1917 mask = MASK(mb, me);
1918
1919 if (mask <= 0xffffffffu) {
1920 TCGv_i32 t0 = tcg_temp_new_i32();
1921 tcg_gen_trunc_tl_i32(t0, t_rs);
1922 tcg_gen_rotli_i32(t0, t0, sh);
1923 tcg_gen_andi_i32(t0, t0, mask);
1924 tcg_gen_extu_i32_tl(t_ra, t0);
1925 tcg_temp_free_i32(t0);
1926 } else {
1927 #if defined(TARGET_PPC64)
1928 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1929 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1930 tcg_gen_andi_i64(t_ra, t_ra, mask);
1931 #else
1932 g_assert_not_reached();
1933 #endif
1934 }
1935 }
1936 if (unlikely(Rc(ctx->opcode) != 0)) {
1937 gen_set_Rc0(ctx, t_ra);
1938 }
1939 }
1940
1941 /* rlwnm & rlwnm. */
1942 static void gen_rlwnm(DisasContext *ctx)
1943 {
1944 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1945 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1946 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1947 uint32_t mb = MB(ctx->opcode);
1948 uint32_t me = ME(ctx->opcode);
1949 target_ulong mask;
1950
1951 #if defined(TARGET_PPC64)
1952 mb += 32;
1953 me += 32;
1954 #endif
1955 mask = MASK(mb, me);
1956
1957 if (mask <= 0xffffffffu) {
1958 TCGv_i32 t0 = tcg_temp_new_i32();
1959 TCGv_i32 t1 = tcg_temp_new_i32();
1960 tcg_gen_trunc_tl_i32(t0, t_rb);
1961 tcg_gen_trunc_tl_i32(t1, t_rs);
1962 tcg_gen_andi_i32(t0, t0, 0x1f);
1963 tcg_gen_rotl_i32(t1, t1, t0);
1964 tcg_gen_extu_i32_tl(t_ra, t1);
1965 tcg_temp_free_i32(t0);
1966 tcg_temp_free_i32(t1);
1967 } else {
1968 #if defined(TARGET_PPC64)
1969 TCGv_i64 t0 = tcg_temp_new_i64();
1970 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1971 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1972 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1973 tcg_temp_free_i64(t0);
1974 #else
1975 g_assert_not_reached();
1976 #endif
1977 }
1978
1979 tcg_gen_andi_tl(t_ra, t_ra, mask);
1980
1981 if (unlikely(Rc(ctx->opcode) != 0)) {
1982 gen_set_Rc0(ctx, t_ra);
1983 }
1984 }
1985
1986 #if defined(TARGET_PPC64)
1987 #define GEN_PPC64_R2(name, opc1, opc2) \
1988 static void glue(gen_, name##0)(DisasContext *ctx) \
1989 { \
1990 gen_##name(ctx, 0); \
1991 } \
1992 \
1993 static void glue(gen_, name##1)(DisasContext *ctx) \
1994 { \
1995 gen_##name(ctx, 1); \
1996 }
1997 #define GEN_PPC64_R4(name, opc1, opc2) \
1998 static void glue(gen_, name##0)(DisasContext *ctx) \
1999 { \
2000 gen_##name(ctx, 0, 0); \
2001 } \
2002 \
2003 static void glue(gen_, name##1)(DisasContext *ctx) \
2004 { \
2005 gen_##name(ctx, 0, 1); \
2006 } \
2007 \
2008 static void glue(gen_, name##2)(DisasContext *ctx) \
2009 { \
2010 gen_##name(ctx, 1, 0); \
2011 } \
2012 \
2013 static void glue(gen_, name##3)(DisasContext *ctx) \
2014 { \
2015 gen_##name(ctx, 1, 1); \
2016 }
2017
2018 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2019 {
2020 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2021 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2022
2023 if (sh != 0 && mb == 0 && me == (63 - sh)) {
2024 tcg_gen_shli_tl(t_ra, t_rs, sh);
2025 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
2026 tcg_gen_shri_tl(t_ra, t_rs, mb);
2027 } else {
2028 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2029 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2030 }
2031 if (unlikely(Rc(ctx->opcode) != 0)) {
2032 gen_set_Rc0(ctx, t_ra);
2033 }
2034 }
2035
2036 /* rldicl - rldicl. */
2037 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2038 {
2039 uint32_t sh, mb;
2040
2041 sh = SH(ctx->opcode) | (shn << 5);
2042 mb = MB(ctx->opcode) | (mbn << 5);
2043 gen_rldinm(ctx, mb, 63, sh);
2044 }
2045 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2046
2047 /* rldicr - rldicr. */
2048 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2049 {
2050 uint32_t sh, me;
2051
2052 sh = SH(ctx->opcode) | (shn << 5);
2053 me = MB(ctx->opcode) | (men << 5);
2054 gen_rldinm(ctx, 0, me, sh);
2055 }
2056 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2057
2058 /* rldic - rldic. */
2059 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2060 {
2061 uint32_t sh, mb;
2062
2063 sh = SH(ctx->opcode) | (shn << 5);
2064 mb = MB(ctx->opcode) | (mbn << 5);
2065 gen_rldinm(ctx, mb, 63 - sh, sh);
2066 }
2067 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2068
2069 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2070 {
2071 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2072 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2073 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2074 TCGv t0;
2075
2076 t0 = tcg_temp_new();
2077 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2078 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2079 tcg_temp_free(t0);
2080
2081 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2082 if (unlikely(Rc(ctx->opcode) != 0)) {
2083 gen_set_Rc0(ctx, t_ra);
2084 }
2085 }
2086
2087 /* rldcl - rldcl. */
2088 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2089 {
2090 uint32_t mb;
2091
2092 mb = MB(ctx->opcode) | (mbn << 5);
2093 gen_rldnm(ctx, mb, 63);
2094 }
2095 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2096
2097 /* rldcr - rldcr. */
2098 static inline void gen_rldcr(DisasContext *ctx, int men)
2099 {
2100 uint32_t me;
2101
2102 me = MB(ctx->opcode) | (men << 5);
2103 gen_rldnm(ctx, 0, me);
2104 }
2105 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2106
2107 /* rldimi - rldimi. */
2108 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2109 {
2110 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2111 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2112 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2113 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2114 uint32_t me = 63 - sh;
2115
2116 if (mb <= me) {
2117 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2118 } else {
2119 target_ulong mask = MASK(mb, me);
2120 TCGv t1 = tcg_temp_new();
2121
2122 tcg_gen_rotli_tl(t1, t_rs, sh);
2123 tcg_gen_andi_tl(t1, t1, mask);
2124 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2125 tcg_gen_or_tl(t_ra, t_ra, t1);
2126 tcg_temp_free(t1);
2127 }
2128 if (unlikely(Rc(ctx->opcode) != 0)) {
2129 gen_set_Rc0(ctx, t_ra);
2130 }
2131 }
2132 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2133 #endif
2134
2135 /*** Integer shift ***/
2136
2137 /* slw & slw. */
2138 static void gen_slw(DisasContext *ctx)
2139 {
2140 TCGv t0, t1;
2141
2142 t0 = tcg_temp_new();
2143 /* AND rS with a mask that is 0 when rB >= 0x20 */
2144 #if defined(TARGET_PPC64)
2145 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2146 tcg_gen_sari_tl(t0, t0, 0x3f);
2147 #else
2148 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2149 tcg_gen_sari_tl(t0, t0, 0x1f);
2150 #endif
2151 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2152 t1 = tcg_temp_new();
2153 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2154 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2155 tcg_temp_free(t1);
2156 tcg_temp_free(t0);
2157 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2158 if (unlikely(Rc(ctx->opcode) != 0))
2159 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2160 }
2161
2162 /* sraw & sraw. */
2163 static void gen_sraw(DisasContext *ctx)
2164 {
2165 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2166 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2167 if (unlikely(Rc(ctx->opcode) != 0))
2168 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2169 }
2170
2171 /* srawi & srawi. */
2172 static void gen_srawi(DisasContext *ctx)
2173 {
2174 int sh = SH(ctx->opcode);
2175 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2176 TCGv src = cpu_gpr[rS(ctx->opcode)];
2177 if (sh == 0) {
2178 tcg_gen_ext32s_tl(dst, src);
2179 tcg_gen_movi_tl(cpu_ca, 0);
2180 } else {
2181 TCGv t0;
2182 tcg_gen_ext32s_tl(dst, src);
2183 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2184 t0 = tcg_temp_new();
2185 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2186 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2187 tcg_temp_free(t0);
2188 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2189 tcg_gen_sari_tl(dst, dst, sh);
2190 }
2191 if (unlikely(Rc(ctx->opcode) != 0)) {
2192 gen_set_Rc0(ctx, dst);
2193 }
2194 }
2195
2196 /* srw & srw. */
2197 static void gen_srw(DisasContext *ctx)
2198 {
2199 TCGv t0, t1;
2200
2201 t0 = tcg_temp_new();
2202 /* AND rS with a mask that is 0 when rB >= 0x20 */
2203 #if defined(TARGET_PPC64)
2204 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2205 tcg_gen_sari_tl(t0, t0, 0x3f);
2206 #else
2207 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2208 tcg_gen_sari_tl(t0, t0, 0x1f);
2209 #endif
2210 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2211 tcg_gen_ext32u_tl(t0, t0);
2212 t1 = tcg_temp_new();
2213 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2214 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2215 tcg_temp_free(t1);
2216 tcg_temp_free(t0);
2217 if (unlikely(Rc(ctx->opcode) != 0))
2218 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2219 }
2220
2221 #if defined(TARGET_PPC64)
2222 /* sld & sld. */
2223 static void gen_sld(DisasContext *ctx)
2224 {
2225 TCGv t0, t1;
2226
2227 t0 = tcg_temp_new();
2228 /* AND rS with a mask that is 0 when rB >= 0x40 */
2229 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2230 tcg_gen_sari_tl(t0, t0, 0x3f);
2231 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2232 t1 = tcg_temp_new();
2233 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2234 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2235 tcg_temp_free(t1);
2236 tcg_temp_free(t0);
2237 if (unlikely(Rc(ctx->opcode) != 0))
2238 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2239 }
2240
2241 /* srad & srad. */
2242 static void gen_srad(DisasContext *ctx)
2243 {
2244 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2245 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2246 if (unlikely(Rc(ctx->opcode) != 0))
2247 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2248 }
2249 /* sradi & sradi. */
2250 static inline void gen_sradi(DisasContext *ctx, int n)
2251 {
2252 int sh = SH(ctx->opcode) + (n << 5);
2253 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2254 TCGv src = cpu_gpr[rS(ctx->opcode)];
2255 if (sh == 0) {
2256 tcg_gen_mov_tl(dst, src);
2257 tcg_gen_movi_tl(cpu_ca, 0);
2258 } else {
2259 TCGv t0;
2260 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2261 t0 = tcg_temp_new();
2262 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2263 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2264 tcg_temp_free(t0);
2265 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2266 tcg_gen_sari_tl(dst, src, sh);
2267 }
2268 if (unlikely(Rc(ctx->opcode) != 0)) {
2269 gen_set_Rc0(ctx, dst);
2270 }
2271 }
2272
2273 static void gen_sradi0(DisasContext *ctx)
2274 {
2275 gen_sradi(ctx, 0);
2276 }
2277
2278 static void gen_sradi1(DisasContext *ctx)
2279 {
2280 gen_sradi(ctx, 1);
2281 }
2282
2283 /* srd & srd. */
2284 static void gen_srd(DisasContext *ctx)
2285 {
2286 TCGv t0, t1;
2287
2288 t0 = tcg_temp_new();
2289 /* AND rS with a mask that is 0 when rB >= 0x40 */
2290 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2291 tcg_gen_sari_tl(t0, t0, 0x3f);
2292 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2293 t1 = tcg_temp_new();
2294 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2295 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2296 tcg_temp_free(t1);
2297 tcg_temp_free(t0);
2298 if (unlikely(Rc(ctx->opcode) != 0))
2299 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2300 }
2301 #endif
2302
2303 #if defined(TARGET_PPC64)
2304 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2305 {
2306 TCGv_i32 tmp = tcg_temp_new_i32();
2307 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2308 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2309 tcg_temp_free_i32(tmp);
2310 }
2311 #else
2312 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2313 {
2314 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2315 }
2316 #endif
2317
2318 /*** Floating-Point arithmetic ***/
2319 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2320 static void gen_f##name(DisasContext *ctx) \
2321 { \
2322 if (unlikely(!ctx->fpu_enabled)) { \
2323 gen_exception(ctx, POWERPC_EXCP_FPU); \
2324 return; \
2325 } \
2326 /* NIP cannot be restored if the memory exception comes from an helper */ \
2327 gen_update_nip(ctx, ctx->nip - 4); \
2328 gen_reset_fpstatus(); \
2329 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2330 cpu_fpr[rA(ctx->opcode)], \
2331 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2332 if (isfloat) { \
2333 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2334 cpu_fpr[rD(ctx->opcode)]); \
2335 } \
2336 if (set_fprf) { \
2337 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2338 } \
2339 if (unlikely(Rc(ctx->opcode) != 0)) { \
2340 gen_set_cr1_from_fpscr(ctx); \
2341 } \
2342 }
2343
2344 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2345 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2346 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2347
2348 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2349 static void gen_f##name(DisasContext *ctx) \
2350 { \
2351 if (unlikely(!ctx->fpu_enabled)) { \
2352 gen_exception(ctx, POWERPC_EXCP_FPU); \
2353 return; \
2354 } \
2355 /* NIP cannot be restored if the memory exception comes from an helper */ \
2356 gen_update_nip(ctx, ctx->nip - 4); \
2357 gen_reset_fpstatus(); \
2358 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2359 cpu_fpr[rA(ctx->opcode)], \
2360 cpu_fpr[rB(ctx->opcode)]); \
2361 if (isfloat) { \
2362 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2363 cpu_fpr[rD(ctx->opcode)]); \
2364 } \
2365 if (set_fprf) { \
2366 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2367 } \
2368 if (unlikely(Rc(ctx->opcode) != 0)) { \
2369 gen_set_cr1_from_fpscr(ctx); \
2370 } \
2371 }
2372 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2373 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2374 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2375
2376 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2377 static void gen_f##name(DisasContext *ctx) \
2378 { \
2379 if (unlikely(!ctx->fpu_enabled)) { \
2380 gen_exception(ctx, POWERPC_EXCP_FPU); \
2381 return; \
2382 } \
2383 /* NIP cannot be restored if the memory exception comes from an helper */ \
2384 gen_update_nip(ctx, ctx->nip - 4); \
2385 gen_reset_fpstatus(); \
2386 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2387 cpu_fpr[rA(ctx->opcode)], \
2388 cpu_fpr[rC(ctx->opcode)]); \
2389 if (isfloat) { \
2390 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2391 cpu_fpr[rD(ctx->opcode)]); \
2392 } \
2393 if (set_fprf) { \
2394 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2395 } \
2396 if (unlikely(Rc(ctx->opcode) != 0)) { \
2397 gen_set_cr1_from_fpscr(ctx); \
2398 } \
2399 }
2400 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2401 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2402 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2403
2404 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2405 static void gen_f##name(DisasContext *ctx) \
2406 { \
2407 if (unlikely(!ctx->fpu_enabled)) { \
2408 gen_exception(ctx, POWERPC_EXCP_FPU); \
2409 return; \
2410 } \
2411 /* NIP cannot be restored if the memory exception comes from an helper */ \
2412 gen_update_nip(ctx, ctx->nip - 4); \
2413 gen_reset_fpstatus(); \
2414 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2415 cpu_fpr[rB(ctx->opcode)]); \
2416 if (set_fprf) { \
2417 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2418 } \
2419 if (unlikely(Rc(ctx->opcode) != 0)) { \
2420 gen_set_cr1_from_fpscr(ctx); \
2421 } \
2422 }
2423
2424 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2425 static void gen_f##name(DisasContext *ctx) \
2426 { \
2427 if (unlikely(!ctx->fpu_enabled)) { \
2428 gen_exception(ctx, POWERPC_EXCP_FPU); \
2429 return; \
2430 } \
2431 /* NIP cannot be restored if the memory exception comes from an helper */ \
2432 gen_update_nip(ctx, ctx->nip - 4); \
2433 gen_reset_fpstatus(); \
2434 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2435 cpu_fpr[rB(ctx->opcode)]); \
2436 if (set_fprf) { \
2437 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2438 } \
2439 if (unlikely(Rc(ctx->opcode) != 0)) { \
2440 gen_set_cr1_from_fpscr(ctx); \
2441 } \
2442 }
2443
2444 /* fadd - fadds */
2445 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2446 /* fdiv - fdivs */
2447 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2448 /* fmul - fmuls */
2449 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2450
2451 /* fre */
2452 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2453
2454 /* fres */
2455 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2456
2457 /* frsqrte */
2458 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2459
2460 /* frsqrtes */
2461 static void gen_frsqrtes(DisasContext *ctx)
2462 {
2463 if (unlikely(!ctx->fpu_enabled)) {
2464 gen_exception(ctx, POWERPC_EXCP_FPU);
2465 return;
2466 }
2467 /* NIP cannot be restored if the memory exception comes from an helper */
2468 gen_update_nip(ctx, ctx->nip - 4);
2469 gen_reset_fpstatus();
2470 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2471 cpu_fpr[rB(ctx->opcode)]);
2472 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2473 cpu_fpr[rD(ctx->opcode)]);
2474 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2475 if (unlikely(Rc(ctx->opcode) != 0)) {
2476 gen_set_cr1_from_fpscr(ctx);
2477 }
2478 }
2479
2480 /* fsel */
2481 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2482 /* fsub - fsubs */
2483 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2484 /* Optional: */
2485
2486 /* fsqrt */
2487 static void gen_fsqrt(DisasContext *ctx)
2488 {
2489 if (unlikely(!ctx->fpu_enabled)) {
2490 gen_exception(ctx, POWERPC_EXCP_FPU);
2491 return;
2492 }
2493 /* NIP cannot be restored if the memory exception comes from an helper */
2494 gen_update_nip(ctx, ctx->nip - 4);
2495 gen_reset_fpstatus();
2496 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2497 cpu_fpr[rB(ctx->opcode)]);
2498 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2499 if (unlikely(Rc(ctx->opcode) != 0)) {
2500 gen_set_cr1_from_fpscr(ctx);
2501 }
2502 }
2503
2504 static void gen_fsqrts(DisasContext *ctx)
2505 {
2506 if (unlikely(!ctx->fpu_enabled)) {
2507 gen_exception(ctx, POWERPC_EXCP_FPU);
2508 return;
2509 }
2510 /* NIP cannot be restored if the memory exception comes from an helper */
2511 gen_update_nip(ctx, ctx->nip - 4);
2512 gen_reset_fpstatus();
2513 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2514 cpu_fpr[rB(ctx->opcode)]);
2515 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2516 cpu_fpr[rD(ctx->opcode)]);
2517 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2518 if (unlikely(Rc(ctx->opcode) != 0)) {
2519 gen_set_cr1_from_fpscr(ctx);
2520 }
2521 }
2522
2523 /*** Floating-Point multiply-and-add ***/
2524 /* fmadd - fmadds */
2525 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2526 /* fmsub - fmsubs */
2527 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2528 /* fnmadd - fnmadds */
2529 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2530 /* fnmsub - fnmsubs */
2531 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2532
2533 /*** Floating-Point round & convert ***/
2534 /* fctiw */
2535 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2536 /* fctiwu */
2537 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2538 /* fctiwz */
2539 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2540 /* fctiwuz */
2541 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2542 /* frsp */
2543 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2544 /* fcfid */
2545 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2546 /* fcfids */
2547 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2548 /* fcfidu */
2549 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2550 /* fcfidus */
2551 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2552 /* fctid */
2553 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2554 /* fctidu */
2555 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2556 /* fctidz */
2557 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2558 /* fctidu */
2559 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2560
2561 /* frin */
2562 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2563 /* friz */
2564 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2565 /* frip */
2566 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2567 /* frim */
2568 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2569
2570 static void gen_ftdiv(DisasContext *ctx)
2571 {
2572 if (unlikely(!ctx->fpu_enabled)) {
2573 gen_exception(ctx, POWERPC_EXCP_FPU);
2574 return;
2575 }
2576 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2577 cpu_fpr[rB(ctx->opcode)]);
2578 }
2579
2580 static void gen_ftsqrt(DisasContext *ctx)
2581 {
2582 if (unlikely(!ctx->fpu_enabled)) {
2583 gen_exception(ctx, POWERPC_EXCP_FPU);
2584 return;
2585 }
2586 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2587 }
2588
2589
2590
2591 /*** Floating-Point compare ***/
2592
2593 /* fcmpo */
2594 static void gen_fcmpo(DisasContext *ctx)
2595 {
2596 TCGv_i32 crf;
2597 if (unlikely(!ctx->fpu_enabled)) {
2598 gen_exception(ctx, POWERPC_EXCP_FPU);
2599 return;
2600 }
2601 /* NIP cannot be restored if the memory exception comes from an helper */
2602 gen_update_nip(ctx, ctx->nip - 4);
2603 gen_reset_fpstatus();
2604 crf = tcg_const_i32(crfD(ctx->opcode));
2605 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2606 cpu_fpr[rB(ctx->opcode)], crf);
2607 tcg_temp_free_i32(crf);
2608 gen_helper_float_check_status(cpu_env);
2609 }
2610
2611 /* fcmpu */
2612 static void gen_fcmpu(DisasContext *ctx)
2613 {
2614 TCGv_i32 crf;
2615 if (unlikely(!ctx->fpu_enabled)) {
2616 gen_exception(ctx, POWERPC_EXCP_FPU);
2617 return;
2618 }
2619 /* NIP cannot be restored if the memory exception comes from an helper */
2620 gen_update_nip(ctx, ctx->nip - 4);
2621 gen_reset_fpstatus();
2622 crf = tcg_const_i32(crfD(ctx->opcode));
2623 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2624 cpu_fpr[rB(ctx->opcode)], crf);
2625 tcg_temp_free_i32(crf);
2626 gen_helper_float_check_status(cpu_env);
2627 }
2628
2629 /*** Floating-point move ***/
2630 /* fabs */
2631 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2632 static void gen_fabs(DisasContext *ctx)
2633 {
2634 if (unlikely(!ctx->fpu_enabled)) {
2635 gen_exception(ctx, POWERPC_EXCP_FPU);
2636 return;
2637 }
2638 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2639 ~(1ULL << 63));
2640 if (unlikely(Rc(ctx->opcode))) {
2641 gen_set_cr1_from_fpscr(ctx);
2642 }
2643 }
2644
2645 /* fmr - fmr. */
2646 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2647 static void gen_fmr(DisasContext *ctx)
2648 {
2649 if (unlikely(!ctx->fpu_enabled)) {
2650 gen_exception(ctx, POWERPC_EXCP_FPU);
2651 return;
2652 }
2653 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2654 if (unlikely(Rc(ctx->opcode))) {
2655 gen_set_cr1_from_fpscr(ctx);
2656 }
2657 }
2658
2659 /* fnabs */
2660 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2661 static void gen_fnabs(DisasContext *ctx)
2662 {
2663 if (unlikely(!ctx->fpu_enabled)) {
2664 gen_exception(ctx, POWERPC_EXCP_FPU);
2665 return;
2666 }
2667 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2668 1ULL << 63);
2669 if (unlikely(Rc(ctx->opcode))) {
2670 gen_set_cr1_from_fpscr(ctx);
2671 }
2672 }
2673
2674 /* fneg */
2675 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2676 static void gen_fneg(DisasContext *ctx)
2677 {
2678 if (unlikely(!ctx->fpu_enabled)) {
2679 gen_exception(ctx, POWERPC_EXCP_FPU);
2680 return;
2681 }
2682 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2683 1ULL << 63);
2684 if (unlikely(Rc(ctx->opcode))) {
2685 gen_set_cr1_from_fpscr(ctx);
2686 }
2687 }
2688
2689 /* fcpsgn: PowerPC 2.05 specification */
2690 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2691 static void gen_fcpsgn(DisasContext *ctx)
2692 {
2693 if (unlikely(!ctx->fpu_enabled)) {
2694 gen_exception(ctx, POWERPC_EXCP_FPU);
2695 return;
2696 }
2697 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2698 cpu_fpr[rB(ctx->opcode)], 0, 63);
2699 if (unlikely(Rc(ctx->opcode))) {
2700 gen_set_cr1_from_fpscr(ctx);
2701 }
2702 }
2703
2704 static void gen_fmrgew(DisasContext *ctx)
2705 {
2706 TCGv_i64 b0;
2707 if (unlikely(!ctx->fpu_enabled)) {
2708 gen_exception(ctx, POWERPC_EXCP_FPU);
2709 return;
2710 }
2711 b0 = tcg_temp_new_i64();
2712 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2713 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2714 b0, 0, 32);
2715 tcg_temp_free_i64(b0);
2716 }
2717
2718 static void gen_fmrgow(DisasContext *ctx)
2719 {
2720 if (unlikely(!ctx->fpu_enabled)) {
2721 gen_exception(ctx, POWERPC_EXCP_FPU);
2722 return;
2723 }
2724 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2725 cpu_fpr[rB(ctx->opcode)],
2726 cpu_fpr[rA(ctx->opcode)],
2727 32, 32);
2728 }
2729
2730 /*** Floating-Point status & ctrl register ***/
2731
2732 /* mcrfs */
2733 static void gen_mcrfs(DisasContext *ctx)
2734 {
2735 TCGv tmp = tcg_temp_new();
2736 TCGv_i32 tmask;
2737 TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
2738 int bfa;
2739 int nibble;
2740 int shift;
2741
2742 if (unlikely(!ctx->fpu_enabled)) {
2743 gen_exception(ctx, POWERPC_EXCP_FPU);
2744 return;
2745 }
2746 bfa = crfS(ctx->opcode);
2747 nibble = 7 - bfa;
2748 shift = 4 * nibble;
2749 tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
2750 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2751 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2752 tcg_temp_free(tmp);
2753 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2754 /* Only the exception bits (including FX) should be cleared if read */
2755 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2756 /* FEX and VX need to be updated, so don't set fpscr directly */
2757 tmask = tcg_const_i32(1 << nibble);
2758 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2759 tcg_temp_free_i32(tmask);
2760 tcg_temp_free_i64(tnew_fpscr);
2761 }
2762
2763 /* mffs */
2764 static void gen_mffs(DisasContext *ctx)
2765 {
2766 if (unlikely(!ctx->fpu_enabled)) {
2767 gen_exception(ctx, POWERPC_EXCP_FPU);
2768 return;
2769 }
2770 gen_reset_fpstatus();
2771 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2772 if (unlikely(Rc(ctx->opcode))) {
2773 gen_set_cr1_from_fpscr(ctx);
2774 }
2775 }
2776
2777 /* mtfsb0 */
2778 static void gen_mtfsb0(DisasContext *ctx)
2779 {
2780 uint8_t crb;
2781
2782 if (unlikely(!ctx->fpu_enabled)) {
2783 gen_exception(ctx, POWERPC_EXCP_FPU);
2784 return;
2785 }
2786 crb = 31 - crbD(ctx->opcode);
2787 gen_reset_fpstatus();
2788 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2789 TCGv_i32 t0;
2790 /* NIP cannot be restored if the memory exception comes from an helper */
2791 gen_update_nip(ctx, ctx->nip - 4);
2792 t0 = tcg_const_i32(crb);
2793 gen_helper_fpscr_clrbit(cpu_env, t0);
2794 tcg_temp_free_i32(t0);
2795 }
2796 if (unlikely(Rc(ctx->opcode) != 0)) {
2797 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2798 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2799 }
2800 }
2801
2802 /* mtfsb1 */
2803 static void gen_mtfsb1(DisasContext *ctx)
2804 {
2805 uint8_t crb;
2806
2807 if (unlikely(!ctx->fpu_enabled)) {
2808 gen_exception(ctx, POWERPC_EXCP_FPU);
2809 return;
2810 }
2811 crb = 31 - crbD(ctx->opcode);
2812 gen_reset_fpstatus();
2813 /* XXX: we pretend we can only do IEEE floating-point computations */
2814 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2815 TCGv_i32 t0;
2816 /* NIP cannot be restored if the memory exception comes from an helper */
2817 gen_update_nip(ctx, ctx->nip - 4);
2818 t0 = tcg_const_i32(crb);
2819 gen_helper_fpscr_setbit(cpu_env, t0);
2820 tcg_temp_free_i32(t0);
2821 }
2822 if (unlikely(Rc(ctx->opcode) != 0)) {
2823 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2824 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2825 }
2826 /* We can raise a differed exception */
2827 gen_helper_float_check_status(cpu_env);
2828 }
2829
2830 /* mtfsf */
2831 static void gen_mtfsf(DisasContext *ctx)
2832 {
2833 TCGv_i32 t0;
2834 int flm, l, w;
2835
2836 if (unlikely(!ctx->fpu_enabled)) {
2837 gen_exception(ctx, POWERPC_EXCP_FPU);
2838 return;
2839 }
2840 flm = FPFLM(ctx->opcode);
2841 l = FPL(ctx->opcode);
2842 w = FPW(ctx->opcode);
2843 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2844 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2845 return;
2846 }
2847 /* NIP cannot be restored if the memory exception comes from an helper */
2848 gen_update_nip(ctx, ctx->nip - 4);
2849 gen_reset_fpstatus();
2850 if (l) {
2851 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2852 } else {
2853 t0 = tcg_const_i32(flm << (w * 8));
2854 }
2855 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2856 tcg_temp_free_i32(t0);
2857 if (unlikely(Rc(ctx->opcode) != 0)) {
2858 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2859 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2860 }
2861 /* We can raise a differed exception */
2862 gen_helper_float_check_status(cpu_env);
2863 }
2864
2865 /* mtfsfi */
2866 static void gen_mtfsfi(DisasContext *ctx)
2867 {
2868 int bf, sh, w;
2869 TCGv_i64 t0;
2870 TCGv_i32 t1;
2871
2872 if (unlikely(!ctx->fpu_enabled)) {
2873 gen_exception(ctx, POWERPC_EXCP_FPU);
2874 return;
2875 }
2876 w = FPW(ctx->opcode);
2877 bf = FPBF(ctx->opcode);
2878 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2879 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2880 return;
2881 }
2882 sh = (8 * w) + 7 - bf;
2883 /* NIP cannot be restored if the memory exception comes from an helper */
2884 gen_update_nip(ctx, ctx->nip - 4);
2885 gen_reset_fpstatus();
2886 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2887 t1 = tcg_const_i32(1 << sh);
2888 gen_helper_store_fpscr(cpu_env, t0, t1);
2889 tcg_temp_free_i64(t0);
2890 tcg_temp_free_i32(t1);
2891 if (unlikely(Rc(ctx->opcode) != 0)) {
2892 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2893 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2894 }
2895 /* We can raise a differed exception */
2896 gen_helper_float_check_status(cpu_env);
2897 }
2898
2899 /*** Addressing modes ***/
2900 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2901 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2902 target_long maskl)
2903 {
2904 target_long simm = SIMM(ctx->opcode);
2905
2906 simm &= ~maskl;
2907 if (rA(ctx->opcode) == 0) {
2908 if (NARROW_MODE(ctx)) {
2909 simm = (uint32_t)simm;
2910 }
2911 tcg_gen_movi_tl(EA, simm);
2912 } else if (likely(simm != 0)) {
2913 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2914 if (NARROW_MODE(ctx)) {
2915 tcg_gen_ext32u_tl(EA, EA);
2916 }
2917 } else {
2918 if (NARROW_MODE(ctx)) {
2919 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2920 } else {
2921 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2922 }
2923 }
2924 }
2925
2926 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2927 {
2928 if (rA(ctx->opcode) == 0) {
2929 if (NARROW_MODE(ctx)) {
2930 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2931 } else {
2932 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2933 }
2934 } else {
2935 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2936 if (NARROW_MODE(ctx)) {
2937 tcg_gen_ext32u_tl(EA, EA);
2938 }
2939 }
2940 }
2941
2942 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2943 {
2944 if (rA(ctx->opcode) == 0) {
2945 tcg_gen_movi_tl(EA, 0);
2946 } else if (NARROW_MODE(ctx)) {
2947 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2948 } else {
2949 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2950 }
2951 }
2952
2953 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2954 target_long val)
2955 {
2956 tcg_gen_addi_tl(ret, arg1, val);
2957 if (NARROW_MODE(ctx)) {
2958 tcg_gen_ext32u_tl(ret, ret);
2959 }
2960 }
2961
2962 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2963 {
2964 TCGLabel *l1 = gen_new_label();
2965 TCGv t0 = tcg_temp_new();
2966 TCGv_i32 t1, t2;
2967 /* NIP cannot be restored if the memory exception comes from an helper */
2968 gen_update_nip(ctx, ctx->nip - 4);
2969 tcg_gen_andi_tl(t0, EA, mask);
2970 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2971 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2972 t2 = tcg_const_i32(0);
2973 gen_helper_raise_exception_err(cpu_env, t1, t2);
2974 tcg_temp_free_i32(t1);
2975 tcg_temp_free_i32(t2);
2976 gen_set_label(l1);
2977 tcg_temp_free(t0);
2978 }
2979
2980 /*** Integer load ***/
2981 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2982 {
2983 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2984 }
2985
2986 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2987 {
2988 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2989 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2990 }
2991
2992 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2993 {
2994 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2995 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2996 }
2997
2998 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2999 {
3000 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
3001 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3002 }
3003
3004 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
3005 {
3006 TCGv tmp = tcg_temp_new();
3007 gen_qemu_ld32u(ctx, tmp, addr);
3008 tcg_gen_extu_tl_i64(val, tmp);
3009 tcg_temp_free(tmp);
3010 }
3011
3012 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
3013 {
3014 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
3015 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3016 }
3017
3018 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
3019 {
3020 TCGv tmp = tcg_temp_new();
3021 gen_qemu_ld32s(ctx, tmp, addr);
3022 tcg_gen_ext_tl_i64(val, tmp);
3023 tcg_temp_free(tmp);
3024 }
3025
3026 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3027 {
3028 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
3029 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3030 }
3031
3032 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
3033 {
3034 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
3035 }
3036
3037 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
3038 {
3039 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
3040 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3041 }
3042
3043 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
3044 {
3045 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
3046 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3047 }
3048
3049 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
3050 {
3051 TCGv tmp = tcg_temp_new();
3052 tcg_gen_trunc_i64_tl(tmp, val);
3053 gen_qemu_st32(ctx, tmp, addr);
3054 tcg_temp_free(tmp);
3055 }
3056
3057 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3058 {
3059 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
3060 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3061 }
3062
3063 #define GEN_LD(name, ldop, opc, type) \
3064 static void glue(gen_, name)(DisasContext *ctx) \
3065 { \
3066 TCGv EA; \
3067 gen_set_access_type(ctx, ACCESS_INT); \
3068 EA = tcg_temp_new(); \
3069 gen_addr_imm_index(ctx, EA, 0); \
3070 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3071 tcg_temp_free(EA); \
3072 }
3073
3074 #define GEN_LDU(name, ldop, opc, type) \
3075 static void glue(gen_, name##u)(DisasContext *ctx) \
3076 { \
3077 TCGv EA; \
3078 if (unlikely(rA(ctx->opcode) == 0 || \
3079 rA(ctx->opcode) == rD(ctx->opcode))) { \
3080 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3081 return; \
3082 } \
3083 gen_set_access_type(ctx, ACCESS_INT); \
3084 EA = tcg_temp_new(); \
3085 if (type == PPC_64B) \
3086 gen_addr_imm_index(ctx, EA, 0x03); \
3087 else \
3088 gen_addr_imm_index(ctx, EA, 0); \
3089 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3090 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3091 tcg_temp_free(EA); \
3092 }
3093
3094 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
3095 static void glue(gen_, name##ux)(DisasContext *ctx) \
3096 { \
3097 TCGv EA; \
3098 if (unlikely(rA(ctx->opcode) == 0 || \
3099 rA(ctx->opcode) == rD(ctx->opcode))) { \
3100 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3101 return; \
3102 } \
3103 gen_set_access_type(ctx, ACCESS_INT); \
3104 EA = tcg_temp_new(); \
3105 gen_addr_reg_index(ctx, EA); \
3106 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3107 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3108 tcg_temp_free(EA); \
3109 }
3110
3111 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
3112 static void glue(gen_, name##x)(DisasContext *ctx) \
3113 { \
3114 TCGv EA; \
3115 chk; \
3116 gen_set_access_type(ctx, ACCESS_INT); \
3117 EA = tcg_temp_new(); \
3118 gen_addr_reg_index(ctx, EA); \
3119 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3120 tcg_temp_free(EA); \
3121 }
3122
3123 #define GEN_LDX(name, ldop, opc2, opc3, type) \
3124 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3125
3126 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
3127 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3128
3129 #define GEN_LDS(name, ldop, op, type) \
3130 GEN_LD(name, ldop, op | 0x20, type); \
3131 GEN_LDU(name, ldop, op | 0x21, type); \
3132 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
3133 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
3134
3135 /* lbz lbzu lbzux lbzx */
3136 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
3137 /* lha lhau lhaux lhax */
3138 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
3139 /* lhz lhzu lhzux lhzx */
3140 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
3141 /* lwz lwzu lwzux lwzx */
3142 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
3143 #if defined(TARGET_PPC64)
3144 /* lwaux */
3145 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
3146 /* lwax */
3147 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
3148 /* ldux */
3149 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
3150 /* ldx */
3151 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
3152
3153 /* CI load/store variants */
3154 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
3155 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
3156 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
3157 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
3158
3159 static void gen_ld(DisasContext *ctx)
3160 {
3161 TCGv EA;
3162 if (Rc(ctx->opcode)) {
3163 if (unlikely(rA(ctx->opcode) == 0 ||
3164 rA(ctx->opcode) == rD(ctx->opcode))) {
3165 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3166 return;
3167 }
3168 }
3169 gen_set_access_type(ctx, ACCESS_INT);
3170 EA = tcg_temp_new();
3171 gen_addr_imm_index(ctx, EA, 0x03);
3172 if (ctx->opcode & 0x02) {
3173 /* lwa (lwau is undefined) */
3174 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
3175 } else {
3176 /* ld - ldu */
3177 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
3178 }
3179 if (Rc(ctx->opcode))
3180 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3181 tcg_temp_free(EA);
3182 }
3183
3184 /* lq */
3185 static void gen_lq(DisasContext *ctx)
3186 {
3187 int ra, rd;
3188 TCGv EA;
3189
3190 /* lq is a legal user mode instruction starting in ISA 2.07 */
3191 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3192 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3193
3194 if (!legal_in_user_mode && ctx->pr) {
3195 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3196 return;
3197 }
3198
3199 if (!le_is_supported && ctx->le_mode) {
3200 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3201 return;
3202 }
3203
3204 ra = rA(ctx->opcode);
3205 rd = rD(ctx->opcode);
3206 if (unlikely((rd & 1) || rd == ra)) {
3207 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3208 return;
3209 }
3210
3211 gen_set_access_type(ctx, ACCESS_INT);
3212 EA = tcg_temp_new();
3213 gen_addr_imm_index(ctx, EA, 0x0F);
3214
3215 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3216 64-bit byteswap already. */
3217 if (unlikely(ctx->le_mode)) {
3218 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
3219 gen_addr_add(ctx, EA, EA, 8);
3220 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
3221 } else {
3222 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
3223 gen_addr_add(ctx, EA, EA, 8);
3224 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
3225 }
3226 tcg_temp_free(EA);
3227 }
3228 #endif
3229
3230 /*** Integer store ***/
3231 #define GEN_ST(name, stop, opc, type) \
3232 static void glue(gen_, name)(DisasContext *ctx) \
3233 { \
3234 TCGv EA; \
3235 gen_set_access_type(ctx, ACCESS_INT); \
3236 EA = tcg_temp_new(); \
3237 gen_addr_imm_index(ctx, EA, 0); \
3238 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3239 tcg_temp_free(EA); \
3240 }
3241
3242 #define GEN_STU(name, stop, opc, type) \
3243 static void glue(gen_, stop##u)(DisasContext *ctx) \
3244 { \
3245 TCGv EA; \
3246 if (unlikely(rA(ctx->opcode) == 0)) { \
3247 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3248 return; \
3249 } \
3250 gen_set_access_type(ctx, ACCESS_INT); \
3251 EA = tcg_temp_new(); \
3252 if (type == PPC_64B) \
3253 gen_addr_imm_index(ctx, EA, 0x03); \
3254 else \
3255 gen_addr_imm_index(ctx, EA, 0); \
3256 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3257 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3258 tcg_temp_free(EA); \
3259 }
3260
3261 #define GEN_STUX(name, stop, opc2, opc3, type) \
3262 static void glue(gen_, name##ux)(DisasContext *ctx) \
3263 { \
3264 TCGv EA; \
3265 if (unlikely(rA(ctx->opcode) == 0)) { \
3266 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3267 return; \
3268 } \
3269 gen_set_access_type(ctx, ACCESS_INT); \
3270 EA = tcg_temp_new(); \
3271 gen_addr_reg_index(ctx, EA); \
3272 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3273 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3274 tcg_temp_free(EA); \
3275 }
3276
3277 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
3278 static void glue(gen_, name##x)(DisasContext *ctx) \
3279 { \
3280 TCGv EA; \
3281 chk; \
3282 gen_set_access_type(ctx, ACCESS_INT); \
3283 EA = tcg_temp_new(); \
3284 gen_addr_reg_index(ctx, EA); \
3285 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3286 tcg_temp_free(EA); \
3287 }
3288 #define GEN_STX(name, stop, opc2, opc3, type) \
3289 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3290
3291 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
3292 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3293
3294 #define GEN_STS(name, stop, op, type) \
3295 GEN_ST(name, stop, op | 0x20, type); \
3296 GEN_STU(name, stop, op | 0x21, type); \
3297 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3298 GEN_STX(name, stop, 0x17, op | 0x00, type)
3299
3300 /* stb stbu stbux stbx */
3301 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3302 /* sth sthu sthux sthx */
3303 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3304 /* stw stwu stwux stwx */
3305 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3306 #if defined(TARGET_PPC64)
3307 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3308 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3309 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
3310 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
3311 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
3312 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
3313
3314 static void gen_std(DisasContext *ctx)
3315 {
3316 int rs;
3317 TCGv EA;
3318
3319 rs = rS(ctx->opcode);
3320 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3321 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3322 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3323
3324 if (!(ctx->insns_flags & PPC_64BX)) {
3325 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3326 }
3327
3328 if (!legal_in_user_mode && ctx->pr) {
3329 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3330 return;
3331 }
3332
3333 if (!le_is_supported && ctx->le_mode) {
3334 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3335 return;
3336 }
3337
3338 if (unlikely(rs & 1)) {
3339 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3340 return;
3341 }
3342 gen_set_access_type(ctx, ACCESS_INT);
3343 EA = tcg_temp_new();
3344 gen_addr_imm_index(ctx, EA, 0x03);
3345
3346 /* We only need to swap high and low halves. gen_qemu_st64 does
3347 necessary 64-bit byteswap already. */
3348 if (unlikely(ctx->le_mode)) {
3349 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3350 gen_addr_add(ctx, EA, EA, 8);
3351 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3352 } else {
3353 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3354 gen_addr_add(ctx, EA, EA, 8);
3355 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3356 }
3357 tcg_temp_free(EA);
3358 } else {
3359 /* std / stdu*/
3360 if (Rc(ctx->opcode)) {
3361 if (unlikely(rA(ctx->opcode) == 0)) {
3362 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3363 return;
3364 }
3365 }
3366 gen_set_access_type(ctx, ACCESS_INT);
3367 EA = tcg_temp_new();
3368 gen_addr_imm_index(ctx, EA, 0x03);
3369 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3370 if (Rc(ctx->opcode))
3371 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3372 tcg_temp_free(EA);
3373 }
3374 }
3375 #endif
3376 /*** Integer load and store with byte reverse ***/
3377
3378 /* lhbrx */
3379 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3380 {
3381 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3382 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3383 }
3384 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3385
3386 /* lwbrx */
3387 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3388 {
3389 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3390 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3391 }
3392 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3393
3394 #if defined(TARGET_PPC64)
3395 /* ldbrx */
3396 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3397 {
3398 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3399 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3400 }
3401 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
3402 #endif /* TARGET_PPC64 */
3403
3404 /* sthbrx */
3405 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3406 {
3407 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3408 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3409 }
3410 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3411
3412 /* stwbrx */
3413 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3414 {
3415 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3416 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3417 }
3418 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3419
3420 #if defined(TARGET_PPC64)
3421 /* stdbrx */
3422 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3423 {
3424 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3425 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3426 }
3427 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
3428 #endif /* TARGET_PPC64 */
3429
3430 /*** Integer load and store multiple ***/
3431
3432 /* lmw */
3433 static void gen_lmw(DisasContext *ctx)
3434 {
3435 TCGv t0;
3436 TCGv_i32 t1;
3437 gen_set_access_type(ctx, ACCESS_INT);
3438 /* NIP cannot be restored if the memory exception comes from an helper */
3439 gen_update_nip(ctx, ctx->nip - 4);
3440 t0 = tcg_temp_new();
3441 t1 = tcg_const_i32(rD(ctx->opcode));
3442 gen_addr_imm_index(ctx, t0, 0);
3443 gen_helper_lmw(cpu_env, t0, t1);
3444 tcg_temp_free(t0);
3445 tcg_temp_free_i32(t1);
3446 }
3447
3448 /* stmw */
3449 static void gen_stmw(DisasContext *ctx)
3450 {
3451 TCGv t0;
3452 TCGv_i32 t1;
3453 gen_set_access_type(ctx, ACCESS_INT);
3454 /* NIP cannot be restored if the memory exception comes from an helper */
3455 gen_update_nip(ctx, ctx->nip - 4);
3456 t0 = tcg_temp_new();
3457 t1 = tcg_const_i32(rS(ctx->opcode));
3458 gen_addr_imm_index(ctx, t0, 0);
3459 gen_helper_stmw(cpu_env, t0, t1);
3460 tcg_temp_free(t0);
3461 tcg_temp_free_i32(t1);
3462 }
3463
3464 /*** Integer load and store strings ***/
3465
3466 /* lswi */
3467 /* PowerPC32 specification says we must generate an exception if
3468 * rA is in the range of registers to be loaded.
3469 * In an other hand, IBM says this is valid, but rA won't be loaded.
3470 * For now, I'll follow the spec...
3471 */
3472 static void gen_lswi(DisasContext *ctx)
3473 {
3474 TCGv t0;
3475 TCGv_i32 t1, t2;
3476 int nb = NB(ctx->opcode);
3477 int start = rD(ctx->opcode);
3478 int ra = rA(ctx->opcode);
3479 int nr;
3480
3481 if (nb == 0)
3482 nb = 32;
3483 nr = (nb + 3) / 4;
3484 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
3485 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3486 return;
3487 }
3488 gen_set_access_type(ctx, ACCESS_INT);
3489 /* NIP cannot be restored if the memory exception comes from an helper */
3490 gen_update_nip(ctx, ctx->nip - 4);
3491 t0 = tcg_temp_new();
3492 gen_addr_register(ctx, t0);
3493 t1 = tcg_const_i32(nb);
3494 t2 = tcg_const_i32(start);
3495 gen_helper_lsw(cpu_env, t0, t1, t2);
3496 tcg_temp_free(t0);
3497 tcg_temp_free_i32(t1);
3498 tcg_temp_free_i32(t2);
3499 }
3500
3501 /* lswx */
3502 static void gen_lswx(DisasContext *ctx)
3503 {
3504 TCGv t0;
3505 TCGv_i32 t1, t2, t3;
3506 gen_set_access_type(ctx, ACCESS_INT);
3507 /* NIP cannot be restored if the memory exception comes from an helper */
3508 gen_update_nip(ctx, ctx->nip - 4);
3509 t0 = tcg_temp_new();
3510 gen_addr_reg_index(ctx, t0);
3511 t1 = tcg_const_i32(rD(ctx->opcode));
3512 t2 = tcg_const_i32(rA(ctx->opcode));
3513 t3 = tcg_const_i32(rB(ctx->opcode));
3514 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3515 tcg_temp_free(t0);
3516 tcg_temp_free_i32(t1);
3517 tcg_temp_free_i32(t2);
3518 tcg_temp_free_i32(t3);
3519 }
3520
3521 /* stswi */
3522 static void gen_stswi(DisasContext *ctx)
3523 {
3524 TCGv t0;
3525 TCGv_i32 t1, t2;
3526 int nb = NB(ctx->opcode);
3527 gen_set_access_type(ctx, ACCESS_INT);
3528 /* NIP cannot be restored if the memory exception comes from an helper */
3529 gen_update_nip(ctx, ctx->nip - 4);
3530 t0 = tcg_temp_new();
3531 gen_addr_register(ctx, t0);
3532 if (nb == 0)
3533 nb = 32;
3534 t1 = tcg_const_i32(nb);
3535 t2 = tcg_const_i32(rS(ctx->opcode));
3536 gen_helper_stsw(cpu_env, t0, t1, t2);
3537 tcg_temp_free(t0);
3538 tcg_temp_free_i32(t1);
3539 tcg_temp_free_i32(t2);
3540 }
3541
3542 /* stswx */
3543 static void gen_stswx(DisasContext *ctx)
3544 {
3545 TCGv t0;
3546 TCGv_i32 t1, t2;
3547 gen_set_access_type(ctx, ACCESS_INT);
3548 /* NIP cannot be restored if the memory exception comes from an helper */
3549 gen_update_nip(ctx, ctx->nip - 4);
3550 t0 = tcg_temp_new();
3551 gen_addr_reg_index(ctx, t0);
3552 t1 = tcg_temp_new_i32();
3553 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3554 tcg_gen_andi_i32(t1, t1, 0x7F);
3555 t2 = tcg_const_i32(rS(ctx->opcode));
3556 gen_helper_stsw(cpu_env, t0, t1, t2);
3557 tcg_temp_free(t0);
3558 tcg_temp_free_i32(t1);
3559 tcg_temp_free_i32(t2);
3560 }
3561
3562 /*** Memory synchronisation ***/
3563 /* eieio */
3564 static void gen_eieio(DisasContext *ctx)
3565 {
3566 }
3567
3568 #if !defined(CONFIG_USER_ONLY)
3569 static inline void gen_check_tlb_flush(DisasContext *ctx)
3570 {
3571 TCGv_i32 t;
3572 TCGLabel *l;
3573
3574 if (!ctx->lazy_tlb_flush) {
3575 return;
3576 }
3577 l = gen_new_label();
3578 t = tcg_temp_new_i32();
3579 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3580 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3581 gen_helper_check_tlb_flush(cpu_env);
3582 gen_set_label(l);
3583 tcg_temp_free_i32(t);
3584 }
3585 #else
3586 static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3587 #endif
3588
3589 /* isync */
3590 static void gen_isync(DisasContext *ctx)
3591 {
3592 /*
3593 * We need to check for a pending TLB flush. This can only happen in
3594 * kernel mode however so check MSR_PR
3595 */
3596 if (!ctx->pr) {
3597 gen_check_tlb_flush(ctx);
3598 }
3599 gen_stop_exception(ctx);
3600 }
3601
3602 #define LARX(name, len, loadop) \
3603 static void gen_##name(DisasContext *ctx) \
3604 { \
3605 TCGv t0; \
3606 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3607 gen_set_access_type(ctx, ACCESS_RES); \
3608 t0 = tcg_temp_local_new(); \
3609 gen_addr_reg_index(ctx, t0); \
3610 if ((len) > 1) { \
3611 gen_check_align(ctx, t0, (len)-1); \
3612 } \
3613 gen_qemu_##loadop(ctx, gpr, t0); \
3614 tcg_gen_mov_tl(cpu_reserve, t0); \
3615 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3616 tcg_temp_free(t0); \
3617 }
3618
3619 /* lwarx */
3620 LARX(lbarx, 1, ld8u);
3621 LARX(lharx, 2, ld16u);
3622 LARX(lwarx, 4, ld32u);
3623
3624
3625 #if defined(CONFIG_USER_ONLY)
3626 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3627 int reg, int size)
3628 {
3629 TCGv t0 = tcg_temp_new();
3630 uint32_t save_exception = ctx->exception;
3631
3632 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3633 tcg_gen_movi_tl(t0, (size << 5) | reg);
3634 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3635 tcg_temp_free(t0);
3636 gen_update_nip(ctx, ctx->nip-4);
3637 ctx->exception = POWERPC_EXCP_BRANCH;
3638 gen_exception(ctx, POWERPC_EXCP_STCX);
3639 ctx->exception = save_exception;
3640 }
3641 #else
3642 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3643 int reg, int size)
3644 {
3645 TCGLabel *l1;
3646
3647 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3648 l1 = gen_new_label();
3649 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3650 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3651 #if defined(TARGET_PPC64)
3652 if (size == 8) {
3653 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3654 } else
3655 #endif
3656 if (size == 4) {
3657 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3658 } else if (size == 2) {
3659 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3660 #if defined(TARGET_PPC64)
3661 } else if (size == 16) {
3662 TCGv gpr1, gpr2 , EA8;
3663 if (unlikely(ctx->le_mode)) {
3664 gpr1 = cpu_gpr[reg+1];
3665 gpr2 = cpu_gpr[reg];
3666 } else {
3667 gpr1 = cpu_gpr[reg];
3668 gpr2 = cpu_gpr[reg+1];
3669 }
3670 gen_qemu_st64(ctx, gpr1, EA);
3671 EA8 = tcg_temp_local_new();
3672 gen_addr_add(ctx, EA8, EA, 8);
3673 gen_qemu_st64(ctx, gpr2, EA8);
3674 tcg_temp_free(EA8);
3675 #endif
3676 } else {
3677 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3678 }
3679 gen_set_label(l1);
3680 tcg_gen_movi_tl(cpu_reserve, -1);
3681 }
3682 #endif
3683
3684 #define STCX(name, len) \
3685 static void gen_##name(DisasContext *ctx) \
3686 { \
3687 TCGv t0; \
3688 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3689 gen_inval_exception(ctx, \
3690 POWERPC_EXCP_INVAL_INVAL); \
3691 return; \
3692 } \
3693 gen_set_access_type(ctx, ACCESS_RES); \
3694 t0 = tcg_temp_local_new(); \
3695 gen_addr_reg_index(ctx, t0); \
3696 if (len > 1) { \
3697 gen_check_align(ctx, t0, (len)-1); \
3698 } \
3699 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3700 tcg_temp_free(t0); \
3701 }
3702
3703 STCX(stbcx_, 1);
3704 STCX(sthcx_, 2);
3705 STCX(stwcx_, 4);
3706
3707 #if defined(TARGET_PPC64)
3708 /* ldarx */
3709 LARX(ldarx, 8, ld64);
3710
3711 /* lqarx */
3712 static void gen_lqarx(DisasContext *ctx)
3713 {
3714 TCGv EA;
3715 int rd = rD(ctx->opcode);
3716 TCGv gpr1, gpr2;
3717
3718 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3719 (rd == rB(ctx->opcode)))) {
3720 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3721 return;
3722 }
3723
3724 gen_set_access_type(ctx, ACCESS_RES);
3725 EA = tcg_temp_local_new();
3726 gen_addr_reg_index(ctx, EA);
3727 gen_check_align(ctx, EA, 15);
3728 if (unlikely(ctx->le_mode)) {
3729 gpr1 = cpu_gpr[rd+1];
3730 gpr2 = cpu_gpr[rd];
3731 } else {
3732 gpr1 = cpu_gpr[rd];
3733 gpr2 = cpu_gpr[rd+1];
3734 }
3735 gen_qemu_ld64(ctx, gpr1, EA);
3736 tcg_gen_mov_tl(cpu_reserve, EA);
3737
3738 gen_addr_add(ctx, EA, EA, 8);
3739 gen_qemu_ld64(ctx, gpr2, EA);
3740
3741 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3742 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3743
3744 tcg_temp_free(EA);
3745 }
3746
3747 /* stdcx. */
3748 STCX(stdcx_, 8);
3749 STCX(stqcx_, 16);
3750 #endif /* defined(TARGET_PPC64) */
3751
3752 /* sync */
3753 static void gen_sync(DisasContext *ctx)
3754 {
3755 uint32_t l = (ctx->opcode >> 21) & 3;
3756
3757 /*
3758 * We may need to check for a pending TLB flush.
3759 *
3760 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3761 *
3762 * Additionally, this can only happen in kernel mode however so
3763 * check MSR_PR as well.
3764 */
3765 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3766 gen_check_tlb_flush(ctx);
3767 }
3768 }
3769
3770 /* wait */
3771 static void gen_wait(DisasContext *ctx)
3772 {
3773 TCGv_i32 t0 = tcg_const_i32(1);
3774 tcg_gen_st_i32(t0, cpu_env,
3775 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3776 tcg_temp_free_i32(t0);
3777 /* Stop translation, as the CPU is supposed to sleep from now */
3778 gen_exception_err(ctx, EXCP_HLT, 1);
3779 }
3780
3781 #if defined(TARGET_PPC64)
3782 static void gen_doze(DisasContext *ctx)
3783 {
3784 #if defined(CONFIG_USER_ONLY)
3785 GEN_PRIV;
3786 #else
3787 TCGv_i32 t;
3788
3789 CHK_HV;
3790 t = tcg_const_i32(PPC_PM_DOZE);
3791 gen_helper_pminsn(cpu_env, t);
3792 tcg_temp_free_i32(t);
3793 gen_stop_exception(ctx);
3794 #endif /* defined(CONFIG_USER_ONLY) */
3795 }
3796
3797 static void gen_nap(DisasContext *ctx)
3798 {
3799 #if defined(CONFIG_USER_ONLY)
3800 GEN_PRIV;
3801 #else
3802 TCGv_i32 t;
3803
3804 CHK_HV;
3805 t = tcg_const_i32(PPC_PM_NAP);
3806 gen_helper_pminsn(cpu_env, t);
3807 tcg_temp_free_i32(t);
3808 gen_stop_exception(ctx);
3809 #endif /* defined(CONFIG_USER_ONLY) */
3810 }
3811
3812 static void gen_sleep(DisasContext *ctx)
3813 {
3814 #if defined(CONFIG_USER_ONLY)
3815 GEN_PRIV;
3816 #else
3817 TCGv_i32 t;
3818
3819 CHK_HV;
3820 t = tcg_const_i32(PPC_PM_SLEEP);
3821 gen_helper_pminsn(cpu_env, t);
3822 tcg_temp_free_i32(t);
3823 gen_stop_exception(ctx);
3824 #endif /* defined(CONFIG_USER_ONLY) */
3825 }
3826
3827 static void gen_rvwinkle(DisasContext *ctx)
3828 {
3829 #if defined(CONFIG_USER_ONLY)
3830 GEN_PRIV;
3831 #else
3832 TCGv_i32 t;
3833
3834 CHK_HV;
3835 t = tcg_const_i32(PPC_PM_RVWINKLE);
3836 gen_helper_pminsn(cpu_env, t);
3837 tcg_temp_free_i32(t);
3838 gen_stop_exception(ctx);
3839 #endif /* defined(CONFIG_USER_ONLY) */
3840 }
3841 #endif /* #if defined(TARGET_PPC64) */
3842
3843 /*** Floating-point load ***/
3844 #define GEN_LDF(name, ldop, opc, type) \
3845 static void glue(gen_, name)(DisasContext *ctx) \
3846 { \
3847 TCGv EA; \
3848 if (unlikely(!ctx->fpu_enabled)) { \
3849 gen_exception(ctx, POWERPC_EXCP_FPU); \
3850 return; \
3851 } \
3852 gen_set_access_type(ctx, ACCESS_FLOAT); \
3853 EA = tcg_temp_new(); \
3854 gen_addr_imm_index(ctx, EA, 0); \
3855 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3856 tcg_temp_free(EA); \
3857 }
3858
3859 #define GEN_LDUF(name, ldop, opc, type) \
3860 static void glue(gen_, name##u)(DisasContext *ctx) \
3861 { \
3862 TCGv EA; \
3863 if (unlikely(!ctx->fpu_enabled)) { \
3864 gen_exception(ctx, POWERPC_EXCP_FPU); \
3865 return; \
3866 } \
3867 if (unlikely(rA(ctx->opcode) == 0)) { \
3868 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3869 return; \
3870 } \
3871 gen_set_access_type(ctx, ACCESS_FLOAT); \
3872 EA = tcg_temp_new(); \
3873 gen_addr_imm_index(ctx, EA, 0); \
3874 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3875 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3876 tcg_temp_free(EA); \
3877 }
3878
3879 #define GEN_LDUXF(name, ldop, opc, type) \
3880 static void glue(gen_, name##ux)(DisasContext *ctx) \
3881 { \
3882 TCGv EA; \
3883 if (unlikely(!ctx->fpu_enabled)) { \
3884 gen_exception(ctx, POWERPC_EXCP_FPU); \
3885 return; \
3886 } \
3887 if (unlikely(rA(ctx->opcode) == 0)) { \
3888 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3889 return; \
3890 } \
3891 gen_set_access_type(ctx, ACCESS_FLOAT); \
3892 EA = tcg_temp_new(); \
3893 gen_addr_reg_index(ctx, EA); \
3894 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3895 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3896 tcg_temp_free(EA); \
3897 }
3898
3899 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3900 static void glue(gen_, name##x)(DisasContext *ctx) \
3901 { \
3902 TCGv EA; \
3903 if (unlikely(!ctx->fpu_enabled)) { \
3904 gen_exception(ctx, POWERPC_EXCP_FPU); \
3905 return; \
3906 } \
3907 gen_set_access_type(ctx, ACCESS_FLOAT); \
3908 EA = tcg_temp_new(); \
3909 gen_addr_reg_index(ctx, EA); \
3910 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3911 tcg_temp_free(EA); \
3912 }
3913
3914 #define GEN_LDFS(name, ldop, op, type) \
3915 GEN_LDF(name, ldop, op | 0x20, type); \
3916 GEN_LDUF(name, ldop, op | 0x21, type); \
3917 GEN_LDUXF(name, ldop, op | 0x01, type); \
3918 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3919
3920 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3921 {
3922 TCGv t0 = tcg_temp_new();
3923 TCGv_i32 t1 = tcg_temp_new_i32();
3924 gen_qemu_ld32u(ctx, t0, arg2);
3925 tcg_gen_trunc_tl_i32(t1, t0);
3926 tcg_temp_free(t0);
3927 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3928 tcg_temp_free_i32(t1);
3929 }
3930
3931 /* lfd lfdu lfdux lfdx */
3932 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3933 /* lfs lfsu lfsux lfsx */
3934 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3935
3936 /* lfdp */
3937 static void gen_lfdp(DisasContext *ctx)
3938 {
3939 TCGv EA;
3940 if (unlikely(!ctx->fpu_enabled)) {
3941 gen_exception(ctx, POWERPC_EXCP_FPU);
3942 return;
3943 }
3944 gen_set_access_type(ctx, ACCESS_FLOAT);
3945 EA = tcg_temp_new();
3946 gen_addr_imm_index(ctx, EA, 0);
3947 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3948 64-bit byteswap already. */
3949 if (unlikely(ctx->le_mode)) {
3950 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3951 tcg_gen_addi_tl(EA, EA, 8);
3952 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3953 } else {
3954 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3955 tcg_gen_addi_tl(EA, EA, 8);
3956 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3957 }
3958 tcg_temp_free(EA);
3959 }
3960
3961 /* lfdpx */
3962 static void gen_lfdpx(DisasContext *ctx)
3963 {
3964 TCGv EA;
3965 if (unlikely(!ctx->fpu_enabled)) {
3966 gen_exception(ctx, POWERPC_EXCP_FPU);
3967 return;
3968 }
3969 gen_set_access_type(ctx, ACCESS_FLOAT);
3970 EA = tcg_temp_new();
3971 gen_addr_reg_index(ctx, EA);
3972 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3973 64-bit byteswap already. */
3974 if (unlikely(ctx->le_mode)) {
3975 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3976 tcg_gen_addi_tl(EA, EA, 8);
3977 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3978 } else {
3979 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3980 tcg_gen_addi_tl(EA, EA, 8);
3981 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3982 }
3983 tcg_temp_free(EA);
3984 }
3985
3986 /* lfiwax */
3987 static void gen_lfiwax(DisasContext *ctx)
3988 {
3989 TCGv EA;
3990 TCGv t0;
3991 if (unlikely(!ctx->fpu_enabled)) {
3992 gen_exception(ctx, POWERPC_EXCP_FPU);
3993 return;
3994 }
3995 gen_set_access_type(ctx, ACCESS_FLOAT);
3996 EA = tcg_temp_new();
3997 t0 = tcg_temp_new();
3998 gen_addr_reg_index(ctx, EA);
3999 gen_qemu_ld32s(ctx, t0, EA);
4000 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
4001 tcg_temp_free(EA);
4002 tcg_temp_free(t0);
4003 }
4004
4005 /* lfiwzx */
4006 static void gen_lfiwzx(DisasContext *ctx)
4007 {
4008 TCGv EA;
4009 if (unlikely(!ctx->fpu_enabled)) {
4010 gen_exception(ctx, POWERPC_EXCP_FPU);
4011 return;
4012 }
4013 gen_set_access_type(ctx, ACCESS_FLOAT);
4014 EA = tcg_temp_new();
4015 gen_addr_reg_index(ctx, EA);
4016 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
4017 tcg_temp_free(EA);
4018 }
4019 /*** Floating-point store ***/
4020 #define GEN_STF(name, stop, opc, type) \
4021 static void glue(gen_, name)(DisasContext *ctx) \
4022 { \
4023 TCGv EA; \
4024 if (unlikely(!ctx->fpu_enabled)) { \
4025 gen_exception(ctx, POWERPC_EXCP_FPU); \
4026 return; \
4027 } \
4028 gen_set_access_type(ctx, ACCESS_FLOAT); \
4029 EA = tcg_temp_new(); \
4030 gen_addr_imm_index(ctx, EA, 0); \
4031 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
4032 tcg_temp_free(EA); \
4033 }
4034
4035 #define GEN_STUF(name, stop, opc, type) \
4036 static void glue(gen_, name##u)(DisasContext *ctx) \
4037 { \
4038 TCGv EA; \
4039 if (unlikely(!ctx->fpu_enabled)) { \
4040 gen_exception(ctx, POWERPC_EXCP_FPU); \
4041 return; \
4042 } \
4043 if (unlikely(rA(ctx->opcode) == 0)) { \
4044 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
4045 return; \
4046 } \
4047 gen_set_access_type(ctx, ACCESS_FLOAT); \
4048 EA = tcg_temp_new(); \
4049 gen_addr_imm_index(ctx, EA, 0); \
4050 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
4051 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
4052 tcg_temp_free(EA); \
4053 }
4054
4055 #define GEN_STUXF(name, stop, opc, type) \
4056 static void glue(gen_, name##ux)(DisasContext *ctx) \
4057 { \
4058 TCGv EA; \
4059 if (unlikely(!ctx->fpu_enabled)) { \
4060 gen_exception(ctx, POWERPC_EXCP_FPU); \
4061 return; \
4062 } \
4063 if (unlikely(rA(ctx->opcode) == 0)) { \
4064 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
4065 return; \
4066 } \
4067 gen_set_access_type(ctx, ACCESS_FLOAT); \
4068 EA = tcg_temp_new(); \
4069 gen_addr_reg_index(ctx, EA); \
4070 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
4071 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
4072 tcg_temp_free(EA); \
4073 }
4074
4075 #define GEN_STXF(name, stop, opc2, opc3, type) \
4076 static void glue(gen_, name##x)(DisasContext *ctx) \
4077 { \
4078 TCGv EA; \
4079 if (unlikely(!ctx->fpu_enabled)) { \
4080 gen_exception(ctx, POWERPC_EXCP_FPU); \
4081 return; \
4082 } \
4083 gen_set_access_type(ctx, ACCESS_FLOAT); \
4084 EA = tcg_temp_new(); \
4085 gen_addr_reg_index(ctx, EA); \
4086 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
4087 tcg_temp_free(EA); \
4088 }
4089
4090 #define GEN_STFS(name, stop, op, type) \
4091 GEN_STF(name, stop, op | 0x20, type); \
4092 GEN_STUF(name, stop, op | 0x21, type); \
4093 GEN_STUXF(name, stop, op | 0x01, type); \
4094 GEN_STXF(name, stop, 0x17, op | 0x00, type)
4095
4096 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
4097 {
4098 TCGv_i32 t0 = tcg_temp_new_i32();
4099 TCGv t1 = tcg_temp_new();
4100 gen_helper_float64_to_float32(t0, cpu_env, arg1);
4101 tcg_gen_extu_i32_tl(t1, t0);
4102 tcg_temp_free_i32(t0);
4103 gen_qemu_st32(ctx, t1, arg2);
4104 tcg_temp_free(t1);
4105 }
4106
4107 /* stfd stfdu stfdux stfdx */
4108 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
4109 /* stfs stfsu stfsux stfsx */
4110 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
4111
4112 /* stfdp */
4113 static void gen_stfdp(DisasContext *ctx)
4114 {
4115 TCGv EA;
4116 if (unlikely(!ctx->fpu_enabled)) {
4117 gen_exception(ctx, POWERPC_EXCP_FPU);
4118 return;
4119 }
4120 gen_set_access_type(ctx, ACCESS_FLOAT);
4121 EA = tcg_temp_new();
4122 gen_addr_imm_index(ctx, EA, 0);
4123 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
4124 64-bit byteswap already. */
4125 if (unlikely(ctx->le_mode)) {
4126 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
4127 tcg_gen_addi_tl(EA, EA, 8);
4128 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
4129 } else {
4130 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
4131 tcg_gen_addi_tl(EA, EA, 8);
4132 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
4133 }
4134 tcg_temp_free(EA);
4135 }
4136
4137 /* stfdpx */
4138 static void gen_stfdpx(DisasContext *ctx)
4139 {
4140 TCGv EA;
4141 if (unlikely(!ctx->fpu_enabled)) {
4142 gen_exception(ctx, POWERPC_EXCP_FPU);
4143 return;
4144 }
4145 gen_set_access_type(ctx, ACCESS_FLOAT);
4146 EA = tcg_temp_new();
4147 gen_addr_reg_index(ctx, EA);
4148 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
4149 64-bit byteswap already. */
4150 if (unlikely(ctx->le_mode)) {
4151 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
4152 tcg_gen_addi_tl(EA, EA, 8);
4153 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
4154 } else {
4155 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
4156 tcg_gen_addi_tl(EA, EA, 8);
4157 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
4158 }
4159 tcg_temp_free(EA);
4160 }
4161
4162 /* Optional: */
4163 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
4164 {
4165 TCGv t0 = tcg_temp_new();
4166 tcg_gen_trunc_i64_tl(t0, arg1),
4167 gen_qemu_st32(ctx, t0, arg2);
4168 tcg_temp_free(t0);
4169 }
4170 /* stfiwx */
4171 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
4172
4173 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
4174 {
4175 #if defined(TARGET_PPC64)
4176 if (ctx->has_cfar)
4177 tcg_gen_movi_tl(cpu_cfar, nip);
4178 #endif
4179 }
4180
4181 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
4182 {
4183 if (unlikely(ctx->singlestep_enabled)) {
4184 return false;
4185 }
4186
4187 #ifndef CONFIG_USER_ONLY
4188 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
4189 #else
4190 return true;
4191 #endif
4192 }
4193
4194 /*** Branch ***/
4195 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
4196 {
4197 if (NARROW_MODE(ctx)) {
4198 dest = (uint32_t) dest;
4199 }
4200 if (use_goto_tb(ctx, dest)) {
4201 tcg_gen_goto_tb(n);
4202 tcg_gen_movi_tl(cpu_nip, dest & ~3);
4203 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
4204 } else {
4205 tcg_gen_movi_tl(cpu_nip, dest & ~3);
4206 if (unlikely(ctx->singlestep_enabled)) {
4207 if ((ctx->singlestep_enabled &
4208 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
4209 (ctx->exception == POWERPC_EXCP_BRANCH ||
4210 ctx->exception == POWERPC_EXCP_TRACE)) {
4211 target_ulong tmp = ctx->nip;
4212 ctx->nip = dest;
4213 gen_exception(ctx, POWERPC_EXCP_TRACE);
4214 ctx->nip = tmp;
4215 }
4216 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
4217 gen_debug_exception(ctx);
4218 }
4219 }
4220 tcg_gen_exit_tb(0);
4221 }
4222 }
4223
4224 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
4225 {
4226 if (NARROW_MODE(ctx)) {
4227 nip = (uint32_t)nip;
4228 }
4229 tcg_gen_movi_tl(cpu_lr, nip);
4230 }
4231
4232 /* b ba bl bla */
4233 static void gen_b(DisasContext *ctx)
4234 {
4235 target_ulong li, target;
4236
4237 ctx->exception = POWERPC_EXCP_BRANCH;
4238 /* sign extend LI */
4239 li = LI(ctx->opcode);
4240 li = (li ^ 0x02000000) - 0x02000000;
4241 if (likely(AA(ctx->opcode) == 0)) {
4242 target = ctx->nip + li - 4;
4243 } else {
4244 target = li;
4245 }
4246 if (LK(ctx->opcode)) {
4247 gen_setlr(ctx, ctx->nip);
4248 }
4249 gen_update_cfar(ctx, ctx->nip);
4250 gen_goto_tb(ctx, 0, target);
4251 }
4252
4253 #define BCOND_IM 0
4254 #define BCOND_LR 1
4255 #define BCOND_CTR 2
4256 #define BCOND_TAR 3
4257
4258 static inline void gen_bcond(DisasContext *ctx, int type)
4259 {
4260 uint32_t bo = BO(ctx->opcode);
4261 TCGLabel *l1;
4262 TCGv target;
4263
4264 ctx->exception = POWERPC_EXCP_BRANCH;
4265 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
4266 target = tcg_temp_local_new();
4267 if (type == BCOND_CTR)
4268 tcg_gen_mov_tl(target, cpu_ctr);
4269 else if (type == BCOND_TAR)
4270 gen_load_spr(target, SPR_TAR);
4271 else
4272 tcg_gen_mov_tl(target, cpu_lr);
4273 } else {
4274 TCGV_UNUSED(target);
4275 }
4276 if (LK(ctx->opcode))
4277 gen_setlr(ctx, ctx->nip);
4278 l1 = gen_new_label();
4279 if ((bo & 0x4) == 0) {
4280 /* Decrement and test CTR */
4281 TCGv temp = tcg_temp_new();
4282 if (unlikely(type == BCOND_CTR)) {
4283 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4284 return;
4285 }
4286 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
4287 if (NARROW_MODE(ctx)) {
4288 tcg_gen_ext32u_tl(temp, cpu_ctr);
4289 } else {
4290 tcg_gen_mov_tl(temp, cpu_ctr);
4291 }
4292 if (bo & 0x2) {
4293 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
4294 } else {
4295 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
4296 }
4297 tcg_temp_free(temp);
4298 }
4299 if ((bo & 0x10) == 0) {
4300 /* Test CR */
4301 uint32_t bi = BI(ctx->opcode);
4302 uint32_t mask = 0x08 >> (bi & 0x03);
4303 TCGv_i32 temp = tcg_temp_new_i32();
4304
4305 if (bo & 0x8) {
4306 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4307 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
4308 } else {
4309 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4310 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
4311 }
4312 tcg_temp_free_i32(temp);
4313 }
4314 gen_update_cfar(ctx, ctx->nip);
4315 if (type == BCOND_IM) {
4316 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
4317 if (likely(AA(ctx->opcode) == 0)) {
4318 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
4319 } else {
4320 gen_goto_tb(ctx, 0, li);
4321 }
4322 gen_set_label(l1);
4323 gen_goto_tb(ctx, 1, ctx->nip);
4324 } else {
4325 if (NARROW_MODE(ctx)) {
4326 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
4327 } else {
4328 tcg_gen_andi_tl(cpu_nip, target, ~3);
4329 }
4330 tcg_gen_exit_tb(0);
4331 gen_set_label(l1);
4332 gen_update_nip(ctx, ctx->nip);
4333 tcg_gen_exit_tb(0);
4334 }
4335 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
4336 tcg_temp_free(target);
4337 }
4338 }
4339
4340 static void gen_bc(DisasContext *ctx)
4341 {
4342 gen_bcond(ctx, BCOND_IM);
4343 }
4344
4345 static void gen_bcctr(DisasContext *ctx)
4346 {
4347 gen_bcond(ctx, BCOND_CTR);
4348 }
4349
4350 static void gen_bclr(DisasContext *ctx)
4351 {
4352 gen_bcond(ctx, BCOND_LR);
4353 }
4354
4355 static void gen_bctar(DisasContext *ctx)
4356 {
4357 gen_bcond(ctx, BCOND_TAR);
4358 }
4359
4360 /*** Condition register logical ***/
4361 #define GEN_CRLOGIC(name, tcg_op, opc) \
4362 static void glue(gen_, name)(DisasContext *ctx) \
4363 { \
4364 uint8_t bitmask; \
4365 int sh; \
4366 TCGv_i32 t0, t1; \
4367 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4368 t0 = tcg_temp_new_i32(); \
4369 if (sh > 0) \
4370 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4371 else if (sh < 0) \
4372 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4373 else \
4374 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4375 t1 = tcg_temp_new_i32(); \
4376 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4377 if (sh > 0) \
4378 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4379 else if (sh < 0) \
4380 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4381 else \
4382 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4383 tcg_op(t0, t0, t1); \
4384 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4385 tcg_gen_andi_i32(t0, t0, bitmask); \
4386 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4387 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4388 tcg_temp_free_i32(t0); \
4389 tcg_temp_free_i32(t1); \
4390 }
4391
4392 /* crand */
4393 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4394 /* crandc */
4395 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4396 /* creqv */
4397 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4398 /* crnand */
4399 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4400 /* crnor */
4401 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4402 /* cror */
4403 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4404 /* crorc */
4405 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4406 /* crxor */
4407 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4408
4409 /* mcrf */
4410 static void gen_mcrf(DisasContext *ctx)
4411 {
4412 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4413 }
4414
4415 /*** System linkage ***/
4416
4417 /* rfi (supervisor only) */
4418 static void gen_rfi(DisasContext *ctx)
4419 {
4420 #if defined(CONFIG_USER_ONLY)
4421 GEN_PRIV;
4422 #else
4423 /* FIXME: This instruction doesn't exist anymore on 64-bit server
4424 * processors compliant with arch 2.x, we should remove it there,
4425 * but we need to fix OpenBIOS not to use it on 970 first
4426 */
4427 /* Restore CPU state */
4428 CHK_SV;
4429 gen_update_cfar(ctx, ctx->nip);
4430 gen_helper_rfi(cpu_env);
4431 gen_sync_exception(ctx);
4432 #endif
4433 }
4434
4435 #if defined(TARGET_PPC64)
4436 static void gen_rfid(DisasContext *ctx)
4437 {
4438 #if defined(CONFIG_USER_ONLY)
4439 GEN_PRIV;
4440 #else
4441 /* Restore CPU state */
4442 CHK_SV;
4443 gen_update_cfar(ctx, ctx->nip);
4444 gen_helper_rfid(cpu_env);
4445 gen_sync_exception(ctx);
4446 #endif
4447 }
4448
4449 static void gen_hrfid(DisasContext *ctx)
4450 {
4451 #if defined(CONFIG_USER_ONLY)
4452 GEN_PRIV;
4453 #else
4454 /* Restore CPU state */
4455 CHK_HV;
4456 gen_helper_hrfid(cpu_env);
4457 gen_sync_exception(ctx);
4458 #endif
4459 }
4460 #endif
4461
4462 /* sc */
4463 #if defined(CONFIG_USER_ONLY)
4464 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4465 #else
4466 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4467 #endif
4468 static void gen_sc(DisasContext *ctx)
4469 {
4470 uint32_t lev;
4471
4472 lev = (ctx->opcode >> 5) & 0x7F;
4473 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4474 }
4475
4476 /*** Trap ***/
4477
4478 /* tw */
4479 static void gen_tw(DisasContext *ctx)
4480 {
4481 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4482 /* Update the nip since this might generate a trap exception */
4483 gen_update_nip(ctx, ctx->nip);
4484 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4485 t0);
4486 tcg_temp_free_i32(t0);
4487 }
4488
4489 /* twi */
4490 static void gen_twi(DisasContext *ctx)
4491 {
4492 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4493 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4494 /* Update the nip since this might generate a trap exception */
4495 gen_update_nip(ctx, ctx->nip);
4496 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4497 tcg_temp_free(t0);
4498 tcg_temp_free_i32(t1);
4499 }
4500
4501 #if defined(TARGET_PPC64)
4502 /* td */
4503 static void gen_td(DisasContext *ctx)
4504 {
4505 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4506 /* Update the nip since this might generate a trap exception */
4507 gen_update_nip(ctx, ctx->nip);
4508 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4509 t0);
4510 tcg_temp_free_i32(t0);
4511 }
4512
4513 /* tdi */
4514 static void gen_tdi(DisasContext *ctx)
4515 {
4516 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4517 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4518 /* Update the nip since this might generate a trap exception */
4519 gen_update_nip(ctx, ctx->nip);
4520 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4521 tcg_temp_free(t0);
4522 tcg_temp_free_i32(t1);
4523 }
4524 #endif
4525
4526 /*** Processor control ***/
4527
4528 static void gen_read_xer(TCGv dst)
4529 {
4530 TCGv t0 = tcg_temp_new();
4531 TCGv t1 = tcg_temp_new();
4532 TCGv t2 = tcg_temp_new();
4533 tcg_gen_mov_tl(dst, cpu_xer);
4534 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4535 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4536 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4537 tcg_gen_or_tl(t0, t0, t1);
4538 tcg_gen_or_tl(dst, dst, t2);
4539 tcg_gen_or_tl(dst, dst, t0);
4540 tcg_temp_free(t0);
4541 tcg_temp_free(t1);
4542 tcg_temp_free(t2);
4543 }
4544
4545 static void gen_write_xer(TCGv src)
4546 {
4547 tcg_gen_andi_tl(cpu_xer, src,
4548 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4549 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4550 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4551 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4552 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4553 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4554 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4555 }
4556
4557 /* mcrxr */
4558 static void gen_mcrxr(DisasContext *ctx)
4559 {
4560 TCGv_i32 t0 = tcg_temp_new_i32();
4561 TCGv_i32 t1 = tcg_temp_new_i32();
4562 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4563
4564 tcg_gen_trunc_tl_i32(t0, cpu_so);
4565 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4566 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4567 tcg_gen_shli_i32(t0, t0, 3);
4568 tcg_gen_shli_i32(t1, t1, 2);
4569 tcg_gen_shli_i32(dst, dst, 1);
4570 tcg_gen_or_i32(dst, dst, t0);
4571 tcg_gen_or_i32(dst, dst, t1);
4572 tcg_temp_free_i32(t0);
4573 tcg_temp_free_i32(t1);
4574
4575 tcg_gen_movi_tl(cpu_so, 0);
4576 tcg_gen_movi_tl(cpu_ov, 0);
4577 tcg_gen_movi_tl(cpu_ca, 0);
4578 }
4579
4580 /* mfcr mfocrf */
4581 static void gen_mfcr(DisasContext *ctx)
4582 {
4583 uint32_t crm, crn;
4584
4585 if (likely(ctx->opcode & 0x00100000)) {
4586 crm = CRM(ctx->opcode);
4587 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4588 crn = ctz32 (crm);
4589 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4590 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4591 cpu_gpr[rD(ctx->opcode)], crn * 4);
4592 }
4593 } else {
4594 TCGv_i32 t0 = tcg_temp_new_i32();
4595 tcg_gen_mov_i32(t0, cpu_crf[0]);
4596 tcg_gen_shli_i32(t0, t0, 4);
4597 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4598 tcg_gen_shli_i32(t0, t0, 4);
4599 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4600 tcg_gen_shli_i32(t0, t0, 4);
4601 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4602 tcg_gen_shli_i32(t0, t0, 4);
4603 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4604 tcg_gen_shli_i32(t0, t0, 4);
4605 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4606 tcg_gen_shli_i32(t0, t0, 4);
4607 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4608 tcg_gen_shli_i32(t0, t0, 4);
4609 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4610 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4611 tcg_temp_free_i32(t0);
4612 }
4613 }
4614
4615 /* mfmsr */
4616 static void gen_mfmsr(DisasContext *ctx)
4617 {
4618 CHK_SV;
4619 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4620 }
4621
4622 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4623 {
4624 #if 0
4625 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4626 printf("ERROR: try to access SPR %d !\n", sprn);
4627 #endif
4628 }
4629 #define SPR_NOACCESS (&spr_noaccess)
4630
4631 /* mfspr */
4632 static inline void gen_op_mfspr(DisasContext *ctx)
4633 {
4634 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4635 uint32_t sprn = SPR(ctx->opcode);
4636
4637 #if defined(CONFIG_USER_ONLY)
4638 read_cb = ctx->spr_cb[sprn].uea_read;
4639 #else
4640 if (ctx->pr) {
4641 read_cb = ctx->spr_cb[sprn].uea_read;
4642 } else if (ctx->hv) {
4643 read_cb = ctx->spr_cb[sprn].hea_read;
4644 } else {
4645 read_cb = ctx->spr_cb[sprn].oea_read;
4646 }
4647 #endif
4648 if (likely(read_cb != NULL)) {
4649 if (likely(read_cb != SPR_NOACCESS)) {
4650 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4651 } else {
4652 /* Privilege exception */
4653 /* This is a hack to avoid warnings when running Linux:
4654 * this OS breaks the PowerPC virtualisation model,
4655 * allowing userland application to read the PVR
4656 */
4657 if (sprn != SPR_PVR) {
4658 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4659 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4660 if (qemu_log_separate()) {
4661 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4662 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4663 }
4664 }
4665 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4666 }
4667 } else {
4668 /* ISA 2.07 defines these as no-ops */
4669 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4670 (sprn >= 808 && sprn <= 811)) {
4671 /* This is a nop */
4672 return;
4673 }
4674 /* Not defined */
4675 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4676 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4677 if (qemu_log_separate()) {
4678 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4679 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4680 }
4681
4682 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4683 * it can generate a priv, a hv emu or a no-op
4684 */
4685 if (sprn & 0x10) {
4686 if (ctx->pr) {
4687 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4688 }
4689 } else {
4690 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
4691 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4692 }
4693 }
4694 }
4695 }
4696
4697 static void gen_mfspr(DisasContext *ctx)
4698 {
4699 gen_op_mfspr(ctx);
4700 }
4701
4702 /* mftb */
4703 static void gen_mftb(DisasContext *ctx)
4704 {
4705 gen_op_mfspr(ctx);
4706 }
4707
4708 /* mtcrf mtocrf*/
4709 static void gen_mtcrf(DisasContext *ctx)
4710 {
4711 uint32_t crm, crn;
4712
4713 crm = CRM(ctx->opcode);
4714 if (likely((ctx->opcode & 0x00100000))) {
4715 if (crm && ((crm & (crm - 1)) == 0)) {
4716 TCGv_i32 temp = tcg_temp_new_i32();
4717 crn = ctz32 (crm);
4718 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4719 tcg_gen_shri_i32(temp, temp, crn * 4);
4720 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4721 tcg_temp_free_i32(temp);
4722 }
4723 } else {
4724 TCGv_i32 temp = tcg_temp_new_i32();
4725 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4726 for (crn = 0 ; crn < 8 ; crn++) {
4727 if (crm & (1 << crn)) {
4728 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4729 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4730 }
4731 }
4732 tcg_temp_free_i32(temp);
4733 }
4734 }
4735
4736 /* mtmsr */
4737 #if defined(TARGET_PPC64)
4738 static void gen_mtmsrd(DisasContext *ctx)
4739 {
4740 CHK_SV;
4741
4742 #if !defined(CONFIG_USER_ONLY)
4743 if (ctx->opcode & 0x00010000) {
4744 /* Special form that does not need any synchronisation */
4745 TCGv t0 = tcg_temp_new();
4746 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4747 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4748 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4749 tcg_temp_free(t0);
4750 } else {
4751 /* XXX: we need to update nip before the store
4752 * if we enter power saving mode, we will exit the loop
4753 * directly from ppc_store_msr
4754 */
4755 gen_update_nip(ctx, ctx->nip);
4756 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4757 /* Must stop the translation as machine state (may have) changed */
4758 /* Note that mtmsr is not always defined as context-synchronizing */
4759 gen_stop_exception(ctx);
4760 }
4761 #endif /* !defined(CONFIG_USER_ONLY) */
4762 }
4763 #endif /* defined(TARGET_PPC64) */
4764
4765 static void gen_mtmsr(DisasContext *ctx)
4766 {
4767 CHK_SV;
4768
4769 #if !defined(CONFIG_USER_ONLY)
4770 if (ctx->opcode & 0x00010000) {
4771 /* Special form that does not need any synchronisation */
4772 TCGv t0 = tcg_temp_new();
4773 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4774 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4775 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4776 tcg_temp_free(t0);
4777 } else {
4778 TCGv msr = tcg_temp_new();
4779
4780 /* XXX: we need to update nip before the store
4781 * if we enter power saving mode, we will exit the loop
4782 * directly from ppc_store_msr
4783 */
4784 gen_update_nip(ctx, ctx->nip);
4785 #if defined(TARGET_PPC64)
4786 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4787 #else
4788 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4789 #endif
4790 gen_helper_store_msr(cpu_env, msr);
4791 tcg_temp_free(msr);
4792 /* Must stop the translation as machine state (may have) changed */
4793 /* Note that mtmsr is not always defined as context-synchronizing */
4794 gen_stop_exception(ctx);
4795 }
4796 #endif
4797 }
4798
4799 /* mtspr */
4800 static void gen_mtspr(DisasContext *ctx)
4801 {
4802 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4803 uint32_t sprn = SPR(ctx->opcode);
4804
4805 #if defined(CONFIG_USER_ONLY)
4806 write_cb = ctx->spr_cb[sprn].uea_write;
4807 #else
4808 if (ctx->pr) {
4809 write_cb = ctx->spr_cb[sprn].uea_write;
4810 } else if (ctx->hv) {
4811 write_cb = ctx->spr_cb[sprn].hea_write;
4812 } else {
4813 write_cb = ctx->spr_cb[sprn].oea_write;
4814 }
4815 #endif
4816 if (likely(write_cb != NULL)) {
4817 if (likely(write_cb != SPR_NOACCESS)) {
4818 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4819 } else {
4820 /* Privilege exception */
4821 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4822 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4823 if (qemu_log_separate()) {
4824 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4825 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4826 }
4827 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4828 }
4829 } else {
4830 /* ISA 2.07 defines these as no-ops */
4831 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4832 (sprn >= 808 && sprn <= 811)) {
4833 /* This is a nop */
4834 return;
4835 }
4836
4837 /* Not defined */
4838 if (qemu_log_separate()) {
4839 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4840 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4841 }
4842 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4843 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4844
4845
4846 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4847 * it can generate a priv, a hv emu or a no-op
4848 */
4849 if (sprn & 0x10) {
4850 if (ctx->pr) {
4851 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4852 }
4853 } else {
4854 if (ctx->pr || sprn == 0) {
4855 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4856 }
4857 }
4858 }
4859 }
4860
4861 /*** Cache management ***/
4862
4863 /* dcbf */
4864 static void gen_dcbf(DisasContext *ctx)
4865 {
4866 /* XXX: specification says this is treated as a load by the MMU */
4867 TCGv t0;
4868 gen_set_access_type(ctx, ACCESS_CACHE);
4869 t0 = tcg_temp_new();
4870 gen_addr_reg_index(ctx, t0);
4871 gen_qemu_ld8u(ctx, t0, t0);
4872 tcg_temp_free(t0);
4873 }
4874
4875 /* dcbi (Supervisor only) */
4876 static void gen_dcbi(DisasContext *ctx)
4877 {
4878 #if defined(CONFIG_USER_ONLY)
4879 GEN_PRIV;
4880 #else
4881 TCGv EA, val;
4882
4883 CHK_SV;
4884 EA = tcg_temp_new();
4885 gen_set_access_type(ctx, ACCESS_CACHE);
4886 gen_addr_reg_index(ctx, EA);
4887 val = tcg_temp_new();
4888 /* XXX: specification says this should be treated as a store by the MMU */
4889 gen_qemu_ld8u(ctx, val, EA);
4890 gen_qemu_st8(ctx, val, EA);
4891 tcg_temp_free(val);
4892 tcg_temp_free(EA);
4893 #endif /* defined(CONFIG_USER_ONLY) */
4894 }
4895
4896 /* dcdst */
4897 static void gen_dcbst(DisasContext *ctx)
4898 {
4899 /* XXX: specification say this is treated as a load by the MMU */
4900 TCGv t0;
4901 gen_set_access_type(ctx, ACCESS_CACHE);
4902 t0 = tcg_temp_new();
4903 gen_addr_reg_index(ctx, t0);
4904 gen_qemu_ld8u(ctx, t0, t0);
4905 tcg_temp_free(t0);
4906 }
4907
4908 /* dcbt */
4909 static void gen_dcbt(DisasContext *ctx)
4910 {
4911 /* interpreted as no-op */
4912 /* XXX: specification say this is treated as a load by the MMU
4913 * but does not generate any exception
4914 */
4915 }
4916
4917 /* dcbtst */
4918 static void gen_dcbtst(DisasContext *ctx)
4919 {
4920 /* interpreted as no-op */
4921 /* XXX: specification say this is treated as a load by the MMU
4922 * but does not generate any exception
4923 */
4924 }
4925
4926 /* dcbtls */
4927 static void gen_dcbtls(DisasContext *ctx)
4928 {
4929 /* Always fails locking the cache */
4930 TCGv t0 = tcg_temp_new();
4931 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4932 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4933 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4934 tcg_temp_free(t0);
4935 }
4936
4937 /* dcbz */
4938 static void gen_dcbz(DisasContext *ctx)
4939 {
4940 TCGv tcgv_addr;
4941 TCGv_i32 tcgv_is_dcbzl;
4942 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4943
4944 gen_set_access_type(ctx, ACCESS_CACHE);
4945 /* NIP cannot be restored if the memory exception comes from an helper */
4946 gen_update_nip(ctx, ctx->nip - 4);
4947 tcgv_addr = tcg_temp_new();
4948 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4949
4950 gen_addr_reg_index(ctx, tcgv_addr);
4951 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4952
4953 tcg_temp_free(tcgv_addr);
4954 tcg_temp_free_i32(tcgv_is_dcbzl);
4955 }
4956
4957 /* dst / dstt */
4958 static void gen_dst(DisasContext *ctx)
4959 {
4960 if (rA(ctx->opcode) == 0) {
4961 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4962 } else {
4963 /* interpreted as no-op */
4964 }
4965 }
4966
4967 /* dstst /dststt */
4968 static void gen_dstst(DisasContext *ctx)
4969 {
4970 if (rA(ctx->opcode) == 0) {
4971 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4972 } else {
4973 /* interpreted as no-op */
4974 }
4975
4976 }
4977
4978 /* dss / dssall */
4979 static void gen_dss(DisasContext *ctx)
4980 {
4981 /* interpreted as no-op */
4982 }
4983
4984 /* icbi */
4985 static void gen_icbi(DisasContext *ctx)
4986 {
4987 TCGv t0;
4988 gen_set_access_type(ctx, ACCESS_CACHE);
4989 /* NIP cannot be restored if the memory exception comes from an helper */
4990 gen_update_nip(ctx, ctx->nip - 4);
4991 t0 = tcg_temp_new();
4992 gen_addr_reg_index(ctx, t0);
4993 gen_helper_icbi(cpu_env, t0);
4994 tcg_temp_free(t0);
4995 }
4996
4997 /* Optional: */
4998 /* dcba */
4999 static void gen_dcba(DisasContext *ctx)
5000 {
5001 /* interpreted as no-op */
5002 /* XXX: specification say this is treated as a store by the MMU
5003 * but does not generate any exception
5004 */
5005 }
5006
5007 /*** Segment register manipulation ***/
5008 /* Supervisor only: */
5009
5010 /* mfsr */
5011 static void gen_mfsr(DisasContext *ctx)
5012 {
5013 #if defined(CONFIG_USER_ONLY)
5014 GEN_PRIV;
5015 #else
5016 TCGv t0;
5017
5018 CHK_SV;
5019 t0 = tcg_const_tl(SR(ctx->opcode));
5020 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5021 tcg_temp_free(t0);
5022 #endif /* defined(CONFIG_USER_ONLY) */
5023 }
5024
5025 /* mfsrin */
5026 static void gen_mfsrin(DisasContext *ctx)
5027 {
5028 #if defined(CONFIG_USER_ONLY)
5029 GEN_PRIV;
5030 #else
5031 TCGv t0;
5032
5033 CHK_SV;
5034 t0 = tcg_temp_new();
5035 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
5036 tcg_gen_andi_tl(t0, t0, 0xF);
5037 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5038 tcg_temp_free(t0);
5039 #endif /* defined(CONFIG_USER_ONLY) */
5040 }
5041
5042 /* mtsr */
5043 static void gen_mtsr(DisasContext *ctx)
5044 {
5045 #if defined(CONFIG_USER_ONLY)
5046 GEN_PRIV;
5047 #else
5048 TCGv t0;
5049
5050 CHK_SV;
5051 t0 = tcg_const_tl(SR(ctx->opcode));
5052 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5053 tcg_temp_free(t0);
5054 #endif /* defined(CONFIG_USER_ONLY) */
5055 }
5056
5057 /* mtsrin */
5058 static void gen_mtsrin(DisasContext *ctx)
5059 {
5060 #if defined(CONFIG_USER_ONLY)
5061 GEN_PRIV;
5062 #else
5063 TCGv t0;
5064 CHK_SV;
5065
5066 t0 = tcg_temp_new();
5067 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
5068 tcg_gen_andi_tl(t0, t0, 0xF);
5069 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
5070 tcg_temp_free(t0);
5071 #endif /* defined(CONFIG_USER_ONLY) */
5072 }
5073
5074 #if defined(TARGET_PPC64)
5075 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
5076
5077 /* mfsr */
5078 static void gen_mfsr_64b(DisasContext *ctx)
5079 {
5080 #if defined(CONFIG_USER_ONLY)
5081 GEN_PRIV;
5082 #else
5083 TCGv t0;
5084
5085 CHK_SV;
5086 t0 = tcg_const_tl(SR(ctx->opcode));
5087 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5088 tcg_temp_free(t0);
5089 #endif /* defined(CONFIG_USER_ONLY) */
5090 }
5091
5092 /* mfsrin */
5093 static void gen_mfsrin_64b(DisasContext *ctx)
5094 {
5095 #if defined(CONFIG_USER_ONLY)
5096 GEN_PRIV;
5097 #else
5098 TCGv t0;
5099
5100 CHK_SV;
5101 t0 = tcg_temp_new();
5102 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
5103 tcg_gen_andi_tl(t0, t0, 0xF);
5104 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5105 tcg_temp_free(t0);
5106 #endif /* defined(CONFIG_USER_ONLY) */
5107 }
5108
5109 /* mtsr */
5110 static void gen_mtsr_64b(DisasContext *ctx)
5111 {
5112 #if defined(CONFIG_USER_ONLY)
5113 GEN_PRIV;
5114 #else
5115 TCGv t0;
5116
5117 CHK_SV;
5118 t0 = tcg_const_tl(SR(ctx->opcode));
5119 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5120 tcg_temp_free(t0);
5121 #endif /* defined(CONFIG_USER_ONLY) */
5122 }
5123
5124 /* mtsrin */
5125 static void gen_mtsrin_64b(DisasContext *ctx)
5126 {
5127 #if defined(CONFIG_USER_ONLY)
5128 GEN_PRIV;
5129 #else
5130 TCGv t0;
5131
5132 CHK_SV;
5133 t0 = tcg_temp_new();
5134 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
5135 tcg_gen_andi_tl(t0, t0, 0xF);
5136 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5137 tcg_temp_free(t0);
5138 #endif /* defined(CONFIG_USER_ONLY) */
5139 }
5140
5141 /* slbmte */
5142 static void gen_slbmte(DisasContext *ctx)
5143 {
5144 #if defined(CONFIG_USER_ONLY)
5145 GEN_PRIV;
5146 #else
5147 CHK_SV;
5148
5149 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
5150 cpu_gpr[rS(ctx->opcode)]);
5151 #endif /* defined(CONFIG_USER_ONLY) */
5152 }
5153
5154 static void gen_slbmfee(DisasContext *ctx)
5155 {
5156 #if defined(CONFIG_USER_ONLY)
5157 GEN_PRIV;
5158 #else
5159 CHK_SV;
5160
5161 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5162 cpu_gpr[rB(ctx->opcode)]);
5163 #endif /* defined(CONFIG_USER_ONLY) */
5164 }
5165
5166 static void gen_slbmfev(DisasContext *ctx)
5167 {
5168 #if defined(CONFIG_USER_ONLY)
5169 GEN_PRIV;
5170 #else
5171 CHK_SV;
5172
5173 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5174 cpu_gpr[rB(ctx->opcode)]);
5175 #endif /* defined(CONFIG_USER_ONLY) */
5176 }
5177
5178 static void gen_slbfee_(DisasContext *ctx)
5179 {
5180 #if defined(CONFIG_USER_ONLY)
5181 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5182 #else
5183 TCGLabel *l1, *l2;
5184
5185 if (unlikely(ctx->pr)) {
5186 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5187 return;
5188 }
5189 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5190 cpu_gpr[rB(ctx->opcode)]);
5191 l1 = gen_new_label();
5192 l2 = gen_new_label();
5193 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5194 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
5195 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
5196 tcg_gen_br(l2);
5197 gen_set_label(l1);
5198 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
5199 gen_set_label(l2);
5200 #endif
5201 }
5202 #endif /* defined(TARGET_PPC64) */
5203
5204 /*** Lookaside buffer management ***/
5205 /* Optional & supervisor only: */
5206
5207 /* tlbia */
5208 static void gen_tlbia(DisasContext *ctx)
5209 {
5210 #if defined(CONFIG_USER_ONLY)
5211 GEN_PRIV;
5212 #else
5213 CHK_HV;
5214
5215 gen_helper_tlbia(cpu_env);
5216 #endif /* defined(CONFIG_USER_ONLY) */
5217 }
5218
5219 /* tlbiel */
5220 static void gen_tlbiel(DisasContext *ctx)
5221 {
5222 #if defined(CONFIG_USER_ONLY)
5223 GEN_PRIV;
5224 #else
5225 CHK_SV;
5226
5227 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5228 #endif /* defined(CONFIG_USER_ONLY) */
5229 }
5230
5231 /* tlbie */
5232 static void gen_tlbie(DisasContext *ctx)
5233 {
5234 #if defined(CONFIG_USER_ONLY)
5235 GEN_PRIV;
5236 #else
5237 CHK_HV;
5238
5239 if (NARROW_MODE(ctx)) {
5240 TCGv t0 = tcg_temp_new();
5241 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
5242 gen_helper_tlbie(cpu_env, t0);
5243 tcg_temp_free(t0);
5244 } else {
5245 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5246 }
5247 #endif /* defined(CONFIG_USER_ONLY) */
5248 }
5249
5250 /* tlbsync */
5251 static void gen_tlbsync(DisasContext *ctx)
5252 {
5253 #if defined(CONFIG_USER_ONLY)
5254 GEN_PRIV;
5255 #else
5256 CHK_HV;
5257
5258 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
5259 * embedded however needs to deal with tlbsync. We don't try to be
5260 * fancy and swallow the overhead of checking for both.
5261 */
5262 gen_check_tlb_flush(ctx);
5263 #endif /* defined(CONFIG_USER_ONLY) */
5264 }
5265
5266 #if defined(TARGET_PPC64)
5267 /* slbia */
5268 static void gen_slbia(DisasContext *ctx)
5269 {
5270 #if defined(CONFIG_USER_ONLY)
5271 GEN_PRIV;
5272 #else
5273 CHK_SV;
5274
5275 gen_helper_slbia(cpu_env);
5276 #endif /* defined(CONFIG_USER_ONLY) */
5277 }
5278
5279 /* slbie */
5280 static void gen_slbie(DisasContext *ctx)
5281 {
5282 #if defined(CONFIG_USER_ONLY)
5283 GEN_PRIV;
5284 #else
5285 CHK_SV;
5286
5287 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5288 #endif /* defined(CONFIG_USER_ONLY) */
5289 }
5290 #endif /* defined(TARGET_PPC64) */
5291
5292 /*** External control ***/
5293 /* Optional: */
5294
5295 /* eciwx */
5296 static void gen_eciwx(DisasContext *ctx)
5297 {
5298 TCGv t0;
5299 /* Should check EAR[E] ! */
5300 gen_set_access_type(ctx, ACCESS_EXT);
5301 t0 = tcg_temp_new();
5302 gen_addr_reg_index(ctx, t0);
5303 gen_check_align(ctx, t0, 0x03);
5304 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
5305 tcg_temp_free(t0);
5306 }
5307
5308 /* ecowx */
5309 static void gen_ecowx(DisasContext *ctx)
5310 {
5311 TCGv t0;
5312 /* Should check EAR[E] ! */
5313 gen_set_access_type(ctx, ACCESS_EXT);
5314 t0 = tcg_temp_new();
5315 gen_addr_reg_index(ctx, t0);
5316 gen_check_align(ctx, t0, 0x03);
5317 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
5318 tcg_temp_free(t0);
5319 }
5320
5321 /* PowerPC 601 specific instructions */
5322
5323 /* abs - abs. */
5324 static void gen_abs(DisasContext *ctx)
5325 {
5326 TCGLabel *l1 = gen_new_label();
5327 TCGLabel *l2 = gen_new_label();
5328 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
5329 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5330 tcg_gen_br(l2);
5331 gen_set_label(l1);
5332 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5333 gen_set_label(l2);
5334 if (unlikely(Rc(ctx->opcode) != 0))
5335 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5336 }
5337
5338 /* abso - abso. */
5339 static void gen_abso(DisasContext *ctx)
5340 {
5341 TCGLabel *l1 = gen_new_label();
5342 TCGLabel *l2 = gen_new_label();
5343 TCGLabel *l3 = gen_new_label();
5344 /* Start with XER OV disabled, the most likely case */
5345 tcg_gen_movi_tl(cpu_ov, 0);
5346 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
5347 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
5348 tcg_gen_movi_tl(cpu_ov, 1);
5349 tcg_gen_movi_tl(cpu_so, 1);
5350 tcg_gen_br(l2);
5351 gen_set_label(l1);
5352 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5353 tcg_gen_br(l3);
5354 gen_set_label(l2);
5355 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5356 gen_set_label(l3);
5357 if (unlikely(Rc(ctx->opcode) != 0))
5358 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5359 }
5360
5361 /* clcs */
5362 static void gen_clcs(DisasContext *ctx)
5363 {
5364 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
5365 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5366 tcg_temp_free_i32(t0);
5367 /* Rc=1 sets CR0 to an undefined state */
5368 }
5369
5370 /* div - div. */
5371 static void gen_div(DisasContext *ctx)
5372 {
5373 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5374 cpu_gpr[rB(ctx->opcode)]);
5375 if (unlikely(Rc(ctx->opcode) != 0))
5376 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5377 }
5378
5379 /* divo - divo. */
5380 static void gen_divo(DisasContext *ctx)
5381 {
5382 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5383 cpu_gpr[rB(ctx->opcode)]);
5384 if (unlikely(Rc(ctx->opcode) != 0))
5385 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5386 }
5387
5388 /* divs - divs. */
5389 static void gen_divs(DisasContext *ctx)
5390 {
5391 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5392 cpu_gpr[rB(ctx->opcode)]);
5393 if (unlikely(Rc(ctx->opcode) != 0))
5394 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5395 }
5396
5397 /* divso - divso. */
5398 static void gen_divso(DisasContext *ctx)
5399 {
5400 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5401 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5402 if (unlikely(Rc(ctx->opcode) != 0))
5403 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5404 }
5405
5406 /* doz - doz. */
5407 static void gen_doz(DisasContext *ctx)
5408 {
5409 TCGLabel *l1 = gen_new_label();
5410 TCGLabel *l2 = gen_new_label();
5411 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5412 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5413 tcg_gen_br(l2);
5414 gen_set_label(l1);
5415 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5416 gen_set_label(l2);
5417 if (unlikely(Rc(ctx->opcode) != 0))
5418 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5419 }
5420
5421 /* dozo - dozo. */
5422 static void gen_dozo(DisasContext *ctx)
5423 {
5424 TCGLabel *l1 = gen_new_label();
5425 TCGLabel *l2 = gen_new_label();
5426 TCGv t0 = tcg_temp_new();
5427 TCGv t1 = tcg_temp_new();
5428 TCGv t2 = tcg_temp_new();
5429 /* Start with XER OV disabled, the most likely case */
5430 tcg_gen_movi_tl(cpu_ov, 0);
5431 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5432 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5433 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5434 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5435 tcg_gen_andc_tl(t1, t1, t2);
5436 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5437 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5438 tcg_gen_movi_tl(cpu_ov, 1);
5439 tcg_gen_movi_tl(cpu_so, 1);
5440 tcg_gen_br(l2);
5441 gen_set_label(l1);
5442 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5443 gen_set_label(l2);
5444 tcg_temp_free(t0);
5445 tcg_temp_free(t1);
5446 tcg_temp_free(t2);
5447 if (unlikely(Rc(ctx->opcode) != 0))
5448 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5449 }
5450
5451 /* dozi */
5452 static void gen_dozi(DisasContext *ctx)
5453 {
5454 target_long simm = SIMM(ctx->opcode);
5455 TCGLabel *l1 = gen_new_label();
5456 TCGLabel *l2 = gen_new_label();
5457 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5458 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5459 tcg_gen_br(l2);
5460 gen_set_label(l1);
5461 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5462 gen_set_label(l2);
5463 if (unlikely(Rc(ctx->opcode) != 0))
5464 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5465 }
5466
5467 /* lscbx - lscbx. */
5468 static void gen_lscbx(DisasContext *ctx)
5469 {
5470 TCGv t0 = tcg_temp_new();
5471 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5472 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5473 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5474
5475 gen_addr_reg_index(ctx, t0);
5476 /* NIP cannot be restored if the memory exception comes from an helper */
5477 gen_update_nip(ctx, ctx->nip - 4);
5478 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5479 tcg_temp_free_i32(t1);
5480 tcg_temp_free_i32(t2);
5481 tcg_temp_free_i32(t3);
5482 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5483 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5484 if (unlikely(Rc(ctx->opcode) != 0))
5485 gen_set_Rc0(ctx, t0);
5486 tcg_temp_free(t0);
5487 }
5488
5489 /* maskg - maskg. */
5490 static void gen_maskg(DisasContext *ctx)
5491 {
5492 TCGLabel *l1 = gen_new_label();
5493 TCGv t0 = tcg_temp_new();
5494 TCGv t1 = tcg_temp_new();
5495 TCGv t2 = tcg_temp_new();
5496 TCGv t3 = tcg_temp_new();
5497 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5498 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5499 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5500 tcg_gen_addi_tl(t2, t0, 1);
5501 tcg_gen_shr_tl(t2, t3, t2);
5502 tcg_gen_shr_tl(t3, t3, t1);
5503 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5504 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5505 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5506 gen_set_label(l1);
5507 tcg_temp_free(t0);
5508 tcg_temp_free(t1);
5509 tcg_temp_free(t2);
5510 tcg_temp_free(t3);
5511 if (unlikely(Rc(ctx->opcode) != 0))
5512 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5513 }
5514
5515 /* maskir - maskir. */
5516 static void gen_maskir(DisasContext *ctx)
5517 {
5518 TCGv t0 = tcg_temp_new();
5519 TCGv t1 = tcg_temp_new();
5520 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5521 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5522 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5523 tcg_temp_free(t0);
5524 tcg_temp_free(t1);
5525 if (unlikely(Rc(ctx->opcode) != 0))
5526 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5527 }
5528
5529 /* mul - mul. */
5530 static void gen_mul(DisasContext *ctx)
5531 {
5532 TCGv_i64 t0 = tcg_temp_new_i64();
5533 TCGv_i64 t1 = tcg_temp_new_i64();
5534 TCGv t2 = tcg_temp_new();
5535 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5536 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5537 tcg_gen_mul_i64(t0, t0, t1);
5538 tcg_gen_trunc_i64_tl(t2, t0);
5539 gen_store_spr(SPR_MQ, t2);
5540 tcg_gen_shri_i64(t1, t0, 32);
5541 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5542 tcg_temp_free_i64(t0);
5543 tcg_temp_free_i64(t1);
5544 tcg_temp_free(t2);
5545 if (unlikely(Rc(ctx->opcode) != 0))
5546 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5547 }
5548
5549 /* mulo - mulo. */
5550 static void gen_mulo(DisasContext *ctx)
5551 {
5552 TCGLabel *l1 = gen_new_label();
5553 TCGv_i64 t0 = tcg_temp_new_i64();
5554 TCGv_i64 t1 = tcg_temp_new_i64();
5555 TCGv t2 = tcg_temp_new();
5556 /* Start with XER OV disabled, the most likely case */
5557 tcg_gen_movi_tl(cpu_ov, 0);
5558 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5559 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5560 tcg_gen_mul_i64(t0, t0, t1);
5561 tcg_gen_trunc_i64_tl(t2, t0);
5562 gen_store_spr(SPR_MQ, t2);
5563 tcg_gen_shri_i64(t1, t0, 32);
5564 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5565 tcg_gen_ext32s_i64(t1, t0);
5566 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5567 tcg_gen_movi_tl(cpu_ov, 1);
5568 tcg_gen_movi_tl(cpu_so, 1);
5569 gen_set_label(l1);
5570 tcg_temp_free_i64(t0);
5571 tcg_temp_free_i64(t1);
5572 tcg_temp_free(t2);
5573 if (unlikely(Rc(ctx->opcode) != 0))
5574 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5575 }
5576
5577 /* nabs - nabs. */
5578 static void gen_nabs(DisasContext *ctx)
5579 {
5580 TCGLabel *l1 = gen_new_label();
5581 TCGLabel *l2 = gen_new_label();
5582 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5583 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5584 tcg_gen_br(l2);
5585 gen_set_label(l1);
5586 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5587 gen_set_label(l2);
5588 if (unlikely(Rc(ctx->opcode) != 0))
5589 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5590 }
5591
5592 /* nabso - nabso. */
5593 static void gen_nabso(DisasContext *ctx)
5594 {
5595 TCGLabel *l1 = gen_new_label();
5596 TCGLabel *l2 = gen_new_label();
5597 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5598 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5599 tcg_gen_br(l2);
5600 gen_set_label(l1);
5601 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5602 gen_set_label(l2);
5603 /* nabs never overflows */
5604 tcg_gen_movi_tl(cpu_ov, 0);
5605 if (unlikely(Rc(ctx->opcode) != 0))
5606 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5607 }
5608
5609 /* rlmi - rlmi. */
5610 static void gen_rlmi(DisasContext *ctx)
5611 {
5612 uint32_t mb = MB(ctx->opcode);
5613 uint32_t me = ME(ctx->opcode);
5614 TCGv t0 = tcg_temp_new();
5615 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5616 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5617 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5618 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5619 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5620 tcg_temp_free(t0);
5621 if (unlikely(Rc(ctx->opcode) != 0))
5622 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5623 }
5624
5625 /* rrib - rrib. */
5626 static void gen_rrib(DisasContext *ctx)
5627 {
5628 TCGv t0 = tcg_temp_new();
5629 TCGv t1 = tcg_temp_new();
5630 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5631 tcg_gen_movi_tl(t1, 0x80000000);
5632 tcg_gen_shr_tl(t1, t1, t0);
5633 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5634 tcg_gen_and_tl(t0, t0, t1);
5635 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5636 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5637 tcg_temp_free(t0);
5638 tcg_temp_free(t1);
5639 if (unlikely(Rc(ctx->opcode) != 0))
5640 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5641 }
5642
5643 /* sle - sle. */
5644 static void gen_sle(DisasContext *ctx)
5645 {
5646 TCGv t0 = tcg_temp_new();
5647 TCGv t1 = tcg_temp_new();
5648 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5649 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5650 tcg_gen_subfi_tl(t1, 32, t1);
5651 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5652 tcg_gen_or_tl(t1, t0, t1);
5653 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5654 gen_store_spr(SPR_MQ, t1);
5655 tcg_temp_free(t0);
5656 tcg_temp_free(t1);
5657 if (unlikely(Rc(ctx->opcode) != 0))
5658 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5659 }
5660
5661 /* sleq - sleq. */
5662 static void gen_sleq(DisasContext *ctx)
5663 {
5664 TCGv t0 = tcg_temp_new();
5665 TCGv t1 = tcg_temp_new();
5666 TCGv t2 = tcg_temp_new();
5667 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5668 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5669 tcg_gen_shl_tl(t2, t2, t0);
5670 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5671 gen_load_spr(t1, SPR_MQ);
5672 gen_store_spr(SPR_MQ, t0);
5673 tcg_gen_and_tl(t0, t0, t2);
5674 tcg_gen_andc_tl(t1, t1, t2);
5675 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5676 tcg_temp_free(t0);
5677 tcg_temp_free(t1);
5678 tcg_temp_free(t2);
5679 if (unlikely(Rc(ctx->opcode) != 0))
5680 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5681 }
5682
5683 /* sliq - sliq. */
5684 static void gen_sliq(DisasContext *ctx)
5685 {
5686 int sh = SH(ctx->opcode);
5687 TCGv t0 = tcg_temp_new();
5688 TCGv t1 = tcg_temp_new();
5689 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5690 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5691 tcg_gen_or_tl(t1, t0, t1);
5692 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5693 gen_store_spr(SPR_MQ, t1);
5694 tcg_temp_free(t0);
5695 tcg_temp_free(t1);
5696 if (unlikely(Rc(ctx->opcode) != 0))
5697 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5698 }
5699
5700 /* slliq - slliq. */
5701 static void gen_slliq(DisasContext *ctx)
5702 {
5703 int sh = SH(ctx->opcode);
5704 TCGv t0 = tcg_temp_new();
5705 TCGv t1 = tcg_temp_new();
5706 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5707 gen_load_spr(t1, SPR_MQ);
5708 gen_store_spr(SPR_MQ, t0);
5709 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5710 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5711 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5712 tcg_temp_free(t0);
5713 tcg_temp_free(t1);
5714 if (unlikely(Rc(ctx->opcode) != 0))
5715 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5716 }
5717
5718 /* sllq - sllq. */
5719 static void gen_sllq(DisasContext *ctx)
5720 {
5721 TCGLabel *l1 = gen_new_label();
5722 TCGLabel *l2 = gen_new_label();
5723 TCGv t0 = tcg_temp_local_new();
5724 TCGv t1 = tcg_temp_local_new();
5725 TCGv t2 = tcg_temp_local_new();
5726 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5727 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5728 tcg_gen_shl_tl(t1, t1, t2);
5729 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5730 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5731 gen_load_spr(t0, SPR_MQ);
5732 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5733 tcg_gen_br(l2);
5734 gen_set_label(l1);
5735 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5736 gen_load_spr(t2, SPR_MQ);
5737 tcg_gen_andc_tl(t1, t2, t1);
5738 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5739 gen_set_label(l2);
5740 tcg_temp_free(t0);
5741 tcg_temp_free(t1);
5742 tcg_temp_free(t2);
5743 if (unlikely(Rc(ctx->opcode) != 0))
5744 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5745 }
5746
5747 /* slq - slq. */
5748 static void gen_slq(DisasContext *ctx)
5749 {
5750 TCGLabel *l1 = gen_new_label();
5751 TCGv t0 = tcg_temp_new();
5752 TCGv t1 = tcg_temp_new();
5753 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5754 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5755 tcg_gen_subfi_tl(t1, 32, t1);
5756 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5757 tcg_gen_or_tl(t1, t0, t1);
5758 gen_store_spr(SPR_MQ, t1);
5759 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5760 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5761 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5762 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5763 gen_set_label(l1);
5764 tcg_temp_free(t0);
5765 tcg_temp_free(t1);
5766 if (unlikely(Rc(ctx->opcode) != 0))
5767 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5768 }
5769
5770 /* sraiq - sraiq. */
5771 static void gen_sraiq(DisasContext *ctx)
5772 {
5773 int sh = SH(ctx->opcode);
5774 TCGLabel *l1 = gen_new_label();
5775 TCGv t0 = tcg_temp_new();
5776 TCGv t1 = tcg_temp_new();
5777 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5778 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5779 tcg_gen_or_tl(t0, t0, t1);
5780 gen_store_spr(SPR_MQ, t0);
5781 tcg_gen_movi_tl(cpu_ca, 0);
5782 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5783 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5784 tcg_gen_movi_tl(cpu_ca, 1);
5785 gen_set_label(l1);
5786 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5787 tcg_temp_free(t0);
5788 tcg_temp_free(t1);
5789 if (unlikely(Rc(ctx->opcode) != 0))
5790 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5791 }
5792
5793 /* sraq - sraq. */
5794 static void gen_sraq(DisasContext *ctx)
5795 {
5796 TCGLabel *l1 = gen_new_label();
5797 TCGLabel *l2 = gen_new_label();
5798 TCGv t0 = tcg_temp_new();
5799 TCGv t1 = tcg_temp_local_new();
5800 TCGv t2 = tcg_temp_local_new();
5801 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5802 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5803 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5804 tcg_gen_subfi_tl(t2, 32, t2);
5805 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5806 tcg_gen_or_tl(t0, t0, t2);
5807 gen_store_spr(SPR_MQ, t0);
5808 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5809 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5810 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5811 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5812 gen_set_label(l1);
5813 tcg_temp_free(t0);
5814 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5815 tcg_gen_movi_tl(cpu_ca, 0);
5816 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5817 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5818 tcg_gen_movi_tl(cpu_ca, 1);
5819 gen_set_label(l2);
5820 tcg_temp_free(t1);
5821 tcg_temp_free(t2);
5822 if (unlikely(Rc(ctx->opcode) != 0))
5823 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5824 }
5825
5826 /* sre - sre. */
5827 static void gen_sre(DisasContext *ctx)
5828 {
5829 TCGv t0 = tcg_temp_new();
5830 TCGv t1 = tcg_temp_new();
5831 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5832 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5833 tcg_gen_subfi_tl(t1, 32, t1);
5834 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5835 tcg_gen_or_tl(t1, t0, t1);
5836 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5837 gen_store_spr(SPR_MQ, t1);
5838 tcg_temp_free(t0);
5839 tcg_temp_free(t1);
5840 if (unlikely(Rc(ctx->opcode) != 0))
5841 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5842 }
5843
5844 /* srea - srea. */
5845 static void gen_srea(DisasContext *ctx)
5846 {
5847 TCGv t0 = tcg_temp_new();
5848 TCGv t1 = tcg_temp_new();
5849 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5850 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5851 gen_store_spr(SPR_MQ, t0);
5852 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5853 tcg_temp_free(t0);
5854 tcg_temp_free(t1);
5855 if (unlikely(Rc(ctx->opcode) != 0))
5856 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5857 }
5858
5859 /* sreq */
5860 static void gen_sreq(DisasContext *ctx)
5861 {
5862 TCGv t0 = tcg_temp_new();
5863 TCGv t1 = tcg_temp_new();
5864 TCGv t2 = tcg_temp_new();
5865 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5866 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5867 tcg_gen_shr_tl(t1, t1, t0);
5868 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5869 gen_load_spr(t2, SPR_MQ);
5870 gen_store_spr(SPR_MQ, t0);
5871 tcg_gen_and_tl(t0, t0, t1);
5872 tcg_gen_andc_tl(t2, t2, t1);
5873 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5874 tcg_temp_free(t0);
5875 tcg_temp_free(t1);
5876 tcg_temp_free(t2);
5877 if (unlikely(Rc(ctx->opcode) != 0))
5878 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5879 }
5880
5881 /* sriq */
5882 static void gen_sriq(DisasContext *ctx)
5883 {
5884 int sh = SH(ctx->opcode);
5885 TCGv t0 = tcg_temp_new();
5886 TCGv t1 = tcg_temp_new();
5887 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5888 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5889 tcg_gen_or_tl(t1, t0, t1);
5890 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5891 gen_store_spr(SPR_MQ, t1);
5892 tcg_temp_free(t0);
5893 tcg_temp_free(t1);
5894 if (unlikely(Rc(ctx->opcode) != 0))
5895 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5896 }
5897
5898 /* srliq */
5899 static void gen_srliq(DisasContext *ctx)
5900 {
5901 int sh = SH(ctx->opcode);
5902 TCGv t0 = tcg_temp_new();
5903 TCGv t1 = tcg_temp_new();
5904 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5905 gen_load_spr(t1, SPR_MQ);
5906 gen_store_spr(SPR_MQ, t0);
5907 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5908 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5909 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5910 tcg_temp_free(t0);
5911 tcg_temp_free(t1);
5912 if (unlikely(Rc(ctx->opcode) != 0))
5913 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5914 }
5915
5916 /* srlq */
5917 static void gen_srlq(DisasContext *ctx)
5918 {
5919 TCGLabel *l1 = gen_new_label();
5920 TCGLabel *l2 = gen_new_label();
5921 TCGv t0 = tcg_temp_local_new();
5922 TCGv t1 = tcg_temp_local_new();
5923 TCGv t2 = tcg_temp_local_new();
5924 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5925 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5926 tcg_gen_shr_tl(t2, t1, t2);
5927 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5928 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5929 gen_load_spr(t0, SPR_MQ);
5930 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5931 tcg_gen_br(l2);
5932 gen_set_label(l1);
5933 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5934 tcg_gen_and_tl(t0, t0, t2);
5935 gen_load_spr(t1, SPR_MQ);
5936 tcg_gen_andc_tl(t1, t1, t2);
5937 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5938 gen_set_label(l2);
5939 tcg_temp_free(t0);
5940 tcg_temp_free(t1);
5941 tcg_temp_free(t2);
5942 if (unlikely(Rc(ctx->opcode) != 0))
5943 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5944 }
5945
5946 /* srq */
5947 static void gen_srq(DisasContext *ctx)
5948 {
5949 TCGLabel *l1 = gen_new_label();
5950 TCGv t0 = tcg_temp_new();
5951 TCGv t1 = tcg_temp_new();
5952 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5953 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5954 tcg_gen_subfi_tl(t1, 32, t1);
5955 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5956 tcg_gen_or_tl(t1, t0, t1);
5957 gen_store_spr(SPR_MQ, t1);
5958 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5959 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5960 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5961 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5962 gen_set_label(l1);
5963 tcg_temp_free(t0);
5964 tcg_temp_free(t1);
5965 if (unlikely(Rc(ctx->opcode) != 0))
5966 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5967 }
5968
5969 /* PowerPC 602 specific instructions */
5970
5971 /* dsa */
5972 static void gen_dsa(DisasContext *ctx)
5973 {
5974 /* XXX: TODO */
5975 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5976 }
5977
5978 /* esa */
5979 static void gen_esa(DisasContext *ctx)
5980 {
5981 /* XXX: TODO */
5982 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5983 }
5984
5985 /* mfrom */
5986 static void gen_mfrom(DisasContext *ctx)
5987 {
5988 #if defined(CONFIG_USER_ONLY)
5989 GEN_PRIV;
5990 #else
5991 CHK_SV;
5992 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5993 #endif /* defined(CONFIG_USER_ONLY) */
5994 }
5995
5996 /* 602 - 603 - G2 TLB management */
5997
5998 /* tlbld */
5999 static void gen_tlbld_6xx(DisasContext *ctx)
6000 {
6001 #if defined(CONFIG_USER_ONLY)
6002 GEN_PRIV;
6003 #else
6004 CHK_SV;
6005 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6006 #endif /* defined(CONFIG_USER_ONLY) */
6007 }
6008
6009 /* tlbli */
6010 static void gen_tlbli_6xx(DisasContext *ctx)
6011 {
6012 #if defined(CONFIG_USER_ONLY)
6013 GEN_PRIV;
6014 #else
6015 CHK_SV;
6016 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6017 #endif /* defined(CONFIG_USER_ONLY) */
6018 }
6019
6020 /* 74xx TLB management */
6021
6022 /* tlbld */
6023 static void gen_tlbld_74xx(DisasContext *ctx)
6024 {
6025 #if defined(CONFIG_USER_ONLY)
6026 GEN_PRIV;
6027 #else
6028 CHK_SV;
6029 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6030 #endif /* defined(CONFIG_USER_ONLY) */
6031 }
6032
6033 /* tlbli */
6034 static void gen_tlbli_74xx(DisasContext *ctx)
6035 {
6036 #if defined(CONFIG_USER_ONLY)
6037 GEN_PRIV;
6038 #else
6039 CHK_SV;
6040 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6041 #endif /* defined(CONFIG_USER_ONLY) */
6042 }
6043
6044 /* POWER instructions not in PowerPC 601 */
6045
6046 /* clf */
6047 static void gen_clf(DisasContext *ctx)
6048 {
6049 /* Cache line flush: implemented as no-op */
6050 }
6051
6052 /* cli */
6053 static void gen_cli(DisasContext *ctx)
6054 {
6055 #if defined(CONFIG_USER_ONLY)
6056 GEN_PRIV;
6057 #else
6058 /* Cache line invalidate: privileged and treated as no-op */
6059 CHK_SV;
6060 #endif /* defined(CONFIG_USER_ONLY) */
6061 }
6062
6063 /* dclst */
6064 static void gen_dclst(DisasContext *ctx)
6065 {
6066 /* Data cache line store: treated as no-op */
6067 }
6068
6069 static void gen_mfsri(DisasContext *ctx)
6070 {
6071 #if defined(CONFIG_USER_ONLY)
6072 GEN_PRIV;
6073 #else
6074 int ra = rA(ctx->opcode);
6075 int rd = rD(ctx->opcode);
6076 TCGv t0;
6077
6078 CHK_SV;
6079 t0 = tcg_temp_new();
6080 gen_addr_reg_index(ctx, t0);
6081 tcg_gen_shri_tl(t0, t0, 28);
6082 tcg_gen_andi_tl(t0, t0, 0xF);
6083 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
6084 tcg_temp_free(t0);
6085 if (ra != 0 && ra != rd)
6086 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
6087 #endif /* defined(CONFIG_USER_ONLY) */
6088 }
6089
6090 static void gen_rac(DisasContext *ctx)
6091 {
6092 #if defined(CONFIG_USER_ONLY)
6093 GEN_PRIV;
6094 #else
6095 TCGv t0;
6096
6097 CHK_SV;
6098 t0 = tcg_temp_new();
6099 gen_addr_reg_index(ctx, t0);
6100 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6101 tcg_temp_free(t0);
6102 #endif /* defined(CONFIG_USER_ONLY) */
6103 }
6104
6105 static void gen_rfsvc(DisasContext *ctx)
6106 {
6107 #if defined(CONFIG_USER_ONLY)
6108 GEN_PRIV;
6109 #else
6110 CHK_SV;
6111
6112 gen_helper_rfsvc(cpu_env);
6113 gen_sync_exception(ctx);
6114 #endif /* defined(CONFIG_USER_ONLY) */
6115 }
6116
6117 /* svc is not implemented for now */
6118
6119 /* POWER2 specific instructions */
6120 /* Quad manipulation (load/store two floats at a time) */
6121
6122 /* lfq */
6123 static void gen_lfq(DisasContext *ctx)
6124 {
6125 int rd = rD(ctx->opcode);
6126 TCGv t0;
6127 gen_set_access_type(ctx, ACCESS_FLOAT);
6128 t0 = tcg_temp_new();
6129 gen_addr_imm_index(ctx, t0, 0);
6130 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
6131 gen_addr_add(ctx, t0, t0, 8);
6132 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
6133 tcg_temp_free(t0);
6134 }
6135
6136 /* lfqu */
6137 static void gen_lfqu(DisasContext *ctx)
6138 {
6139 int ra = rA(ctx->opcode);
6140 int rd = rD(ctx->opcode);
6141 TCGv t0, t1;
6142 gen_set_access_type(ctx, ACCESS_FLOAT);
6143 t0 = tcg_temp_new();
6144 t1 = tcg_temp_new();
6145 gen_addr_imm_index(ctx, t0, 0);
6146 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
6147 gen_addr_add(ctx, t1, t0, 8);
6148 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
6149 if (ra != 0)
6150 tcg_gen_mov_tl(cpu_gpr[ra], t0);
6151 tcg_temp_free(t0);
6152 tcg_temp_free(t1);
6153 }
6154
6155 /* lfqux */
6156 static void gen_lfqux(DisasContext *ctx)
6157 {
6158 int ra = rA(ctx->opcode);
6159 int rd = rD(ctx->opcode);
6160 gen_set_access_type(ctx, ACCESS_FLOAT);
6161 TCGv t0, t1;
6162 t0 = tcg_temp_new();
6163 gen_addr_reg_index(ctx, t0);
6164 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
6165 t1 = tcg_temp_new();
6166 gen_addr_add(ctx, t1, t0, 8);
6167 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
6168 tcg_temp_free(t1);
6169 if (ra != 0)
6170 tcg_gen_mov_tl(cpu_gpr[ra], t0);
6171 tcg_temp_free(t0);
6172 }
6173
6174 /* lfqx */
6175 static void gen_lfqx(DisasContext *ctx)
6176 {
6177 int rd = rD(ctx->opcode);
6178 TCGv t0;
6179 gen_set_access_type(ctx, ACCESS_FLOAT);
6180 t0 = tcg_temp_new();
6181 gen_addr_reg_index(ctx, t0);
6182 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
6183 gen_addr_add(ctx, t0, t0, 8);
6184 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
6185 tcg_temp_free(t0);
6186 }
6187
6188 /* stfq */
6189 static void gen_stfq(DisasContext *ctx)
6190 {
6191 int rd = rD(ctx->opcode);
6192 TCGv t0;
6193 gen_set_access_type(ctx, ACCESS_FLOAT);
6194 t0 = tcg_temp_new();
6195 gen_addr_imm_index(ctx, t0, 0);
6196 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
6197 gen_addr_add(ctx, t0, t0, 8);
6198 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
6199 tcg_temp_free(t0);
6200 }
6201
6202 /* stfqu */
6203 static void gen_stfqu(DisasContext *ctx)
6204 {
6205 int ra = rA(ctx->opcode);
6206 int rd = rD(ctx->opcode);
6207 TCGv t0, t1;
6208 gen_set_access_type(ctx, ACCESS_FLOAT);
6209 t0 = tcg_temp_new();
6210 gen_addr_imm_index(ctx, t0, 0);
6211 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
6212 t1 = tcg_temp_new();
6213 gen_addr_add(ctx, t1, t0, 8);
6214 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
6215 tcg_temp_free(t1);
6216 if (ra != 0)
6217 tcg_gen_mov_tl(cpu_gpr[ra], t0);
6218 tcg_temp_free(t0);
6219 }
6220
6221 /* stfqux */
6222 static void gen_stfqux(DisasContext *ctx)
6223 {
6224 int ra = rA(ctx->opcode);
6225 int rd = rD(ctx->opcode);
6226 TCGv t0, t1;
6227 gen_set_access_type(ctx, ACCESS_FLOAT);
6228 t0 = tcg_temp_new();
6229 gen_addr_reg_index(ctx, t0);
6230 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
6231 t1 = tcg_temp_new();
6232 gen_addr_add(ctx, t1, t0, 8);
6233 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
6234 tcg_temp_free(t1);
6235 if (ra != 0)
6236 tcg_gen_mov_tl(cpu_gpr[ra], t0);
6237 tcg_temp_free(t0);
6238 }
6239
6240 /* stfqx */
6241 static void gen_stfqx(DisasContext *ctx)
6242 {
6243 int rd = rD(ctx->opcode);
6244 TCGv t0;
6245 gen_set_access_type(ctx, ACCESS_FLOAT);
6246 t0 = tcg_temp_new();
6247 gen_addr_reg_index(ctx, t0);
6248 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
6249 gen_addr_add(ctx, t0, t0, 8);
6250 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
6251 tcg_temp_free(t0);
6252 }
6253
6254 /* BookE specific instructions */
6255
6256 /* XXX: not implemented on 440 ? */
6257 static void gen_mfapidi(DisasContext *ctx)
6258 {
6259 /* XXX: TODO */
6260 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6261 }
6262
6263 /* XXX: not implemented on 440 ? */
6264 static void gen_tlbiva(DisasContext *ctx)
6265 {
6266 #if defined(CONFIG_USER_ONLY)
6267 GEN_PRIV;
6268 #else
6269 TCGv t0;
6270
6271 CHK_SV;
6272 t0 = tcg_temp_new();
6273 gen_addr_reg_index(ctx, t0);
6274 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6275 tcg_temp_free(t0);
6276 #endif /* defined(CONFIG_USER_ONLY) */
6277 }
6278
6279 /* All 405 MAC instructions are translated here */
6280 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
6281 int ra, int rb, int rt, int Rc)
6282 {
6283 TCGv t0, t1;
6284
6285 t0 = tcg_temp_local_new();
6286 t1 = tcg_temp_local_new();
6287
6288 switch (opc3 & 0x0D) {
6289 case 0x05:
6290 /* macchw - macchw. - macchwo - macchwo. */
6291 /* macchws - macchws. - macchwso - macchwso. */
6292 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
6293 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
6294 /* mulchw - mulchw. */
6295 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6296 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6297 tcg_gen_ext16s_tl(t1, t1);
6298 break;
6299 case 0x04:
6300 /* macchwu - macchwu. - macchwuo - macchwuo. */
6301 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
6302 /* mulchwu - mulchwu. */
6303 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6304 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6305 tcg_gen_ext16u_tl(t1, t1);
6306 break;
6307 case 0x01:
6308 /* machhw - machhw. - machhwo - machhwo. */
6309 /* machhws - machhws. - machhwso - machhwso. */
6310 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
6311 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
6312 /* mulhhw - mulhhw. */
6313 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
6314 tcg_gen_ext16s_tl(t0, t0);
6315 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6316 tcg_gen_ext16s_tl(t1, t1);
6317 break;
6318 case 0x00:
6319 /* machhwu - machhwu. - machhwuo - machhwuo. */
6320 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
6321 /* mulhhwu - mulhhwu. */
6322 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
6323 tcg_gen_ext16u_tl(t0, t0);
6324 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6325 tcg_gen_ext16u_tl(t1, t1);
6326 break;
6327 case 0x0D:
6328 /* maclhw - maclhw. - maclhwo - maclhwo. */
6329 /* maclhws - maclhws. - maclhwso - maclhwso. */
6330 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
6331 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
6332 /* mullhw - mullhw. */
6333 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6334 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
6335 break;
6336 case 0x0C:
6337 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6338 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6339 /* mullhwu - mullhwu. */
6340 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6341 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
6342 break;
6343 }
6344 if (opc2 & 0x04) {
6345 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6346 tcg_gen_mul_tl(t1, t0, t1);
6347 if (opc2 & 0x02) {
6348 /* nmultiply-and-accumulate (0x0E) */
6349 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
6350 } else {
6351 /* multiply-and-accumulate (0x0C) */
6352 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
6353 }
6354
6355 if (opc3 & 0x12) {
6356 /* Check overflow and/or saturate */
6357 TCGLabel *l1 = gen_new_label();
6358
6359 if (opc3 & 0x10) {
6360 /* Start with XER OV disabled, the most likely case */
6361 tcg_gen_movi_tl(cpu_ov, 0);
6362 }
6363 if (opc3 & 0x01) {
6364 /* Signed */
6365 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6366 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6367 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6368 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
6369 if (opc3 & 0x02) {
6370 /* Saturate */
6371 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6372 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6373 }
6374 } else {
6375 /* Unsigned */
6376 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
6377 if (opc3 & 0x02) {
6378 /* Saturate */
6379 tcg_gen_movi_tl(t0, UINT32_MAX);
6380 }
6381 }
6382 if (opc3 & 0x10) {
6383 /* Check overflow */
6384 tcg_gen_movi_tl(cpu_ov, 1);
6385 tcg_gen_movi_tl(cpu_so, 1);
6386 }
6387 gen_set_label(l1);
6388 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6389 }
6390 } else {
6391 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6392 }
6393 tcg_temp_free(t0);
6394 tcg_temp_free(t1);
6395 if (unlikely(Rc) != 0) {
6396 /* Update Rc0 */
6397 gen_set_Rc0(ctx, cpu_gpr[rt]);
6398 }
6399 }
6400
6401 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6402 static void glue(gen_, name)(DisasContext *ctx) \
6403 { \
6404 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6405 rD(ctx->opcode), Rc(ctx->opcode)); \
6406 }
6407
6408 /* macchw - macchw. */
6409 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6410 /* macchwo - macchwo. */
6411 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6412 /* macchws - macchws. */
6413 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6414 /* macchwso - macchwso. */
6415 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6416 /* macchwsu - macchwsu. */
6417 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6418 /* macchwsuo - macchwsuo. */
6419 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6420 /* macchwu - macchwu. */
6421 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6422 /* macchwuo - macchwuo. */
6423 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6424 /* machhw - machhw. */
6425 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6426 /* machhwo - machhwo. */
6427 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6428 /* machhws - machhws. */
6429 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6430 /* machhwso - machhwso. */
6431 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6432 /* machhwsu - machhwsu. */
6433 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6434 /* machhwsuo - machhwsuo. */
6435 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6436 /* machhwu - machhwu. */
6437 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6438 /* machhwuo - machhwuo. */
6439 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6440 /* maclhw - maclhw. */
6441 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6442 /* maclhwo - maclhwo. */
6443 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6444 /* maclhws - maclhws. */
6445 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6446 /* maclhwso - maclhwso. */
6447 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6448 /* maclhwu - maclhwu. */
6449 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6450 /* maclhwuo - maclhwuo. */
6451 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6452 /* maclhwsu - maclhwsu. */
6453 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6454 /* maclhwsuo - maclhwsuo. */
6455 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6456 /* nmacchw - nmacchw. */
6457 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6458 /* nmacchwo - nmacchwo. */
6459 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6460 /* nmacchws - nmacchws. */
6461 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6462 /* nmacchwso - nmacchwso. */
6463 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6464 /* nmachhw - nmachhw. */
6465 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6466 /* nmachhwo - nmachhwo. */
6467 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6468 /* nmachhws - nmachhws. */
6469 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6470 /* nmachhwso - nmachhwso. */
6471 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6472 /* nmaclhw - nmaclhw. */
6473 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6474 /* nmaclhwo - nmaclhwo. */
6475 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6476 /* nmaclhws - nmaclhws. */
6477 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6478 /* nmaclhwso - nmaclhwso. */
6479 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6480
6481 /* mulchw - mulchw. */
6482 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6483 /* mulchwu - mulchwu. */
6484 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6485 /* mulhhw - mulhhw. */
6486 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6487 /* mulhhwu - mulhhwu. */
6488 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6489 /* mullhw - mullhw. */
6490 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6491 /* mullhwu - mullhwu. */
6492 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6493
6494 /* mfdcr */
6495 static void gen_mfdcr(DisasContext *ctx)
6496 {
6497 #if defined(CONFIG_USER_ONLY)
6498 GEN_PRIV;
6499 #else
6500 TCGv dcrn;
6501
6502 CHK_SV;
6503 /* NIP cannot be restored if the memory exception comes from an helper */
6504 gen_update_nip(ctx, ctx->nip - 4);
6505 dcrn = tcg_const_tl(SPR(ctx->opcode));
6506 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6507 tcg_temp_free(dcrn);
6508 #endif /* defined(CONFIG_USER_ONLY) */
6509 }
6510
6511 /* mtdcr */
6512 static void gen_mtdcr(DisasContext *ctx)
6513 {
6514 #if defined(CONFIG_USER_ONLY)
6515 GEN_PRIV;
6516 #else
6517 TCGv dcrn;
6518
6519 CHK_SV;
6520 /* NIP cannot be restored if the memory exception comes from an helper */
6521 gen_update_nip(ctx, ctx->nip - 4);
6522 dcrn = tcg_const_tl(SPR(ctx->opcode));
6523 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6524 tcg_temp_free(dcrn);
6525 #endif /* defined(CONFIG_USER_ONLY) */
6526 }
6527
6528 /* mfdcrx */
6529 /* XXX: not implemented on 440 ? */
6530 static void gen_mfdcrx(DisasContext *ctx)
6531 {
6532 #if defined(CONFIG_USER_ONLY)
6533 GEN_PRIV;
6534 #else
6535 CHK_SV;
6536 /* NIP cannot be restored if the memory exception comes from an helper */
6537 gen_update_nip(ctx, ctx->nip - 4);
6538 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6539 cpu_gpr[rA(ctx->opcode)]);
6540 /* Note: Rc update flag set leads to undefined state of Rc0 */
6541 #endif /* defined(CONFIG_USER_ONLY) */
6542 }
6543
6544 /* mtdcrx */
6545 /* XXX: not implemented on 440 ? */
6546 static void gen_mtdcrx(DisasContext *ctx)
6547 {
6548 #if defined(CONFIG_USER_ONLY)
6549 GEN_PRIV;
6550 #else
6551 CHK_SV;
6552 /* NIP cannot be restored if the memory exception comes from an helper */
6553 gen_update_nip(ctx, ctx->nip - 4);
6554 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6555 cpu_gpr[rS(ctx->opcode)]);
6556 /* Note: Rc update flag set leads to undefined state of Rc0 */
6557 #endif /* defined(CONFIG_USER_ONLY) */
6558 }
6559
6560 /* mfdcrux (PPC 460) : user-mode access to DCR */
6561 static void gen_mfdcrux(DisasContext *ctx)
6562 {
6563 /* NIP cannot be restored if the memory exception comes from an helper */
6564 gen_update_nip(ctx, ctx->nip - 4);
6565 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6566 cpu_gpr[rA(ctx->opcode)]);
6567 /* Note: Rc update flag set leads to undefined state of Rc0 */
6568 }
6569
6570 /* mtdcrux (PPC 460) : user-mode access to DCR */
6571 static void gen_mtdcrux(DisasContext *ctx)
6572 {
6573 /* NIP cannot be restored if the memory exception comes from an helper */
6574 gen_update_nip(ctx, ctx->nip - 4);
6575 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6576 cpu_gpr[rS(ctx->opcode)]);
6577 /* Note: Rc update flag set leads to undefined state of Rc0 */
6578 }
6579
6580 /* dccci */
6581 static void gen_dccci(DisasContext *ctx)
6582 {
6583 CHK_SV;
6584 /* interpreted as no-op */
6585 }
6586
6587 /* dcread */
6588 static void gen_dcread(DisasContext *ctx)
6589 {
6590 #if defined(CONFIG_USER_ONLY)
6591 GEN_PRIV;
6592 #else
6593 TCGv EA, val;
6594
6595 CHK_SV;
6596 gen_set_access_type(ctx, ACCESS_CACHE);
6597 EA = tcg_temp_new();
6598 gen_addr_reg_index(ctx, EA);
6599 val = tcg_temp_new();
6600 gen_qemu_ld32u(ctx, val, EA);
6601 tcg_temp_free(val);
6602 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6603 tcg_temp_free(EA);
6604 #endif /* defined(CONFIG_USER_ONLY) */
6605 }
6606
6607 /* icbt */
6608 static void gen_icbt_40x(DisasContext *ctx)
6609 {
6610 /* interpreted as no-op */
6611 /* XXX: specification say this is treated as a load by the MMU
6612 * but does not generate any exception
6613 */
6614 }
6615
6616 /* iccci */
6617 static void gen_iccci(DisasContext *ctx)
6618 {
6619 CHK_SV;
6620 /* interpreted as no-op */
6621 }
6622
6623 /* icread */
6624 static void gen_icread(DisasContext *ctx)
6625 {
6626 CHK_SV;
6627 /* interpreted as no-op */
6628 }
6629
6630 /* rfci (supervisor only) */
6631 static void gen_rfci_40x(DisasContext *ctx)
6632 {
6633 #if defined(CONFIG_USER_ONLY)
6634 GEN_PRIV;
6635 #else
6636 CHK_SV;
6637 /* Restore CPU state */
6638 gen_helper_40x_rfci(cpu_env);
6639 gen_sync_exception(ctx);
6640 #endif /* defined(CONFIG_USER_ONLY) */
6641 }
6642
6643 static void gen_rfci(DisasContext *ctx)
6644 {
6645 #if defined(CONFIG_USER_ONLY)
6646 GEN_PRIV;
6647 #else
6648 CHK_SV;
6649 /* Restore CPU state */
6650 gen_helper_rfci(cpu_env);
6651 gen_sync_exception(ctx);
6652 #endif /* defined(CONFIG_USER_ONLY) */
6653 }
6654
6655 /* BookE specific */
6656
6657 /* XXX: not implemented on 440 ? */
6658 static void gen_rfdi(DisasContext *ctx)
6659 {
6660 #if defined(CONFIG_USER_ONLY)
6661 GEN_PRIV;
6662 #else
6663 CHK_SV;
6664 /* Restore CPU state */
6665 gen_helper_rfdi(cpu_env);
6666 gen_sync_exception(ctx);
6667 #endif /* defined(CONFIG_USER_ONLY) */
6668 }
6669
6670 /* XXX: not implemented on 440 ? */
6671 static void gen_rfmci(DisasContext *ctx)
6672 {
6673 #if defined(CONFIG_USER_ONLY)
6674 GEN_PRIV;
6675 #else
6676 CHK_SV;
6677 /* Restore CPU state */
6678 gen_helper_rfmci(cpu_env);
6679 gen_sync_exception(ctx);
6680 #endif /* defined(CONFIG_USER_ONLY) */
6681 }
6682
6683 /* TLB management - PowerPC 405 implementation */
6684
6685 /* tlbre */
6686 static void gen_tlbre_40x(DisasContext *ctx)
6687 {
6688 #if defined(CONFIG_USER_ONLY)
6689 GEN_PRIV;
6690 #else
6691 CHK_SV;
6692 switch (rB(ctx->opcode)) {
6693 case 0:
6694 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6695 cpu_gpr[rA(ctx->opcode)]);
6696 break;
6697 case 1:
6698 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6699 cpu_gpr[rA(ctx->opcode)]);
6700 break;
6701 default:
6702 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6703 break;
6704 }
6705 #endif /* defined(CONFIG_USER_ONLY) */
6706 }
6707
6708 /* tlbsx - tlbsx. */
6709 static void gen_tlbsx_40x(DisasContext *ctx)
6710 {
6711 #if defined(CONFIG_USER_ONLY)
6712 GEN_PRIV;
6713 #else
6714 TCGv t0;
6715
6716 CHK_SV;
6717 t0 = tcg_temp_new();
6718 gen_addr_reg_index(ctx, t0);
6719 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6720 tcg_temp_free(t0);
6721 if (Rc(ctx->opcode)) {
6722 TCGLabel *l1 = gen_new_label();
6723 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6724 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6725 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6726 gen_set_label(l1);
6727 }
6728 #endif /* defined(CONFIG_USER_ONLY) */
6729 }
6730
6731 /* tlbwe */
6732 static void gen_tlbwe_40x(DisasContext *ctx)
6733 {
6734 #if defined(CONFIG_USER_ONLY)
6735 GEN_PRIV;
6736 #else
6737 CHK_SV;
6738
6739 switch (rB(ctx->opcode)) {
6740 case 0:
6741 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6742 cpu_gpr[rS(ctx->opcode)]);
6743 break;
6744 case 1:
6745 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6746 cpu_gpr[rS(ctx->opcode)]);
6747 break;
6748 default:
6749 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6750 break;
6751 }
6752 #endif /* defined(CONFIG_USER_ONLY) */
6753 }
6754
6755 /* TLB management - PowerPC 440 implementation */
6756
6757 /* tlbre */
6758 static void gen_tlbre_440(DisasContext *ctx)
6759 {
6760 #if defined(CONFIG_USER_ONLY)
6761 GEN_PRIV;
6762 #else
6763 CHK_SV;
6764
6765 switch (rB(ctx->opcode)) {
6766 case 0:
6767 case 1:
6768 case 2:
6769 {
6770 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6771 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6772 t0, cpu_gpr[rA(ctx->opcode)]);
6773 tcg_temp_free_i32(t0);
6774 }
6775 break;
6776 default:
6777 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6778 break;
6779 }
6780 #endif /* defined(CONFIG_USER_ONLY) */
6781 }
6782
6783 /* tlbsx - tlbsx. */
6784 static void gen_tlbsx_440(DisasContext *ctx)
6785 {
6786 #if defined(CONFIG_USER_ONLY)
6787 GEN_PRIV;
6788 #else
6789 TCGv t0;
6790
6791 CHK_SV;
6792 t0 = tcg_temp_new();
6793 gen_addr_reg_index(ctx, t0);
6794 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6795 tcg_temp_free(t0);
6796 if (Rc(ctx->opcode)) {
6797 TCGLabel *l1 = gen_new_label();
6798 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6799 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6800 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6801 gen_set_label(l1);
6802 }
6803 #endif /* defined(CONFIG_USER_ONLY) */
6804 }
6805
6806 /* tlbwe */
6807 static void gen_tlbwe_440(DisasContext *ctx)
6808 {
6809 #if defined(CONFIG_USER_ONLY)
6810 GEN_PRIV;
6811 #else
6812 CHK_SV;
6813 switch (rB(ctx->opcode)) {
6814 case 0:
6815 case 1:
6816 case 2:
6817 {
6818 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6819 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6820 cpu_gpr[rS(ctx->opcode)]);
6821 tcg_temp_free_i32(t0);
6822 }
6823 break;
6824 default:
6825 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6826 break;
6827 }
6828 #endif /* defined(CONFIG_USER_ONLY) */
6829 }
6830
6831 /* TLB management - PowerPC BookE 2.06 implementation */
6832
6833 /* tlbre */
6834 static void gen_tlbre_booke206(DisasContext *ctx)
6835 {
6836 #if defined(CONFIG_USER_ONLY)
6837 GEN_PRIV;
6838 #else
6839 CHK_SV;
6840 gen_helper_booke206_tlbre(cpu_env);
6841 #endif /* defined(CONFIG_USER_ONLY) */
6842 }
6843
6844 /* tlbsx - tlbsx. */
6845 static void gen_tlbsx_booke206(DisasContext *ctx)
6846 {
6847 #if defined(CONFIG_USER_ONLY)
6848 GEN_PRIV;
6849 #else
6850 TCGv t0;
6851
6852 CHK_SV;
6853 if (rA(ctx->opcode)) {
6854 t0 = tcg_temp_new();
6855 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6856 } else {
6857 t0 = tcg_const_tl(0);
6858 }
6859
6860 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6861 gen_helper_booke206_tlbsx(cpu_env, t0);
6862 tcg_temp_free(t0);
6863 #endif /* defined(CONFIG_USER_ONLY) */
6864 }
6865
6866 /* tlbwe */
6867 static void gen_tlbwe_booke206(DisasContext *ctx)
6868 {
6869 #if defined(CONFIG_USER_ONLY)
6870 GEN_PRIV;
6871 #else
6872 CHK_SV;
6873 gen_update_nip(ctx, ctx->nip - 4);
6874 gen_helper_booke206_tlbwe(cpu_env);
6875 #endif /* defined(CONFIG_USER_ONLY) */
6876 }
6877
6878 static void gen_tlbivax_booke206(DisasContext *ctx)
6879 {
6880 #if defined(CONFIG_USER_ONLY)
6881 GEN_PRIV;
6882 #else
6883 TCGv t0;
6884
6885 CHK_SV;
6886 t0 = tcg_temp_new();
6887 gen_addr_reg_index(ctx, t0);
6888 gen_helper_booke206_tlbivax(cpu_env, t0);
6889 tcg_temp_free(t0);
6890 #endif /* defined(CONFIG_USER_ONLY) */
6891 }
6892
6893 static void gen_tlbilx_booke206(DisasContext *ctx)
6894 {
6895 #if defined(CONFIG_USER_ONLY)
6896 GEN_PRIV;
6897 #else
6898 TCGv t0;
6899
6900 CHK_SV;
6901 t0 = tcg_temp_new();
6902 gen_addr_reg_index(ctx, t0);
6903
6904 switch((ctx->opcode >> 21) & 0x3) {
6905 case 0:
6906 gen_helper_booke206_tlbilx0(cpu_env, t0);
6907 break;
6908 case 1:
6909 gen_helper_booke206_tlbilx1(cpu_env, t0);
6910 break;
6911 case 3:
6912 gen_helper_booke206_tlbilx3(cpu_env, t0);
6913 break;
6914 default:
6915 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6916 break;
6917 }
6918
6919 tcg_temp_free(t0);
6920 #endif /* defined(CONFIG_USER_ONLY) */
6921 }
6922
6923
6924 /* wrtee */
6925 static void gen_wrtee(DisasContext *ctx)
6926 {
6927 #if defined(CONFIG_USER_ONLY)
6928 GEN_PRIV;
6929 #else
6930 TCGv t0;
6931
6932 CHK_SV;
6933 t0 = tcg_temp_new();
6934 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6935 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6936 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6937 tcg_temp_free(t0);
6938 /* Stop translation to have a chance to raise an exception
6939 * if we just set msr_ee to 1
6940 */
6941 gen_stop_exception(ctx);
6942 #endif /* defined(CONFIG_USER_ONLY) */
6943 }
6944
6945 /* wrteei */
6946 static void gen_wrteei(DisasContext *ctx)
6947 {
6948 #if defined(CONFIG_USER_ONLY)
6949 GEN_PRIV;
6950 #else
6951 CHK_SV;
6952 if (ctx->opcode & 0x00008000) {
6953 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6954 /* Stop translation to have a chance to raise an exception */
6955 gen_stop_exception(ctx);
6956 } else {
6957 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6958 }
6959 #endif /* defined(CONFIG_USER_ONLY) */
6960 }
6961
6962 /* PowerPC 440 specific instructions */
6963
6964 /* dlmzb */
6965 static void gen_dlmzb(DisasContext *ctx)
6966 {
6967 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6968 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6969 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6970 tcg_temp_free_i32(t0);
6971 }
6972
6973 /* mbar replaces eieio on 440 */
6974 static void gen_mbar(DisasContext *ctx)
6975 {
6976 /* interpreted as no-op */
6977 }
6978
6979 /* msync replaces sync on 440 */
6980 static void gen_msync_4xx(DisasContext *ctx)
6981 {
6982 /* interpreted as no-op */
6983 }
6984
6985 /* icbt */
6986 static void gen_icbt_440(DisasContext *ctx)
6987 {
6988 /* interpreted as no-op */
6989 /* XXX: specification say this is treated as a load by the MMU
6990 * but does not generate any exception
6991 */
6992 }
6993
6994 /* Embedded.Processor Control */
6995
6996 static void gen_msgclr(DisasContext *ctx)
6997 {
6998 #if defined(CONFIG_USER_ONLY)
6999 GEN_PRIV;
7000 #else
7001 CHK_SV;
7002 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7003 #endif /* defined(CONFIG_USER_ONLY) */
7004 }
7005
7006 static void gen_msgsnd(DisasContext *ctx)
7007 {
7008 #if defined(CONFIG_USER_ONLY)
7009 GEN_PRIV;
7010 #else
7011 CHK_SV;
7012 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
7013 #endif /* defined(CONFIG_USER_ONLY) */
7014 }
7015
7016 /*** Altivec vector extension ***/
7017 /* Altivec registers moves */
7018
7019 static inline TCGv_ptr gen_avr_ptr(int reg)
7020 {
7021 TCGv_ptr r = tcg_temp_new_ptr();
7022 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
7023 return r;
7024 }
7025
7026 #define GEN_VR_LDX(name, opc2, opc3) \
7027 static void glue(gen_, name)(DisasContext *ctx) \
7028 { \
7029 TCGv EA; \
7030 if (unlikely(!ctx->altivec_enabled)) { \
7031 gen_exception(ctx, POWERPC_EXCP_VPU); \
7032 return; \
7033 } \
7034 gen_set_access_type(ctx, ACCESS_INT); \
7035 EA = tcg_temp_new(); \
7036 gen_addr_reg_index(ctx, EA); \
7037 tcg_gen_andi_tl(EA, EA, ~0xf); \
7038 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
7039 64-bit byteswap already. */ \
7040 if (ctx->le_mode) { \
7041 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
7042 tcg_gen_addi_tl(EA, EA, 8); \
7043 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
7044 } else { \
7045 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
7046 tcg_gen_addi_tl(EA, EA, 8); \
7047 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
7048 } \
7049 tcg_temp_free(EA); \
7050 }
7051
7052 #define GEN_VR_STX(name, opc2, opc3) \
7053 static void gen_st##name(DisasContext *ctx) \
7054 { \
7055 TCGv EA; \
7056 if (unlikely(!ctx->altivec_enabled)) { \
7057 gen_exception(ctx, POWERPC_EXCP_VPU); \
7058 return; \
7059 } \
7060 gen_set_access_type(ctx, ACCESS_INT); \
7061 EA = tcg_temp_new(); \
7062 gen_addr_reg_index(ctx, EA); \
7063 tcg_gen_andi_tl(EA, EA, ~0xf); \
7064 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
7065 64-bit byteswap already. */ \
7066 if (ctx->le_mode) { \
7067 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
7068 tcg_gen_addi_tl(EA, EA, 8); \
7069 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
7070 } else { \
7071 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
7072 tcg_gen_addi_tl(EA, EA, 8); \
7073 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
7074 } \
7075 tcg_temp_free(EA); \
7076 }
7077
7078 #define GEN_VR_LVE(name, opc2, opc3, size) \
7079 static void gen_lve##name(DisasContext *ctx) \
7080 { \
7081 TCGv EA; \
7082 TCGv_ptr rs; \
7083 if (unlikely(!ctx->altivec_enabled)) { \
7084 gen_exception(ctx, POWERPC_EXCP_VPU); \
7085 return; \
7086 } \
7087 gen_set_access_type(ctx, ACCESS_INT); \
7088 EA = tcg_temp_new(); \
7089 gen_addr_reg_index(ctx, EA); \
7090 if (size > 1) { \
7091 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
7092 } \
7093 rs = gen_avr_ptr(rS(ctx->opcode)); \
7094 gen_helper_lve##name(cpu_env, rs, EA); \
7095 tcg_temp_free(EA); \
7096 tcg_temp_free_ptr(rs); \
7097 }
7098
7099 #define GEN_VR_STVE(name, opc2, opc3, size) \
7100 static void gen_stve##name(DisasContext *ctx) \
7101 { \
7102 TCGv EA; \
7103 TCGv_ptr rs; \
7104 if (unlikely(!ctx->altivec_enabled)) { \
7105 gen_exception(ctx, POWERPC_EXCP_VPU); \
7106 return; \
7107 } \
7108 gen_set_access_type(ctx, ACCESS_INT); \
7109 EA = tcg_temp_new(); \
7110 gen_addr_reg_index(ctx, EA); \
7111 if (size > 1) { \
7112 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
7113 } \
7114 rs = gen_avr_ptr(rS(ctx->opcode)); \
7115 gen_helper_stve##name(cpu_env, rs, EA); \
7116 tcg_temp_free(EA); \
7117 tcg_temp_free_ptr(rs); \
7118 }
7119
7120 GEN_VR_LDX(lvx, 0x07, 0x03);
7121 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
7122 GEN_VR_LDX(lvxl, 0x07, 0x0B);
7123
7124 GEN_VR_LVE(bx, 0x07, 0x00, 1);
7125 GEN_VR_LVE(hx, 0x07, 0x01, 2);
7126 GEN_VR_LVE(wx, 0x07, 0x02, 4);
7127
7128 GEN_VR_STX(svx, 0x07, 0x07);
7129 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
7130 GEN_VR_STX(svxl, 0x07, 0x0F);
7131
7132 GEN_VR_STVE(bx, 0x07, 0x04, 1);
7133 GEN_VR_STVE(hx, 0x07, 0x05, 2);
7134 GEN_VR_STVE(wx, 0x07, 0x06, 4);
7135
7136 static void gen_lvsl(DisasContext *ctx)
7137 {
7138 TCGv_ptr rd;
7139 TCGv EA;
7140 if (unlikely(!ctx->altivec_enabled)) {
7141 gen_exception(ctx, POWERPC_EXCP_VPU);
7142 return;
7143 }
7144 EA = tcg_temp_new();
7145 gen_addr_reg_index(ctx, EA);
7146 rd = gen_avr_ptr(rD(ctx->opcode));
7147 gen_helper_lvsl(rd, EA);
7148 tcg_temp_free(EA);
7149 tcg_temp_free_ptr(rd);
7150 }
7151
7152 static void gen_lvsr(DisasContext *ctx)
7153 {
7154 TCGv_ptr rd;
7155 TCGv EA;
7156 if (unlikely(!ctx->altivec_enabled)) {
7157 gen_exception(ctx, POWERPC_EXCP_VPU);
7158 return;
7159 }
7160 EA = tcg_temp_new();
7161 gen_addr_reg_index(ctx, EA);
7162 rd = gen_avr_ptr(rD(ctx->opcode));
7163 gen_helper_lvsr(rd, EA);
7164 tcg_temp_free(EA);
7165 tcg_temp_free_ptr(rd);
7166 }
7167
7168 static void gen_mfvscr(DisasContext *ctx)
7169 {
7170 TCGv_i32 t;
7171 if (unlikely(!ctx->altivec_enabled)) {
7172 gen_exception(ctx, POWERPC_EXCP_VPU);
7173 return;
7174 }
7175 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
7176 t = tcg_temp_new_i32();
7177 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
7178 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
7179 tcg_temp_free_i32(t);
7180 }
7181
7182 static void gen_mtvscr(DisasContext *ctx)
7183 {
7184 TCGv_ptr p;
7185 if (unlikely(!ctx->altivec_enabled)) {
7186 gen_exception(ctx, POWERPC_EXCP_VPU);
7187 return;
7188 }
7189 p = gen_avr_ptr(rB(ctx->opcode));
7190 gen_helper_mtvscr(cpu_env, p);
7191 tcg_temp_free_ptr(p);
7192 }
7193
7194 /* Logical operations */
7195 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
7196 static void glue(gen_, name)(DisasContext *ctx) \
7197 { \
7198 if (unlikely(!ctx->altivec_enabled)) { \
7199 gen_exception(ctx, POWERPC_EXCP_VPU); \
7200 return; \
7201 } \
7202 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
7203 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
7204 }
7205
7206 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
7207 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
7208 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
7209 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
7210 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
7211 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
7212 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
7213 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
7214
7215 #define GEN_VXFORM(name, opc2, opc3) \
7216 static void glue(gen_, name)(DisasContext *ctx) \
7217 { \
7218 TCGv_ptr ra, rb, rd; \
7219 if (unlikely(!ctx->altivec_enabled)) { \
7220 gen_exception(ctx, POWERPC_EXCP_VPU); \
7221 return; \
7222 } \
7223 ra = gen_avr_ptr(rA(ctx->opcode)); \
7224 rb = gen_avr_ptr(rB(ctx->opcode)); \
7225 rd = gen_avr_ptr(rD(ctx->opcode)); \
7226 gen_helper_##name (rd, ra, rb); \
7227 tcg_temp_free_ptr(ra); \
7228 tcg_temp_free_ptr(rb); \
7229 tcg_temp_free_ptr(rd); \
7230 }
7231
7232 #define GEN_VXFORM_ENV(name, opc2, opc3) \
7233 static void glue(gen_, name)(DisasContext *ctx) \
7234 { \
7235 TCGv_ptr ra, rb, rd; \
7236 if (unlikely(!ctx->altivec_enabled)) { \
7237 gen_exception(ctx, POWERPC_EXCP_VPU); \
7238 return; \
7239 } \
7240 ra = gen_avr_ptr(rA(ctx->opcode)); \
7241 rb = gen_avr_ptr(rB(ctx->opcode)); \
7242 rd = gen_avr_ptr(rD(ctx->opcode)); \
7243 gen_helper_##name(cpu_env, rd, ra, rb); \
7244 tcg_temp_free_ptr(ra); \
7245 tcg_temp_free_ptr(rb); \
7246 tcg_temp_free_ptr(rd); \
7247 }
7248
7249 #define GEN_VXFORM3(name, opc2, opc3) \
7250 static void glue(gen_, name)(DisasContext *ctx) \
7251 { \
7252 TCGv_ptr ra, rb, rc, rd; \
7253 if (unlikely(!ctx->altivec_enabled)) { \
7254 gen_exception(ctx, POWERPC_EXCP_VPU); \
7255 return; \
7256 } \
7257 ra = gen_avr_ptr(rA(ctx->opcode)); \
7258 rb = gen_avr_ptr(rB(ctx->opcode)); \
7259 rc = gen_avr_ptr(rC(ctx->opcode)); \
7260 rd = gen_avr_ptr(rD(ctx->opcode)); \
7261 gen_helper_##name(rd, ra, rb, rc); \
7262 tcg_temp_free_ptr(ra); \
7263 tcg_temp_free_ptr(rb); \
7264 tcg_temp_free_ptr(rc); \
7265 tcg_temp_free_ptr(rd); \
7266 }
7267
7268 /*
7269 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7270 * an opcode bit. In general, these pairs come from different
7271 * versions of the ISA, so we must also support a pair of flags for
7272 * each instruction.
7273 */
7274 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7275 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7276 { \
7277 if ((Rc(ctx->opcode) == 0) && \
7278 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7279 gen_##name0(ctx); \
7280 } else if ((Rc(ctx->opcode) == 1) && \
7281 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7282 gen_##name1(ctx); \
7283 } else { \
7284 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7285 } \
7286 }
7287
7288 GEN_VXFORM(vaddubm, 0, 0);
7289 GEN_VXFORM(vadduhm, 0, 1);
7290 GEN_VXFORM(vadduwm, 0, 2);
7291 GEN_VXFORM(vaddudm, 0, 3);
7292 GEN_VXFORM(vsububm, 0, 16);
7293 GEN_VXFORM(vsubuhm, 0, 17);
7294 GEN_VXFORM(vsubuwm, 0, 18);
7295 GEN_VXFORM(vsubudm, 0, 19);
7296 GEN_VXFORM(vmaxub, 1, 0);
7297 GEN_VXFORM(vmaxuh, 1, 1);
7298 GEN_VXFORM(vmaxuw, 1, 2);
7299 GEN_VXFORM(vmaxud, 1, 3);
7300 GEN_VXFORM(vmaxsb, 1, 4);
7301 GEN_VXFORM(vmaxsh, 1, 5);
7302 GEN_VXFORM(vmaxsw, 1, 6);
7303 GEN_VXFORM(vmaxsd, 1, 7);
7304 GEN_VXFORM(vminub, 1, 8);
7305 GEN_VXFORM(vminuh, 1, 9);
7306 GEN_VXFORM(vminuw, 1, 10);
7307 GEN_VXFORM(vminud, 1, 11);
7308 GEN_VXFORM(vminsb, 1, 12);
7309 GEN_VXFORM(vminsh, 1, 13);
7310 GEN_VXFORM(vminsw, 1, 14);
7311 GEN_VXFORM(vminsd, 1, 15);
7312 GEN_VXFORM(vavgub, 1, 16);
7313 GEN_VXFORM(vavguh, 1, 17);
7314 GEN_VXFORM(vavguw, 1, 18);
7315 GEN_VXFORM(vavgsb, 1, 20);
7316 GEN_VXFORM(vavgsh, 1, 21);
7317 GEN_VXFORM(vavgsw, 1, 22);
7318 GEN_VXFORM(vmrghb, 6, 0);
7319 GEN_VXFORM(vmrghh, 6, 1);
7320 GEN_VXFORM(vmrghw, 6, 2);
7321 GEN_VXFORM(vmrglb, 6, 4);
7322 GEN_VXFORM(vmrglh, 6, 5);
7323 GEN_VXFORM(vmrglw, 6, 6);
7324
7325 static void gen_vmrgew(DisasContext *ctx)
7326 {
7327 TCGv_i64 tmp;
7328 int VT, VA, VB;
7329 if (unlikely(!ctx->altivec_enabled)) {
7330 gen_exception(ctx, POWERPC_EXCP_VPU);
7331 return;
7332 }
7333 VT = rD(ctx->opcode);
7334 VA = rA(ctx->opcode);
7335 VB = rB(ctx->opcode);
7336 tmp = tcg_temp_new_i64();
7337 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7338 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7339 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7340 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7341 tcg_temp_free_i64(tmp);
7342 }
7343
7344 static void gen_vmrgow(DisasContext *ctx)
7345 {
7346 int VT, VA, VB;
7347 if (unlikely(!ctx->altivec_enabled)) {
7348 gen_exception(ctx, POWERPC_EXCP_VPU);
7349 return;
7350 }
7351 VT = rD(ctx->opcode);
7352 VA = rA(ctx->opcode);
7353 VB = rB(ctx->opcode);
7354
7355 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7356 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7357 }
7358
7359 GEN_VXFORM(vmuloub, 4, 0);
7360 GEN_VXFORM(vmulouh, 4, 1);
7361 GEN_VXFORM(vmulouw, 4, 2);
7362 GEN_VXFORM(vmuluwm, 4, 2);
7363 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7364 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7365 GEN_VXFORM(vmulosb, 4, 4);
7366 GEN_VXFORM(vmulosh, 4, 5);
7367 GEN_VXFORM(vmulosw, 4, 6);
7368 GEN_VXFORM(vmuleub, 4, 8);
7369 GEN_VXFORM(vmuleuh, 4, 9);
7370 GEN_VXFORM(vmuleuw, 4, 10);
7371 GEN_VXFORM(vmulesb, 4, 12);
7372 GEN_VXFORM(vmulesh, 4, 13);
7373 GEN_VXFORM(vmulesw, 4, 14);
7374 GEN_VXFORM(vslb, 2, 4);
7375 GEN_VXFORM(vslh, 2, 5);
7376 GEN_VXFORM(vslw, 2, 6);
7377 GEN_VXFORM(vsld, 2, 23);
7378 GEN_VXFORM(vsrb, 2, 8);
7379 GEN_VXFORM(vsrh, 2, 9);
7380 GEN_VXFORM(vsrw, 2, 10);
7381 GEN_VXFORM(vsrd, 2, 27);
7382 GEN_VXFORM(vsrab, 2, 12);
7383 GEN_VXFORM(vsrah, 2, 13);
7384 GEN_VXFORM(vsraw, 2, 14);
7385 GEN_VXFORM(vsrad, 2, 15);
7386 GEN_VXFORM(vslo, 6, 16);
7387 GEN_VXFORM(vsro, 6, 17);
7388 GEN_VXFORM(vaddcuw, 0, 6);
7389 GEN_VXFORM(vsubcuw, 0, 22);
7390 GEN_VXFORM_ENV(vaddubs, 0, 8);
7391 GEN_VXFORM_ENV(vadduhs, 0, 9);
7392 GEN_VXFORM_ENV(vadduws, 0, 10);
7393 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7394 GEN_VXFORM_ENV(vaddshs, 0, 13);
7395 GEN_VXFORM_ENV(vaddsws, 0, 14);
7396 GEN_VXFORM_ENV(vsububs, 0, 24);
7397 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7398 GEN_VXFORM_ENV(vsubuws, 0, 26);
7399 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7400 GEN_VXFORM_ENV(vsubshs, 0, 29);
7401 GEN_VXFORM_ENV(vsubsws, 0, 30);
7402 GEN_VXFORM(vadduqm, 0, 4);
7403 GEN_VXFORM(vaddcuq, 0, 5);
7404 GEN_VXFORM3(vaddeuqm, 30, 0);
7405 GEN_VXFORM3(vaddecuq, 30, 0);
7406 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7407 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7408 GEN_VXFORM(vsubuqm, 0, 20);
7409 GEN_VXFORM(vsubcuq, 0, 21);
7410 GEN_VXFORM3(vsubeuqm, 31, 0);
7411 GEN_VXFORM3(vsubecuq, 31, 0);
7412 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7413 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7414 GEN_VXFORM(vrlb, 2, 0);
7415 GEN_VXFORM(vrlh, 2, 1);
7416 GEN_VXFORM(vrlw, 2, 2);
7417 GEN_VXFORM(vrld, 2, 3);
7418 GEN_VXFORM(vsl, 2, 7);
7419 GEN_VXFORM(vsr, 2, 11);
7420 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7421 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7422 GEN_VXFORM_ENV(vpkudum, 7, 17);
7423 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7424 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7425 GEN_VXFORM_ENV(vpkudus, 7, 19);
7426 GEN_VXFORM_ENV(vpkshus, 7, 4);
7427 GEN_VXFORM_ENV(vpkswus, 7, 5);
7428 GEN_VXFORM_ENV(vpksdus, 7, 21);
7429 GEN_VXFORM_ENV(vpkshss, 7, 6);
7430 GEN_VXFORM_ENV(vpkswss, 7, 7);
7431 GEN_VXFORM_ENV(vpksdss, 7, 23);
7432 GEN_VXFORM(vpkpx, 7, 12);
7433 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7434 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7435 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7436 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7437 GEN_VXFORM_ENV(vsumsws, 4, 30);
7438 GEN_VXFORM_ENV(vaddfp, 5, 0);
7439 GEN_VXFORM_ENV(vsubfp, 5, 1);
7440 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7441 GEN_VXFORM_ENV(vminfp, 5, 17);
7442
7443 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7444 static void glue(gen_, name)(DisasContext *ctx) \
7445 { \
7446 TCGv_ptr ra, rb, rd; \
7447 if (unlikely(!ctx->altivec_enabled)) { \
7448 gen_exception(ctx, POWERPC_EXCP_VPU); \
7449 return; \
7450 } \
7451 ra = gen_avr_ptr(rA(ctx->opcode)); \
7452 rb = gen_avr_ptr(rB(ctx->opcode)); \
7453 rd = gen_avr_ptr(rD(ctx->opcode)); \
7454 gen_helper_##opname(cpu_env, rd, ra, rb); \
7455 tcg_temp_free_ptr(ra); \
7456 tcg_temp_free_ptr(rb); \
7457 tcg_temp_free_ptr(rd); \
7458 }
7459
7460 #define GEN_VXRFORM(name, opc2, opc3) \
7461 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7462 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7463
7464 /*
7465 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7466 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7467 * come from different versions of the ISA, so we must also support a
7468 * pair of flags for each instruction.
7469 */
7470 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7471 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7472 { \
7473 if ((Rc(ctx->opcode) == 0) && \
7474 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7475 if (Rc21(ctx->opcode) == 0) { \
7476 gen_##name0(ctx); \
7477 } else { \
7478 gen_##name0##_(ctx); \
7479 } \
7480 } else if ((Rc(ctx->opcode) == 1) && \
7481 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7482 if (Rc21(ctx->opcode) == 0) { \
7483 gen_##name1(ctx); \
7484 } else { \
7485 gen_##name1##_(ctx); \
7486 } \
7487 } else { \
7488 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7489 } \
7490 }
7491
7492 GEN_VXRFORM(vcmpequb, 3, 0)
7493 GEN_VXRFORM(vcmpequh, 3, 1)
7494 GEN_VXRFORM(vcmpequw, 3, 2)
7495 GEN_VXRFORM(vcmpequd, 3, 3)
7496 GEN_VXRFORM(vcmpgtsb, 3, 12)
7497 GEN_VXRFORM(vcmpgtsh, 3, 13)
7498 GEN_VXRFORM(vcmpgtsw, 3, 14)
7499 GEN_VXRFORM(vcmpgtsd, 3, 15)
7500 GEN_VXRFORM(vcmpgtub, 3, 8)
7501 GEN_VXRFORM(vcmpgtuh, 3, 9)
7502 GEN_VXRFORM(vcmpgtuw, 3, 10)
7503 GEN_VXRFORM(vcmpgtud, 3, 11)
7504 GEN_VXRFORM(vcmpeqfp, 3, 3)
7505 GEN_VXRFORM(vcmpgefp, 3, 7)
7506 GEN_VXRFORM(vcmpgtfp, 3, 11)
7507 GEN_VXRFORM(vcmpbfp, 3, 15)
7508
7509 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7510 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7511 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7512 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7513 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7514 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7515
7516 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7517 static void glue(gen_, name)(DisasContext *ctx) \
7518 { \
7519 TCGv_ptr rd; \
7520 TCGv_i32 simm; \
7521 if (unlikely(!ctx->altivec_enabled)) { \
7522 gen_exception(ctx, POWERPC_EXCP_VPU); \
7523 return; \
7524 } \
7525 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7526 rd = gen_avr_ptr(rD(ctx->opcode)); \
7527 gen_helper_##name (rd, simm); \
7528 tcg_temp_free_i32(simm); \
7529 tcg_temp_free_ptr(rd); \
7530 }
7531
7532 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7533 GEN_VXFORM_SIMM(vspltish, 6, 13);
7534 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7535
7536 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7537 static void glue(gen_, name)(DisasContext *ctx) \
7538 { \
7539 TCGv_ptr rb, rd; \
7540 if (unlikely(!ctx->altivec_enabled)) { \
7541 gen_exception(ctx, POWERPC_EXCP_VPU); \
7542 return; \
7543 } \
7544 rb = gen_avr_ptr(rB(ctx->opcode)); \
7545 rd = gen_avr_ptr(rD(ctx->opcode)); \
7546 gen_helper_##name (rd, rb); \
7547 tcg_temp_free_ptr(rb); \
7548 tcg_temp_free_ptr(rd); \
7549 }
7550
7551 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7552 static void glue(gen_, name)(DisasContext *ctx) \
7553 { \
7554 TCGv_ptr rb, rd; \
7555 \
7556 if (unlikely(!ctx->altivec_enabled)) { \
7557 gen_exception(ctx, POWERPC_EXCP_VPU); \
7558 return; \
7559 } \
7560 rb = gen_avr_ptr(rB(ctx->opcode)); \
7561 rd = gen_avr_ptr(rD(ctx->opcode)); \
7562 gen_helper_##name(cpu_env, rd, rb); \
7563 tcg_temp_free_ptr(rb); \
7564 tcg_temp_free_ptr(rd); \
7565 }
7566
7567 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7568 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7569 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7570 GEN_VXFORM_NOA(vupklsb, 7, 10);
7571 GEN_VXFORM_NOA(vupklsh, 7, 11);
7572 GEN_VXFORM_NOA(vupklsw, 7, 27);
7573 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7574 GEN_VXFORM_NOA(vupklpx, 7, 15);
7575 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7576 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7577 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7578 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7579 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7580 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
7581 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7582 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
7583
7584 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7585 static void glue(gen_, name)(DisasContext *ctx) \
7586 { \
7587 TCGv_ptr rd; \
7588 TCGv_i32 simm; \
7589 if (unlikely(!ctx->altivec_enabled)) { \
7590 gen_exception(ctx, POWERPC_EXCP_VPU); \
7591 return; \
7592 } \
7593 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7594 rd = gen_avr_ptr(rD(ctx->opcode)); \
7595 gen_helper_##name (rd, simm); \
7596 tcg_temp_free_i32(simm); \
7597 tcg_temp_free_ptr(rd); \
7598 }
7599
7600 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7601 static void glue(gen_, name)(DisasContext *ctx) \
7602 { \
7603 TCGv_ptr rb, rd; \
7604 TCGv_i32 uimm; \
7605 if (unlikely(!ctx->altivec_enabled)) { \
7606 gen_exception(ctx, POWERPC_EXCP_VPU); \
7607 return; \
7608 } \
7609 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7610 rb = gen_avr_ptr(rB(ctx->opcode)); \
7611 rd = gen_avr_ptr(rD(ctx->opcode)); \
7612 gen_helper_##name (rd, rb, uimm); \
7613 tcg_temp_free_i32(uimm); \
7614 tcg_temp_free_ptr(rb); \
7615 tcg_temp_free_ptr(rd); \
7616 }
7617
7618 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7619 static void glue(gen_, name)(DisasContext *ctx) \
7620 { \
7621 TCGv_ptr rb, rd; \
7622 TCGv_i32 uimm; \
7623 \
7624 if (unlikely(!ctx->altivec_enabled)) { \
7625 gen_exception(ctx, POWERPC_EXCP_VPU); \
7626 return; \
7627 } \
7628 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7629 rb = gen_avr_ptr(rB(ctx->opcode)); \
7630 rd = gen_avr_ptr(rD(ctx->opcode)); \
7631 gen_helper_##name(cpu_env, rd, rb, uimm); \
7632 tcg_temp_free_i32(uimm); \
7633 tcg_temp_free_ptr(rb); \
7634 tcg_temp_free_ptr(rd); \
7635 }
7636
7637 GEN_VXFORM_UIMM(vspltb, 6, 8);
7638 GEN_VXFORM_UIMM(vsplth, 6, 9);
7639 GEN_VXFORM_UIMM(vspltw, 6, 10);
7640 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7641 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7642 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7643 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7644
7645 static void gen_vsldoi(DisasContext *ctx)
7646 {
7647 TCGv_ptr ra, rb, rd;
7648 TCGv_i32 sh;
7649 if (unlikely(!ctx->altivec_enabled)) {
7650 gen_exception(ctx, POWERPC_EXCP_VPU);
7651 return;
7652 }
7653 ra = gen_avr_ptr(rA(ctx->opcode));
7654 rb = gen_avr_ptr(rB(ctx->opcode));
7655 rd = gen_avr_ptr(rD(ctx->opcode));
7656 sh = tcg_const_i32(VSH(ctx->opcode));
7657 gen_helper_vsldoi (rd, ra, rb, sh);
7658 tcg_temp_free_ptr(ra);
7659 tcg_temp_free_ptr(rb);
7660 tcg_temp_free_ptr(rd);
7661 tcg_temp_free_i32(sh);
7662 }
7663
7664 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7665 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7666 { \
7667 TCGv_ptr ra, rb, rc, rd; \
7668 if (unlikely(!ctx->altivec_enabled)) { \
7669 gen_exception(ctx, POWERPC_EXCP_VPU); \
7670 return; \
7671 } \
7672 ra = gen_avr_ptr(rA(ctx->opcode)); \
7673 rb = gen_avr_ptr(rB(ctx->opcode)); \
7674 rc = gen_avr_ptr(rC(ctx->opcode)); \
7675 rd = gen_avr_ptr(rD(ctx->opcode)); \
7676 if (Rc(ctx->opcode)) { \
7677 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7678 } else { \
7679 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7680 } \
7681 tcg_temp_free_ptr(ra); \
7682 tcg_temp_free_ptr(rb); \
7683 tcg_temp_free_ptr(rc); \
7684 tcg_temp_free_ptr(rd); \
7685 }
7686
7687 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7688
7689 static void gen_vmladduhm(DisasContext *ctx)
7690 {
7691 TCGv_ptr ra, rb, rc, rd;
7692 if (unlikely(!ctx->altivec_enabled)) {
7693 gen_exception(ctx, POWERPC_EXCP_VPU);
7694 return;
7695 }
7696 ra = gen_avr_ptr(rA(ctx->opcode));
7697 rb = gen_avr_ptr(rB(ctx->opcode));
7698 rc = gen_avr_ptr(rC(ctx->opcode));
7699 rd = gen_avr_ptr(rD(ctx->opcode));
7700 gen_helper_vmladduhm(rd, ra, rb, rc);
7701 tcg_temp_free_ptr(ra);
7702 tcg_temp_free_ptr(rb);
7703 tcg_temp_free_ptr(rc);
7704 tcg_temp_free_ptr(rd);
7705 }
7706
7707 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7708 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7709 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7710 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7711 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7712
7713 GEN_VXFORM_NOA(vclzb, 1, 28)
7714 GEN_VXFORM_NOA(vclzh, 1, 29)
7715 GEN_VXFORM_NOA(vclzw, 1, 30)
7716 GEN_VXFORM_NOA(vclzd, 1, 31)
7717 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7718 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7719 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7720 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7721 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7722 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7723 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7724 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7725 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7726 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7727 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7728 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7729 GEN_VXFORM(vbpermq, 6, 21);
7730 GEN_VXFORM_NOA(vgbbd, 6, 20);
7731 GEN_VXFORM(vpmsumb, 4, 16)
7732 GEN_VXFORM(vpmsumh, 4, 17)
7733 GEN_VXFORM(vpmsumw, 4, 18)
7734 GEN_VXFORM(vpmsumd, 4, 19)
7735
7736 #define GEN_BCD(op) \
7737 static void gen_##op(DisasContext *ctx) \
7738 { \
7739 TCGv_ptr ra, rb, rd; \
7740 TCGv_i32 ps; \
7741 \
7742 if (unlikely(!ctx->altivec_enabled)) { \
7743 gen_exception(ctx, POWERPC_EXCP_VPU); \
7744 return; \
7745 } \
7746 \
7747 ra = gen_avr_ptr(rA(ctx->opcode)); \
7748 rb = gen_avr_ptr(rB(ctx->opcode)); \
7749 rd = gen_avr_ptr(rD(ctx->opcode)); \
7750 \
7751 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7752 \
7753 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7754 \
7755 tcg_temp_free_ptr(ra); \
7756 tcg_temp_free_ptr(rb); \
7757 tcg_temp_free_ptr(rd); \
7758 tcg_temp_free_i32(ps); \
7759 }
7760
7761 GEN_BCD(bcdadd)
7762 GEN_BCD(bcdsub)
7763
7764 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7765 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7766 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7767 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7768 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7769 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7770 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7771 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7772
7773 static void gen_vsbox(DisasContext *ctx)
7774 {
7775 TCGv_ptr ra, rd;
7776 if (unlikely(!ctx->altivec_enabled)) {
7777 gen_exception(ctx, POWERPC_EXCP_VPU);
7778 return;
7779 }
7780 ra = gen_avr_ptr(rA(ctx->opcode));
7781 rd = gen_avr_ptr(rD(ctx->opcode));
7782 gen_helper_vsbox(rd, ra);
7783 tcg_temp_free_ptr(ra);
7784 tcg_temp_free_ptr(rd);
7785 }
7786
7787 GEN_VXFORM(vcipher, 4, 20)
7788 GEN_VXFORM(vcipherlast, 4, 20)
7789 GEN_VXFORM(vncipher, 4, 21)
7790 GEN_VXFORM(vncipherlast, 4, 21)
7791
7792 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7793 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7794 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7795 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7796
7797 #define VSHASIGMA(op) \
7798 static void gen_##op(DisasContext *ctx) \
7799 { \
7800 TCGv_ptr ra, rd; \
7801 TCGv_i32 st_six; \
7802 if (unlikely(!ctx->altivec_enabled)) { \
7803 gen_exception(ctx, POWERPC_EXCP_VPU); \
7804 return; \
7805 } \
7806 ra = gen_avr_ptr(rA(ctx->opcode)); \
7807 rd = gen_avr_ptr(rD(ctx->opcode)); \
7808 st_six = tcg_const_i32(rB(ctx->opcode)); \
7809 gen_helper_##op(rd, ra, st_six); \
7810 tcg_temp_free_ptr(ra); \
7811 tcg_temp_free_ptr(rd); \
7812 tcg_temp_free_i32(st_six); \
7813 }
7814
7815 VSHASIGMA(vshasigmaw)
7816 VSHASIGMA(vshasigmad)
7817
7818 GEN_VXFORM3(vpermxor, 22, 0xFF)
7819 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7820 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7821
7822 /*** VSX extension ***/
7823
7824 static inline TCGv_i64 cpu_vsrh(int n)
7825 {
7826 if (n < 32) {
7827 return cpu_fpr[n];
7828 } else {
7829 return cpu_avrh[n-32];
7830 }
7831 }
7832
7833 static inline TCGv_i64 cpu_vsrl(int n)
7834 {
7835 if (n < 32) {
7836 return cpu_vsr[n];
7837 } else {
7838 return cpu_avrl[n-32];
7839 }
7840 }
7841
7842 #define VSX_LOAD_SCALAR(name, operation) \
7843 static void gen_##name(DisasContext *ctx) \
7844 { \
7845 TCGv EA; \
7846 if (unlikely(!ctx->vsx_enabled)) { \
7847 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7848 return; \
7849 } \
7850 gen_set_access_type(ctx, ACCESS_INT); \
7851 EA = tcg_temp_new(); \
7852 gen_addr_reg_index(ctx, EA); \
7853 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7854 /* NOTE: cpu_vsrl is undefined */ \
7855 tcg_temp_free(EA); \
7856 }
7857
7858 VSX_LOAD_SCALAR(lxsdx, ld64)
7859 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7860 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7861 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7862
7863 static void gen_lxvd2x(DisasContext *ctx)
7864 {
7865 TCGv EA;
7866 if (unlikely(!ctx->vsx_enabled)) {
7867 gen_exception(ctx, POWERPC_EXCP_VSXU);
7868 return;
7869 }
7870 gen_set_access_type(ctx, ACCESS_INT);
7871 EA = tcg_temp_new();
7872 gen_addr_reg_index(ctx, EA);
7873 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7874 tcg_gen_addi_tl(EA, EA, 8);
7875 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7876 tcg_temp_free(EA);
7877 }
7878
7879 static void gen_lxvdsx(DisasContext *ctx)
7880 {
7881 TCGv EA;
7882 if (unlikely(!ctx->vsx_enabled)) {
7883 gen_exception(ctx, POWERPC_EXCP_VSXU);
7884 return;
7885 }
7886 gen_set_access_type(ctx, ACCESS_INT);
7887 EA = tcg_temp_new();
7888 gen_addr_reg_index(ctx, EA);
7889 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7890 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7891 tcg_temp_free(EA);
7892 }
7893
7894 static void gen_lxvw4x(DisasContext *ctx)
7895 {
7896 TCGv EA;
7897 TCGv_i64 tmp;
7898 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7899 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7900 if (unlikely(!ctx->vsx_enabled)) {
7901 gen_exception(ctx, POWERPC_EXCP_VSXU);
7902 return;
7903 }
7904 gen_set_access_type(ctx, ACCESS_INT);
7905 EA = tcg_temp_new();
7906 tmp = tcg_temp_new_i64();
7907
7908 gen_addr_reg_index(ctx, EA);
7909 gen_qemu_ld32u_i64(ctx, tmp, EA);
7910 tcg_gen_addi_tl(EA, EA, 4);
7911 gen_qemu_ld32u_i64(ctx, xth, EA);
7912 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7913
7914 tcg_gen_addi_tl(EA, EA, 4);
7915 gen_qemu_ld32u_i64(ctx, tmp, EA);
7916 tcg_gen_addi_tl(EA, EA, 4);
7917 gen_qemu_ld32u_i64(ctx, xtl, EA);
7918 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7919
7920 tcg_temp_free(EA);
7921 tcg_temp_free_i64(tmp);
7922 }
7923
7924 #define VSX_STORE_SCALAR(name, operation) \
7925 static void gen_##name(DisasContext *ctx) \
7926 { \
7927 TCGv EA; \
7928 if (unlikely(!ctx->vsx_enabled)) { \
7929 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7930 return; \
7931 } \
7932 gen_set_access_type(ctx, ACCESS_INT); \
7933 EA = tcg_temp_new(); \
7934 gen_addr_reg_index(ctx, EA); \
7935 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7936 tcg_temp_free(EA); \
7937 }
7938
7939 VSX_STORE_SCALAR(stxsdx, st64)
7940 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7941 VSX_STORE_SCALAR(stxsspx, st32fs)
7942
7943 static void gen_stxvd2x(DisasContext *ctx)
7944 {
7945 TCGv EA;
7946 if (unlikely(!ctx->vsx_enabled)) {
7947 gen_exception(ctx, POWERPC_EXCP_VSXU);
7948 return;
7949 }
7950 gen_set_access_type(ctx, ACCESS_INT);
7951 EA = tcg_temp_new();
7952 gen_addr_reg_index(ctx, EA);
7953 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7954 tcg_gen_addi_tl(EA, EA, 8);
7955 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7956 tcg_temp_free(EA);
7957 }
7958
7959 static void gen_stxvw4x(DisasContext *ctx)
7960 {
7961 TCGv_i64 tmp;
7962 TCGv EA;
7963 if (unlikely(!ctx->vsx_enabled)) {
7964 gen_exception(ctx, POWERPC_EXCP_VSXU);
7965 return;
7966 }
7967 gen_set_access_type(ctx, ACCESS_INT);
7968 EA = tcg_temp_new();
7969 gen_addr_reg_index(ctx, EA);
7970 tmp = tcg_temp_new_i64();
7971
7972 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7973 gen_qemu_st32_i64(ctx, tmp, EA);
7974 tcg_gen_addi_tl(EA, EA, 4);
7975 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7976
7977 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7978 tcg_gen_addi_tl(EA, EA, 4);
7979 gen_qemu_st32_i64(ctx, tmp, EA);
7980 tcg_gen_addi_tl(EA, EA, 4);
7981 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7982
7983 tcg_temp_free(EA);
7984 tcg_temp_free_i64(tmp);
7985 }
7986
7987 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7988 static void gen_##name(DisasContext *ctx) \
7989 { \
7990 if (xS(ctx->opcode) < 32) { \
7991 if (unlikely(!ctx->fpu_enabled)) { \
7992 gen_exception(ctx, POWERPC_EXCP_FPU); \
7993 return; \
7994 } \
7995 } else { \
7996 if (unlikely(!ctx->altivec_enabled)) { \
7997 gen_exception(ctx, POWERPC_EXCP_VPU); \
7998 return; \
7999 } \
8000 } \
8001 TCGv_i64 tmp = tcg_temp_new_i64(); \
8002 tcg_gen_##tcgop1(tmp, source); \
8003 tcg_gen_##tcgop2(target, tmp); \
8004 tcg_temp_free_i64(tmp); \
8005 }
8006
8007
8008 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
8009 cpu_vsrh(xS(ctx->opcode)))
8010 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
8011 cpu_gpr[rA(ctx->opcode)])
8012 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
8013 cpu_gpr[rA(ctx->opcode)])
8014
8015 #if defined(TARGET_PPC64)
8016 #define MV_VSRD(name, target, source) \
8017 static void gen_##name(DisasContext *ctx) \
8018 { \
8019 if (xS(ctx->opcode) < 32) { \
8020 if (unlikely(!ctx->fpu_enabled)) { \
8021 gen_exception(ctx, POWERPC_EXCP_FPU); \
8022 return; \
8023 } \
8024 } else { \
8025 if (unlikely(!ctx->altivec_enabled)) { \
8026 gen_exception(ctx, POWERPC_EXCP_VPU); \
8027 return; \
8028 } \
8029 } \
8030 tcg_gen_mov_i64(target, source); \
8031 }
8032
8033 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
8034 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
8035
8036 #endif
8037
8038 static void gen_xxpermdi(DisasContext *ctx)
8039 {
8040 if (unlikely(!ctx->vsx_enabled)) {
8041 gen_exception(ctx, POWERPC_EXCP_VSXU);
8042 return;
8043 }
8044
8045 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
8046 (xT(ctx->opcode) == xB(ctx->opcode)))) {
8047 TCGv_i64 xh, xl;
8048
8049 xh = tcg_temp_new_i64();
8050 xl = tcg_temp_new_i64();
8051
8052 if ((DM(ctx->opcode) & 2) == 0) {
8053 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
8054 } else {
8055 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
8056 }
8057 if ((DM(ctx->opcode) & 1) == 0) {
8058 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
8059 } else {
8060 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
8061 }
8062
8063 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
8064 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
8065
8066 tcg_temp_free_i64(xh);
8067 tcg_temp_free_i64(xl);
8068 } else {
8069 if ((DM(ctx->opcode) & 2) == 0) {
8070 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
8071 } else {
8072 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
8073 }
8074 if ((DM(ctx->opcode) & 1) == 0) {
8075 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
8076 } else {
8077 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
8078 }
8079 }
8080 }
8081
8082 #define OP_ABS 1
8083 #define OP_NABS 2
8084 #define OP_NEG 3
8085 #define OP_CPSGN 4
8086 #define SGN_MASK_DP 0x8000000000000000ull
8087 #define SGN_MASK_SP 0x8000000080000000ull
8088
8089 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
8090 static void glue(gen_, name)(DisasContext * ctx) \
8091 { \
8092 TCGv_i64 xb, sgm; \
8093 if (unlikely(!ctx->vsx_enabled)) { \
8094 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8095 return; \
8096 } \
8097 xb = tcg_temp_new_i64(); \
8098 sgm = tcg_temp_new_i64(); \
8099 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
8100 tcg_gen_movi_i64(sgm, sgn_mask); \
8101 switch (op) { \
8102 case OP_ABS: { \
8103 tcg_gen_andc_i64(xb, xb, sgm); \
8104 break; \
8105 } \
8106 case OP_NABS: { \
8107 tcg_gen_or_i64(xb, xb, sgm); \
8108 break; \
8109 } \
8110 case OP_NEG: { \
8111 tcg_gen_xor_i64(xb, xb, sgm); \
8112 break; \
8113 } \
8114 case OP_CPSGN: { \
8115 TCGv_i64 xa = tcg_temp_new_i64(); \
8116 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
8117 tcg_gen_and_i64(xa, xa, sgm); \
8118 tcg_gen_andc_i64(xb, xb, sgm); \
8119 tcg_gen_or_i64(xb, xb, xa); \
8120 tcg_temp_free_i64(xa); \
8121 break; \
8122 } \
8123 } \
8124 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
8125 tcg_temp_free_i64(xb); \
8126 tcg_temp_free_i64(sgm); \
8127 }
8128
8129 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
8130 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
8131 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
8132 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
8133
8134 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
8135 static void glue(gen_, name)(DisasContext * ctx) \
8136 { \
8137 TCGv_i64 xbh, xbl, sgm; \
8138 if (unlikely(!ctx->vsx_enabled)) { \
8139 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8140 return; \
8141 } \
8142 xbh = tcg_temp_new_i64(); \
8143 xbl = tcg_temp_new_i64(); \
8144 sgm = tcg_temp_new_i64(); \
8145 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
8146 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
8147 tcg_gen_movi_i64(sgm, sgn_mask); \
8148 switch (op) { \
8149 case OP_ABS: { \
8150 tcg_gen_andc_i64(xbh, xbh, sgm); \
8151 tcg_gen_andc_i64(xbl, xbl, sgm); \
8152 break; \
8153 } \
8154 case OP_NABS: { \
8155 tcg_gen_or_i64(xbh, xbh, sgm); \
8156 tcg_gen_or_i64(xbl, xbl, sgm); \
8157 break; \
8158 } \
8159 case OP_NEG: { \
8160 tcg_gen_xor_i64(xbh, xbh, sgm); \
8161 tcg_gen_xor_i64(xbl, xbl, sgm); \
8162 break; \
8163 } \
8164 case OP_CPSGN: { \
8165 TCGv_i64 xah = tcg_temp_new_i64(); \
8166 TCGv_i64 xal = tcg_temp_new_i64(); \
8167 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
8168 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
8169 tcg_gen_and_i64(xah, xah, sgm); \
8170 tcg_gen_and_i64(xal, xal, sgm); \
8171 tcg_gen_andc_i64(xbh, xbh, sgm); \
8172 tcg_gen_andc_i64(xbl, xbl, sgm); \
8173 tcg_gen_or_i64(xbh, xbh, xah); \
8174 tcg_gen_or_i64(xbl, xbl, xal); \
8175 tcg_temp_free_i64(xah); \
8176 tcg_temp_free_i64(xal); \
8177 break; \
8178 } \
8179 } \
8180 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
8181 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
8182 tcg_temp_free_i64(xbh); \
8183 tcg_temp_free_i64(xbl); \
8184 tcg_temp_free_i64(sgm); \
8185 }
8186
8187 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
8188 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
8189 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
8190 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
8191 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
8192 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
8193 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
8194 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
8195
8196 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
8197 static void gen_##name(DisasContext * ctx) \
8198 { \
8199 TCGv_i32 opc; \
8200 if (unlikely(!ctx->vsx_enabled)) { \
8201 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8202 return; \
8203 } \
8204 /* NIP cannot be restored if the memory exception comes from an helper */ \
8205 gen_update_nip(ctx, ctx->nip - 4); \
8206 opc = tcg_const_i32(ctx->opcode); \
8207 gen_helper_##name(cpu_env, opc); \
8208 tcg_temp_free_i32(opc); \
8209 }
8210
8211 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
8212 static void gen_##name(DisasContext * ctx) \
8213 { \
8214 if (unlikely(!ctx->vsx_enabled)) { \
8215 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8216 return; \
8217 } \
8218 /* NIP cannot be restored if the exception comes */ \
8219 /* from a helper. */ \
8220 gen_update_nip(ctx, ctx->nip - 4); \
8221 \
8222 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
8223 cpu_vsrh(xB(ctx->opcode))); \
8224 }
8225
8226 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
8227 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
8228 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
8229 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
8230 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
8231 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
8232 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
8233 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
8234 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
8235 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
8236 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
8237 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
8238 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
8239 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
8240 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
8241 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
8242 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
8243 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
8244 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
8245 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
8246 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
8247 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
8248 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
8249 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
8250 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
8251 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
8252 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
8253 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
8254 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
8255 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
8256 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
8257 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
8258 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
8259 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
8260 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
8261 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
8262 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
8263
8264 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
8265 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
8266 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
8267 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
8268 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
8269 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
8270 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
8271 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
8272 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
8273 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
8274 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
8275 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
8276 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
8277 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
8278 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
8279 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
8280 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
8281
8282 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
8283 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
8284 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
8285 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
8286 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
8287 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
8288 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
8289 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
8290 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
8291 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8292 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8293 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8294 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8295 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8296 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8297 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8298 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
8299 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8300 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
8301 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8302 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8303 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
8304 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
8305 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8306 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8307 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8308 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8309 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8310 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8311 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8312 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
8313 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8314 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8315 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8316 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8317 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
8318
8319 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8320 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
8321 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
8322 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
8323 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
8324 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
8325 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
8326 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
8327 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
8328 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8329 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8330 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8331 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8332 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8333 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8334 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8335 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
8336 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8337 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8338 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8339 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8340 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8341 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8342 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8343 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8344 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8345 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8346 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8347 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8348 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8349 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8350 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8351 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8352 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8353 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8354 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8355
8356 #define VSX_LOGICAL(name, tcg_op) \
8357 static void glue(gen_, name)(DisasContext * ctx) \
8358 { \
8359 if (unlikely(!ctx->vsx_enabled)) { \
8360 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8361 return; \
8362 } \
8363 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8364 cpu_vsrh(xB(ctx->opcode))); \
8365 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8366 cpu_vsrl(xB(ctx->opcode))); \
8367 }
8368
8369 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8370 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8371 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8372 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8373 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8374 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8375 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8376 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8377
8378 #define VSX_XXMRG(name, high) \
8379 static void glue(gen_, name)(DisasContext * ctx) \
8380 { \
8381 TCGv_i64 a0, a1, b0, b1; \
8382 if (unlikely(!ctx->vsx_enabled)) { \
8383 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8384 return; \
8385 } \
8386 a0 = tcg_temp_new_i64(); \
8387 a1 = tcg_temp_new_i64(); \
8388 b0 = tcg_temp_new_i64(); \
8389 b1 = tcg_temp_new_i64(); \
8390 if (high) { \
8391 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8392 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8393 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8394 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8395 } else { \
8396 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8397 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8398 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8399 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8400 } \
8401 tcg_gen_shri_i64(a0, a0, 32); \
8402 tcg_gen_shri_i64(b0, b0, 32); \
8403 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8404 b0, a0, 32, 32); \
8405 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8406 b1, a1, 32, 32); \
8407 tcg_temp_free_i64(a0); \
8408 tcg_temp_free_i64(a1); \
8409 tcg_temp_free_i64(b0); \
8410 tcg_temp_free_i64(b1); \
8411 }
8412
8413 VSX_XXMRG(xxmrghw, 1)
8414 VSX_XXMRG(xxmrglw, 0)
8415
8416 static void gen_xxsel(DisasContext * ctx)
8417 {
8418 TCGv_i64 a, b, c;
8419 if (unlikely(!ctx->vsx_enabled)) {
8420 gen_exception(ctx, POWERPC_EXCP_VSXU);
8421 return;
8422 }
8423 a = tcg_temp_new_i64();
8424 b = tcg_temp_new_i64();
8425 c = tcg_temp_new_i64();
8426
8427 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8428 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8429 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8430
8431 tcg_gen_and_i64(b, b, c);
8432 tcg_gen_andc_i64(a, a, c);
8433 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8434
8435 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8436 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8437 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8438
8439 tcg_gen_and_i64(b, b, c);
8440 tcg_gen_andc_i64(a, a, c);
8441 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8442
8443 tcg_temp_free_i64(a);
8444 tcg_temp_free_i64(b);
8445 tcg_temp_free_i64(c);
8446 }
8447
8448 static void gen_xxspltw(DisasContext *ctx)
8449 {
8450 TCGv_i64 b, b2;
8451 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8452 cpu_vsrl(xB(ctx->opcode)) :
8453 cpu_vsrh(xB(ctx->opcode));
8454
8455 if (unlikely(!ctx->vsx_enabled)) {
8456 gen_exception(ctx, POWERPC_EXCP_VSXU);
8457 return;
8458 }
8459
8460 b = tcg_temp_new_i64();
8461 b2 = tcg_temp_new_i64();
8462
8463 if (UIM(ctx->opcode) & 1) {
8464 tcg_gen_ext32u_i64(b, vsr);
8465 } else {
8466 tcg_gen_shri_i64(b, vsr, 32);
8467 }
8468
8469 tcg_gen_shli_i64(b2, b, 32);
8470 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8471 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8472
8473 tcg_temp_free_i64(b);
8474 tcg_temp_free_i64(b2);
8475 }
8476
8477 static void gen_xxsldwi(DisasContext *ctx)
8478 {
8479 TCGv_i64 xth, xtl;
8480 if (unlikely(!ctx->vsx_enabled)) {
8481 gen_exception(ctx, POWERPC_EXCP_VSXU);
8482 return;
8483 }
8484 xth = tcg_temp_new_i64();
8485 xtl = tcg_temp_new_i64();
8486
8487 switch (SHW(ctx->opcode)) {
8488 case 0: {
8489 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8490 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8491 break;
8492 }
8493 case 1: {
8494 TCGv_i64 t0 = tcg_temp_new_i64();
8495 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8496 tcg_gen_shli_i64(xth, xth, 32);
8497 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8498 tcg_gen_shri_i64(t0, t0, 32);
8499 tcg_gen_or_i64(xth, xth, t0);
8500 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8501 tcg_gen_shli_i64(xtl, xtl, 32);
8502 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8503 tcg_gen_shri_i64(t0, t0, 32);
8504 tcg_gen_or_i64(xtl, xtl, t0);
8505 tcg_temp_free_i64(t0);
8506 break;
8507 }
8508 case 2: {
8509 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8510 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8511 break;
8512 }
8513 case 3: {
8514 TCGv_i64 t0 = tcg_temp_new_i64();
8515 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8516 tcg_gen_shli_i64(xth, xth, 32);
8517 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8518 tcg_gen_shri_i64(t0, t0, 32);
8519 tcg_gen_or_i64(xth, xth, t0);
8520 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8521 tcg_gen_shli_i64(xtl, xtl, 32);
8522 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8523 tcg_gen_shri_i64(t0, t0, 32);
8524 tcg_gen_or_i64(xtl, xtl, t0);
8525 tcg_temp_free_i64(t0);
8526 break;
8527 }
8528 }
8529
8530 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8531 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8532
8533 tcg_temp_free_i64(xth);
8534 tcg_temp_free_i64(xtl);
8535 }
8536
8537 /*** Decimal Floating Point ***/
8538
8539 static inline TCGv_ptr gen_fprp_ptr(int reg)
8540 {
8541 TCGv_ptr r = tcg_temp_new_ptr();
8542 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8543 return r;
8544 }
8545
8546 #define GEN_DFP_T_A_B_Rc(name) \
8547 static void gen_##name(DisasContext *ctx) \
8548 { \
8549 TCGv_ptr rd, ra, rb; \
8550 if (unlikely(!ctx->fpu_enabled)) { \
8551 gen_exception(ctx, POWERPC_EXCP_FPU); \
8552 return; \
8553 } \
8554 gen_update_nip(ctx, ctx->nip - 4); \
8555 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8556 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8557 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8558 gen_helper_##name(cpu_env, rd, ra, rb); \
8559 if (unlikely(Rc(ctx->opcode) != 0)) { \
8560 gen_set_cr1_from_fpscr(ctx); \
8561 } \
8562 tcg_temp_free_ptr(rd); \
8563 tcg_temp_free_ptr(ra); \
8564 tcg_temp_free_ptr(rb); \
8565 }
8566
8567 #define GEN_DFP_BF_A_B(name) \
8568 static void gen_##name(DisasContext *ctx) \
8569 { \
8570 TCGv_ptr ra, rb; \
8571 if (unlikely(!ctx->fpu_enabled)) { \
8572 gen_exception(ctx, POWERPC_EXCP_FPU); \
8573 return; \
8574 } \
8575 gen_update_nip(ctx, ctx->nip - 4); \
8576 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8577 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8578 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8579 cpu_env, ra, rb); \
8580 tcg_temp_free_ptr(ra); \
8581 tcg_temp_free_ptr(rb); \
8582 }
8583
8584 #define GEN_DFP_BF_A_DCM(name) \
8585 static void gen_##name(DisasContext *ctx) \
8586 { \
8587 TCGv_ptr ra; \
8588 TCGv_i32 dcm; \
8589 if (unlikely(!ctx->fpu_enabled)) { \
8590 gen_exception(ctx, POWERPC_EXCP_FPU); \
8591 return; \
8592 } \
8593 gen_update_nip(ctx, ctx->nip - 4); \
8594 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8595 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8596 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8597 cpu_env, ra, dcm); \
8598 tcg_temp_free_ptr(ra); \
8599 tcg_temp_free_i32(dcm); \
8600 }
8601
8602 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8603 static void gen_##name(DisasContext *ctx) \
8604 { \
8605 TCGv_ptr rt, rb; \
8606 TCGv_i32 u32_1, u32_2; \
8607 if (unlikely(!ctx->fpu_enabled)) { \
8608 gen_exception(ctx, POWERPC_EXCP_FPU); \
8609 return; \
8610 } \
8611 gen_update_nip(ctx, ctx->nip - 4); \
8612 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8613 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8614 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8615 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8616 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8617 if (unlikely(Rc(ctx->opcode) != 0)) { \
8618 gen_set_cr1_from_fpscr(ctx); \
8619 } \
8620 tcg_temp_free_ptr(rt); \
8621 tcg_temp_free_ptr(rb); \
8622 tcg_temp_free_i32(u32_1); \
8623 tcg_temp_free_i32(u32_2); \
8624 }
8625
8626 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8627 static void gen_##name(DisasContext *ctx) \
8628 { \
8629 TCGv_ptr rt, ra, rb; \
8630 TCGv_i32 i32; \
8631 if (unlikely(!ctx->fpu_enabled)) { \
8632 gen_exception(ctx, POWERPC_EXCP_FPU); \
8633 return; \
8634 } \
8635 gen_update_nip(ctx, ctx->nip - 4); \
8636 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8637 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8638 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8639 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8640 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8641 if (unlikely(Rc(ctx->opcode) != 0)) { \
8642 gen_set_cr1_from_fpscr(ctx); \
8643 } \
8644 tcg_temp_free_ptr(rt); \
8645 tcg_temp_free_ptr(rb); \
8646 tcg_temp_free_ptr(ra); \
8647 tcg_temp_free_i32(i32); \
8648 }
8649
8650 #define GEN_DFP_T_B_Rc(name) \
8651 static void gen_##name(DisasContext *ctx) \
8652 { \
8653 TCGv_ptr rt, rb; \
8654 if (unlikely(!ctx->fpu_enabled)) { \
8655 gen_exception(ctx, POWERPC_EXCP_FPU); \
8656 return; \
8657 } \
8658 gen_update_nip(ctx, ctx->nip - 4); \
8659 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8660 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8661 gen_helper_##name(cpu_env, rt, rb); \
8662 if (unlikely(Rc(ctx->opcode) != 0)) { \
8663 gen_set_cr1_from_fpscr(ctx); \
8664 } \
8665 tcg_temp_free_ptr(rt); \
8666 tcg_temp_free_ptr(rb); \
8667 }
8668
8669 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8670 static void gen_##name(DisasContext *ctx) \
8671 { \
8672 TCGv_ptr rt, rs; \
8673 TCGv_i32 i32; \
8674 if (unlikely(!ctx->fpu_enabled)) { \
8675 gen_exception(ctx, POWERPC_EXCP_FPU); \
8676 return; \
8677 } \
8678 gen_update_nip(ctx, ctx->nip - 4); \
8679 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8680 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8681 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8682 gen_helper_##name(cpu_env, rt, rs, i32); \
8683 if (unlikely(Rc(ctx->opcode) != 0)) { \
8684 gen_set_cr1_from_fpscr(ctx); \
8685 } \
8686 tcg_temp_free_ptr(rt); \
8687 tcg_temp_free_ptr(rs); \
8688 tcg_temp_free_i32(i32); \
8689 }
8690
8691 GEN_DFP_T_A_B_Rc(dadd)
8692 GEN_DFP_T_A_B_Rc(daddq)
8693 GEN_DFP_T_A_B_Rc(dsub)
8694 GEN_DFP_T_A_B_Rc(dsubq)
8695 GEN_DFP_T_A_B_Rc(dmul)
8696 GEN_DFP_T_A_B_Rc(dmulq)
8697 GEN_DFP_T_A_B_Rc(ddiv)
8698 GEN_DFP_T_A_B_Rc(ddivq)
8699 GEN_DFP_BF_A_B(dcmpu)
8700 GEN_DFP_BF_A_B(dcmpuq)
8701 GEN_DFP_BF_A_B(dcmpo)
8702 GEN_DFP_BF_A_B(dcmpoq)
8703 GEN_DFP_BF_A_DCM(dtstdc)
8704 GEN_DFP_BF_A_DCM(dtstdcq)
8705 GEN_DFP_BF_A_DCM(dtstdg)
8706 GEN_DFP_BF_A_DCM(dtstdgq)
8707 GEN_DFP_BF_A_B(dtstex)
8708 GEN_DFP_BF_A_B(dtstexq)
8709 GEN_DFP_BF_A_B(dtstsf)
8710 GEN_DFP_BF_A_B(dtstsfq)
8711 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8712 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8713 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8714 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8715 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8716 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8717 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8718 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8719 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8720 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8721 GEN_DFP_T_B_Rc(dctdp)
8722 GEN_DFP_T_B_Rc(dctqpq)
8723 GEN_DFP_T_B_Rc(drsp)
8724 GEN_DFP_T_B_Rc(drdpq)
8725 GEN_DFP_T_B_Rc(dcffix)
8726 GEN_DFP_T_B_Rc(dcffixq)
8727 GEN_DFP_T_B_Rc(dctfix)
8728 GEN_DFP_T_B_Rc(dctfixq)
8729 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8730 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8731 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8732 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8733 GEN_DFP_T_B_Rc(dxex)
8734 GEN_DFP_T_B_Rc(dxexq)
8735 GEN_DFP_T_A_B_Rc(diex)
8736 GEN_DFP_T_A_B_Rc(diexq)
8737 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8738 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8739 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8740 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8741
8742 /*** SPE extension ***/
8743 /* Register moves */
8744
8745 static inline void gen_evmra(DisasContext *ctx)
8746 {
8747
8748 if (unlikely(!ctx->spe_enabled)) {
8749 gen_exception(ctx, POWERPC_EXCP_SPEU);
8750 return;
8751 }
8752
8753 TCGv_i64 tmp = tcg_temp_new_i64();
8754
8755 /* tmp := rA_lo + rA_hi << 32 */
8756 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8757
8758 /* spe_acc := tmp */
8759 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8760 tcg_temp_free_i64(tmp);
8761
8762 /* rD := rA */
8763 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8764 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8765 }
8766
8767 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8768 {
8769 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8770 }
8771
8772 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8773 {
8774 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8775 }
8776
8777 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8778 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8779 { \
8780 if (Rc(ctx->opcode)) \
8781 gen_##name1(ctx); \
8782 else \
8783 gen_##name0(ctx); \
8784 }
8785
8786 /* Handler for undefined SPE opcodes */
8787 static inline void gen_speundef(DisasContext *ctx)
8788 {
8789 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8790 }
8791
8792 /* SPE logic */
8793 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8794 static inline void gen_##name(DisasContext *ctx) \
8795 { \
8796 if (unlikely(!ctx->spe_enabled)) { \
8797 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8798 return; \
8799 } \
8800 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8801 cpu_gpr[rB(ctx->opcode)]); \
8802 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8803 cpu_gprh[rB(ctx->opcode)]); \
8804 }
8805
8806 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8807 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8808 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8809 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8810 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8811 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8812 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8813 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8814
8815 /* SPE logic immediate */
8816 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8817 static inline void gen_##name(DisasContext *ctx) \
8818 { \
8819 TCGv_i32 t0; \
8820 if (unlikely(!ctx->spe_enabled)) { \
8821 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8822 return; \
8823 } \
8824 t0 = tcg_temp_new_i32(); \
8825 \
8826 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8827 tcg_opi(t0, t0, rB(ctx->opcode)); \
8828 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8829 \
8830 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8831 tcg_opi(t0, t0, rB(ctx->opcode)); \
8832 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8833 \
8834 tcg_temp_free_i32(t0); \
8835 }
8836 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8837 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8838 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8839 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8840
8841 /* SPE arithmetic */
8842 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8843 static inline void gen_##name(DisasContext *ctx) \
8844 { \
8845 TCGv_i32 t0; \
8846 if (unlikely(!ctx->spe_enabled)) { \
8847 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8848 return; \
8849 } \
8850 t0 = tcg_temp_new_i32(); \
8851 \
8852 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8853 tcg_op(t0, t0); \
8854 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8855 \
8856 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8857 tcg_op(t0, t0); \
8858 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8859 \
8860 tcg_temp_free_i32(t0); \
8861 }
8862
8863 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8864 {
8865 TCGLabel *l1 = gen_new_label();
8866 TCGLabel *l2 = gen_new_label();
8867
8868 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8869 tcg_gen_neg_i32(ret, arg1);
8870 tcg_gen_br(l2);
8871 gen_set_label(l1);
8872 tcg_gen_mov_i32(ret, arg1);
8873 gen_set_label(l2);
8874 }
8875 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8876 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8877 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8878 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8879 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8880 {
8881 tcg_gen_addi_i32(ret, arg1, 0x8000);
8882 tcg_gen_ext16u_i32(ret, ret);
8883 }
8884 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8885 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8886 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8887
8888 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8889 static inline void gen_##name(DisasContext *ctx) \
8890 { \
8891 TCGv_i32 t0, t1; \
8892 if (unlikely(!ctx->spe_enabled)) { \
8893 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8894 return; \
8895 } \
8896 t0 = tcg_temp_new_i32(); \
8897 t1 = tcg_temp_new_i32(); \
8898 \
8899 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8900 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8901 tcg_op(t0, t0, t1); \
8902 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8903 \
8904 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8905 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8906 tcg_op(t0, t0, t1); \
8907 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8908 \
8909 tcg_temp_free_i32(t0); \
8910 tcg_temp_free_i32(t1); \
8911 }
8912
8913 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8914 {
8915 TCGLabel *l1 = gen_new_label();
8916 TCGLabel *l2 = gen_new_label();
8917 TCGv_i32 t0 = tcg_temp_local_new_i32();
8918
8919 /* No error here: 6 bits are used */
8920 tcg_gen_andi_i32(t0, arg2, 0x3F);
8921 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8922 tcg_gen_shr_i32(ret, arg1, t0);
8923 tcg_gen_br(l2);
8924 gen_set_label(l1);
8925 tcg_gen_movi_i32(ret, 0);
8926 gen_set_label(l2);
8927 tcg_temp_free_i32(t0);
8928 }
8929 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8930 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8931 {
8932 TCGLabel *l1 = gen_new_label();
8933 TCGLabel *l2 = gen_new_label();
8934 TCGv_i32 t0 = tcg_temp_local_new_i32();
8935
8936 /* No error here: 6 bits are used */
8937 tcg_gen_andi_i32(t0, arg2, 0x3F);
8938 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8939 tcg_gen_sar_i32(ret, arg1, t0);
8940 tcg_gen_br(l2);
8941 gen_set_label(l1);
8942 tcg_gen_movi_i32(ret, 0);
8943 gen_set_label(l2);
8944 tcg_temp_free_i32(t0);
8945 }
8946 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8947 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8948 {
8949 TCGLabel *l1 = gen_new_label();
8950 TCGLabel *l2 = gen_new_label();
8951 TCGv_i32 t0 = tcg_temp_local_new_i32();
8952
8953 /* No error here: 6 bits are used */
8954 tcg_gen_andi_i32(t0, arg2, 0x3F);
8955 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8956 tcg_gen_shl_i32(ret, arg1, t0);
8957 tcg_gen_br(l2);
8958 gen_set_label(l1);
8959 tcg_gen_movi_i32(ret, 0);
8960 gen_set_label(l2);
8961 tcg_temp_free_i32(t0);
8962 }
8963 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8964 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8965 {
8966 TCGv_i32 t0 = tcg_temp_new_i32();
8967 tcg_gen_andi_i32(t0, arg2, 0x1F);
8968 tcg_gen_rotl_i32(ret, arg1, t0);
8969 tcg_temp_free_i32(t0);
8970 }
8971 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8972 static inline void gen_evmergehi(DisasContext *ctx)
8973 {
8974 if (unlikely(!ctx->spe_enabled)) {
8975 gen_exception(ctx, POWERPC_EXCP_SPEU);
8976 return;
8977 }
8978 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8979 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8980 }
8981 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8982 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8983 {
8984 tcg_gen_sub_i32(ret, arg2, arg1);
8985 }
8986 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8987
8988 /* SPE arithmetic immediate */
8989 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8990 static inline void gen_##name(DisasContext *ctx) \
8991 { \
8992 TCGv_i32 t0; \
8993 if (unlikely(!ctx->spe_enabled)) { \
8994 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8995 return; \
8996 } \
8997 t0 = tcg_temp_new_i32(); \
8998 \
8999 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9000 tcg_op(t0, t0, rA(ctx->opcode)); \
9001 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9002 \
9003 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
9004 tcg_op(t0, t0, rA(ctx->opcode)); \
9005 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
9006 \
9007 tcg_temp_free_i32(t0); \
9008 }
9009 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
9010 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
9011
9012 /* SPE comparison */
9013 #define GEN_SPEOP_COMP(name, tcg_cond) \
9014 static inline void gen_##name(DisasContext *ctx) \
9015 { \
9016 if (unlikely(!ctx->spe_enabled)) { \
9017 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9018 return; \
9019 } \
9020 TCGLabel *l1 = gen_new_label(); \
9021 TCGLabel *l2 = gen_new_label(); \
9022 TCGLabel *l3 = gen_new_label(); \
9023 TCGLabel *l4 = gen_new_label(); \
9024 \
9025 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
9026 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9027 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
9028 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
9029 \
9030 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
9031 cpu_gpr[rB(ctx->opcode)], l1); \
9032 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
9033 tcg_gen_br(l2); \
9034 gen_set_label(l1); \
9035 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
9036 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
9037 gen_set_label(l2); \
9038 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
9039 cpu_gprh[rB(ctx->opcode)], l3); \
9040 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
9041 ~(CRF_CH | CRF_CH_AND_CL)); \
9042 tcg_gen_br(l4); \
9043 gen_set_label(l3); \
9044 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
9045 CRF_CH | CRF_CH_OR_CL); \
9046 gen_set_label(l4); \
9047 }
9048 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
9049 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
9050 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
9051 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
9052 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
9053
9054 /* SPE misc */
9055 static inline void gen_brinc(DisasContext *ctx)
9056 {
9057 /* Note: brinc is usable even if SPE is disabled */
9058 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
9059 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
9060 }
9061 static inline void gen_evmergelo(DisasContext *ctx)
9062 {
9063 if (unlikely(!ctx->spe_enabled)) {
9064 gen_exception(ctx, POWERPC_EXCP_SPEU);
9065 return;
9066 }
9067 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9068 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
9069 }
9070 static inline void gen_evmergehilo(DisasContext *ctx)
9071 {
9072 if (unlikely(!ctx->spe_enabled)) {
9073 gen_exception(ctx, POWERPC_EXCP_SPEU);
9074 return;
9075 }
9076 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
9077 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
9078 }
9079 static inline void gen_evmergelohi(DisasContext *ctx)
9080 {
9081 if (unlikely(!ctx->spe_enabled)) {
9082 gen_exception(ctx, POWERPC_EXCP_SPEU);
9083 return;
9084 }
9085 if (rD(ctx->opcode) == rA(ctx->opcode)) {
9086 TCGv tmp = tcg_temp_new();
9087 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
9088 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
9089 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
9090 tcg_temp_free(tmp);
9091 } else {
9092 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
9093 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9094 }
9095 }
9096 static inline void gen_evsplati(DisasContext *ctx)
9097 {
9098 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
9099
9100 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
9101 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
9102 }
9103 static inline void gen_evsplatfi(DisasContext *ctx)
9104 {
9105 uint64_t imm = rA(ctx->opcode) << 27;
9106
9107 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
9108 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
9109 }
9110
9111 static inline void gen_evsel(DisasContext *ctx)
9112 {
9113 TCGLabel *l1 = gen_new_label();
9114 TCGLabel *l2 = gen_new_label();
9115 TCGLabel *l3 = gen_new_label();
9116 TCGLabel *l4 = gen_new_label();
9117 TCGv_i32 t0 = tcg_temp_local_new_i32();
9118
9119 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
9120 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
9121 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
9122 tcg_gen_br(l2);
9123 gen_set_label(l1);
9124 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
9125 gen_set_label(l2);
9126 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
9127 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
9128 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9129 tcg_gen_br(l4);
9130 gen_set_label(l3);
9131 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
9132 gen_set_label(l4);
9133 tcg_temp_free_i32(t0);
9134 }
9135
9136 static void gen_evsel0(DisasContext *ctx)
9137 {
9138 gen_evsel(ctx);
9139 }
9140
9141 static void gen_evsel1(DisasContext *ctx)
9142 {
9143 gen_evsel(ctx);
9144 }
9145
9146 static void gen_evsel2(DisasContext *ctx)
9147 {
9148 gen_evsel(ctx);
9149 }
9150
9151 static void gen_evsel3(DisasContext *ctx)
9152 {
9153 gen_evsel(ctx);
9154 }
9155
9156 /* Multiply */
9157
9158 static inline void gen_evmwumi(DisasContext *ctx)
9159 {
9160 TCGv_i64 t0, t1;
9161
9162 if (unlikely(!ctx->spe_enabled)) {
9163 gen_exception(ctx, POWERPC_EXCP_SPEU);
9164 return;
9165 }
9166
9167 t0 = tcg_temp_new_i64();
9168 t1 = tcg_temp_new_i64();
9169
9170 /* t0 := rA; t1 := rB */
9171 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9172 tcg_gen_ext32u_i64(t0, t0);
9173 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9174 tcg_gen_ext32u_i64(t1, t1);
9175
9176 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9177
9178 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9179
9180 tcg_temp_free_i64(t0);
9181 tcg_temp_free_i64(t1);
9182 }
9183
9184 static inline void gen_evmwumia(DisasContext *ctx)
9185 {
9186 TCGv_i64 tmp;
9187
9188 if (unlikely(!ctx->spe_enabled)) {
9189 gen_exception(ctx, POWERPC_EXCP_SPEU);
9190 return;
9191 }
9192
9193 gen_evmwumi(ctx); /* rD := rA * rB */
9194
9195 tmp = tcg_temp_new_i64();
9196
9197 /* acc := rD */
9198 gen_load_gpr64(tmp, rD(ctx->opcode));
9199 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
9200 tcg_temp_free_i64(tmp);
9201 }
9202
9203 static inline void gen_evmwumiaa(DisasContext *ctx)
9204 {
9205 TCGv_i64 acc;
9206 TCGv_i64 tmp;
9207
9208 if (unlikely(!ctx->spe_enabled)) {
9209 gen_exception(ctx, POWERPC_EXCP_SPEU);
9210 return;
9211 }
9212
9213 gen_evmwumi(ctx); /* rD := rA * rB */
9214
9215 acc = tcg_temp_new_i64();
9216 tmp = tcg_temp_new_i64();
9217
9218 /* tmp := rD */
9219 gen_load_gpr64(tmp, rD(ctx->opcode));
9220
9221 /* Load acc */
9222 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9223
9224 /* acc := tmp + acc */
9225 tcg_gen_add_i64(acc, acc, tmp);
9226
9227 /* Store acc */
9228 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9229
9230 /* rD := acc */
9231 gen_store_gpr64(rD(ctx->opcode), acc);
9232
9233 tcg_temp_free_i64(acc);
9234 tcg_temp_free_i64(tmp);
9235 }
9236
9237 static inline void gen_evmwsmi(DisasContext *ctx)
9238 {
9239 TCGv_i64 t0, t1;
9240
9241 if (unlikely(!ctx->spe_enabled)) {
9242 gen_exception(ctx, POWERPC_EXCP_SPEU);
9243 return;
9244 }
9245
9246 t0 = tcg_temp_new_i64();
9247 t1 = tcg_temp_new_i64();
9248
9249 /* t0 := rA; t1 := rB */
9250 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9251 tcg_gen_ext32s_i64(t0, t0);
9252 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9253 tcg_gen_ext32s_i64(t1, t1);
9254
9255 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9256
9257 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9258
9259 tcg_temp_free_i64(t0);
9260 tcg_temp_free_i64(t1);
9261 }
9262
9263 static inline void gen_evmwsmia(DisasContext *ctx)
9264 {
9265 TCGv_i64 tmp;
9266
9267 gen_evmwsmi(ctx); /* rD := rA * rB */
9268
9269 tmp = tcg_temp_new_i64();
9270
9271 /* acc := rD */
9272 gen_load_gpr64(tmp, rD(ctx->opcode));
9273 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
9274
9275 tcg_temp_free_i64(tmp);
9276 }
9277
9278 static inline void gen_evmwsmiaa(DisasContext *ctx)
9279 {
9280 TCGv_i64 acc = tcg_temp_new_i64();
9281 TCGv_i64 tmp = tcg_temp_new_i64();
9282
9283 gen_evmwsmi(ctx); /* rD := rA * rB */
9284
9285 acc = tcg_temp_new_i64();
9286 tmp = tcg_temp_new_i64();
9287
9288 /* tmp := rD */
9289 gen_load_gpr64(tmp, rD(ctx->opcode));
9290
9291 /* Load acc */
9292 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9293
9294 /* acc := tmp + acc */
9295 tcg_gen_add_i64(acc, acc, tmp);
9296
9297 /* Store acc */
9298 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9299
9300 /* rD := acc */
9301 gen_store_gpr64(rD(ctx->opcode), acc);
9302
9303 tcg_temp_free_i64(acc);
9304 tcg_temp_free_i64(tmp);
9305 }
9306
9307 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9308 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9309 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9310 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9311 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9312 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9313 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9314 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9315 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9316 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9317 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9318 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9319 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9320 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9321 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9322 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9323 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9324 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9325 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9326 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9327 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9328 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9329 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9330 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9331 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9332 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9333 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9334 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9335 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9336
9337 /* SPE load and stores */
9338 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9339 {
9340 target_ulong uimm = rB(ctx->opcode);
9341
9342 if (rA(ctx->opcode) == 0) {
9343 tcg_gen_movi_tl(EA, uimm << sh);
9344 } else {
9345 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9346 if (NARROW_MODE(ctx)) {
9347 tcg_gen_ext32u_tl(EA, EA);
9348 }
9349 }
9350 }
9351
9352 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9353 {
9354 TCGv_i64 t0 = tcg_temp_new_i64();
9355 gen_qemu_ld64(ctx, t0, addr);
9356 gen_store_gpr64(rD(ctx->opcode), t0);
9357 tcg_temp_free_i64(t0);
9358 }
9359
9360 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9361 {
9362 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9363 gen_addr_add(ctx, addr, addr, 4);
9364 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9365 }
9366
9367 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9368 {
9369 TCGv t0 = tcg_temp_new();
9370 gen_qemu_ld16u(ctx, t0, addr);
9371 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9372 gen_addr_add(ctx, addr, addr, 2);
9373 gen_qemu_ld16u(ctx, t0, addr);
9374 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9375 gen_addr_add(ctx, addr, addr, 2);
9376 gen_qemu_ld16u(ctx, t0, addr);
9377 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9378 gen_addr_add(ctx, addr, addr, 2);
9379 gen_qemu_ld16u(ctx, t0, addr);
9380 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9381 tcg_temp_free(t0);
9382 }
9383
9384 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9385 {
9386 TCGv t0 = tcg_temp_new();
9387 gen_qemu_ld16u(ctx, t0, addr);
9388 tcg_gen_shli_tl(t0, t0, 16);
9389 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9390 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9391 tcg_temp_free(t0);
9392 }
9393
9394 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9395 {
9396 TCGv t0 = tcg_temp_new();
9397 gen_qemu_ld16u(ctx, t0, addr);
9398 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9399 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9400 tcg_temp_free(t0);
9401 }
9402
9403 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9404 {
9405 TCGv t0 = tcg_temp_new();
9406 gen_qemu_ld16s(ctx, t0, addr);
9407 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9408 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9409 tcg_temp_free(t0);
9410 }
9411
9412 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9413 {
9414 TCGv t0 = tcg_temp_new();
9415 gen_qemu_ld16u(ctx, t0, addr);
9416 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9417 gen_addr_add(ctx, addr, addr, 2);
9418 gen_qemu_ld16u(ctx, t0, addr);
9419 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9420 tcg_temp_free(t0);
9421 }
9422
9423 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9424 {
9425 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9426 gen_addr_add(ctx, addr, addr, 2);
9427 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9428 }
9429
9430 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9431 {
9432 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9433 gen_addr_add(ctx, addr, addr, 2);
9434 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9435 }
9436
9437 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9438 {
9439 TCGv t0 = tcg_temp_new();
9440 gen_qemu_ld32u(ctx, t0, addr);
9441 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9442 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9443 tcg_temp_free(t0);
9444 }
9445
9446 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9447 {
9448 TCGv t0 = tcg_temp_new();
9449 gen_qemu_ld16u(ctx, t0, addr);
9450 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9451 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9452 gen_addr_add(ctx, addr, addr, 2);
9453 gen_qemu_ld16u(ctx, t0, addr);
9454 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9455 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9456 tcg_temp_free(t0);
9457 }
9458
9459 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9460 {
9461 TCGv_i64 t0 = tcg_temp_new_i64();
9462 gen_load_gpr64(t0, rS(ctx->opcode));
9463 gen_qemu_st64(ctx, t0, addr);
9464 tcg_temp_free_i64(t0);
9465 }
9466
9467 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9468 {
9469 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9470 gen_addr_add(ctx, addr, addr, 4);
9471 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9472 }
9473
9474 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9475 {
9476 TCGv t0 = tcg_temp_new();
9477 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9478 gen_qemu_st16(ctx, t0, addr);
9479 gen_addr_add(ctx, addr, addr, 2);
9480 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9481 gen_addr_add(ctx, addr, addr, 2);
9482 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9483 gen_qemu_st16(ctx, t0, addr);
9484 tcg_temp_free(t0);
9485 gen_addr_add(ctx, addr, addr, 2);
9486 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9487 }
9488
9489 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9490 {
9491 TCGv t0 = tcg_temp_new();
9492 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9493 gen_qemu_st16(ctx, t0, addr);
9494 gen_addr_add(ctx, addr, addr, 2);
9495 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9496 gen_qemu_st16(ctx, t0, addr);
9497 tcg_temp_free(t0);
9498 }
9499
9500 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9501 {
9502 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9503 gen_addr_add(ctx, addr, addr, 2);
9504 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9505 }
9506
9507 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9508 {
9509 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9510 }
9511
9512 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9513 {
9514 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9515 }
9516
9517 #define GEN_SPEOP_LDST(name, opc2, sh) \
9518 static void glue(gen_, name)(DisasContext *ctx) \
9519 { \
9520 TCGv t0; \
9521 if (unlikely(!ctx->spe_enabled)) { \
9522 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9523 return; \
9524 } \
9525 gen_set_access_type(ctx, ACCESS_INT); \
9526 t0 = tcg_temp_new(); \
9527 if (Rc(ctx->opcode)) { \
9528 gen_addr_spe_imm_index(ctx, t0, sh); \
9529 } else { \
9530 gen_addr_reg_index(ctx, t0); \
9531 } \
9532 gen_op_##name(ctx, t0); \
9533 tcg_temp_free(t0); \
9534 }
9535
9536 GEN_SPEOP_LDST(evldd, 0x00, 3);
9537 GEN_SPEOP_LDST(evldw, 0x01, 3);
9538 GEN_SPEOP_LDST(evldh, 0x02, 3);
9539 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9540 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9541 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9542 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9543 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9544 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9545 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9546 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9547
9548 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9549 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9550 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9551 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9552 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9553 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9554 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9555
9556 /* Multiply and add - TODO */
9557 #if 0
9558 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9559 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9560 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9561 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9562 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9563 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9564 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9565 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9566 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9567 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9568 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9569 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9570
9571 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9572 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9573 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9574 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9575 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9576 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9577 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9578 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9579 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9580 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9581 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9582 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9583
9584 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9585 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9586 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9587 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9588 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9589
9590 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9591 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9592 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9593 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9594 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9595 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9596 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9597 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9598 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9599 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9600 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9601 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9602
9603 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9604 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9605 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9606 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9607
9608 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9609 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9610 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9611 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9612 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9613 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9614 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9615 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9616 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9617 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9618 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9619 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9620
9621 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9622 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9623 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9624 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9625 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9626 #endif
9627
9628 /*** SPE floating-point extension ***/
9629 #define GEN_SPEFPUOP_CONV_32_32(name) \
9630 static inline void gen_##name(DisasContext *ctx) \
9631 { \
9632 TCGv_i32 t0 = tcg_temp_new_i32(); \
9633 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9634 gen_helper_##name(t0, cpu_env, t0); \
9635 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9636 tcg_temp_free_i32(t0); \
9637 }
9638 #define GEN_SPEFPUOP_CONV_32_64(name) \
9639 static inline void gen_##name(DisasContext *ctx) \
9640 { \
9641 TCGv_i64 t0 = tcg_temp_new_i64(); \
9642 TCGv_i32 t1 = tcg_temp_new_i32(); \
9643 gen_load_gpr64(t0, rB(ctx->opcode)); \
9644 gen_helper_##name(t1, cpu_env, t0); \
9645 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9646 tcg_temp_free_i64(t0); \
9647 tcg_temp_free_i32(t1); \
9648 }
9649 #define GEN_SPEFPUOP_CONV_64_32(name) \
9650 static inline void gen_##name(DisasContext *ctx) \
9651 { \
9652 TCGv_i64 t0 = tcg_temp_new_i64(); \
9653 TCGv_i32 t1 = tcg_temp_new_i32(); \
9654 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9655 gen_helper_##name(t0, cpu_env, t1); \
9656 gen_store_gpr64(rD(ctx->opcode), t0); \
9657 tcg_temp_free_i64(t0); \
9658 tcg_temp_free_i32(t1); \
9659 }
9660 #define GEN_SPEFPUOP_CONV_64_64(name) \
9661 static inline void gen_##name(DisasContext *ctx) \
9662 { \
9663 TCGv_i64 t0 = tcg_temp_new_i64(); \
9664 gen_load_gpr64(t0, rB(ctx->opcode)); \
9665 gen_helper_##name(t0, cpu_env, t0); \
9666 gen_store_gpr64(rD(ctx->opcode), t0); \
9667 tcg_temp_free_i64(t0); \
9668 }
9669 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9670 static inline void gen_##name(DisasContext *ctx) \
9671 { \
9672 TCGv_i32 t0, t1; \
9673 if (unlikely(!ctx->spe_enabled)) { \
9674 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9675 return; \
9676 } \
9677 t0 = tcg_temp_new_i32(); \
9678 t1 = tcg_temp_new_i32(); \
9679 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9680 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9681 gen_helper_##name(t0, cpu_env, t0, t1); \
9682 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9683 \
9684 tcg_temp_free_i32(t0); \
9685 tcg_temp_free_i32(t1); \
9686 }
9687 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9688 static inline void gen_##name(DisasContext *ctx) \
9689 { \
9690 TCGv_i64 t0, t1; \
9691 if (unlikely(!ctx->spe_enabled)) { \
9692 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9693 return; \
9694 } \
9695 t0 = tcg_temp_new_i64(); \
9696 t1 = tcg_temp_new_i64(); \
9697 gen_load_gpr64(t0, rA(ctx->opcode)); \
9698 gen_load_gpr64(t1, rB(ctx->opcode)); \
9699 gen_helper_##name(t0, cpu_env, t0, t1); \
9700 gen_store_gpr64(rD(ctx->opcode), t0); \
9701 tcg_temp_free_i64(t0); \
9702 tcg_temp_free_i64(t1); \
9703 }
9704 #define GEN_SPEFPUOP_COMP_32(name) \
9705 static inline void gen_##name(DisasContext *ctx) \
9706 { \
9707 TCGv_i32 t0, t1; \
9708 if (unlikely(!ctx->spe_enabled)) { \
9709 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9710 return; \
9711 } \
9712 t0 = tcg_temp_new_i32(); \
9713 t1 = tcg_temp_new_i32(); \
9714 \
9715 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9716 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9717 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9718 \
9719 tcg_temp_free_i32(t0); \
9720 tcg_temp_free_i32(t1); \
9721 }
9722 #define GEN_SPEFPUOP_COMP_64(name) \
9723 static inline void gen_##name(DisasContext *ctx) \
9724 { \
9725 TCGv_i64 t0, t1; \
9726 if (unlikely(!ctx->spe_enabled)) { \
9727 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9728 return; \
9729 } \
9730 t0 = tcg_temp_new_i64(); \
9731 t1 = tcg_temp_new_i64(); \
9732 gen_load_gpr64(t0, rA(ctx->opcode)); \
9733 gen_load_gpr64(t1, rB(ctx->opcode)); \
9734 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9735 tcg_temp_free_i64(t0); \
9736 tcg_temp_free_i64(t1); \
9737 }
9738
9739 /* Single precision floating-point vectors operations */
9740 /* Arithmetic */
9741 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9742 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9743 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9744 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9745 static inline void gen_evfsabs(DisasContext *ctx)
9746 {
9747 if (unlikely(!ctx->spe_enabled)) {
9748 gen_exception(ctx, POWERPC_EXCP_SPEU);
9749 return;
9750 }
9751 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9752 ~0x80000000);
9753 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9754 ~0x80000000);
9755 }
9756 static inline void gen_evfsnabs(DisasContext *ctx)
9757 {
9758 if (unlikely(!ctx->spe_enabled)) {
9759 gen_exception(ctx, POWERPC_EXCP_SPEU);
9760 return;
9761 }
9762 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9763 0x80000000);
9764 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9765 0x80000000);
9766 }
9767 static inline void gen_evfsneg(DisasContext *ctx)
9768 {
9769 if (unlikely(!ctx->spe_enabled)) {
9770 gen_exception(ctx, POWERPC_EXCP_SPEU);
9771 return;
9772 }
9773 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9774 0x80000000);
9775 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9776 0x80000000);
9777 }
9778
9779 /* Conversion */
9780 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9781 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9782 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9783 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9784 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9785 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9786 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9787 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9788 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9789 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9790
9791 /* Comparison */
9792 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9793 GEN_SPEFPUOP_COMP_64(evfscmplt);
9794 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9795 GEN_SPEFPUOP_COMP_64(evfststgt);
9796 GEN_SPEFPUOP_COMP_64(evfststlt);
9797 GEN_SPEFPUOP_COMP_64(evfststeq);
9798
9799 /* Opcodes definitions */
9800 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9801 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9802 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9803 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9804 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9805 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9806 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9807 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9808 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9809 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9810 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9811 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9812 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9813 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9814
9815 /* Single precision floating-point operations */
9816 /* Arithmetic */
9817 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9818 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9819 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9820 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9821 static inline void gen_efsabs(DisasContext *ctx)
9822 {
9823 if (unlikely(!ctx->spe_enabled)) {
9824 gen_exception(ctx, POWERPC_EXCP_SPEU);
9825 return;
9826 }
9827 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9828 }
9829 static inline void gen_efsnabs(DisasContext *ctx)
9830 {
9831 if (unlikely(!ctx->spe_enabled)) {
9832 gen_exception(ctx, POWERPC_EXCP_SPEU);
9833 return;
9834 }
9835 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9836 }
9837 static inline void gen_efsneg(DisasContext *ctx)
9838 {
9839 if (unlikely(!ctx->spe_enabled)) {
9840 gen_exception(ctx, POWERPC_EXCP_SPEU);
9841 return;
9842 }
9843 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9844 }
9845
9846 /* Conversion */
9847 GEN_SPEFPUOP_CONV_32_32(efscfui);
9848 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9849 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9850 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9851 GEN_SPEFPUOP_CONV_32_32(efsctui);
9852 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9853 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9854 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9855 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9856 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9857 GEN_SPEFPUOP_CONV_32_64(efscfd);
9858
9859 /* Comparison */
9860 GEN_SPEFPUOP_COMP_32(efscmpgt);
9861 GEN_SPEFPUOP_COMP_32(efscmplt);
9862 GEN_SPEFPUOP_COMP_32(efscmpeq);
9863 GEN_SPEFPUOP_COMP_32(efststgt);
9864 GEN_SPEFPUOP_COMP_32(efststlt);
9865 GEN_SPEFPUOP_COMP_32(efststeq);
9866
9867 /* Opcodes definitions */
9868 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9869 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9870 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9871 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9872 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9873 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9874 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9875 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9876 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9877 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9878 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9879 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9880 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9881 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9882
9883 /* Double precision floating-point operations */
9884 /* Arithmetic */
9885 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9886 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9887 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9888 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9889 static inline void gen_efdabs(DisasContext *ctx)
9890 {
9891 if (unlikely(!ctx->spe_enabled)) {
9892 gen_exception(ctx, POWERPC_EXCP_SPEU);
9893 return;
9894 }
9895 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9896 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9897 ~0x80000000);
9898 }
9899 static inline void gen_efdnabs(DisasContext *ctx)
9900 {
9901 if (unlikely(!ctx->spe_enabled)) {
9902 gen_exception(ctx, POWERPC_EXCP_SPEU);
9903 return;
9904 }
9905 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9906 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9907 0x80000000);
9908 }
9909 static inline void gen_efdneg(DisasContext *ctx)
9910 {
9911 if (unlikely(!ctx->spe_enabled)) {
9912 gen_exception(ctx, POWERPC_EXCP_SPEU);
9913 return;
9914 }
9915 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9916 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9917 0x80000000);
9918 }
9919
9920 /* Conversion */
9921 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9922 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9923 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9924 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9925 GEN_SPEFPUOP_CONV_32_64(efdctui);
9926 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9927 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9928 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9929 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9930 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9931 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9932 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9933 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9934 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9935 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9936
9937 /* Comparison */
9938 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9939 GEN_SPEFPUOP_COMP_64(efdcmplt);
9940 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9941 GEN_SPEFPUOP_COMP_64(efdtstgt);
9942 GEN_SPEFPUOP_COMP_64(efdtstlt);
9943 GEN_SPEFPUOP_COMP_64(efdtsteq);
9944
9945 /* Opcodes definitions */
9946 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9947 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9948 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9949 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9950 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9951 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9952 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9953 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9954 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9955 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9956 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9957 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9958 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9959 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9960 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9961 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9962
9963 static void gen_tbegin(DisasContext *ctx)
9964 {
9965 if (unlikely(!ctx->tm_enabled)) {
9966 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9967 return;
9968 }
9969 gen_helper_tbegin(cpu_env);
9970 }
9971
9972 #define GEN_TM_NOOP(name) \
9973 static inline void gen_##name(DisasContext *ctx) \
9974 { \
9975 if (unlikely(!ctx->tm_enabled)) { \
9976 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9977 return; \
9978 } \
9979 /* Because tbegin always fails in QEMU, these user \
9980 * space instructions all have a simple implementation: \
9981 * \
9982 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9983 * = 0b0 || 0b00 || 0b0 \
9984 */ \
9985 tcg_gen_movi_i32(cpu_crf[0], 0); \
9986 }
9987
9988 GEN_TM_NOOP(tend);
9989 GEN_TM_NOOP(tabort);
9990 GEN_TM_NOOP(tabortwc);
9991 GEN_TM_NOOP(tabortwci);
9992 GEN_TM_NOOP(tabortdc);
9993 GEN_TM_NOOP(tabortdci);
9994 GEN_TM_NOOP(tsr);
9995
9996 static void gen_tcheck(DisasContext *ctx)
9997 {
9998 if (unlikely(!ctx->tm_enabled)) {
9999 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
10000 return;
10001 }
10002 /* Because tbegin always fails, the tcheck implementation
10003 * is simple:
10004 *
10005 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
10006 * = 0b1 || 0b00 || 0b0
10007 */
10008 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
10009 }
10010
10011 #if defined(CONFIG_USER_ONLY)
10012 #define GEN_TM_PRIV_NOOP(name) \
10013 static inline void gen_##name(DisasContext *ctx) \
10014 { \
10015 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
10016 }
10017
10018 #else
10019
10020 #define GEN_TM_PRIV_NOOP(name) \
10021 static inline void gen_##name(DisasContext *ctx) \
10022 { \
10023 CHK_SV; \
10024 if (unlikely(!ctx->tm_enabled)) { \
10025 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
10026 return; \
10027 } \
10028 /* Because tbegin always fails, the implementation is \
10029 * simple: \
10030 * \
10031 * CR[0] = 0b0 || MSR[TS] || 0b0 \
10032 * = 0b0 || 0b00 | 0b0 \
10033 */ \
10034 tcg_gen_movi_i32(cpu_crf[0], 0); \
10035 }
10036
10037 #endif
10038
10039 GEN_TM_PRIV_NOOP(treclaim);
10040 GEN_TM_PRIV_NOOP(trechkpt);
10041
10042 static opcode_t opcodes[] = {
10043 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
10044 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
10045 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
10046 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
10047 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
10048 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
10049 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
10050 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
10051 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10052 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10053 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10054 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10055 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
10056 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
10057 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
10058 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
10059 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
10060 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10061 #if defined(TARGET_PPC64)
10062 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
10063 #endif
10064 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
10065 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
10066 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10067 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10068 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10069 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
10070 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
10071 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
10072 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
10073 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10074 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10075 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10076 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10077 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
10078 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
10079 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
10080 #if defined(TARGET_PPC64)
10081 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
10082 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
10083 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
10084 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
10085 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
10086 #endif
10087 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10088 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10089 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10090 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
10091 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
10092 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
10093 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
10094 #if defined(TARGET_PPC64)
10095 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
10096 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
10097 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
10098 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
10099 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
10100 #endif
10101 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
10102 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
10103 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
10104 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
10105 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
10106 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
10107 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
10108 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
10109 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
10110 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
10111 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
10112 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
10113 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
10114 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
10115 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
10116 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
10117 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
10118 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
10119 #if defined(TARGET_PPC64)
10120 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
10121 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
10122 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
10123 #endif
10124 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10125 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
10126 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
10127 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
10128 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
10129 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
10130 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
10131 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
10132 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
10133 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
10134 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
10135 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
10136 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
10137 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
10138 #if defined(TARGET_PPC64)
10139 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
10140 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
10141 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
10142 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
10143 #endif
10144 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
10145 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
10146 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
10147 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
10148 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
10149 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
10150 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
10151 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
10152 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
10153 #if defined(TARGET_PPC64)
10154 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
10155 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
10156 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
10157 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
10158 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
10159 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
10160 #endif
10161 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
10162 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
10163 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
10164 #if defined(TARGET_PPC64)
10165 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
10166 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
10167 #endif
10168 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
10169 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
10170 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
10171 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
10172 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
10173 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
10174 #if defined(TARGET_PPC64)
10175 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
10176 #endif
10177 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
10178 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
10179 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
10180 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
10181 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
10182 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
10183 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
10184 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
10185 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
10186 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
10187 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
10188 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
10189 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
10190 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
10191 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
10192 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
10193 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
10194 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
10195 #if defined(TARGET_PPC64)
10196 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
10197 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
10198 PPC_SEGMENT_64B),
10199 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
10200 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
10201 PPC_SEGMENT_64B),
10202 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
10203 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
10204 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
10205 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
10206 #endif
10207 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
10208 /* XXX Those instructions will need to be handled differently for
10209 * different ISA versions */
10210 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
10211 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
10212 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
10213 #if defined(TARGET_PPC64)
10214 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
10215 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
10216 #endif
10217 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
10218 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
10219 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
10220 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
10221 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
10222 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
10223 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
10224 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
10225 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
10226 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
10227 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
10228 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10229 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
10230 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
10231 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
10232 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
10233 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
10234 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
10235 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
10236 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10237 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
10238 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
10239 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
10240 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
10241 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
10242 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
10243 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
10244 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
10245 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
10246 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
10247 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
10248 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
10249 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
10250 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
10251 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
10252 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
10253 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
10254 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
10255 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
10256 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
10257 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
10258 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
10259 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
10260 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
10261 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
10262 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
10263 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
10264 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
10265 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
10266 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10267 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10268 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
10269 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
10270 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10271 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10272 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
10273 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
10274 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
10275 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
10276 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
10277 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
10278 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
10279 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
10280 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
10281 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
10282 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
10283 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
10284 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10285 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10286 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10287 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
10288 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
10289 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10290 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10291 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10292 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10293 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10294 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10295 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10296 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
10297 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10298 PPC_NONE, PPC2_BOOKE206),
10299 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10300 PPC_NONE, PPC2_BOOKE206),
10301 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10302 PPC_NONE, PPC2_BOOKE206),
10303 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10304 PPC_NONE, PPC2_BOOKE206),
10305 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10306 PPC_NONE, PPC2_BOOKE206),
10307 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10308 PPC_NONE, PPC2_PRCNTL),
10309 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10310 PPC_NONE, PPC2_PRCNTL),
10311 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
10312 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
10313 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
10314 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10315 PPC_BOOKE, PPC2_BOOKE206),
10316 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
10317 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10318 PPC_BOOKE, PPC2_BOOKE206),
10319 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10320 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10321 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10322 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
10323 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10324 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10325 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10326 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10327 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10328
10329 #undef GEN_INT_ARITH_ADD
10330 #undef GEN_INT_ARITH_ADD_CONST
10331 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10332 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10333 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10334 add_ca, compute_ca, compute_ov) \
10335 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10336 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10337 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10338 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10339 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10340 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10341 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10342 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10343 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10344 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10345 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10346
10347 #undef GEN_INT_ARITH_DIVW
10348 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10349 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10350 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10351 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10352 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10353 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10354 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10355 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10356 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10357 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10358 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
10359 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
10360
10361 #if defined(TARGET_PPC64)
10362 #undef GEN_INT_ARITH_DIVD
10363 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10364 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10365 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10366 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10367 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10368 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10369
10370 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10371 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10372 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10373 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10374 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
10375 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
10376
10377 #undef GEN_INT_ARITH_MUL_HELPER
10378 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10379 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10380 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10381 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10382 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10383 #endif
10384
10385 #undef GEN_INT_ARITH_SUBF
10386 #undef GEN_INT_ARITH_SUBF_CONST
10387 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10388 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10389 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10390 add_ca, compute_ca, compute_ov) \
10391 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10392 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10393 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10394 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10395 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10396 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10397 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10398 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10399 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10400 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10401 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10402
10403 #undef GEN_LOGICAL1
10404 #undef GEN_LOGICAL2
10405 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10406 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10407 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10408 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10409 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10410 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10411 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10412 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10413 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10414 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10415 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10416 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10417 #if defined(TARGET_PPC64)
10418 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10419 #endif
10420
10421 #if defined(TARGET_PPC64)
10422 #undef GEN_PPC64_R2
10423 #undef GEN_PPC64_R4
10424 #define GEN_PPC64_R2(name, opc1, opc2) \
10425 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10426 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10427 PPC_64B)
10428 #define GEN_PPC64_R4(name, opc1, opc2) \
10429 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10430 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10431 PPC_64B), \
10432 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10433 PPC_64B), \
10434 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10435 PPC_64B)
10436 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10437 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10438 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10439 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10440 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10441 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10442 #endif
10443
10444 #undef _GEN_FLOAT_ACB
10445 #undef GEN_FLOAT_ACB
10446 #undef _GEN_FLOAT_AB
10447 #undef GEN_FLOAT_AB
10448 #undef _GEN_FLOAT_AC
10449 #undef GEN_FLOAT_AC
10450 #undef GEN_FLOAT_B
10451 #undef GEN_FLOAT_BS
10452 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10453 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10454 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10455 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10456 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10457 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10458 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10459 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10460 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10461 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10462 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10463 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10464 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10465 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10466 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10467 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10468 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10469 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10470 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10471
10472 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10473 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10474 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10475 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10476 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10477 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10478 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10479 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10480 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10481 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10482 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10483 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10484 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10485 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10486 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10487 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10488 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10489 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10490 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10491 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10492 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10493 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10494 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10495 GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10496 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10497 GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10498 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10499 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10500 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10501 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10502 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10503
10504 #undef GEN_LD
10505 #undef GEN_LDU
10506 #undef GEN_LDUX
10507 #undef GEN_LDX_E
10508 #undef GEN_LDS
10509 #define GEN_LD(name, ldop, opc, type) \
10510 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10511 #define GEN_LDU(name, ldop, opc, type) \
10512 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10513 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10514 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10515 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
10516 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10517 #define GEN_LDS(name, ldop, op, type) \
10518 GEN_LD(name, ldop, op | 0x20, type) \
10519 GEN_LDU(name, ldop, op | 0x21, type) \
10520 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10521 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10522
10523 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10524 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10525 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10526 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10527 #if defined(TARGET_PPC64)
10528 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10529 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10530 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10531 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10532 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
10533
10534 /* HV/P7 and later only */
10535 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
10536 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
10537 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
10538 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
10539 #endif
10540 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10541 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10542
10543 #undef GEN_ST
10544 #undef GEN_STU
10545 #undef GEN_STUX
10546 #undef GEN_STX_E
10547 #undef GEN_STS
10548 #define GEN_ST(name, stop, opc, type) \
10549 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10550 #define GEN_STU(name, stop, opc, type) \
10551 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10552 #define GEN_STUX(name, stop, opc2, opc3, type) \
10553 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10554 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
10555 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10556 #define GEN_STS(name, stop, op, type) \
10557 GEN_ST(name, stop, op | 0x20, type) \
10558 GEN_STU(name, stop, op | 0x21, type) \
10559 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10560 GEN_STX(name, stop, 0x17, op | 0x00, type)
10561
10562 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10563 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10564 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10565 #if defined(TARGET_PPC64)
10566 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10567 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10568 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
10569 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
10570 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
10571 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
10572 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
10573 #endif
10574 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10575 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10576
10577 #undef GEN_LDF
10578 #undef GEN_LDUF
10579 #undef GEN_LDUXF
10580 #undef GEN_LDXF
10581 #undef GEN_LDFS
10582 #define GEN_LDF(name, ldop, opc, type) \
10583 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10584 #define GEN_LDUF(name, ldop, opc, type) \
10585 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10586 #define GEN_LDUXF(name, ldop, opc, type) \
10587 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10588 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10589 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10590 #define GEN_LDFS(name, ldop, op, type) \
10591 GEN_LDF(name, ldop, op | 0x20, type) \
10592 GEN_LDUF(name, ldop, op | 0x21, type) \
10593 GEN_LDUXF(name, ldop, op | 0x01, type) \
10594 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10595
10596 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10597 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10598 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10599 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10600 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10601 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10602
10603 #undef GEN_STF
10604 #undef GEN_STUF
10605 #undef GEN_STUXF
10606 #undef GEN_STXF
10607 #undef GEN_STFS
10608 #define GEN_STF(name, stop, opc, type) \
10609 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10610 #define GEN_STUF(name, stop, opc, type) \
10611 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10612 #define GEN_STUXF(name, stop, opc, type) \
10613 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10614 #define GEN_STXF(name, stop, opc2, opc3, type) \
10615 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10616 #define GEN_STFS(name, stop, op, type) \
10617 GEN_STF(name, stop, op | 0x20, type) \
10618 GEN_STUF(name, stop, op | 0x21, type) \
10619 GEN_STUXF(name, stop, op | 0x01, type) \
10620 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10621
10622 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10623 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10624 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10625 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10626 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10627
10628 #undef GEN_CRLOGIC
10629 #define GEN_CRLOGIC(name, tcg_op, opc) \
10630 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10631 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10632 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10633 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10634 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10635 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10636 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10637 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10638 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10639
10640 #undef GEN_MAC_HANDLER
10641 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10642 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10643 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10644 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10645 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10646 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10647 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10648 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10649 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10650 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10651 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10652 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10653 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10654 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10655 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10656 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10657 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10658 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10659 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10660 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10661 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10662 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10663 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10664 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10665 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10666 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10667 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10668 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10669 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10670 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10671 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10672 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10673 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10674 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10675 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10676 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10677 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10678 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10679 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10680 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10681 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10682 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10683 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10684 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10685
10686 #undef GEN_VR_LDX
10687 #undef GEN_VR_STX
10688 #undef GEN_VR_LVE
10689 #undef GEN_VR_STVE
10690 #define GEN_VR_LDX(name, opc2, opc3) \
10691 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10692 #define GEN_VR_STX(name, opc2, opc3) \
10693 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10694 #define GEN_VR_LVE(name, opc2, opc3) \
10695 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10696 #define GEN_VR_STVE(name, opc2, opc3) \
10697 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10698 GEN_VR_LDX(lvx, 0x07, 0x03),
10699 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10700 GEN_VR_LVE(bx, 0x07, 0x00),
10701 GEN_VR_LVE(hx, 0x07, 0x01),
10702 GEN_VR_LVE(wx, 0x07, 0x02),
10703 GEN_VR_STX(svx, 0x07, 0x07),
10704 GEN_VR_STX(svxl, 0x07, 0x0F),
10705 GEN_VR_STVE(bx, 0x07, 0x04),
10706 GEN_VR_STVE(hx, 0x07, 0x05),
10707 GEN_VR_STVE(wx, 0x07, 0x06),
10708
10709 #undef GEN_VX_LOGICAL
10710 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10711 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10712
10713 #undef GEN_VX_LOGICAL_207
10714 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10715 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10716
10717 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10718 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10719 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10720 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10721 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10722 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10723 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10724 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10725
10726 #undef GEN_VXFORM
10727 #define GEN_VXFORM(name, opc2, opc3) \
10728 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10729
10730 #undef GEN_VXFORM_207
10731 #define GEN_VXFORM_207(name, opc2, opc3) \
10732 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10733
10734 #undef GEN_VXFORM_DUAL
10735 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10736 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10737
10738 #undef GEN_VXRFORM_DUAL
10739 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10740 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10741 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10742
10743 GEN_VXFORM(vaddubm, 0, 0),
10744 GEN_VXFORM(vadduhm, 0, 1),
10745 GEN_VXFORM(vadduwm, 0, 2),
10746 GEN_VXFORM_207(vaddudm, 0, 3),
10747 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10748 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10749 GEN_VXFORM(vsubuwm, 0, 18),
10750 GEN_VXFORM_207(vsubudm, 0, 19),
10751 GEN_VXFORM(vmaxub, 1, 0),
10752 GEN_VXFORM(vmaxuh, 1, 1),
10753 GEN_VXFORM(vmaxuw, 1, 2),
10754 GEN_VXFORM_207(vmaxud, 1, 3),
10755 GEN_VXFORM(vmaxsb, 1, 4),
10756 GEN_VXFORM(vmaxsh, 1, 5),
10757 GEN_VXFORM(vmaxsw, 1, 6),
10758 GEN_VXFORM_207(vmaxsd, 1, 7),
10759 GEN_VXFORM(vminub, 1, 8),
10760 GEN_VXFORM(vminuh, 1, 9),
10761 GEN_VXFORM(vminuw, 1, 10),
10762 GEN_VXFORM_207(vminud, 1, 11),
10763 GEN_VXFORM(vminsb, 1, 12),
10764 GEN_VXFORM(vminsh, 1, 13),
10765 GEN_VXFORM(vminsw, 1, 14),
10766 GEN_VXFORM_207(vminsd, 1, 15),
10767 GEN_VXFORM(vavgub, 1, 16),
10768 GEN_VXFORM(vavguh, 1, 17),
10769 GEN_VXFORM(vavguw, 1, 18),
10770 GEN_VXFORM(vavgsb, 1, 20),
10771 GEN_VXFORM(vavgsh, 1, 21),
10772 GEN_VXFORM(vavgsw, 1, 22),
10773 GEN_VXFORM(vmrghb, 6, 0),
10774 GEN_VXFORM(vmrghh, 6, 1),
10775 GEN_VXFORM(vmrghw, 6, 2),
10776 GEN_VXFORM(vmrglb, 6, 4),
10777 GEN_VXFORM(vmrglh, 6, 5),
10778 GEN_VXFORM(vmrglw, 6, 6),
10779 GEN_VXFORM_207(vmrgew, 6, 30),
10780 GEN_VXFORM_207(vmrgow, 6, 26),
10781 GEN_VXFORM(vmuloub, 4, 0),
10782 GEN_VXFORM(vmulouh, 4, 1),
10783 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10784 GEN_VXFORM(vmulosb, 4, 4),
10785 GEN_VXFORM(vmulosh, 4, 5),
10786 GEN_VXFORM_207(vmulosw, 4, 6),
10787 GEN_VXFORM(vmuleub, 4, 8),
10788 GEN_VXFORM(vmuleuh, 4, 9),
10789 GEN_VXFORM_207(vmuleuw, 4, 10),
10790 GEN_VXFORM(vmulesb, 4, 12),
10791 GEN_VXFORM(vmulesh, 4, 13),
10792 GEN_VXFORM_207(vmulesw, 4, 14),
10793 GEN_VXFORM(vslb, 2, 4),
10794 GEN_VXFORM(vslh, 2, 5),
10795 GEN_VXFORM(vslw, 2, 6),
10796 GEN_VXFORM_207(vsld, 2, 23),
10797 GEN_VXFORM(vsrb, 2, 8),
10798 GEN_VXFORM(vsrh, 2, 9),
10799 GEN_VXFORM(vsrw, 2, 10),
10800 GEN_VXFORM_207(vsrd, 2, 27),
10801 GEN_VXFORM(vsrab, 2, 12),
10802 GEN_VXFORM(vsrah, 2, 13),
10803 GEN_VXFORM(vsraw, 2, 14),
10804 GEN_VXFORM_207(vsrad, 2, 15),
10805 GEN_VXFORM(vslo, 6, 16),
10806 GEN_VXFORM(vsro, 6, 17),
10807 GEN_VXFORM(vaddcuw, 0, 6),
10808 GEN_VXFORM(vsubcuw, 0, 22),
10809 GEN_VXFORM(vaddubs, 0, 8),
10810 GEN_VXFORM(vadduhs, 0, 9),
10811 GEN_VXFORM(vadduws, 0, 10),
10812 GEN_VXFORM(vaddsbs, 0, 12),
10813 GEN_VXFORM(vaddshs, 0, 13),
10814 GEN_VXFORM(vaddsws, 0, 14),
10815 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10816 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10817 GEN_VXFORM(vsubuws, 0, 26),
10818 GEN_VXFORM(vsubsbs, 0, 28),
10819 GEN_VXFORM(vsubshs, 0, 29),
10820 GEN_VXFORM(vsubsws, 0, 30),
10821 GEN_VXFORM_207(vadduqm, 0, 4),
10822 GEN_VXFORM_207(vaddcuq, 0, 5),
10823 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10824 GEN_VXFORM_207(vsubuqm, 0, 20),
10825 GEN_VXFORM_207(vsubcuq, 0, 21),
10826 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10827 GEN_VXFORM(vrlb, 2, 0),
10828 GEN_VXFORM(vrlh, 2, 1),
10829 GEN_VXFORM(vrlw, 2, 2),
10830 GEN_VXFORM_207(vrld, 2, 3),
10831 GEN_VXFORM(vsl, 2, 7),
10832 GEN_VXFORM(vsr, 2, 11),
10833 GEN_VXFORM(vpkuhum, 7, 0),
10834 GEN_VXFORM(vpkuwum, 7, 1),
10835 GEN_VXFORM_207(vpkudum, 7, 17),
10836 GEN_VXFORM(vpkuhus, 7, 2),
10837 GEN_VXFORM(vpkuwus, 7, 3),
10838 GEN_VXFORM_207(vpkudus, 7, 19),
10839 GEN_VXFORM(vpkshus, 7, 4),
10840 GEN_VXFORM(vpkswus, 7, 5),
10841 GEN_VXFORM_207(vpksdus, 7, 21),
10842 GEN_VXFORM(vpkshss, 7, 6),
10843 GEN_VXFORM(vpkswss, 7, 7),
10844 GEN_VXFORM_207(vpksdss, 7, 23),
10845 GEN_VXFORM(vpkpx, 7, 12),
10846 GEN_VXFORM(vsum4ubs, 4, 24),
10847 GEN_VXFORM(vsum4sbs, 4, 28),
10848 GEN_VXFORM(vsum4shs, 4, 25),
10849 GEN_VXFORM(vsum2sws, 4, 26),
10850 GEN_VXFORM(vsumsws, 4, 30),
10851 GEN_VXFORM(vaddfp, 5, 0),
10852 GEN_VXFORM(vsubfp, 5, 1),
10853 GEN_VXFORM(vmaxfp, 5, 16),
10854 GEN_VXFORM(vminfp, 5, 17),
10855
10856 #undef GEN_VXRFORM1
10857 #undef GEN_VXRFORM
10858 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10859 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10860 #define GEN_VXRFORM(name, opc2, opc3) \
10861 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10862 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10863 GEN_VXRFORM(vcmpequb, 3, 0)
10864 GEN_VXRFORM(vcmpequh, 3, 1)
10865 GEN_VXRFORM(vcmpequw, 3, 2)
10866 GEN_VXRFORM(vcmpgtsb, 3, 12)
10867 GEN_VXRFORM(vcmpgtsh, 3, 13)
10868 GEN_VXRFORM(vcmpgtsw, 3, 14)
10869 GEN_VXRFORM(vcmpgtub, 3, 8)
10870 GEN_VXRFORM(vcmpgtuh, 3, 9)
10871 GEN_VXRFORM(vcmpgtuw, 3, 10)
10872 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10873 GEN_VXRFORM(vcmpgefp, 3, 7)
10874 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10875 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10876
10877 #undef GEN_VXFORM_SIMM
10878 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10879 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10880 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10881 GEN_VXFORM_SIMM(vspltish, 6, 13),
10882 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10883
10884 #undef GEN_VXFORM_NOA
10885 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10886 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10887 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10888 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10889 GEN_VXFORM_207(vupkhsw, 7, 25),
10890 GEN_VXFORM_NOA(vupklsb, 7, 10),
10891 GEN_VXFORM_NOA(vupklsh, 7, 11),
10892 GEN_VXFORM_207(vupklsw, 7, 27),
10893 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10894 GEN_VXFORM_NOA(vupklpx, 7, 15),
10895 GEN_VXFORM_NOA(vrefp, 5, 4),
10896 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10897 GEN_VXFORM_NOA(vexptefp, 5, 6),
10898 GEN_VXFORM_NOA(vlogefp, 5, 7),
10899 GEN_VXFORM_NOA(vrfim, 5, 11),
10900 GEN_VXFORM_NOA(vrfin, 5, 8),
10901 GEN_VXFORM_NOA(vrfip, 5, 10),
10902 GEN_VXFORM_NOA(vrfiz, 5, 9),
10903
10904 #undef GEN_VXFORM_UIMM
10905 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10906 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10907 GEN_VXFORM_UIMM(vspltb, 6, 8),
10908 GEN_VXFORM_UIMM(vsplth, 6, 9),
10909 GEN_VXFORM_UIMM(vspltw, 6, 10),
10910 GEN_VXFORM_UIMM(vcfux, 5, 12),
10911 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10912 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10913 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10914
10915 #undef GEN_VAFORM_PAIRED
10916 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10917 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10918 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10919 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10920 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10921 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10922 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10923 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10924
10925 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10926 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10927 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10928 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10929
10930 GEN_VXFORM_207(vbpermq, 6, 21),
10931 GEN_VXFORM_207(vgbbd, 6, 20),
10932 GEN_VXFORM_207(vpmsumb, 4, 16),
10933 GEN_VXFORM_207(vpmsumh, 4, 17),
10934 GEN_VXFORM_207(vpmsumw, 4, 18),
10935 GEN_VXFORM_207(vpmsumd, 4, 19),
10936
10937 GEN_VXFORM_207(vsbox, 4, 23),
10938
10939 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10940 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10941
10942 GEN_VXFORM_207(vshasigmaw, 1, 26),
10943 GEN_VXFORM_207(vshasigmad, 1, 27),
10944
10945 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10946
10947 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10948 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10949 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10950 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10951 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10952 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10953 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10954
10955 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10956 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10957 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10958 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10959 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10960
10961 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10962 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10963 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10964 #if defined(TARGET_PPC64)
10965 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10966 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10967 #endif
10968
10969 #undef GEN_XX2FORM
10970 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10971 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10972 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10973
10974 #undef GEN_XX3FORM
10975 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10976 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10977 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10978 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10979 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10980
10981 #undef GEN_XX2IFORM
10982 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10983 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10984 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10985 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10986 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10987
10988 #undef GEN_XX3_RC_FORM
10989 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10990 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10991 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10992 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10993 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10994 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10995 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10996 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10997 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10998
10999 #undef GEN_XX3FORM_DM
11000 #define GEN_XX3FORM_DM(name, opc2, opc3) \
11001 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
11002 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
11003 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
11004 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
11005 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
11006 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
11007 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
11008 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
11009 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
11010 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
11011 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
11012 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
11013 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
11014 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
11015 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
11016 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
11017
11018 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
11019 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
11020 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
11021 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
11022
11023 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
11024 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
11025 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
11026 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
11027 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
11028 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
11029 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
11030 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
11031
11032 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
11033 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
11034 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
11035 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
11036 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
11037 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
11038 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
11039 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
11040 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
11041 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
11042 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
11043 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
11044 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
11045 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
11046 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
11047 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
11048 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
11049 GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
11050 GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
11051 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
11052 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
11053 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
11054 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
11055 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
11056 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
11057 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
11058 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
11059 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
11060 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
11061 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
11062 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
11063 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
11064 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
11065 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
11066 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
11067 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
11068
11069 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
11070 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
11071 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
11072 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
11073 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
11074 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
11075 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
11076 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
11077 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
11078 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
11079 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
11080 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
11081 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
11082 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
11083 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
11084 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
11085 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
11086 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
11087
11088 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
11089 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
11090 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
11091 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
11092 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
11093 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
11094 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
11095 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
11096 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
11097 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
11098 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
11099 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
11100 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
11101 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
11102 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
11103 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
11104 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
11105 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
11106 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
11107 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
11108 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
11109 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
11110 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
11111 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
11112 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
11113 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
11114 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
11115 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
11116 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
11117 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
11118 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
11119 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
11120 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
11121 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
11122 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
11123 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
11124
11125 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
11126 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
11127 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
11128 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
11129 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
11130 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
11131 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
11132 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
11133 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
11134 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
11135 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
11136 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
11137 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
11138 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
11139 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
11140 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
11141 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
11142 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
11143 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
11144 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
11145 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
11146 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
11147 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
11148 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
11149 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
11150 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
11151 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
11152 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
11153 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
11154 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
11155 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
11156 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
11157 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
11158 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
11159 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
11160 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
11161
11162 #undef VSX_LOGICAL
11163 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
11164 GEN_XX3FORM(name, opc2, opc3, fl2)
11165
11166 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
11167 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
11168 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
11169 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
11170 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
11171 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
11172 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
11173 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
11174 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
11175 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
11176 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
11177 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
11178
11179 #define GEN_XXSEL_ROW(opc3) \
11180 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
11181 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
11182 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
11183 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
11184 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
11185 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
11186 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
11187 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
11188
11189 GEN_XXSEL_ROW(0x00)
11190 GEN_XXSEL_ROW(0x01)
11191 GEN_XXSEL_ROW(0x02)
11192 GEN_XXSEL_ROW(0x03)
11193 GEN_XXSEL_ROW(0x04)
11194 GEN_XXSEL_ROW(0x05)
11195 GEN_XXSEL_ROW(0x06)
11196 GEN_XXSEL_ROW(0x07)
11197 GEN_XXSEL_ROW(0x08)
11198 GEN_XXSEL_ROW(0x09)
11199 GEN_XXSEL_ROW(0x0A)
11200 GEN_XXSEL_ROW(0x0B)
11201 GEN_XXSEL_ROW(0x0C)
11202 GEN_XXSEL_ROW(0x0D)
11203 GEN_XXSEL_ROW(0x0E)
11204 GEN_XXSEL_ROW(0x0F)
11205 GEN_XXSEL_ROW(0x10)
11206 GEN_XXSEL_ROW(0x11)
11207 GEN_XXSEL_ROW(0x12)
11208 GEN_XXSEL_ROW(0x13)
11209 GEN_XXSEL_ROW(0x14)
11210 GEN_XXSEL_ROW(0x15)
11211 GEN_XXSEL_ROW(0x16)
11212 GEN_XXSEL_ROW(0x17)
11213 GEN_XXSEL_ROW(0x18)
11214 GEN_XXSEL_ROW(0x19)
11215 GEN_XXSEL_ROW(0x1A)
11216 GEN_XXSEL_ROW(0x1B)
11217 GEN_XXSEL_ROW(0x1C)
11218 GEN_XXSEL_ROW(0x1D)
11219 GEN_XXSEL_ROW(0x1E)
11220 GEN_XXSEL_ROW(0x1F)
11221
11222 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
11223
11224 #undef GEN_DFP_T_A_B_Rc
11225 #undef GEN_DFP_BF_A_B
11226 #undef GEN_DFP_BF_A_DCM
11227 #undef GEN_DFP_T_B_U32_U32_Rc
11228 #undef GEN_DFP_T_A_B_I32_Rc
11229 #undef GEN_DFP_T_B_Rc
11230 #undef GEN_DFP_T_FPR_I32_Rc
11231
11232 #define _GEN_DFP_LONG(name, op1, op2, mask) \
11233 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
11234
11235 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
11236 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11237 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11238
11239 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
11240 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11241 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11242 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11243 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11244
11245 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
11246 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
11247
11248 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
11249 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11250 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11251
11252 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
11253 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11254 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11255 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11256 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11257
11258 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
11259 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
11260
11261 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
11262 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
11263
11264 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
11265 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
11266
11267 #define GEN_DFP_T_B_Rc(name, op1, op2) \
11268 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
11269
11270 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
11271 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
11272
11273 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
11274 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
11275
11276 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
11277 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
11278
11279 #define GEN_DFP_BF_A_B(name, op1, op2) \
11280 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
11281
11282 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
11283 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11284
11285 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
11286 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11287
11288 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
11289 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11290
11291 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11292 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11293
11294 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11295 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11296
11297 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11298 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11299
11300 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11301 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11302
11303 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11304 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11305
11306 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11307 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11308
11309 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11310 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11311
11312 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11313 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11314
11315 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11316 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11317
11318 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11319 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11320
11321 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11322 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11323
11324 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11325 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11326
11327 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11328 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11329
11330 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11331 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11332
11333 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11334 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
11335 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11336 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
11337 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11338 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
11339 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11340 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
11341 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11342 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11343 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11344 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
11345 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11346 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
11347 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11348 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
11349 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11350 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
11351 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11352 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
11353 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11354 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11355 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11356 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
11357 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11358 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
11359 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11360 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11361 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11362 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
11363 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11364 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
11365 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11366 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
11367 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11368 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
11369 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11370 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
11371 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11372 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
11373 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11374 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
11375 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11376 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
11377 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11378 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
11379 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11380 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11381 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11382 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11383
11384 #undef GEN_SPE
11385 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11386 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11387 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11388 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11389 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11390 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11391 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11392 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11393 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11394 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11395 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11396 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11397 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11398 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11399 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11400 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11401 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11402 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11403 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11404 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11405 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11406 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11407 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11408 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11409 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11410 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11411 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11412 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11413 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11414 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11415 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11416
11417 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11418 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11419 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11420 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11421 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11422 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11423 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11424 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11425 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11426 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11427 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11428 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11429 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11430 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11431
11432 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11433 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11434 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11435 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11436 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11437 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11438 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11439 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11440 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11441 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11442 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11443 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11444 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11445 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11446
11447 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11448 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11449 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11450 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11451 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11452 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11453 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11454 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11455 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11456 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11457 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11458 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11459 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11460 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11461 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11462 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11463
11464 #undef GEN_SPEOP_LDST
11465 #define GEN_SPEOP_LDST(name, opc2, sh) \
11466 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11467 GEN_SPEOP_LDST(evldd, 0x00, 3),
11468 GEN_SPEOP_LDST(evldw, 0x01, 3),
11469 GEN_SPEOP_LDST(evldh, 0x02, 3),
11470 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11471 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11472 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11473 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11474 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11475 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11476 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11477 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11478
11479 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11480 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11481 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11482 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11483 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11484 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11485 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11486
11487 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11488 PPC_NONE, PPC2_TM),
11489 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11490 PPC_NONE, PPC2_TM),
11491 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11492 PPC_NONE, PPC2_TM),
11493 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11494 PPC_NONE, PPC2_TM),
11495 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11496 PPC_NONE, PPC2_TM),
11497 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11498 PPC_NONE, PPC2_TM),
11499 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11500 PPC_NONE, PPC2_TM),
11501 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11502 PPC_NONE, PPC2_TM),
11503 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11504 PPC_NONE, PPC2_TM),
11505 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11506 PPC_NONE, PPC2_TM),
11507 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11508 PPC_NONE, PPC2_TM),
11509 };
11510
11511 #include "helper_regs.h"
11512 #include "translate_init.c"
11513
11514 /*****************************************************************************/
11515 /* Misc PowerPC helpers */
11516 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11517 int flags)
11518 {
11519 #define RGPL 4
11520 #define RFPL 4
11521
11522 PowerPCCPU *cpu = POWERPC_CPU(cs);
11523 CPUPPCState *env = &cpu->env;
11524 int i;
11525
11526 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11527 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11528 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11529 cs->cpu_index);
11530 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11531 TARGET_FMT_lx " iidx %d didx %d\n",
11532 env->msr, env->spr[SPR_HID0],
11533 env->hflags, env->immu_idx, env->dmmu_idx);
11534 #if !defined(NO_TIMER_DUMP)
11535 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11536 #if !defined(CONFIG_USER_ONLY)
11537 " DECR %08" PRIu32
11538 #endif
11539 "\n",
11540 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11541 #if !defined(CONFIG_USER_ONLY)
11542 , cpu_ppc_load_decr(env)
11543 #endif
11544 );
11545 #endif
11546 for (i = 0; i < 32; i++) {
11547 if ((i & (RGPL - 1)) == 0)
11548 cpu_fprintf(f, "GPR%02d", i);
11549 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11550 if ((i & (RGPL - 1)) == (RGPL - 1))
11551 cpu_fprintf(f, "\n");
11552 }
11553 cpu_fprintf(f, "CR ");
11554 for (i = 0; i < 8; i++)
11555 cpu_fprintf(f, "%01x", env->crf[i]);
11556 cpu_fprintf(f, " [");
11557 for (i = 0; i < 8; i++) {
11558 char a = '-';
11559 if (env->crf[i] & 0x08)
11560 a = 'L';
11561 else if (env->crf[i] & 0x04)
11562 a = 'G';
11563 else if (env->crf[i] & 0x02)
11564 a = 'E';
11565 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11566 }
11567 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11568 env->reserve_addr);
11569 for (i = 0; i < 32; i++) {
11570 if ((i & (RFPL - 1)) == 0)
11571 cpu_fprintf(f, "FPR%02d", i);
11572 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11573 if ((i & (RFPL - 1)) == (RFPL - 1))
11574 cpu_fprintf(f, "\n");
11575 }
11576 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11577 #if !defined(CONFIG_USER_ONLY)
11578 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11579 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11580 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11581 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11582
11583 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11584 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11585 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11586 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11587
11588 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11589 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11590 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11591 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11592
11593 #if defined(TARGET_PPC64)
11594 if (env->excp_model == POWERPC_EXCP_POWER7 ||
11595 env->excp_model == POWERPC_EXCP_POWER8) {
11596 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
11597 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
11598 }
11599 #endif
11600 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11601 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11602 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11603 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11604 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11605
11606 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11607 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11608 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11609 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11610
11611 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11612 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11613 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11614 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11615
11616 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11617 " EPR " TARGET_FMT_lx "\n",
11618 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11619 env->spr[SPR_BOOKE_EPR]);
11620
11621 /* FSL-specific */
11622 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11623 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11624 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11625 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11626
11627 /*
11628 * IVORs are left out as they are large and do not change often --
11629 * they can be read with "p $ivor0", "p $ivor1", etc.
11630 */
11631 }
11632
11633 #if defined(TARGET_PPC64)
11634 if (env->flags & POWERPC_FLAG_CFAR) {
11635 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11636 }
11637 #endif
11638
11639 switch (env->mmu_model) {
11640 case POWERPC_MMU_32B:
11641 case POWERPC_MMU_601:
11642 case POWERPC_MMU_SOFT_6xx:
11643 case POWERPC_MMU_SOFT_74xx:
11644 #if defined(TARGET_PPC64)
11645 case POWERPC_MMU_64B:
11646 case POWERPC_MMU_2_03:
11647 case POWERPC_MMU_2_06:
11648 case POWERPC_MMU_2_06a:
11649 case POWERPC_MMU_2_07:
11650 case POWERPC_MMU_2_07a:
11651 #endif
11652 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11653 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11654 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11655 break;
11656 case POWERPC_MMU_BOOKE206:
11657 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11658 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11659 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11660 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11661
11662 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11663 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11664 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11665 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11666
11667 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11668 " TLB1CFG " TARGET_FMT_lx "\n",
11669 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11670 env->spr[SPR_BOOKE_TLB1CFG]);
11671 break;
11672 default:
11673 break;
11674 }
11675 #endif
11676
11677 #undef RGPL
11678 #undef RFPL
11679 }
11680
11681 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11682 fprintf_function cpu_fprintf, int flags)
11683 {
11684 #if defined(DO_PPC_STATISTICS)
11685 PowerPCCPU *cpu = POWERPC_CPU(cs);
11686 opc_handler_t **t1, **t2, **t3, *handler;
11687 int op1, op2, op3;
11688
11689 t1 = cpu->env.opcodes;
11690 for (op1 = 0; op1 < 64; op1++) {
11691 handler = t1[op1];
11692 if (is_indirect_opcode(handler)) {
11693 t2 = ind_table(handler);
11694 for (op2 = 0; op2 < 32; op2++) {
11695 handler = t2[op2];
11696 if (is_indirect_opcode(handler)) {
11697 t3 = ind_table(handler);
11698 for (op3 = 0; op3 < 32; op3++) {
11699 handler = t3[op3];
11700 if (handler->count == 0)
11701 continue;
11702 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11703 "%016" PRIx64 " %" PRId64 "\n",
11704 op1, op2, op3, op1, (op3 << 5) | op2,
11705 handler->oname,
11706 handler->count, handler->count);
11707 }
11708 } else {
11709 if (handler->count == 0)
11710 continue;
11711 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11712 "%016" PRIx64 " %" PRId64 "\n",
11713 op1, op2, op1, op2, handler->oname,
11714 handler->count, handler->count);
11715 }
11716 }
11717 } else {
11718 if (handler->count == 0)
11719 continue;
11720 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11721 " %" PRId64 "\n",
11722 op1, op1, handler->oname,
11723 handler->count, handler->count);
11724 }
11725 }
11726 #endif
11727 }
11728
11729 /*****************************************************************************/
11730 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
11731 {
11732 PowerPCCPU *cpu = ppc_env_get_cpu(env);
11733 CPUState *cs = CPU(cpu);
11734 DisasContext ctx, *ctxp = &ctx;
11735 opc_handler_t **table, *handler;
11736 target_ulong pc_start;
11737 int num_insns;
11738 int max_insns;
11739
11740 pc_start = tb->pc;
11741 ctx.nip = pc_start;
11742 ctx.tb = tb;
11743 ctx.exception = POWERPC_EXCP_NONE;
11744 ctx.spr_cb = env->spr_cb;
11745 ctx.pr = msr_pr;
11746 ctx.mem_idx = env->dmmu_idx;
11747 ctx.dr = msr_dr;
11748 #if !defined(CONFIG_USER_ONLY)
11749 ctx.hv = msr_hv || !env->has_hv_mode;
11750 #endif
11751 ctx.insns_flags = env->insns_flags;
11752 ctx.insns_flags2 = env->insns_flags2;
11753 ctx.access_type = -1;
11754 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
11755 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11756 #if defined(TARGET_PPC64)
11757 ctx.sf_mode = msr_is_64bit(env, env->msr);
11758 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11759 #endif
11760 if (env->mmu_model == POWERPC_MMU_32B ||
11761 env->mmu_model == POWERPC_MMU_601 ||
11762 (env->mmu_model & POWERPC_MMU_64B))
11763 ctx.lazy_tlb_flush = true;
11764
11765 ctx.fpu_enabled = !!msr_fp;
11766 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11767 ctx.spe_enabled = !!msr_spe;
11768 else
11769 ctx.spe_enabled = false;
11770 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11771 ctx.altivec_enabled = !!msr_vr;
11772 else
11773 ctx.altivec_enabled = false;
11774 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11775 ctx.vsx_enabled = !!msr_vsx;
11776 } else {
11777 ctx.vsx_enabled = false;
11778 }
11779 #if defined(TARGET_PPC64)
11780 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11781 ctx.tm_enabled = !!msr_tm;
11782 } else {
11783 ctx.tm_enabled = false;
11784 }
11785 #endif
11786 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11787 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11788 else
11789 ctx.singlestep_enabled = 0;
11790 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11791 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11792 if (unlikely(cs->singlestep_enabled)) {
11793 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11794 }
11795 #if defined (DO_SINGLE_STEP) && 0
11796 /* Single step trace mode */
11797 msr_se = 1;
11798 #endif
11799 num_insns = 0;
11800 max_insns = tb->cflags & CF_COUNT_MASK;
11801 if (max_insns == 0) {
11802 max_insns = CF_COUNT_MASK;
11803 }
11804 if (max_insns > TCG_MAX_INSNS) {
11805 max_insns = TCG_MAX_INSNS;
11806 }
11807
11808 gen_tb_start(tb);
11809 tcg_clear_temp_count();
11810 /* Set env in case of segfault during code fetch */
11811 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
11812 tcg_gen_insn_start(ctx.nip);
11813 num_insns++;
11814
11815 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11816 gen_debug_exception(ctxp);
11817 /* The address covered by the breakpoint must be included in
11818 [tb->pc, tb->pc + tb->size) in order to for it to be
11819 properly cleared -- thus we increment the PC here so that
11820 the logic setting tb->size below does the right thing. */
11821 ctx.nip += 4;
11822 break;
11823 }
11824
11825 LOG_DISAS("----------------\n");
11826 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11827 ctx.nip, ctx.mem_idx, (int)msr_ir);
11828 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
11829 gen_io_start();
11830 if (unlikely(need_byteswap(&ctx))) {
11831 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11832 } else {
11833 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11834 }
11835 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11836 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11837 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11838 ctx.nip += 4;
11839 table = env->opcodes;
11840 handler = table[opc1(ctx.opcode)];
11841 if (is_indirect_opcode(handler)) {
11842 table = ind_table(handler);
11843 handler = table[opc2(ctx.opcode)];
11844 if (is_indirect_opcode(handler)) {
11845 table = ind_table(handler);
11846 handler = table[opc3(ctx.opcode)];
11847 }
11848 }
11849 /* Is opcode *REALLY* valid ? */
11850 if (unlikely(handler->handler == &gen_invalid)) {
11851 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11852 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11853 opc1(ctx.opcode), opc2(ctx.opcode),
11854 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11855 } else {
11856 uint32_t inval;
11857
11858 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11859 inval = handler->inval2;
11860 } else {
11861 inval = handler->inval1;
11862 }
11863
11864 if (unlikely((ctx.opcode & inval) != 0)) {
11865 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11866 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11867 ctx.opcode & inval, opc1(ctx.opcode),
11868 opc2(ctx.opcode), opc3(ctx.opcode),
11869 ctx.opcode, ctx.nip - 4);
11870 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11871 break;
11872 }
11873 }
11874 (*(handler->handler))(&ctx);
11875 #if defined(DO_PPC_STATISTICS)
11876 handler->count++;
11877 #endif
11878 /* Check trace mode exceptions */
11879 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11880 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11881 ctx.exception != POWERPC_SYSCALL &&
11882 ctx.exception != POWERPC_EXCP_TRAP &&
11883 ctx.exception != POWERPC_EXCP_BRANCH)) {
11884 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11885 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11886 (cs->singlestep_enabled) ||
11887 singlestep ||
11888 num_insns >= max_insns)) {
11889 /* if we reach a page boundary or are single stepping, stop
11890 * generation
11891 */
11892 break;
11893 }
11894 if (tcg_check_temp_count()) {
11895 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11896 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11897 ctx.opcode);
11898 exit(1);
11899 }
11900 }
11901 if (tb->cflags & CF_LAST_IO)
11902 gen_io_end();
11903 if (ctx.exception == POWERPC_EXCP_NONE) {
11904 gen_goto_tb(&ctx, 0, ctx.nip);
11905 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11906 if (unlikely(cs->singlestep_enabled)) {
11907 gen_debug_exception(ctxp);
11908 }
11909 /* Generate the return instruction */
11910 tcg_gen_exit_tb(0);
11911 }
11912 gen_tb_end(tb, num_insns);
11913
11914 tb->size = ctx.nip - pc_start;
11915 tb->icount = num_insns;
11916
11917 #if defined(DEBUG_DISAS)
11918 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
11919 && qemu_log_in_addr_range(pc_start)) {
11920 int flags;
11921 flags = env->bfd_mach;
11922 flags |= ctx.le_mode << 16;
11923 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11924 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
11925 qemu_log("\n");
11926 }
11927 #endif
11928 }
11929
11930 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
11931 target_ulong *data)
11932 {
11933 env->nip = data[0];
11934 }
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