s390x/kvm: Handle bpb feature
[qemu/kevin.git] / target / s390x / cpu.h
bloba1123ad621f42a5b2222af42049c042e891e10bf
1 /*
2 * S/390 virtual CPU header
4 * Copyright (c) 2009 Ulrich Hecht
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
19 * You should have received a copy of the GNU (Lesser) General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #ifndef S390X_CPU_H
24 #define S390X_CPU_H
26 #include "qemu-common.h"
27 #include "cpu-qom.h"
28 #include "cpu_models.h"
30 #define TARGET_LONG_BITS 64
32 #define ELF_MACHINE_UNAME "S390X"
34 #define CPUArchState struct CPUS390XState
36 #include "exec/cpu-defs.h"
37 #define TARGET_PAGE_BITS 12
39 #define TARGET_PHYS_ADDR_SPACE_BITS 64
40 #define TARGET_VIRT_ADDR_SPACE_BITS 64
42 #include "exec/cpu-all.h"
44 #include "fpu/softfloat.h"
46 #define NB_MMU_MODES 4
47 #define TARGET_INSN_START_EXTRA_WORDS 1
49 #define MMU_MODE0_SUFFIX _primary
50 #define MMU_MODE1_SUFFIX _secondary
51 #define MMU_MODE2_SUFFIX _home
52 #define MMU_MODE3_SUFFIX _real
54 #define MMU_USER_IDX 0
56 #define MAX_IO_QUEUE 16
57 #define MAX_MCHK_QUEUE 16
59 #define PSW_MCHK_MASK 0x0004000000000000
60 #define PSW_IO_MASK 0x0200000000000000
62 #define S390_MAX_CPUS 248
64 typedef struct PSW {
65 uint64_t mask;
66 uint64_t addr;
67 } PSW;
69 typedef struct IOIntQueue {
70 uint16_t id;
71 uint16_t nr;
72 uint32_t parm;
73 uint32_t word;
74 } IOIntQueue;
76 typedef struct MchkQueue {
77 uint16_t type;
78 } MchkQueue;
80 struct CPUS390XState {
81 uint64_t regs[16]; /* GP registers */
83 * The floating point registers are part of the vector registers.
84 * vregs[0][0] -> vregs[15][0] are 16 floating point registers
86 CPU_DoubleU vregs[32][2]; /* vector registers */
87 uint32_t aregs[16]; /* access registers */
88 uint8_t riccb[64]; /* runtime instrumentation control */
89 uint64_t gscb[4]; /* guarded storage control */
91 /* Fields up to this point are not cleared by initial CPU reset */
92 struct {} start_initial_reset_fields;
94 uint32_t fpc; /* floating-point control register */
95 uint32_t cc_op;
96 bool bpbc; /* branch prediction blocking */
98 float_status fpu_status; /* passed to softfloat lib */
100 /* The low part of a 128-bit return, or remainder of a divide. */
101 uint64_t retxl;
103 PSW psw;
105 uint64_t cc_src;
106 uint64_t cc_dst;
107 uint64_t cc_vr;
109 uint64_t ex_value;
111 uint64_t __excp_addr;
112 uint64_t psa;
114 uint32_t int_pgm_code;
115 uint32_t int_pgm_ilen;
117 uint32_t int_svc_code;
118 uint32_t int_svc_ilen;
120 uint64_t per_address;
121 uint16_t per_perc_atmid;
123 uint64_t cregs[16]; /* control registers */
125 IOIntQueue io_queue[MAX_IO_QUEUE][8];
126 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
128 int pending_int;
129 uint32_t service_param;
130 uint16_t external_call_addr;
131 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS);
132 int io_index[8];
133 int mchk_index;
135 uint64_t ckc;
136 uint64_t cputm;
137 uint32_t todpr;
139 uint64_t pfault_token;
140 uint64_t pfault_compare;
141 uint64_t pfault_select;
143 uint64_t gbea;
144 uint64_t pp;
146 /* Fields up to this point are cleared by a CPU reset */
147 struct {} end_reset_fields;
149 CPU_COMMON
151 #if !defined(CONFIG_USER_ONLY)
152 uint32_t core_id; /* PoP "CPU address", same as cpu_index */
153 uint64_t cpuid;
154 #endif
156 uint64_t tod_offset;
157 uint64_t tod_basetime;
158 QEMUTimer *tod_timer;
160 QEMUTimer *cpu_timer;
163 * The cpu state represents the logical state of a cpu. In contrast to other
164 * architectures, there is a difference between a halt and a stop on s390.
165 * If all cpus are either stopped (including check stop) or in the disabled
166 * wait state, the vm can be shut down.
168 #define CPU_STATE_UNINITIALIZED 0x00
169 #define CPU_STATE_STOPPED 0x01
170 #define CPU_STATE_CHECK_STOP 0x02
171 #define CPU_STATE_OPERATING 0x03
172 #define CPU_STATE_LOAD 0x04
173 uint8_t cpu_state;
175 /* currently processed sigp order */
176 uint8_t sigp_order;
180 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
182 return &cs->vregs[nr][0];
186 * S390CPU:
187 * @env: #CPUS390XState.
189 * An S/390 CPU.
191 struct S390CPU {
192 /*< private >*/
193 CPUState parent_obj;
194 /*< public >*/
196 CPUS390XState env;
197 S390CPUModel *model;
198 /* needed for live migration */
199 void *irqstate;
200 uint32_t irqstate_saved_size;
203 static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
205 return container_of(env, S390CPU, env);
208 #define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
210 #define ENV_OFFSET offsetof(S390CPU, env)
212 #ifndef CONFIG_USER_ONLY
213 extern const struct VMStateDescription vmstate_s390_cpu;
214 #endif
216 /* distinguish between 24 bit and 31 bit addressing */
217 #define HIGH_ORDER_BIT 0x80000000
219 /* Interrupt Codes */
220 /* Program Interrupts */
221 #define PGM_OPERATION 0x0001
222 #define PGM_PRIVILEGED 0x0002
223 #define PGM_EXECUTE 0x0003
224 #define PGM_PROTECTION 0x0004
225 #define PGM_ADDRESSING 0x0005
226 #define PGM_SPECIFICATION 0x0006
227 #define PGM_DATA 0x0007
228 #define PGM_FIXPT_OVERFLOW 0x0008
229 #define PGM_FIXPT_DIVIDE 0x0009
230 #define PGM_DEC_OVERFLOW 0x000a
231 #define PGM_DEC_DIVIDE 0x000b
232 #define PGM_HFP_EXP_OVERFLOW 0x000c
233 #define PGM_HFP_EXP_UNDERFLOW 0x000d
234 #define PGM_HFP_SIGNIFICANCE 0x000e
235 #define PGM_HFP_DIVIDE 0x000f
236 #define PGM_SEGMENT_TRANS 0x0010
237 #define PGM_PAGE_TRANS 0x0011
238 #define PGM_TRANS_SPEC 0x0012
239 #define PGM_SPECIAL_OP 0x0013
240 #define PGM_OPERAND 0x0015
241 #define PGM_TRACE_TABLE 0x0016
242 #define PGM_SPACE_SWITCH 0x001c
243 #define PGM_HFP_SQRT 0x001d
244 #define PGM_PC_TRANS_SPEC 0x001f
245 #define PGM_AFX_TRANS 0x0020
246 #define PGM_ASX_TRANS 0x0021
247 #define PGM_LX_TRANS 0x0022
248 #define PGM_EX_TRANS 0x0023
249 #define PGM_PRIM_AUTH 0x0024
250 #define PGM_SEC_AUTH 0x0025
251 #define PGM_ALET_SPEC 0x0028
252 #define PGM_ALEN_SPEC 0x0029
253 #define PGM_ALE_SEQ 0x002a
254 #define PGM_ASTE_VALID 0x002b
255 #define PGM_ASTE_SEQ 0x002c
256 #define PGM_EXT_AUTH 0x002d
257 #define PGM_STACK_FULL 0x0030
258 #define PGM_STACK_EMPTY 0x0031
259 #define PGM_STACK_SPEC 0x0032
260 #define PGM_STACK_TYPE 0x0033
261 #define PGM_STACK_OP 0x0034
262 #define PGM_ASCE_TYPE 0x0038
263 #define PGM_REG_FIRST_TRANS 0x0039
264 #define PGM_REG_SEC_TRANS 0x003a
265 #define PGM_REG_THIRD_TRANS 0x003b
266 #define PGM_MONITOR 0x0040
267 #define PGM_PER 0x0080
268 #define PGM_CRYPTO 0x0119
270 /* External Interrupts */
271 #define EXT_INTERRUPT_KEY 0x0040
272 #define EXT_CLOCK_COMP 0x1004
273 #define EXT_CPU_TIMER 0x1005
274 #define EXT_MALFUNCTION 0x1200
275 #define EXT_EMERGENCY 0x1201
276 #define EXT_EXTERNAL_CALL 0x1202
277 #define EXT_ETR 0x1406
278 #define EXT_SERVICE 0x2401
279 #define EXT_VIRTIO 0x2603
281 /* PSW defines */
282 #undef PSW_MASK_PER
283 #undef PSW_MASK_DAT
284 #undef PSW_MASK_IO
285 #undef PSW_MASK_EXT
286 #undef PSW_MASK_KEY
287 #undef PSW_SHIFT_KEY
288 #undef PSW_MASK_MCHECK
289 #undef PSW_MASK_WAIT
290 #undef PSW_MASK_PSTATE
291 #undef PSW_MASK_ASC
292 #undef PSW_SHIFT_ASC
293 #undef PSW_MASK_CC
294 #undef PSW_MASK_PM
295 #undef PSW_SHIFT_MASK_PM
296 #undef PSW_MASK_64
297 #undef PSW_MASK_32
298 #undef PSW_MASK_ESA_ADDR
300 #define PSW_MASK_PER 0x4000000000000000ULL
301 #define PSW_MASK_DAT 0x0400000000000000ULL
302 #define PSW_MASK_IO 0x0200000000000000ULL
303 #define PSW_MASK_EXT 0x0100000000000000ULL
304 #define PSW_MASK_KEY 0x00F0000000000000ULL
305 #define PSW_SHIFT_KEY 52
306 #define PSW_MASK_MCHECK 0x0004000000000000ULL
307 #define PSW_MASK_WAIT 0x0002000000000000ULL
308 #define PSW_MASK_PSTATE 0x0001000000000000ULL
309 #define PSW_MASK_ASC 0x0000C00000000000ULL
310 #define PSW_SHIFT_ASC 46
311 #define PSW_MASK_CC 0x0000300000000000ULL
312 #define PSW_MASK_PM 0x00000F0000000000ULL
313 #define PSW_SHIFT_MASK_PM 40
314 #define PSW_MASK_64 0x0000000100000000ULL
315 #define PSW_MASK_32 0x0000000080000000ULL
316 #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
318 #undef PSW_ASC_PRIMARY
319 #undef PSW_ASC_ACCREG
320 #undef PSW_ASC_SECONDARY
321 #undef PSW_ASC_HOME
323 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
324 #define PSW_ASC_ACCREG 0x0000400000000000ULL
325 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
326 #define PSW_ASC_HOME 0x0000C00000000000ULL
328 /* the address space values shifted */
329 #define AS_PRIMARY 0
330 #define AS_ACCREG 1
331 #define AS_SECONDARY 2
332 #define AS_HOME 3
334 /* tb flags */
336 #define FLAG_MASK_PSW_SHIFT 31
337 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT)
338 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
339 #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT)
340 #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT)
341 #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT)
342 #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_PSTATE \
343 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
345 /* Control register 0 bits */
346 #define CR0_LOWPROT 0x0000000010000000ULL
347 #define CR0_SECONDARY 0x0000000004000000ULL
348 #define CR0_EDAT 0x0000000000800000ULL
349 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
350 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL
351 #define CR0_CKC_SC 0x0000000000000800ULL
352 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL
353 #define CR0_SERVICE_SC 0x0000000000000200ULL
355 /* Control register 14 bits */
356 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL
358 /* MMU */
359 #define MMU_PRIMARY_IDX 0
360 #define MMU_SECONDARY_IDX 1
361 #define MMU_HOME_IDX 2
362 #define MMU_REAL_IDX 3
364 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
366 switch (env->psw.mask & PSW_MASK_ASC) {
367 case PSW_ASC_PRIMARY:
368 return MMU_PRIMARY_IDX;
369 case PSW_ASC_SECONDARY:
370 return MMU_SECONDARY_IDX;
371 case PSW_ASC_HOME:
372 return MMU_HOME_IDX;
373 case PSW_ASC_ACCREG:
374 /* Fallthrough: access register mode is not yet supported */
375 default:
376 abort();
380 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
381 target_ulong *cs_base, uint32_t *flags)
383 *pc = env->psw.addr;
384 *cs_base = env->ex_value;
385 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
388 /* PER bits from control register 9 */
389 #define PER_CR9_EVENT_BRANCH 0x80000000
390 #define PER_CR9_EVENT_IFETCH 0x40000000
391 #define PER_CR9_EVENT_STORE 0x20000000
392 #define PER_CR9_EVENT_STORE_REAL 0x08000000
393 #define PER_CR9_EVENT_NULLIFICATION 0x01000000
394 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
395 #define PER_CR9_CONTROL_ALTERATION 0x00200000
397 /* PER bits from the PER CODE/ATMID/AI in lowcore */
398 #define PER_CODE_EVENT_BRANCH 0x8000
399 #define PER_CODE_EVENT_IFETCH 0x4000
400 #define PER_CODE_EVENT_STORE 0x2000
401 #define PER_CODE_EVENT_STORE_REAL 0x0800
402 #define PER_CODE_EVENT_NULLIFICATION 0x0100
404 #define EXCP_EXT 1 /* external interrupt */
405 #define EXCP_SVC 2 /* supervisor call (syscall) */
406 #define EXCP_PGM 3 /* program interruption */
407 #define EXCP_RESTART 4 /* restart interrupt */
408 #define EXCP_STOP 5 /* stop interrupt */
409 #define EXCP_IO 7 /* I/O interrupt */
410 #define EXCP_MCHK 8 /* machine check */
412 #define INTERRUPT_IO (1 << 0)
413 #define INTERRUPT_MCHK (1 << 1)
414 #define INTERRUPT_EXT_SERVICE (1 << 2)
415 #define INTERRUPT_EXT_CPU_TIMER (1 << 3)
416 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4)
417 #define INTERRUPT_EXTERNAL_CALL (1 << 5)
418 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6)
419 #define INTERRUPT_RESTART (1 << 7)
420 #define INTERRUPT_STOP (1 << 8)
422 /* Program Status Word. */
423 #define S390_PSWM_REGNUM 0
424 #define S390_PSWA_REGNUM 1
425 /* General Purpose Registers. */
426 #define S390_R0_REGNUM 2
427 #define S390_R1_REGNUM 3
428 #define S390_R2_REGNUM 4
429 #define S390_R3_REGNUM 5
430 #define S390_R4_REGNUM 6
431 #define S390_R5_REGNUM 7
432 #define S390_R6_REGNUM 8
433 #define S390_R7_REGNUM 9
434 #define S390_R8_REGNUM 10
435 #define S390_R9_REGNUM 11
436 #define S390_R10_REGNUM 12
437 #define S390_R11_REGNUM 13
438 #define S390_R12_REGNUM 14
439 #define S390_R13_REGNUM 15
440 #define S390_R14_REGNUM 16
441 #define S390_R15_REGNUM 17
442 /* Total Core Registers. */
443 #define S390_NUM_CORE_REGS 18
445 static inline void setcc(S390CPU *cpu, uint64_t cc)
447 CPUS390XState *env = &cpu->env;
449 env->psw.mask &= ~(3ull << 44);
450 env->psw.mask |= (cc & 3) << 44;
451 env->cc_op = cc;
454 /* STSI */
455 #define STSI_LEVEL_MASK 0x00000000f0000000ULL
456 #define STSI_LEVEL_CURRENT 0x0000000000000000ULL
457 #define STSI_LEVEL_1 0x0000000010000000ULL
458 #define STSI_LEVEL_2 0x0000000020000000ULL
459 #define STSI_LEVEL_3 0x0000000030000000ULL
460 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
461 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
462 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
463 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
465 /* Basic Machine Configuration */
466 struct sysib_111 {
467 uint32_t res1[8];
468 uint8_t manuf[16];
469 uint8_t type[4];
470 uint8_t res2[12];
471 uint8_t model[16];
472 uint8_t sequence[16];
473 uint8_t plant[4];
474 uint8_t res3[156];
477 /* Basic Machine CPU */
478 struct sysib_121 {
479 uint32_t res1[80];
480 uint8_t sequence[16];
481 uint8_t plant[4];
482 uint8_t res2[2];
483 uint16_t cpu_addr;
484 uint8_t res3[152];
487 /* Basic Machine CPUs */
488 struct sysib_122 {
489 uint8_t res1[32];
490 uint32_t capability;
491 uint16_t total_cpus;
492 uint16_t active_cpus;
493 uint16_t standby_cpus;
494 uint16_t reserved_cpus;
495 uint16_t adjustments[2026];
498 /* LPAR CPU */
499 struct sysib_221 {
500 uint32_t res1[80];
501 uint8_t sequence[16];
502 uint8_t plant[4];
503 uint16_t cpu_id;
504 uint16_t cpu_addr;
505 uint8_t res3[152];
508 /* LPAR CPUs */
509 struct sysib_222 {
510 uint32_t res1[32];
511 uint16_t lpar_num;
512 uint8_t res2;
513 uint8_t lcpuc;
514 uint16_t total_cpus;
515 uint16_t conf_cpus;
516 uint16_t standby_cpus;
517 uint16_t reserved_cpus;
518 uint8_t name[8];
519 uint32_t caf;
520 uint8_t res3[16];
521 uint16_t dedicated_cpus;
522 uint16_t shared_cpus;
523 uint8_t res4[180];
526 /* VM CPUs */
527 struct sysib_322 {
528 uint8_t res1[31];
529 uint8_t count;
530 struct {
531 uint8_t res2[4];
532 uint16_t total_cpus;
533 uint16_t conf_cpus;
534 uint16_t standby_cpus;
535 uint16_t reserved_cpus;
536 uint8_t name[8];
537 uint32_t caf;
538 uint8_t cpi[16];
539 uint8_t res5[3];
540 uint8_t ext_name_encoding;
541 uint32_t res3;
542 uint8_t uuid[16];
543 } vm[8];
544 uint8_t res4[1504];
545 uint8_t ext_names[8][256];
548 /* MMU defines */
549 #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
550 #define _ASCE_SUBSPACE 0x200 /* subspace group control */
551 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
552 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
553 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
554 #define _ASCE_REAL_SPACE 0x20 /* real space control */
555 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
556 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */
557 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */
558 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */
559 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
560 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */
562 #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
563 #define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */
564 #define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */
565 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
566 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
567 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
568 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
569 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
570 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */
572 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
573 #define _SEGMENT_ENTRY_FC 0x400 /* format control */
574 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
575 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
577 #define VADDR_PX 0xff000 /* page index bits */
579 #define _PAGE_RO 0x200 /* HW read-only bit */
580 #define _PAGE_INVALID 0x400 /* HW invalid bit */
581 #define _PAGE_RES0 0x800 /* bit must be zero */
583 #define SK_C (0x1 << 1)
584 #define SK_R (0x1 << 2)
585 #define SK_F (0x1 << 3)
586 #define SK_ACC_MASK (0xf << 4)
588 /* SIGP order codes */
589 #define SIGP_SENSE 0x01
590 #define SIGP_EXTERNAL_CALL 0x02
591 #define SIGP_EMERGENCY 0x03
592 #define SIGP_START 0x04
593 #define SIGP_STOP 0x05
594 #define SIGP_RESTART 0x06
595 #define SIGP_STOP_STORE_STATUS 0x09
596 #define SIGP_INITIAL_CPU_RESET 0x0b
597 #define SIGP_CPU_RESET 0x0c
598 #define SIGP_SET_PREFIX 0x0d
599 #define SIGP_STORE_STATUS_ADDR 0x0e
600 #define SIGP_SET_ARCH 0x12
601 #define SIGP_COND_EMERGENCY 0x13
602 #define SIGP_SENSE_RUNNING 0x15
603 #define SIGP_STORE_ADTL_STATUS 0x17
605 /* SIGP condition codes */
606 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
607 #define SIGP_CC_STATUS_STORED 1
608 #define SIGP_CC_BUSY 2
609 #define SIGP_CC_NOT_OPERATIONAL 3
611 /* SIGP status bits */
612 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
613 #define SIGP_STAT_NOT_RUNNING 0x00000400UL
614 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
615 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
616 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
617 #define SIGP_STAT_STOPPED 0x00000040UL
618 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
619 #define SIGP_STAT_CHECK_STOP 0x00000010UL
620 #define SIGP_STAT_INOPERATIVE 0x00000004UL
621 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
622 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
624 /* SIGP SET ARCHITECTURE modes */
625 #define SIGP_MODE_ESA_S390 0
626 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
627 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
629 /* SIGP order code mask corresponding to bit positions 56-63 */
630 #define SIGP_ORDER_MASK 0x000000ff
632 /* from s390-virtio-ccw */
633 #define MEM_SECTION_SIZE 0x10000000UL
634 #define MAX_AVAIL_SLOTS 32
636 /* machine check interruption code */
638 /* subclasses */
639 #define MCIC_SC_SD 0x8000000000000000ULL
640 #define MCIC_SC_PD 0x4000000000000000ULL
641 #define MCIC_SC_SR 0x2000000000000000ULL
642 #define MCIC_SC_CD 0x0800000000000000ULL
643 #define MCIC_SC_ED 0x0400000000000000ULL
644 #define MCIC_SC_DG 0x0100000000000000ULL
645 #define MCIC_SC_W 0x0080000000000000ULL
646 #define MCIC_SC_CP 0x0040000000000000ULL
647 #define MCIC_SC_SP 0x0020000000000000ULL
648 #define MCIC_SC_CK 0x0010000000000000ULL
650 /* subclass modifiers */
651 #define MCIC_SCM_B 0x0002000000000000ULL
652 #define MCIC_SCM_DA 0x0000000020000000ULL
653 #define MCIC_SCM_AP 0x0000000000080000ULL
655 /* storage errors */
656 #define MCIC_SE_SE 0x0000800000000000ULL
657 #define MCIC_SE_SC 0x0000400000000000ULL
658 #define MCIC_SE_KE 0x0000200000000000ULL
659 #define MCIC_SE_DS 0x0000100000000000ULL
660 #define MCIC_SE_IE 0x0000000080000000ULL
662 /* validity bits */
663 #define MCIC_VB_WP 0x0000080000000000ULL
664 #define MCIC_VB_MS 0x0000040000000000ULL
665 #define MCIC_VB_PM 0x0000020000000000ULL
666 #define MCIC_VB_IA 0x0000010000000000ULL
667 #define MCIC_VB_FA 0x0000008000000000ULL
668 #define MCIC_VB_VR 0x0000004000000000ULL
669 #define MCIC_VB_EC 0x0000002000000000ULL
670 #define MCIC_VB_FP 0x0000001000000000ULL
671 #define MCIC_VB_GR 0x0000000800000000ULL
672 #define MCIC_VB_CR 0x0000000400000000ULL
673 #define MCIC_VB_ST 0x0000000100000000ULL
674 #define MCIC_VB_AR 0x0000000040000000ULL
675 #define MCIC_VB_GS 0x0000000008000000ULL
676 #define MCIC_VB_PR 0x0000000000200000ULL
677 #define MCIC_VB_FC 0x0000000000100000ULL
678 #define MCIC_VB_CT 0x0000000000020000ULL
679 #define MCIC_VB_CC 0x0000000000010000ULL
681 static inline uint64_t s390_build_validity_mcic(void)
683 uint64_t mcic;
686 * Indicate all validity bits (no damage) only. Other bits have to be
687 * added by the caller. (storage errors, subclasses and subclass modifiers)
689 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP |
690 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR |
691 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC;
692 if (s390_has_feat(S390_FEAT_VECTOR)) {
693 mcic |= MCIC_VB_VR;
695 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) {
696 mcic |= MCIC_VB_GS;
698 return mcic;
702 /* cpu.c */
703 int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low);
704 int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low);
705 void s390_crypto_reset(void);
706 bool s390_get_squash_mcss(void);
707 int s390_get_memslot_count(void);
708 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit);
709 void s390_cmma_reset(void);
710 void s390_enable_css_support(S390CPU *cpu);
711 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id,
712 int vq, bool assign);
713 #ifndef CONFIG_USER_ONLY
714 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
715 #else
716 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
718 return 0;
720 #endif /* CONFIG_USER_ONLY */
723 /* cpu_models.c */
724 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
725 #define cpu_list s390_cpu_list
726 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
727 const S390FeatInit feat_init);
730 /* helper.c */
731 #define cpu_init(cpu_model) cpu_generic_init(TYPE_S390_CPU, cpu_model)
733 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
734 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
736 /* you can call this signal handler from your SIGBUS and SIGSEGV
737 signal handlers to inform the virtual CPU of exceptions. non zero
738 is returned if the signal was handled by the virtual CPU. */
739 int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc);
740 #define cpu_signal_handler cpu_s390x_signal_handler
743 /* interrupt.c */
744 void s390_crw_mchk(void);
745 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
746 uint32_t io_int_parm, uint32_t io_int_word);
747 /* automatically detect the instruction length */
748 #define ILEN_AUTO 0xff
749 #define RA_IGNORED 0
750 void s390_program_interrupt(CPUS390XState *env, uint32_t code, int ilen,
751 uintptr_t ra);
752 /* service interrupts are floating therefore we must not pass an cpustate */
753 void s390_sclp_extint(uint32_t parm);
756 /* mmu_helper.c */
757 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
758 int len, bool is_write);
759 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
760 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
761 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
762 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
763 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \
764 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false)
765 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
766 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
767 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra);
770 /* sigp.c */
771 int s390_cpu_restart(S390CPU *cpu);
772 void s390_init_sigp(void);
775 /* outside of target/s390x/ */
776 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
778 #endif