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target/ppc: booke: Data Storage exception cleanup
[qemu/kevin.git] / target / ppc / excp_helper.c
blobc8bd78d5cbb00d020807e4e8a8e6886d3608da84
1 /*
2 * PowerPC exception emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu/main-loop.h"
21 #include "cpu.h"
22 #include "exec/exec-all.h"
23 #include "internal.h"
24 #include "helper_regs.h"
25
26 #include "trace.h"
27
28 #ifdef CONFIG_TCG
29 #include "exec/helper-proto.h"
30 #include "exec/cpu_ldst.h"
31 #endif
32
33 /*****************************************************************************/
34 /* Exception processing */
35 #if !defined(CONFIG_USER_ONLY)
36
37 static const char *powerpc_excp_name(int excp)
38 {
39 switch (excp) {
40 case POWERPC_EXCP_CRITICAL: return "CRITICAL";
41 case POWERPC_EXCP_MCHECK: return "MCHECK";
42 case POWERPC_EXCP_DSI: return "DSI";
43 case POWERPC_EXCP_ISI: return "ISI";
44 case POWERPC_EXCP_EXTERNAL: return "EXTERNAL";
45 case POWERPC_EXCP_ALIGN: return "ALIGN";
46 case POWERPC_EXCP_PROGRAM: return "PROGRAM";
47 case POWERPC_EXCP_FPU: return "FPU";
48 case POWERPC_EXCP_SYSCALL: return "SYSCALL";
49 case POWERPC_EXCP_APU: return "APU";
50 case POWERPC_EXCP_DECR: return "DECR";
51 case POWERPC_EXCP_FIT: return "FIT";
52 case POWERPC_EXCP_WDT: return "WDT";
53 case POWERPC_EXCP_DTLB: return "DTLB";
54 case POWERPC_EXCP_ITLB: return "ITLB";
55 case POWERPC_EXCP_DEBUG: return "DEBUG";
56 case POWERPC_EXCP_SPEU: return "SPEU";
57 case POWERPC_EXCP_EFPDI: return "EFPDI";
58 case POWERPC_EXCP_EFPRI: return "EFPRI";
59 case POWERPC_EXCP_EPERFM: return "EPERFM";
60 case POWERPC_EXCP_DOORI: return "DOORI";
61 case POWERPC_EXCP_DOORCI: return "DOORCI";
62 case POWERPC_EXCP_GDOORI: return "GDOORI";
63 case POWERPC_EXCP_GDOORCI: return "GDOORCI";
64 case POWERPC_EXCP_HYPPRIV: return "HYPPRIV";
65 case POWERPC_EXCP_RESET: return "RESET";
66 case POWERPC_EXCP_DSEG: return "DSEG";
67 case POWERPC_EXCP_ISEG: return "ISEG";
68 case POWERPC_EXCP_HDECR: return "HDECR";
69 case POWERPC_EXCP_TRACE: return "TRACE";
70 case POWERPC_EXCP_HDSI: return "HDSI";
71 case POWERPC_EXCP_HISI: return "HISI";
72 case POWERPC_EXCP_HDSEG: return "HDSEG";
73 case POWERPC_EXCP_HISEG: return "HISEG";
74 case POWERPC_EXCP_VPU: return "VPU";
75 case POWERPC_EXCP_PIT: return "PIT";
76 case POWERPC_EXCP_IO: return "IO";
77 case POWERPC_EXCP_RUNM: return "RUNM";
78 case POWERPC_EXCP_EMUL: return "EMUL";
79 case POWERPC_EXCP_IFTLB: return "IFTLB";
80 case POWERPC_EXCP_DLTLB: return "DLTLB";
81 case POWERPC_EXCP_DSTLB: return "DSTLB";
82 case POWERPC_EXCP_FPA: return "FPA";
83 case POWERPC_EXCP_DABR: return "DABR";
84 case POWERPC_EXCP_IABR: return "IABR";
85 case POWERPC_EXCP_SMI: return "SMI";
86 case POWERPC_EXCP_PERFM: return "PERFM";
87 case POWERPC_EXCP_THERM: return "THERM";
88 case POWERPC_EXCP_VPUA: return "VPUA";
89 case POWERPC_EXCP_SOFTP: return "SOFTP";
90 case POWERPC_EXCP_MAINT: return "MAINT";
91 case POWERPC_EXCP_MEXTBR: return "MEXTBR";
92 case POWERPC_EXCP_NMEXTBR: return "NMEXTBR";
93 case POWERPC_EXCP_ITLBE: return "ITLBE";
94 case POWERPC_EXCP_DTLBE: return "DTLBE";
95 case POWERPC_EXCP_VSXU: return "VSXU";
96 case POWERPC_EXCP_FU: return "FU";
97 case POWERPC_EXCP_HV_EMU: return "HV_EMU";
98 case POWERPC_EXCP_HV_MAINT: return "HV_MAINT";
99 case POWERPC_EXCP_HV_FU: return "HV_FU";
100 case POWERPC_EXCP_SDOOR: return "SDOOR";
101 case POWERPC_EXCP_SDOOR_HV: return "SDOOR_HV";
102 case POWERPC_EXCP_HVIRT: return "HVIRT";
103 case POWERPC_EXCP_SYSCALL_VECTORED: return "SYSCALL_VECTORED";
104 default:
105 g_assert_not_reached();
106 }
107 }
108
109 static void dump_syscall(CPUPPCState *env)
110 {
111 qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64
112 " r3=%016" PRIx64 " r4=%016" PRIx64 " r5=%016" PRIx64
113 " r6=%016" PRIx64 " r7=%016" PRIx64 " r8=%016" PRIx64
114 " nip=" TARGET_FMT_lx "\n",
115 ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
116 ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
117 ppc_dump_gpr(env, 6), ppc_dump_gpr(env, 7),
118 ppc_dump_gpr(env, 8), env->nip);
119 }
120
121 static void dump_hcall(CPUPPCState *env)
122 {
123 qemu_log_mask(CPU_LOG_INT, "hypercall r3=%016" PRIx64
124 " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
125 " r7=%016" PRIx64 " r8=%016" PRIx64 " r9=%016" PRIx64
126 " r10=%016" PRIx64 " r11=%016" PRIx64 " r12=%016" PRIx64
127 " nip=" TARGET_FMT_lx "\n",
128 ppc_dump_gpr(env, 3), ppc_dump_gpr(env, 4),
129 ppc_dump_gpr(env, 5), ppc_dump_gpr(env, 6),
130 ppc_dump_gpr(env, 7), ppc_dump_gpr(env, 8),
131 ppc_dump_gpr(env, 9), ppc_dump_gpr(env, 10),
132 ppc_dump_gpr(env, 11), ppc_dump_gpr(env, 12),
133 env->nip);
134 }
135
136 static void ppc_excp_debug_sw_tlb(CPUPPCState *env, int excp)
137 {
138 const char *es;
139 target_ulong *miss, *cmp;
140 int en;
141
142 if (!qemu_loglevel_mask(CPU_LOG_MMU)) {
143 return;
144 }
145
146 if (excp == POWERPC_EXCP_IFTLB) {
147 es = "I";
148 en = 'I';
149 miss = &env->spr[SPR_IMISS];
150 cmp = &env->spr[SPR_ICMP];
151 } else {
152 if (excp == POWERPC_EXCP_DLTLB) {
153 es = "DL";
154 } else {
155 es = "DS";
156 }
157 en = 'D';
158 miss = &env->spr[SPR_DMISS];
159 cmp = &env->spr[SPR_DCMP];
160 }
161 qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
162 TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 "
163 TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
164 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
165 env->error_code);
166 }
167
168
169 static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp,
170 target_ulong *msr)
171 {
172 /* We no longer are in a PM state */
173 env->resume_as_sreset = false;
174
175 /* Pretend to be returning from doze always as we don't lose state */
176 *msr |= SRR1_WS_NOLOSS;
177
178 /* Machine checks are sent normally */
179 if (excp == POWERPC_EXCP_MCHECK) {
180 return excp;
181 }
182 switch (excp) {
183 case POWERPC_EXCP_RESET:
184 *msr |= SRR1_WAKERESET;
185 break;
186 case POWERPC_EXCP_EXTERNAL:
187 *msr |= SRR1_WAKEEE;
188 break;
189 case POWERPC_EXCP_DECR:
190 *msr |= SRR1_WAKEDEC;
191 break;
192 case POWERPC_EXCP_SDOOR:
193 *msr |= SRR1_WAKEDBELL;
194 break;
195 case POWERPC_EXCP_SDOOR_HV:
196 *msr |= SRR1_WAKEHDBELL;
197 break;
198 case POWERPC_EXCP_HV_MAINT:
199 *msr |= SRR1_WAKEHMI;
200 break;
201 case POWERPC_EXCP_HVIRT:
202 *msr |= SRR1_WAKEHVI;
203 break;
204 default:
205 cpu_abort(cs, "Unsupported exception %d in Power Save mode\n",
206 excp);
207 }
208 return POWERPC_EXCP_RESET;
209 }
210
211 /*
212 * AIL - Alternate Interrupt Location, a mode that allows interrupts to be
213 * taken with the MMU on, and which uses an alternate location (e.g., so the
214 * kernel/hv can map the vectors there with an effective address).
215 *
216 * An interrupt is considered to be taken "with AIL" or "AIL applies" if they
217 * are delivered in this way. AIL requires the LPCR to be set to enable this
218 * mode, and then a number of conditions have to be true for AIL to apply.
219 *
220 * First of all, SRESET, MCE, and HMI are always delivered without AIL, because
221 * they specifically want to be in real mode (e.g., the MCE might be signaling
222 * a SLB multi-hit which requires SLB flush before the MMU can be enabled).
223 *
224 * After that, behaviour depends on the current MSR[IR], MSR[DR], MSR[HV],
225 * whether or not the interrupt changes MSR[HV] from 0 to 1, and the current
226 * radix mode (LPCR[HR]).
227 *
228 * POWER8, POWER9 with LPCR[HR]=0
229 * | LPCR[AIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL |
230 * +-----------+-------------+---------+-------------+-----+
231 * | a | 00/01/10 | x | x | 0 |
232 * | a | 11 | 0 | 1 | 0 |
233 * | a | 11 | 1 | 1 | a |
234 * | a | 11 | 0 | 0 | a |
235 * +-------------------------------------------------------+
236 *
237 * POWER9 with LPCR[HR]=1
238 * | LPCR[AIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL |
239 * +-----------+-------------+---------+-------------+-----+
240 * | a | 00/01/10 | x | x | 0 |
241 * | a | 11 | x | x | a |
242 * +-------------------------------------------------------+
243 *
244 * The difference with POWER9 being that MSR[HV] 0->1 interrupts can be sent to
245 * the hypervisor in AIL mode if the guest is radix. This is good for
246 * performance but allows the guest to influence the AIL of hypervisor
247 * interrupts using its MSR, and also the hypervisor must disallow guest
248 * interrupts (MSR[HV] 0->0) from using AIL if the hypervisor does not want to
249 * use AIL for its MSR[HV] 0->1 interrupts.
250 *
251 * POWER10 addresses those issues with a new LPCR[HAIL] bit that is applied to
252 * interrupts that begin execution with MSR[HV]=1 (so both MSR[HV] 0->1 and
253 * MSR[HV] 1->1).
254 *
255 * HAIL=1 is equivalent to AIL=3, for interrupts delivered with MSR[HV]=1.
256 *
257 * POWER10 behaviour is
258 * | LPCR[AIL] | LPCR[HAIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL |
259 * +-----------+------------+-------------+---------+-------------+-----+
260 * | a | h | 00/01/10 | 0 | 0 | 0 |
261 * | a | h | 11 | 0 | 0 | a |
262 * | a | h | x | 0 | 1 | h |
263 * | a | h | 00/01/10 | 1 | 1 | 0 |
264 * | a | h | 11 | 1 | 1 | h |
265 * +--------------------------------------------------------------------+
266 */
267 static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
268 target_ulong msr,
269 target_ulong *new_msr,
270 target_ulong *vector)
271 {
272 #if defined(TARGET_PPC64)
273 CPUPPCState *env = &cpu->env;
274 bool mmu_all_on = ((msr >> MSR_IR) & 1) && ((msr >> MSR_DR) & 1);
275 bool hv_escalation = !(msr & MSR_HVB) && (*new_msr & MSR_HVB);
276 int ail = 0;
277
278 if (excp == POWERPC_EXCP_MCHECK ||
279 excp == POWERPC_EXCP_RESET ||
280 excp == POWERPC_EXCP_HV_MAINT) {
281 /* SRESET, MCE, HMI never apply AIL */
282 return;
283 }
284
285 if (excp_model == POWERPC_EXCP_POWER8 ||
286 excp_model == POWERPC_EXCP_POWER9) {
287 if (!mmu_all_on) {
288 /* AIL only works if MSR[IR] and MSR[DR] are both enabled. */
289 return;
290 }
291 if (hv_escalation && !(env->spr[SPR_LPCR] & LPCR_HR)) {
292 /*
293 * AIL does not work if there is a MSR[HV] 0->1 transition and the
294 * partition is in HPT mode. For radix guests, such interrupts are
295 * allowed to be delivered to the hypervisor in ail mode.
296 */
297 return;
298 }
299
300 ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT;
301 if (ail == 0) {
302 return;
303 }
304 if (ail == 1) {
305 /* AIL=1 is reserved, treat it like AIL=0 */
306 return;
307 }
308
309 } else if (excp_model == POWERPC_EXCP_POWER10) {
310 if (!mmu_all_on && !hv_escalation) {
311 /*
312 * AIL works for HV interrupts even with guest MSR[IR/DR] disabled.
313 * Guest->guest and HV->HV interrupts do require MMU on.
314 */
315 return;
316 }
317
318 if (*new_msr & MSR_HVB) {
319 if (!(env->spr[SPR_LPCR] & LPCR_HAIL)) {
320 /* HV interrupts depend on LPCR[HAIL] */
321 return;
322 }
323 ail = 3; /* HAIL=1 gives AIL=3 behaviour for HV interrupts */
324 } else {
325 ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT;
326 }
327 if (ail == 0) {
328 return;
329 }
330 if (ail == 1 || ail == 2) {
331 /* AIL=1 and AIL=2 are reserved, treat them like AIL=0 */
332 return;
333 }
334 } else {
335 /* Other processors do not support AIL */
336 return;
337 }
338
339 /*
340 * AIL applies, so the new MSR gets IR and DR set, and an offset applied
341 * to the new IP.
342 */
343 *new_msr |= (1 << MSR_IR) | (1 << MSR_DR);
344
345 if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
346 if (ail == 2) {
347 *vector |= 0x0000000000018000ull;
348 } else if (ail == 3) {
349 *vector |= 0xc000000000004000ull;
350 }
351 } else {
352 /*
353 * scv AIL is a little different. AIL=2 does not change the address,
354 * only the MSR. AIL=3 replaces the 0x17000 base with 0xc...3000.
355 */
356 if (ail == 3) {
357 *vector &= ~0x0000000000017000ull; /* Un-apply the base offset */
358 *vector |= 0xc000000000003000ull; /* Apply scv's AIL=3 offset */
359 }
360 }
361 #endif
362 }
363
364 static void powerpc_set_excp_state(PowerPCCPU *cpu,
365 target_ulong vector, target_ulong msr)
366 {
367 CPUState *cs = CPU(cpu);
368 CPUPPCState *env = &cpu->env;
369
370 /*
371 * We don't use hreg_store_msr here as already have treated any
372 * special case that could occur. Just store MSR and update hflags
373 *
374 * Note: We *MUST* not use hreg_store_msr() as-is anyway because it
375 * will prevent setting of the HV bit which some exceptions might need
376 * to do.
377 */
378 env->msr = msr & env->msr_mask;
379 hreg_compute_hflags(env);
380 env->nip = vector;
381 /* Reset exception state */
382 cs->exception_index = POWERPC_EXCP_NONE;
383 env->error_code = 0;
384
385 /* Reset the reservation */
386 env->reserve_addr = -1;
387
388 /*
389 * Any interrupt is context synchronizing, check if TCG TLB needs
390 * a delayed flush on ppc64
391 */
392 check_tlb_flush(env, false);
393 }
394
395 static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
396 {
397 CPUState *cs = CPU(cpu);
398 CPUPPCState *env = &cpu->env;
399 target_ulong msr, new_msr, vector;
400 int srr0, srr1;
401
402 if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
403 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
404 }
405
406 qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
407 " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
408 excp, env->error_code);
409
410 /* new srr1 value excluding must-be-zero bits */
411 msr = env->msr & ~0x783f0000ULL;
412
413 /*
414 * new interrupt handler msr preserves existing ME unless
415 * explicitly overriden.
416 */
417 new_msr = env->msr & (((target_ulong)1 << MSR_ME));
418
419 /* target registers */
420 srr0 = SPR_SRR0;
421 srr1 = SPR_SRR1;
422
423 /*
424 * Hypervisor emulation assistance interrupt only exists on server
425 * arch 2.05 server or later.
426 */
427 if (excp == POWERPC_EXCP_HV_EMU) {
428 excp = POWERPC_EXCP_PROGRAM;
429 }
430
431 vector = env->excp_vectors[excp];
432 if (vector == (target_ulong)-1ULL) {
433 cpu_abort(cs, "Raised an exception without defined vector %d\n",
434 excp);
435 }
436
437 vector |= env->excp_prefix;
438
439 switch (excp) {
440 case POWERPC_EXCP_CRITICAL: /* Critical input */
441 srr0 = SPR_40x_SRR2;
442 srr1 = SPR_40x_SRR3;
443 break;
444 case POWERPC_EXCP_MCHECK: /* Machine check exception */
445 if (msr_me == 0) {
446 /*
447 * Machine check exception is not enabled. Enter
448 * checkstop state.
449 */
450 fprintf(stderr, "Machine check while not allowed. "
451 "Entering checkstop state\n");
452 if (qemu_log_separate()) {
453 qemu_log("Machine check while not allowed. "
454 "Entering checkstop state\n");
455 }
456 cs->halted = 1;
457 cpu_interrupt_exittb(cs);
458 }
459
460 /* machine check exceptions don't have ME set */
461 new_msr &= ~((target_ulong)1 << MSR_ME);
462
463 srr0 = SPR_40x_SRR2;
464 srr1 = SPR_40x_SRR3;
465 break;
466 case POWERPC_EXCP_DSI: /* Data storage exception */
467 trace_ppc_excp_dsi(env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
468 break;
469 case POWERPC_EXCP_ISI: /* Instruction storage exception */
470 trace_ppc_excp_isi(msr, env->nip);
471 break;
472 case POWERPC_EXCP_EXTERNAL: /* External input */
473 break;
474 case POWERPC_EXCP_ALIGN: /* Alignment exception */
475 break;
476 case POWERPC_EXCP_PROGRAM: /* Program exception */
477 switch (env->error_code & ~0xF) {
478 case POWERPC_EXCP_FP:
479 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
480 trace_ppc_excp_fp_ignore();
481 cs->exception_index = POWERPC_EXCP_NONE;
482 env->error_code = 0;
483 return;
484 }
485 env->spr[SPR_40x_ESR] = ESR_FP;
486 break;
487 case POWERPC_EXCP_INVAL:
488 trace_ppc_excp_inval(env->nip);
489 env->spr[SPR_40x_ESR] = ESR_PIL;
490 break;
491 case POWERPC_EXCP_PRIV:
492 env->spr[SPR_40x_ESR] = ESR_PPR;
493 break;
494 case POWERPC_EXCP_TRAP:
495 env->spr[SPR_40x_ESR] = ESR_PTR;
496 break;
497 default:
498 cpu_abort(cs, "Invalid program exception %d. Aborting\n",
499 env->error_code);
500 break;
501 }
502 break;
503 case POWERPC_EXCP_SYSCALL: /* System call exception */
504 dump_syscall(env);
505
506 /*
507 * We need to correct the NIP which in this case is supposed
508 * to point to the next instruction
509 */
510 env->nip += 4;
511 break;
512 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
513 trace_ppc_excp_print("FIT");
514 break;
515 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
516 trace_ppc_excp_print("WDT");
517 break;
518 case POWERPC_EXCP_DTLB: /* Data TLB error */
519 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
520 break;
521 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
522 trace_ppc_excp_print("PIT");
523 break;
524 case POWERPC_EXCP_DEBUG: /* Debug interrupt */
525 cpu_abort(cs, "%s exception not implemented\n",
526 powerpc_excp_name(excp));
527 break;
528 default:
529 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
530 break;
531 }
532
533 /* Sanity check */
534 if (!(env->msr_mask & MSR_HVB)) {
535 if (new_msr & MSR_HVB) {
536 cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
537 "no HV support\n", excp);
538 }
539 if (srr0 == SPR_HSRR0) {
540 cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
541 "no HV support\n", excp);
542 }
543 }
544
545 /* Save PC */
546 env->spr[srr0] = env->nip;
547
548 /* Save MSR */
549 env->spr[srr1] = msr;
550
551 powerpc_set_excp_state(cpu, vector, new_msr);
552 }
553
554 static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
555 {
556 CPUState *cs = CPU(cpu);
557 CPUPPCState *env = &cpu->env;
558 target_ulong msr, new_msr, vector;
559
560 if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
561 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
562 }
563
564 qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
565 " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
566 excp, env->error_code);
567
568 /* new srr1 value excluding must-be-zero bits */
569 msr = env->msr & ~0x783f0000ULL;
570
571 /*
572 * new interrupt handler msr preserves existing ME unless
573 * explicitly overriden
574 */
575 new_msr = env->msr & ((target_ulong)1 << MSR_ME);
576
577 /*
578 * Hypervisor emulation assistance interrupt only exists on server
579 * arch 2.05 server or later.
580 */
581 if (excp == POWERPC_EXCP_HV_EMU) {
582 excp = POWERPC_EXCP_PROGRAM;
583 }
584
585 vector = env->excp_vectors[excp];
586 if (vector == (target_ulong)-1ULL) {
587 cpu_abort(cs, "Raised an exception without defined vector %d\n",
588 excp);
589 }
590
591 vector |= env->excp_prefix;
592
593 switch (excp) {
594 case POWERPC_EXCP_MCHECK: /* Machine check exception */
595 if (msr_me == 0) {
596 /*
597 * Machine check exception is not enabled. Enter
598 * checkstop state.
599 */
600 fprintf(stderr, "Machine check while not allowed. "
601 "Entering checkstop state\n");
602 if (qemu_log_separate()) {
603 qemu_log("Machine check while not allowed. "
604 "Entering checkstop state\n");
605 }
606 cs->halted = 1;
607 cpu_interrupt_exittb(cs);
608 }
609
610 /* machine check exceptions don't have ME set */
611 new_msr &= ~((target_ulong)1 << MSR_ME);
612
613 break;
614 case POWERPC_EXCP_DSI: /* Data storage exception */
615 trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
616 break;
617 case POWERPC_EXCP_ISI: /* Instruction storage exception */
618 trace_ppc_excp_isi(msr, env->nip);
619 msr |= env->error_code;
620 break;
621 case POWERPC_EXCP_EXTERNAL: /* External input */
622 break;
623 case POWERPC_EXCP_ALIGN: /* Alignment exception */
624 /* Get rS/rD and rA from faulting opcode */
625 /*
626 * Note: the opcode fields will not be set properly for a
627 * direct store load/store, but nobody cares as nobody
628 * actually uses direct store segments.
629 */
630 env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
631 break;
632 case POWERPC_EXCP_PROGRAM: /* Program exception */
633 switch (env->error_code & ~0xF) {
634 case POWERPC_EXCP_FP:
635 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
636 trace_ppc_excp_fp_ignore();
637 cs->exception_index = POWERPC_EXCP_NONE;
638 env->error_code = 0;
639 return;
640 }
641
642 /*
643 * FP exceptions always have NIP pointing to the faulting
644 * instruction, so always use store_next and claim we are
645 * precise in the MSR.
646 */
647 msr |= 0x00100000;
648 break;
649 case POWERPC_EXCP_INVAL:
650 trace_ppc_excp_inval(env->nip);
651 msr |= 0x00080000;
652 break;
653 case POWERPC_EXCP_PRIV:
654 msr |= 0x00040000;
655 break;
656 case POWERPC_EXCP_TRAP:
657 msr |= 0x00020000;
658 break;
659 default:
660 /* Should never occur */
661 cpu_abort(cs, "Invalid program exception %d. Aborting\n",
662 env->error_code);
663 break;
664 }
665 break;
666 case POWERPC_EXCP_SYSCALL: /* System call exception */
667 {
668 int lev = env->error_code;
669
670 if ((lev == 1) && cpu->vhyp) {
671 dump_hcall(env);
672 } else {
673 dump_syscall(env);
674 }
675
676 /*
677 * We need to correct the NIP which in this case is supposed
678 * to point to the next instruction
679 */
680 env->nip += 4;
681
682 /*
683 * The Virtual Open Firmware (VOF) relies on the 'sc 1'
684 * instruction to communicate with QEMU. The pegasos2 machine
685 * uses VOF and the 74xx CPUs, so although the 74xx don't have
686 * HV mode, we need to keep hypercall support.
687 */
688 if ((lev == 1) && cpu->vhyp) {
689 PPCVirtualHypervisorClass *vhc =
690 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
691 vhc->hypercall(cpu->vhyp, cpu);
692 return;
693 }
694
695 break;
696 }
697 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
698 case POWERPC_EXCP_DECR: /* Decrementer exception */
699 break;
700 case POWERPC_EXCP_RESET: /* System reset exception */
701 if (msr_pow) {
702 cpu_abort(cs, "Trying to deliver power-saving system reset "
703 "exception %d with no HV support\n", excp);
704 }
705 break;
706 case POWERPC_EXCP_TRACE: /* Trace exception */
707 break;
708 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
709 break;
710 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
711 case POWERPC_EXCP_SMI: /* System management interrupt */
712 case POWERPC_EXCP_THERM: /* Thermal interrupt */
713 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
714 case POWERPC_EXCP_VPUA: /* Vector assist exception */
715 cpu_abort(cs, "%s exception not implemented\n",
716 powerpc_excp_name(excp));
717 break;
718 default:
719 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
720 break;
721 }
722
723 /* Sanity check */
724 if (!(env->msr_mask & MSR_HVB)) {
725 if (new_msr & MSR_HVB) {
726 cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
727 "no HV support\n", excp);
728 }
729 }
730
731 /*
732 * Sort out endianness of interrupt, this differs depending on the
733 * CPU, the HV mode, etc...
734 */
735 if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
736 new_msr |= (target_ulong)1 << MSR_LE;
737 }
738
739 /* Save PC */
740 env->spr[SPR_SRR0] = env->nip;
741
742 /* Save MSR */
743 env->spr[SPR_SRR1] = msr;
744
745 powerpc_set_excp_state(cpu, vector, new_msr);
746 }
747
748 static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
749 {
750 CPUState *cs = CPU(cpu);
751 CPUPPCState *env = &cpu->env;
752 int excp_model = env->excp_model;
753 target_ulong msr, new_msr, vector;
754 int srr0, srr1, lev = -1;
755
756 if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
757 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
758 }
759
760 qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
761 " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
762 excp, env->error_code);
763
764 msr = env->msr;
765
766 /*
767 * new interrupt handler msr preserves existing ME unless
768 * explicitly overriden
769 */
770 new_msr = env->msr & ((target_ulong)1 << MSR_ME);
771
772 /* target registers */
773 srr0 = SPR_SRR0;
774 srr1 = SPR_SRR1;
775
776 /*
777 * Hypervisor emulation assistance interrupt only exists on server
778 * arch 2.05 server or later.
779 */
780 if (excp == POWERPC_EXCP_HV_EMU) {
781 excp = POWERPC_EXCP_PROGRAM;
782 }
783
784 #ifdef TARGET_PPC64
785 /*
786 * SPEU and VPU share the same IVOR but they exist in different
787 * processors. SPEU is e500v1/2 only and VPU is e6500 only.
788 */
789 if (excp == POWERPC_EXCP_VPU) {
790 excp = POWERPC_EXCP_SPEU;
791 }
792 #endif
793
794 vector = env->excp_vectors[excp];
795 if (vector == (target_ulong)-1ULL) {
796 cpu_abort(cs, "Raised an exception without defined vector %d\n",
797 excp);
798 }
799
800 vector |= env->excp_prefix;
801
802 switch (excp) {
803 case POWERPC_EXCP_CRITICAL: /* Critical input */
804 srr0 = SPR_BOOKE_CSRR0;
805 srr1 = SPR_BOOKE_CSRR1;
806 break;
807 case POWERPC_EXCP_MCHECK: /* Machine check exception */
808 if (msr_me == 0) {
809 /*
810 * Machine check exception is not enabled. Enter
811 * checkstop state.
812 */
813 fprintf(stderr, "Machine check while not allowed. "
814 "Entering checkstop state\n");
815 if (qemu_log_separate()) {
816 qemu_log("Machine check while not allowed. "
817 "Entering checkstop state\n");
818 }
819 cs->halted = 1;
820 cpu_interrupt_exittb(cs);
821 }
822
823 /* machine check exceptions don't have ME set */
824 new_msr &= ~((target_ulong)1 << MSR_ME);
825
826 /* FIXME: choose one or the other based on CPU type */
827 srr0 = SPR_BOOKE_MCSRR0;
828 srr1 = SPR_BOOKE_MCSRR1;
829
830 env->spr[SPR_BOOKE_CSRR0] = env->nip;
831 env->spr[SPR_BOOKE_CSRR1] = msr;
832
833 break;
834 case POWERPC_EXCP_DSI: /* Data storage exception */
835 trace_ppc_excp_dsi(env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
836 break;
837 case POWERPC_EXCP_ISI: /* Instruction storage exception */
838 trace_ppc_excp_isi(msr, env->nip);
839 msr |= env->error_code;
840 break;
841 case POWERPC_EXCP_EXTERNAL: /* External input */
842 {
843 bool lpes0;
844
845 cs = CPU(cpu);
846
847 /*
848 * Exception targeting modifiers
849 *
850 * LPES0 is supported on POWER7/8/9
851 * LPES1 is not supported (old iSeries mode)
852 *
853 * On anything else, we behave as if LPES0 is 1
854 * (externals don't alter MSR:HV)
855 */
856 #if defined(TARGET_PPC64)
857 if (excp_model == POWERPC_EXCP_POWER7 ||
858 excp_model == POWERPC_EXCP_POWER8 ||
859 excp_model == POWERPC_EXCP_POWER9 ||
860 excp_model == POWERPC_EXCP_POWER10) {
861 lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
862 } else
863 #endif /* defined(TARGET_PPC64) */
864 {
865 lpes0 = true;
866 }
867
868 if (!lpes0) {
869 new_msr |= (target_ulong)MSR_HVB;
870 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
871 srr0 = SPR_HSRR0;
872 srr1 = SPR_HSRR1;
873 }
874 if (env->mpic_proxy) {
875 /* IACK the IRQ on delivery */
876 env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
877 }
878 break;
879 }
880 case POWERPC_EXCP_ALIGN: /* Alignment exception */
881 /* Get rS/rD and rA from faulting opcode */
882 /*
883 * Note: the opcode fields will not be set properly for a
884 * direct store load/store, but nobody cares as nobody
885 * actually uses direct store segments.
886 */
887 env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
888 break;
889 case POWERPC_EXCP_PROGRAM: /* Program exception */
890 switch (env->error_code & ~0xF) {
891 case POWERPC_EXCP_FP:
892 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
893 trace_ppc_excp_fp_ignore();
894 cs->exception_index = POWERPC_EXCP_NONE;
895 env->error_code = 0;
896 return;
897 }
898
899 /*
900 * FP exceptions always have NIP pointing to the faulting
901 * instruction, so always use store_next and claim we are
902 * precise in the MSR.
903 */
904 msr |= 0x00100000;
905 env->spr[SPR_BOOKE_ESR] = ESR_FP;
906 break;
907 case POWERPC_EXCP_INVAL:
908 trace_ppc_excp_inval(env->nip);
909 msr |= 0x00080000;
910 env->spr[SPR_BOOKE_ESR] = ESR_PIL;
911 break;
912 case POWERPC_EXCP_PRIV:
913 msr |= 0x00040000;
914 env->spr[SPR_BOOKE_ESR] = ESR_PPR;
915 break;
916 case POWERPC_EXCP_TRAP:
917 msr |= 0x00020000;
918 env->spr[SPR_BOOKE_ESR] = ESR_PTR;
919 break;
920 default:
921 /* Should never occur */
922 cpu_abort(cs, "Invalid program exception %d. Aborting\n",
923 env->error_code);
924 break;
925 }
926 break;
927 case POWERPC_EXCP_SYSCALL: /* System call exception */
928 lev = env->error_code;
929
930 if ((lev == 1) && cpu->vhyp) {
931 dump_hcall(env);
932 } else {
933 dump_syscall(env);
934 }
935
936 /*
937 * We need to correct the NIP which in this case is supposed
938 * to point to the next instruction
939 */
940 env->nip += 4;
941
942 /* "PAPR mode" built-in hypercall emulation */
943 if ((lev == 1) && cpu->vhyp) {
944 PPCVirtualHypervisorClass *vhc =
945 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
946 vhc->hypercall(cpu->vhyp, cpu);
947 return;
948 }
949 if (lev == 1) {
950 new_msr |= (target_ulong)MSR_HVB;
951 }
952 break;
953 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
954 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
955 case POWERPC_EXCP_DECR: /* Decrementer exception */
956 break;
957 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
958 /* FIT on 4xx */
959 trace_ppc_excp_print("FIT");
960 break;
961 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
962 trace_ppc_excp_print("WDT");
963 switch (excp_model) {
964 case POWERPC_EXCP_BOOKE:
965 srr0 = SPR_BOOKE_CSRR0;
966 srr1 = SPR_BOOKE_CSRR1;
967 break;
968 default:
969 break;
970 }
971 break;
972 case POWERPC_EXCP_DTLB: /* Data TLB error */
973 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
974 break;
975 case POWERPC_EXCP_DEBUG: /* Debug interrupt */
976 if (env->flags & POWERPC_FLAG_DE) {
977 /* FIXME: choose one or the other based on CPU type */
978 srr0 = SPR_BOOKE_DSRR0;
979 srr1 = SPR_BOOKE_DSRR1;
980
981 env->spr[SPR_BOOKE_CSRR0] = env->nip;
982 env->spr[SPR_BOOKE_CSRR1] = msr;
983
984 /* DBSR already modified by caller */
985 } else {
986 cpu_abort(cs, "Debug exception triggered on unsupported model\n");
987 }
988 break;
989 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
990 env->spr[SPR_BOOKE_ESR] = ESR_SPV;
991 break;
992 case POWERPC_EXCP_RESET: /* System reset exception */
993 /* A power-saving exception sets ME, otherwise it is unchanged */
994 if (msr_pow) {
995 /* indicate that we resumed from power save mode */
996 msr |= 0x10000;
997 new_msr |= ((target_ulong)1 << MSR_ME);
998 }
999 if (env->msr_mask & MSR_HVB) {
1000 /*
1001 * ISA specifies HV, but can be delivered to guest with HV
1002 * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
1003 */
1004 new_msr |= (target_ulong)MSR_HVB;
1005 } else {
1006 if (msr_pow) {
1007 cpu_abort(cs, "Trying to deliver power-saving system reset "
1008 "exception %d with no HV support\n", excp);
1009 }
1010 }
1011 break;
1012 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
1013 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
1014 cpu_abort(cs, "%s exception not implemented\n",
1015 powerpc_excp_name(excp));
1016 break;
1017 default:
1018 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
1019 break;
1020 }
1021
1022 /* Sanity check */
1023 if (!(env->msr_mask & MSR_HVB)) {
1024 if (new_msr & MSR_HVB) {
1025 cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
1026 "no HV support\n", excp);
1027 }
1028 if (srr0 == SPR_HSRR0) {
1029 cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
1030 "no HV support\n", excp);
1031 }
1032 }
1033
1034 #if defined(TARGET_PPC64)
1035 if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
1036 /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
1037 new_msr |= (target_ulong)1 << MSR_CM;
1038 } else {
1039 vector = (uint32_t)vector;
1040 }
1041 #endif
1042
1043 /* Save PC */
1044 env->spr[srr0] = env->nip;
1045
1046 /* Save MSR */
1047 env->spr[srr1] = msr;
1048
1049 powerpc_set_excp_state(cpu, vector, new_msr);
1050 }
1051
1052 #ifdef TARGET_PPC64
1053 static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
1054 {
1055 CPUState *cs = CPU(cpu);
1056 CPUPPCState *env = &cpu->env;
1057 int excp_model = env->excp_model;
1058 target_ulong msr, new_msr, vector;
1059 int srr0, srr1, lev = -1;
1060
1061 if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
1062 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
1063 }
1064
1065 qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
1066 " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
1067 excp, env->error_code);
1068
1069 /* new srr1 value excluding must-be-zero bits */
1070 msr = env->msr & ~0x783f0000ULL;
1071
1072 /*
1073 * new interrupt handler msr preserves existing HV and ME unless
1074 * explicitly overriden
1075 */
1076 new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
1077
1078 /* target registers */
1079 srr0 = SPR_SRR0;
1080 srr1 = SPR_SRR1;
1081
1082 /*
1083 * check for special resume at 0x100 from doze/nap/sleep/winkle on
1084 * P7/P8/P9
1085 */
1086 if (env->resume_as_sreset) {
1087 excp = powerpc_reset_wakeup(cs, env, excp, &msr);
1088 }
1089
1090 /*
1091 * We don't want to generate a Hypervisor Emulation Assistance
1092 * Interrupt if we don't have HVB in msr_mask (PAPR mode).
1093 */
1094 if (excp == POWERPC_EXCP_HV_EMU && !(env->msr_mask & MSR_HVB)) {
1095 excp = POWERPC_EXCP_PROGRAM;
1096 }
1097
1098 vector = env->excp_vectors[excp];
1099 if (vector == (target_ulong)-1ULL) {
1100 cpu_abort(cs, "Raised an exception without defined vector %d\n",
1101 excp);
1102 }
1103
1104 vector |= env->excp_prefix;
1105
1106 switch (excp) {
1107 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1108 if (msr_me == 0) {
1109 /*
1110 * Machine check exception is not enabled. Enter
1111 * checkstop state.
1112 */
1113 fprintf(stderr, "Machine check while not allowed. "
1114 "Entering checkstop state\n");
1115 if (qemu_log_separate()) {
1116 qemu_log("Machine check while not allowed. "
1117 "Entering checkstop state\n");
1118 }
1119 cs->halted = 1;
1120 cpu_interrupt_exittb(cs);
1121 }
1122 if (env->msr_mask & MSR_HVB) {
1123 /*
1124 * ISA specifies HV, but can be delivered to guest with HV
1125 * clear (e.g., see FWNMI in PAPR).
1126 */
1127 new_msr |= (target_ulong)MSR_HVB;
1128 }
1129
1130 /* machine check exceptions don't have ME set */
1131 new_msr &= ~((target_ulong)1 << MSR_ME);
1132
1133 break;
1134 case POWERPC_EXCP_DSI: /* Data storage exception */
1135 trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
1136 break;
1137 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1138 trace_ppc_excp_isi(msr, env->nip);
1139 msr |= env->error_code;
1140 break;
1141 case POWERPC_EXCP_EXTERNAL: /* External input */
1142 {
1143 bool lpes0;
1144
1145 /*
1146 * LPES0 is only taken into consideration if we support HV
1147 * mode for this CPU.
1148 */
1149 if (!env->has_hv_mode) {
1150 break;
1151 }
1152
1153 lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
1154
1155 if (!lpes0) {
1156 new_msr |= (target_ulong)MSR_HVB;
1157 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
1158 srr0 = SPR_HSRR0;
1159 srr1 = SPR_HSRR1;
1160 }
1161
1162 break;
1163 }
1164 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1165 /* Get rS/rD and rA from faulting opcode */
1166 /*
1167 * Note: the opcode fields will not be set properly for a
1168 * direct store load/store, but nobody cares as nobody
1169 * actually uses direct store segments.
1170 */
1171 env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
1172 break;
1173 case POWERPC_EXCP_PROGRAM: /* Program exception */
1174 switch (env->error_code & ~0xF) {
1175 case POWERPC_EXCP_FP:
1176 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
1177 trace_ppc_excp_fp_ignore();
1178 cs->exception_index = POWERPC_EXCP_NONE;
1179 env->error_code = 0;
1180 return;
1181 }
1182
1183 /*
1184 * FP exceptions always have NIP pointing to the faulting
1185 * instruction, so always use store_next and claim we are
1186 * precise in the MSR.
1187 */
1188 msr |= 0x00100000;
1189 break;
1190 case POWERPC_EXCP_INVAL:
1191 trace_ppc_excp_inval(env->nip);
1192 msr |= 0x00080000;
1193 break;
1194 case POWERPC_EXCP_PRIV:
1195 msr |= 0x00040000;
1196 break;
1197 case POWERPC_EXCP_TRAP:
1198 msr |= 0x00020000;
1199 break;
1200 default:
1201 /* Should never occur */
1202 cpu_abort(cs, "Invalid program exception %d. Aborting\n",
1203 env->error_code);
1204 break;
1205 }
1206 break;
1207 case POWERPC_EXCP_SYSCALL: /* System call exception */
1208 lev = env->error_code;
1209
1210 if ((lev == 1) && cpu->vhyp) {
1211 dump_hcall(env);
1212 } else {
1213 dump_syscall(env);
1214 }
1215
1216 /*
1217 * We need to correct the NIP which in this case is supposed
1218 * to point to the next instruction
1219 */
1220 env->nip += 4;
1221
1222 /* "PAPR mode" built-in hypercall emulation */
1223 if ((lev == 1) && cpu->vhyp) {
1224 PPCVirtualHypervisorClass *vhc =
1225 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
1226 vhc->hypercall(cpu->vhyp, cpu);
1227 return;
1228 }
1229 if (lev == 1) {
1230 new_msr |= (target_ulong)MSR_HVB;
1231 }
1232 break;
1233 case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
1234 lev = env->error_code;
1235 dump_syscall(env);
1236 env->nip += 4;
1237 new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
1238 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
1239
1240 vector += lev * 0x20;
1241
1242 env->lr = env->nip;
1243 env->ctr = msr;
1244 break;
1245 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1246 case POWERPC_EXCP_DECR: /* Decrementer exception */
1247 break;
1248 case POWERPC_EXCP_RESET: /* System reset exception */
1249 /* A power-saving exception sets ME, otherwise it is unchanged */
1250 if (msr_pow) {
1251 /* indicate that we resumed from power save mode */
1252 msr |= 0x10000;
1253 new_msr |= ((target_ulong)1 << MSR_ME);
1254 }
1255 if (env->msr_mask & MSR_HVB) {
1256 /*
1257 * ISA specifies HV, but can be delivered to guest with HV
1258 * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
1259 */
1260 new_msr |= (target_ulong)MSR_HVB;
1261 } else {
1262 if (msr_pow) {
1263 cpu_abort(cs, "Trying to deliver power-saving system reset "
1264 "exception %d with no HV support\n", excp);
1265 }
1266 }
1267 break;
1268 case POWERPC_EXCP_DSEG: /* Data segment exception */
1269 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1270 case POWERPC_EXCP_TRACE: /* Trace exception */
1271 break;
1272 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
1273 msr |= env->error_code;
1274 /* fall through */
1275 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1276 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1277 case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
1278 case POWERPC_EXCP_HV_EMU:
1279 case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
1280 srr0 = SPR_HSRR0;
1281 srr1 = SPR_HSRR1;
1282 new_msr |= (target_ulong)MSR_HVB;
1283 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
1284 break;
1285 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1286 case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
1287 case POWERPC_EXCP_FU: /* Facility unavailable exception */
1288 env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
1289 break;
1290 case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
1291 env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
1292 srr0 = SPR_HSRR0;
1293 srr1 = SPR_HSRR1;
1294 new_msr |= (target_ulong)MSR_HVB;
1295 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
1296 break;
1297 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1298 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
1299 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1300 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1301 case POWERPC_EXCP_SDOOR: /* Doorbell interrupt */
1302 case POWERPC_EXCP_HV_MAINT: /* Hypervisor Maintenance exception */
1303 cpu_abort(cs, "%s exception not implemented\n",
1304 powerpc_excp_name(excp));
1305 break;
1306 default:
1307 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
1308 break;
1309 }
1310
1311 /* Sanity check */
1312 if (!(env->msr_mask & MSR_HVB)) {
1313 if (new_msr & MSR_HVB) {
1314 cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
1315 "no HV support\n", excp);
1316 }
1317 if (srr0 == SPR_HSRR0) {
1318 cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
1319 "no HV support\n", excp);
1320 }
1321 }
1322
1323 /*
1324 * Sort out endianness of interrupt, this differs depending on the
1325 * CPU, the HV mode, etc...
1326 */
1327 if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
1328 new_msr |= (target_ulong)1 << MSR_LE;
1329 }
1330
1331 new_msr |= (target_ulong)1 << MSR_SF;
1332
1333 if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
1334 /* Save PC */
1335 env->spr[srr0] = env->nip;
1336
1337 /* Save MSR */
1338 env->spr[srr1] = msr;
1339 }
1340
1341 /* This can update new_msr and vector if AIL applies */
1342 ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
1343
1344 powerpc_set_excp_state(cpu, vector, new_msr);
1345 }
1346 #else
1347 static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp)
1348 {
1349 g_assert_not_reached();
1350 }
1351 #endif
1352
1353 /*
1354 * Note that this function should be greatly optimized when called
1355 * with a constant excp, from ppc_hw_interrupt
1356 */
1357 static inline void powerpc_excp_legacy(PowerPCCPU *cpu, int excp)
1358 {
1359 CPUState *cs = CPU(cpu);
1360 CPUPPCState *env = &cpu->env;
1361 int excp_model = env->excp_model;
1362 target_ulong msr, new_msr, vector;
1363 int srr0, srr1, lev = -1;
1364
1365 if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
1366 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
1367 }
1368
1369 qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
1370 " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
1371 excp, env->error_code);
1372
1373 /* new srr1 value excluding must-be-zero bits */
1374 if (excp_model == POWERPC_EXCP_BOOKE) {
1375 msr = env->msr;
1376 } else {
1377 msr = env->msr & ~0x783f0000ULL;
1378 }
1379
1380 /*
1381 * new interrupt handler msr preserves existing HV and ME unless
1382 * explicitly overriden
1383 */
1384 new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
1385
1386 /* target registers */
1387 srr0 = SPR_SRR0;
1388 srr1 = SPR_SRR1;
1389
1390 /*
1391 * check for special resume at 0x100 from doze/nap/sleep/winkle on
1392 * P7/P8/P9
1393 */
1394 if (env->resume_as_sreset) {
1395 excp = powerpc_reset_wakeup(cs, env, excp, &msr);
1396 }
1397
1398 /*
1399 * Hypervisor emulation assistance interrupt only exists on server
1400 * arch 2.05 server or later. We also don't want to generate it if
1401 * we don't have HVB in msr_mask (PAPR mode).
1402 */
1403 if (excp == POWERPC_EXCP_HV_EMU
1404 #if defined(TARGET_PPC64)
1405 && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
1406 #endif /* defined(TARGET_PPC64) */
1407
1408 ) {
1409 excp = POWERPC_EXCP_PROGRAM;
1410 }
1411
1412 #ifdef TARGET_PPC64
1413 /*
1414 * SPEU and VPU share the same IVOR but they exist in different
1415 * processors. SPEU is e500v1/2 only and VPU is e6500 only.
1416 */
1417 if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
1418 excp = POWERPC_EXCP_SPEU;
1419 }
1420 #endif
1421
1422 vector = env->excp_vectors[excp];
1423 if (vector == (target_ulong)-1ULL) {
1424 cpu_abort(cs, "Raised an exception without defined vector %d\n",
1425 excp);
1426 }
1427
1428 vector |= env->excp_prefix;
1429
1430 switch (excp) {
1431 case POWERPC_EXCP_CRITICAL: /* Critical input */
1432 switch (excp_model) {
1433 case POWERPC_EXCP_40x:
1434 srr0 = SPR_40x_SRR2;
1435 srr1 = SPR_40x_SRR3;
1436 break;
1437 case POWERPC_EXCP_BOOKE:
1438 srr0 = SPR_BOOKE_CSRR0;
1439 srr1 = SPR_BOOKE_CSRR1;
1440 break;
1441 case POWERPC_EXCP_G2:
1442 break;
1443 default:
1444 goto excp_invalid;
1445 }
1446 break;
1447 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1448 if (msr_me == 0) {
1449 /*
1450 * Machine check exception is not enabled. Enter
1451 * checkstop state.
1452 */
1453 fprintf(stderr, "Machine check while not allowed. "
1454 "Entering checkstop state\n");
1455 if (qemu_log_separate()) {
1456 qemu_log("Machine check while not allowed. "
1457 "Entering checkstop state\n");
1458 }
1459 cs->halted = 1;
1460 cpu_interrupt_exittb(cs);
1461 }
1462 if (env->msr_mask & MSR_HVB) {
1463 /*
1464 * ISA specifies HV, but can be delivered to guest with HV
1465 * clear (e.g., see FWNMI in PAPR).
1466 */
1467 new_msr |= (target_ulong)MSR_HVB;
1468 }
1469
1470 /* machine check exceptions don't have ME set */
1471 new_msr &= ~((target_ulong)1 << MSR_ME);
1472
1473 /* XXX: should also have something loaded in DAR / DSISR */
1474 switch (excp_model) {
1475 case POWERPC_EXCP_40x:
1476 srr0 = SPR_40x_SRR2;
1477 srr1 = SPR_40x_SRR3;
1478 break;
1479 case POWERPC_EXCP_BOOKE:
1480 /* FIXME: choose one or the other based on CPU type */
1481 srr0 = SPR_BOOKE_MCSRR0;
1482 srr1 = SPR_BOOKE_MCSRR1;
1483
1484 env->spr[SPR_BOOKE_CSRR0] = env->nip;
1485 env->spr[SPR_BOOKE_CSRR1] = msr;
1486 break;
1487 default:
1488 break;
1489 }
1490 break;
1491 case POWERPC_EXCP_DSI: /* Data storage exception */
1492 trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
1493 break;
1494 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1495 trace_ppc_excp_isi(msr, env->nip);
1496 msr |= env->error_code;
1497 break;
1498 case POWERPC_EXCP_EXTERNAL: /* External input */
1499 {
1500 bool lpes0;
1501
1502 cs = CPU(cpu);
1503
1504 /*
1505 * Exception targeting modifiers
1506 *
1507 * LPES0 is supported on POWER7/8/9
1508 * LPES1 is not supported (old iSeries mode)
1509 *
1510 * On anything else, we behave as if LPES0 is 1
1511 * (externals don't alter MSR:HV)
1512 */
1513 #if defined(TARGET_PPC64)
1514 if (excp_model == POWERPC_EXCP_POWER7 ||
1515 excp_model == POWERPC_EXCP_POWER8 ||
1516 excp_model == POWERPC_EXCP_POWER9 ||
1517 excp_model == POWERPC_EXCP_POWER10) {
1518 lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
1519 } else
1520 #endif /* defined(TARGET_PPC64) */
1521 {
1522 lpes0 = true;
1523 }
1524
1525 if (!lpes0) {
1526 new_msr |= (target_ulong)MSR_HVB;
1527 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
1528 srr0 = SPR_HSRR0;
1529 srr1 = SPR_HSRR1;
1530 }
1531 if (env->mpic_proxy) {
1532 /* IACK the IRQ on delivery */
1533 env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
1534 }
1535 break;
1536 }
1537 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1538 /* Get rS/rD and rA from faulting opcode */
1539 /*
1540 * Note: the opcode fields will not be set properly for a
1541 * direct store load/store, but nobody cares as nobody
1542 * actually uses direct store segments.
1543 */
1544 env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
1545 break;
1546 case POWERPC_EXCP_PROGRAM: /* Program exception */
1547 switch (env->error_code & ~0xF) {
1548 case POWERPC_EXCP_FP:
1549 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
1550 trace_ppc_excp_fp_ignore();
1551 cs->exception_index = POWERPC_EXCP_NONE;
1552 env->error_code = 0;
1553 return;
1554 }
1555
1556 /*
1557 * FP exceptions always have NIP pointing to the faulting
1558 * instruction, so always use store_next and claim we are
1559 * precise in the MSR.
1560 */
1561 msr |= 0x00100000;
1562 env->spr[SPR_BOOKE_ESR] = ESR_FP;
1563 break;
1564 case POWERPC_EXCP_INVAL:
1565 trace_ppc_excp_inval(env->nip);
1566 msr |= 0x00080000;
1567 env->spr[SPR_BOOKE_ESR] = ESR_PIL;
1568 break;
1569 case POWERPC_EXCP_PRIV:
1570 msr |= 0x00040000;
1571 env->spr[SPR_BOOKE_ESR] = ESR_PPR;
1572 break;
1573 case POWERPC_EXCP_TRAP:
1574 msr |= 0x00020000;
1575 env->spr[SPR_BOOKE_ESR] = ESR_PTR;
1576 break;
1577 default:
1578 /* Should never occur */
1579 cpu_abort(cs, "Invalid program exception %d. Aborting\n",
1580 env->error_code);
1581 break;
1582 }
1583 break;
1584 case POWERPC_EXCP_SYSCALL: /* System call exception */
1585 lev = env->error_code;
1586
1587 if ((lev == 1) && cpu->vhyp) {
1588 dump_hcall(env);
1589 } else {
1590 dump_syscall(env);
1591 }
1592
1593 /*
1594 * We need to correct the NIP which in this case is supposed
1595 * to point to the next instruction
1596 */
1597 env->nip += 4;
1598
1599 /* "PAPR mode" built-in hypercall emulation */
1600 if ((lev == 1) && cpu->vhyp) {
1601 PPCVirtualHypervisorClass *vhc =
1602 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
1603 vhc->hypercall(cpu->vhyp, cpu);
1604 return;
1605 }
1606 if (lev == 1) {
1607 new_msr |= (target_ulong)MSR_HVB;
1608 }
1609 break;
1610 case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
1611 lev = env->error_code;
1612 dump_syscall(env);
1613 env->nip += 4;
1614 new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
1615 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
1616
1617 vector += lev * 0x20;
1618
1619 env->lr = env->nip;
1620 env->ctr = msr;
1621 break;
1622 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1623 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1624 case POWERPC_EXCP_DECR: /* Decrementer exception */
1625 break;
1626 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1627 /* FIT on 4xx */
1628 trace_ppc_excp_print("FIT");
1629 break;
1630 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1631 trace_ppc_excp_print("WDT");
1632 switch (excp_model) {
1633 case POWERPC_EXCP_BOOKE:
1634 srr0 = SPR_BOOKE_CSRR0;
1635 srr1 = SPR_BOOKE_CSRR1;
1636 break;
1637 default:
1638 break;
1639 }
1640 break;
1641 case POWERPC_EXCP_DTLB: /* Data TLB error */
1642 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1643 break;
1644 case POWERPC_EXCP_DEBUG: /* Debug interrupt */
1645 if (env->flags & POWERPC_FLAG_DE) {
1646 /* FIXME: choose one or the other based on CPU type */
1647 srr0 = SPR_BOOKE_DSRR0;
1648 srr1 = SPR_BOOKE_DSRR1;
1649
1650 env->spr[SPR_BOOKE_CSRR0] = env->nip;
1651 env->spr[SPR_BOOKE_CSRR1] = msr;
1652
1653 /* DBSR already modified by caller */
1654 } else {
1655 cpu_abort(cs, "Debug exception triggered on unsupported model\n");
1656 }
1657 break;
1658 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
1659 env->spr[SPR_BOOKE_ESR] = ESR_SPV;
1660 break;
1661 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1662 break;
1663 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1664 srr0 = SPR_BOOKE_CSRR0;
1665 srr1 = SPR_BOOKE_CSRR1;
1666 break;
1667 case POWERPC_EXCP_RESET: /* System reset exception */
1668 /* A power-saving exception sets ME, otherwise it is unchanged */
1669 if (msr_pow) {
1670 /* indicate that we resumed from power save mode */
1671 msr |= 0x10000;
1672 new_msr |= ((target_ulong)1 << MSR_ME);
1673 }
1674 if (env->msr_mask & MSR_HVB) {
1675 /*
1676 * ISA specifies HV, but can be delivered to guest with HV
1677 * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
1678 */
1679 new_msr |= (target_ulong)MSR_HVB;
1680 } else {
1681 if (msr_pow) {
1682 cpu_abort(cs, "Trying to deliver power-saving system reset "
1683 "exception %d with no HV support\n", excp);
1684 }
1685 }
1686 break;
1687 case POWERPC_EXCP_DSEG: /* Data segment exception */
1688 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1689 case POWERPC_EXCP_TRACE: /* Trace exception */
1690 break;
1691 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
1692 msr |= env->error_code;
1693 /* fall through */
1694 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1695 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1696 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1697 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
1698 case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
1699 case POWERPC_EXCP_HV_EMU:
1700 case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
1701 srr0 = SPR_HSRR0;
1702 srr1 = SPR_HSRR1;
1703 new_msr |= (target_ulong)MSR_HVB;
1704 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
1705 break;
1706 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1707 case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
1708 case POWERPC_EXCP_FU: /* Facility unavailable exception */
1709 #ifdef TARGET_PPC64
1710 env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
1711 #endif
1712 break;
1713 case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
1714 #ifdef TARGET_PPC64
1715 env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
1716 srr0 = SPR_HSRR0;
1717 srr1 = SPR_HSRR1;
1718 new_msr |= (target_ulong)MSR_HVB;
1719 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
1720 #endif
1721 break;
1722 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
1723 trace_ppc_excp_print("PIT");
1724 break;
1725 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1726 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1727 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1728 switch (excp_model) {
1729 case POWERPC_EXCP_603:
1730 case POWERPC_EXCP_G2:
1731 /* Swap temporary saved registers with GPRs */
1732 if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
1733 new_msr |= (target_ulong)1 << MSR_TGPR;
1734 hreg_swap_gpr_tgpr(env);
1735 }
1736 /* fall through */
1737 case POWERPC_EXCP_7x5:
1738 ppc_excp_debug_sw_tlb(env, excp);
1739
1740 msr |= env->crf[0] << 28;
1741 msr |= env->error_code; /* key, D/I, S/L bits */
1742 /* Set way using a LRU mechanism */
1743 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
1744 break;
1745 default:
1746 cpu_abort(cs, "Invalid TLB miss exception\n");
1747 break;
1748 }
1749 break;
1750 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
1751 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
1752 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
1753 case POWERPC_EXCP_IO: /* IO error exception */
1754 case POWERPC_EXCP_RUNM: /* Run mode exception */
1755 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1756 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1757 case POWERPC_EXCP_DABR: /* Data address breakpoint */
1758 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1759 case POWERPC_EXCP_SMI: /* System management interrupt */
1760 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1761 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
1762 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1763 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1764 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1765 case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
1766 case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
1767 cpu_abort(cs, "%s exception not implemented\n",
1768 powerpc_excp_name(excp));
1769 break;
1770 default:
1771 excp_invalid:
1772 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
1773 break;
1774 }
1775
1776 /* Sanity check */
1777 if (!(env->msr_mask & MSR_HVB)) {
1778 if (new_msr & MSR_HVB) {
1779 cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
1780 "no HV support\n", excp);
1781 }
1782 if (srr0 == SPR_HSRR0) {
1783 cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
1784 "no HV support\n", excp);
1785 }
1786 }
1787
1788 /*
1789 * Sort out endianness of interrupt, this differs depending on the
1790 * CPU, the HV mode, etc...
1791 */
1792 if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
1793 new_msr |= (target_ulong)1 << MSR_LE;
1794 }
1795
1796 #if defined(TARGET_PPC64)
1797 if (excp_model == POWERPC_EXCP_BOOKE) {
1798 if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
1799 /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
1800 new_msr |= (target_ulong)1 << MSR_CM;
1801 } else {
1802 vector = (uint32_t)vector;
1803 }
1804 } else {
1805 if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
1806 vector = (uint32_t)vector;
1807 } else {
1808 new_msr |= (target_ulong)1 << MSR_SF;
1809 }
1810 }
1811 #endif
1812
1813 if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
1814 /* Save PC */
1815 env->spr[srr0] = env->nip;
1816
1817 /* Save MSR */
1818 env->spr[srr1] = msr;
1819 }
1820
1821 /* This can update new_msr and vector if AIL applies */
1822 ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
1823
1824 powerpc_set_excp_state(cpu, vector, new_msr);
1825 }
1826
1827 static void powerpc_excp(PowerPCCPU *cpu, int excp)
1828 {
1829 CPUPPCState *env = &cpu->env;
1830
1831 switch (env->excp_model) {
1832 case POWERPC_EXCP_40x:
1833 powerpc_excp_40x(cpu, excp);
1834 break;
1835 case POWERPC_EXCP_74xx:
1836 powerpc_excp_74xx(cpu, excp);
1837 break;
1838 case POWERPC_EXCP_BOOKE:
1839 powerpc_excp_booke(cpu, excp);
1840 break;
1841 case POWERPC_EXCP_970:
1842 case POWERPC_EXCP_POWER7:
1843 case POWERPC_EXCP_POWER8:
1844 case POWERPC_EXCP_POWER9:
1845 case POWERPC_EXCP_POWER10:
1846 powerpc_excp_books(cpu, excp);
1847 break;
1848 default:
1849 powerpc_excp_legacy(cpu, excp);
1850 }
1851 }
1852
1853 void ppc_cpu_do_interrupt(CPUState *cs)
1854 {
1855 PowerPCCPU *cpu = POWERPC_CPU(cs);
1856
1857 powerpc_excp(cpu, cs->exception_index);
1858 }
1859
1860 static void ppc_hw_interrupt(CPUPPCState *env)
1861 {
1862 PowerPCCPU *cpu = env_archcpu(env);
1863 bool async_deliver;
1864
1865 /* External reset */
1866 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
1867 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
1868 powerpc_excp(cpu, POWERPC_EXCP_RESET);
1869 return;
1870 }
1871 /* Machine check exception */
1872 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
1873 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
1874 powerpc_excp(cpu, POWERPC_EXCP_MCHECK);
1875 return;
1876 }
1877 #if 0 /* TODO */
1878 /* External debug exception */
1879 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
1880 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
1881 powerpc_excp(cpu, POWERPC_EXCP_DEBUG);
1882 return;
1883 }
1884 #endif
1885
1886 /*
1887 * For interrupts that gate on MSR:EE, we need to do something a
1888 * bit more subtle, as we need to let them through even when EE is
1889 * clear when coming out of some power management states (in order
1890 * for them to become a 0x100).
1891 */
1892 async_deliver = (msr_ee != 0) || env->resume_as_sreset;
1893
1894 /* Hypervisor decrementer exception */
1895 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
1896 /* LPCR will be clear when not supported so this will work */
1897 bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
1898 if ((async_deliver || msr_hv == 0) && hdice) {
1899 /* HDEC clears on delivery */
1900 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
1901 powerpc_excp(cpu, POWERPC_EXCP_HDECR);
1902 return;
1903 }
1904 }
1905
1906 /* Hypervisor virtualization interrupt */
1907 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HVIRT)) {
1908 /* LPCR will be clear when not supported so this will work */
1909 bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE);
1910 if ((async_deliver || msr_hv == 0) && hvice) {
1911 powerpc_excp(cpu, POWERPC_EXCP_HVIRT);
1912 return;
1913 }
1914 }
1915
1916 /* External interrupt can ignore MSR:EE under some circumstances */
1917 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
1918 bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
1919 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
1920 /* HEIC blocks delivery to the hypervisor */
1921 if ((async_deliver && !(heic && msr_hv && !msr_pr)) ||
1922 (env->has_hv_mode && msr_hv == 0 && !lpes0)) {
1923 powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL);
1924 return;
1925 }
1926 }
1927 if (msr_ce != 0) {
1928 /* External critical interrupt */
1929 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
1930 powerpc_excp(cpu, POWERPC_EXCP_CRITICAL);
1931 return;
1932 }
1933 }
1934 if (async_deliver != 0) {
1935 /* Watchdog timer on embedded PowerPC */
1936 if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
1937 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
1938 powerpc_excp(cpu, POWERPC_EXCP_WDT);
1939 return;
1940 }
1941 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
1942 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
1943 powerpc_excp(cpu, POWERPC_EXCP_DOORCI);
1944 return;
1945 }
1946 /* Fixed interval timer on embedded PowerPC */
1947 if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
1948 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
1949 powerpc_excp(cpu, POWERPC_EXCP_FIT);
1950 return;
1951 }
1952 /* Programmable interval timer on embedded PowerPC */
1953 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
1954 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
1955 powerpc_excp(cpu, POWERPC_EXCP_PIT);
1956 return;
1957 }
1958 /* Decrementer exception */
1959 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
1960 if (ppc_decr_clear_on_delivery(env)) {
1961 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
1962 }
1963 powerpc_excp(cpu, POWERPC_EXCP_DECR);
1964 return;
1965 }
1966 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
1967 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
1968 if (is_book3s_arch2x(env)) {
1969 powerpc_excp(cpu, POWERPC_EXCP_SDOOR);
1970 } else {
1971 powerpc_excp(cpu, POWERPC_EXCP_DOORI);
1972 }
1973 return;
1974 }
1975 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDOORBELL)) {
1976 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDOORBELL);
1977 powerpc_excp(cpu, POWERPC_EXCP_SDOOR_HV);
1978 return;
1979 }
1980 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
1981 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
1982 powerpc_excp(cpu, POWERPC_EXCP_PERFM);
1983 return;
1984 }
1985 /* Thermal interrupt */
1986 if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
1987 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
1988 powerpc_excp(cpu, POWERPC_EXCP_THERM);
1989 return;
1990 }
1991 }
1992
1993 if (env->resume_as_sreset) {
1994 /*
1995 * This is a bug ! It means that has_work took us out of halt without
1996 * anything to deliver while in a PM state that requires getting
1997 * out via a 0x100
1998 *
1999 * This means we will incorrectly execute past the power management
2000 * instruction instead of triggering a reset.
2001 *
2002 * It generally means a discrepancy between the wakeup conditions in the
2003 * processor has_work implementation and the logic in this function.
2004 */
2005 cpu_abort(env_cpu(env),
2006 "Wakeup from PM state but interrupt Undelivered");
2007 }
2008 }
2009
2010 void ppc_cpu_do_system_reset(CPUState *cs)
2011 {
2012 PowerPCCPU *cpu = POWERPC_CPU(cs);
2013
2014 powerpc_excp(cpu, POWERPC_EXCP_RESET);
2015 }
2016
2017 void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector)
2018 {
2019 PowerPCCPU *cpu = POWERPC_CPU(cs);
2020 CPUPPCState *env = &cpu->env;
2021 target_ulong msr = 0;
2022
2023 /*
2024 * Set MSR and NIP for the handler, SRR0/1, DAR and DSISR have already
2025 * been set by KVM.
2026 */
2027 msr = (1ULL << MSR_ME);
2028 msr |= env->msr & (1ULL << MSR_SF);
2029 if (ppc_interrupts_little_endian(cpu, false)) {
2030 msr |= (1ULL << MSR_LE);
2031 }
2032
2033 powerpc_set_excp_state(cpu, vector, msr);
2034 }
2035
2036 bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
2037 {
2038 PowerPCCPU *cpu = POWERPC_CPU(cs);
2039 CPUPPCState *env = &cpu->env;
2040
2041 if (interrupt_request & CPU_INTERRUPT_HARD) {
2042 ppc_hw_interrupt(env);
2043 if (env->pending_interrupts == 0) {
2044 cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
2045 }
2046 return true;
2047 }
2048 return false;
2049 }
2050
2051 #endif /* !CONFIG_USER_ONLY */
2052
2053 /*****************************************************************************/
2054 /* Exceptions processing helpers */
2055
2056 void raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2057 uint32_t error_code, uintptr_t raddr)
2058 {
2059 CPUState *cs = env_cpu(env);
2060
2061 cs->exception_index = exception;
2062 env->error_code = error_code;
2063 cpu_loop_exit_restore(cs, raddr);
2064 }
2065
2066 void raise_exception_err(CPUPPCState *env, uint32_t exception,
2067 uint32_t error_code)
2068 {
2069 raise_exception_err_ra(env, exception, error_code, 0);
2070 }
2071
2072 void raise_exception(CPUPPCState *env, uint32_t exception)
2073 {
2074 raise_exception_err_ra(env, exception, 0, 0);
2075 }
2076
2077 void raise_exception_ra(CPUPPCState *env, uint32_t exception,
2078 uintptr_t raddr)
2079 {
2080 raise_exception_err_ra(env, exception, 0, raddr);
2081 }
2082
2083 #ifdef CONFIG_TCG
2084 void helper_raise_exception_err(CPUPPCState *env, uint32_t exception,
2085 uint32_t error_code)
2086 {
2087 raise_exception_err_ra(env, exception, error_code, 0);
2088 }
2089
2090 void helper_raise_exception(CPUPPCState *env, uint32_t exception)
2091 {
2092 raise_exception_err_ra(env, exception, 0, 0);
2093 }
2094 #endif
2095
2096 #if !defined(CONFIG_USER_ONLY)
2097 #ifdef CONFIG_TCG
2098 void helper_store_msr(CPUPPCState *env, target_ulong val)
2099 {
2100 uint32_t excp = hreg_store_msr(env, val, 0);
2101
2102 if (excp != 0) {
2103 CPUState *cs = env_cpu(env);
2104 cpu_interrupt_exittb(cs);
2105 raise_exception(env, excp);
2106 }
2107 }
2108
2109 #if defined(TARGET_PPC64)
2110 void helper_scv(CPUPPCState *env, uint32_t lev)
2111 {
2112 if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) {
2113 raise_exception_err(env, POWERPC_EXCP_SYSCALL_VECTORED, lev);
2114 } else {
2115 raise_exception_err(env, POWERPC_EXCP_FU, FSCR_IC_SCV);
2116 }
2117 }
2118
2119 void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
2120 {
2121 CPUState *cs;
2122
2123 cs = env_cpu(env);
2124 cs->halted = 1;
2125
2126 /* Condition for waking up at 0x100 */
2127 env->resume_as_sreset = (insn != PPC_PM_STOP) ||
2128 (env->spr[SPR_PSSCR] & PSSCR_EC);
2129 }
2130 #endif /* defined(TARGET_PPC64) */
2131
2132 static void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
2133 {
2134 CPUState *cs = env_cpu(env);
2135
2136 /* MSR:POW cannot be set by any form of rfi */
2137 msr &= ~(1ULL << MSR_POW);
2138
2139 /* MSR:TGPR cannot be set by any form of rfi */
2140 if (env->flags & POWERPC_FLAG_TGPR)
2141 msr &= ~(1ULL << MSR_TGPR);
2142
2143 #if defined(TARGET_PPC64)
2144 /* Switching to 32-bit ? Crop the nip */
2145 if (!msr_is_64bit(env, msr)) {
2146 nip = (uint32_t)nip;
2147 }
2148 #else
2149 nip = (uint32_t)nip;
2150 #endif
2151 /* XXX: beware: this is false if VLE is supported */
2152 env->nip = nip & ~((target_ulong)0x00000003);
2153 hreg_store_msr(env, msr, 1);
2154 trace_ppc_excp_rfi(env->nip, env->msr);
2155 /*
2156 * No need to raise an exception here, as rfi is always the last
2157 * insn of a TB
2158 */
2159 cpu_interrupt_exittb(cs);
2160 /* Reset the reservation */
2161 env->reserve_addr = -1;
2162
2163 /* Context synchronizing: check if TCG TLB needs flush */
2164 check_tlb_flush(env, false);
2165 }
2166
2167 void helper_rfi(CPUPPCState *env)
2168 {
2169 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful);
2170 }
2171
2172 #define MSR_BOOK3S_MASK
2173 #if defined(TARGET_PPC64)
2174 void helper_rfid(CPUPPCState *env)
2175 {
2176 /*
2177 * The architecture defines a number of rules for which bits can
2178 * change but in practice, we handle this in hreg_store_msr()
2179 * which will be called by do_rfi(), so there is no need to filter
2180 * here
2181 */
2182 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]);
2183 }
2184
2185 void helper_rfscv(CPUPPCState *env)
2186 {
2187 do_rfi(env, env->lr, env->ctr);
2188 }
2189
2190 void helper_hrfid(CPUPPCState *env)
2191 {
2192 do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
2193 }
2194 #endif
2195
2196 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
2197 void helper_rfebb(CPUPPCState *env, target_ulong s)
2198 {
2199 target_ulong msr = env->msr;
2200
2201 /*
2202 * Handling of BESCR bits 32:33 according to PowerISA v3.1:
2203 *
2204 * "If BESCR 32:33 != 0b00 the instruction is treated as if
2205 * the instruction form were invalid."
2206 */
2207 if (env->spr[SPR_BESCR] & BESCR_INVALID) {
2208 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
2209 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
2210 }
2211
2212 env->nip = env->spr[SPR_EBBRR];
2213
2214 /* Switching to 32-bit ? Crop the nip */
2215 if (!msr_is_64bit(env, msr)) {
2216 env->nip = (uint32_t)env->spr[SPR_EBBRR];
2217 }
2218
2219 if (s) {
2220 env->spr[SPR_BESCR] |= BESCR_GE;
2221 } else {
2222 env->spr[SPR_BESCR] &= ~BESCR_GE;
2223 }
2224 }
2225 #endif
2226
2227 /*****************************************************************************/
2228 /* Embedded PowerPC specific helpers */
2229 void helper_40x_rfci(CPUPPCState *env)
2230 {
2231 do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]);
2232 }
2233
2234 void helper_rfci(CPUPPCState *env)
2235 {
2236 do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]);
2237 }
2238
2239 void helper_rfdi(CPUPPCState *env)
2240 {
2241 /* FIXME: choose CSRR1 or DSRR1 based on cpu type */
2242 do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1]);
2243 }
2244
2245 void helper_rfmci(CPUPPCState *env)
2246 {
2247 /* FIXME: choose CSRR1 or MCSRR1 based on cpu type */
2248 do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
2249 }
2250 #endif /* CONFIG_TCG */
2251 #endif /* !defined(CONFIG_USER_ONLY) */
2252
2253 #ifdef CONFIG_TCG
2254 void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
2255 uint32_t flags)
2256 {
2257 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
2258 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
2259 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
2260 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
2261 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
2262 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
2263 POWERPC_EXCP_TRAP, GETPC());
2264 }
2265 }
2266
2267 #if defined(TARGET_PPC64)
2268 void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
2269 uint32_t flags)
2270 {
2271 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
2272 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
2273 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
2274 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
2275 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) {
2276 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
2277 POWERPC_EXCP_TRAP, GETPC());
2278 }
2279 }
2280 #endif
2281 #endif
2282
2283 #if !defined(CONFIG_USER_ONLY)
2284 /*****************************************************************************/
2285 /* PowerPC 601 specific instructions (POWER bridge) */
2286
2287 #ifdef CONFIG_TCG
2288 void helper_rfsvc(CPUPPCState *env)
2289 {
2290 do_rfi(env, env->lr, env->ctr & 0x0000FFFF);
2291 }
2292
2293 /* Embedded.Processor Control */
2294 static int dbell2irq(target_ulong rb)
2295 {
2296 int msg = rb & DBELL_TYPE_MASK;
2297 int irq = -1;
2298
2299 switch (msg) {
2300 case DBELL_TYPE_DBELL:
2301 irq = PPC_INTERRUPT_DOORBELL;
2302 break;
2303 case DBELL_TYPE_DBELL_CRIT:
2304 irq = PPC_INTERRUPT_CDOORBELL;
2305 break;
2306 case DBELL_TYPE_G_DBELL:
2307 case DBELL_TYPE_G_DBELL_CRIT:
2308 case DBELL_TYPE_G_DBELL_MC:
2309 /* XXX implement */
2310 default:
2311 break;
2312 }
2313
2314 return irq;
2315 }
2316
2317 void helper_msgclr(CPUPPCState *env, target_ulong rb)
2318 {
2319 int irq = dbell2irq(rb);
2320
2321 if (irq < 0) {
2322 return;
2323 }
2324
2325 env->pending_interrupts &= ~(1 << irq);
2326 }
2327
2328 void helper_msgsnd(target_ulong rb)
2329 {
2330 int irq = dbell2irq(rb);
2331 int pir = rb & DBELL_PIRTAG_MASK;
2332 CPUState *cs;
2333
2334 if (irq < 0) {
2335 return;
2336 }
2337
2338 qemu_mutex_lock_iothread();
2339 CPU_FOREACH(cs) {
2340 PowerPCCPU *cpu = POWERPC_CPU(cs);
2341 CPUPPCState *cenv = &cpu->env;
2342
2343 if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) {
2344 cenv->pending_interrupts |= 1 << irq;
2345 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
2346 }
2347 }
2348 qemu_mutex_unlock_iothread();
2349 }
2350
2351 /* Server Processor Control */
2352
2353 static bool dbell_type_server(target_ulong rb)
2354 {
2355 /*
2356 * A Directed Hypervisor Doorbell message is sent only if the
2357 * message type is 5. All other types are reserved and the
2358 * instruction is a no-op
2359 */
2360 return (rb & DBELL_TYPE_MASK) == DBELL_TYPE_DBELL_SERVER;
2361 }
2362
2363 void helper_book3s_msgclr(CPUPPCState *env, target_ulong rb)
2364 {
2365 if (!dbell_type_server(rb)) {
2366 return;
2367 }
2368
2369 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDOORBELL);
2370 }
2371
2372 static void book3s_msgsnd_common(int pir, int irq)
2373 {
2374 CPUState *cs;
2375
2376 qemu_mutex_lock_iothread();
2377 CPU_FOREACH(cs) {
2378 PowerPCCPU *cpu = POWERPC_CPU(cs);
2379 CPUPPCState *cenv = &cpu->env;
2380
2381 /* TODO: broadcast message to all threads of the same processor */
2382 if (cenv->spr_cb[SPR_PIR].default_value == pir) {
2383 cenv->pending_interrupts |= 1 << irq;
2384 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
2385 }
2386 }
2387 qemu_mutex_unlock_iothread();
2388 }
2389
2390 void helper_book3s_msgsnd(target_ulong rb)
2391 {
2392 int pir = rb & DBELL_PROCIDTAG_MASK;
2393
2394 if (!dbell_type_server(rb)) {
2395 return;
2396 }
2397
2398 book3s_msgsnd_common(pir, PPC_INTERRUPT_HDOORBELL);
2399 }
2400
2401 #if defined(TARGET_PPC64)
2402 void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb)
2403 {
2404 helper_hfscr_facility_check(env, HFSCR_MSGP, "msgclrp", HFSCR_IC_MSGP);
2405
2406 if (!dbell_type_server(rb)) {
2407 return;
2408 }
2409
2410 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
2411 }
2412
2413 /*
2414 * sends a message to other threads that are on the same
2415 * multi-threaded processor
2416 */
2417 void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb)
2418 {
2419 int pir = env->spr_cb[SPR_PIR].default_value;
2420
2421 helper_hfscr_facility_check(env, HFSCR_MSGP, "msgsndp", HFSCR_IC_MSGP);
2422
2423 if (!dbell_type_server(rb)) {
2424 return;
2425 }
2426
2427 /* TODO: TCG supports only one thread */
2428
2429 book3s_msgsnd_common(pir, PPC_INTERRUPT_DOORBELL);
2430 }
2431 #endif /* TARGET_PPC64 */
2432
2433 void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
2434 MMUAccessType access_type,
2435 int mmu_idx, uintptr_t retaddr)
2436 {
2437 CPUPPCState *env = cs->env_ptr;
2438 uint32_t insn;
2439
2440 /* Restore state and reload the insn we executed, for filling in DSISR. */
2441 cpu_restore_state(cs, retaddr, true);
2442 insn = cpu_ldl_code(env, env->nip);
2443
2444 switch (env->mmu_model) {
2445 case POWERPC_MMU_SOFT_4xx:
2446 env->spr[SPR_40x_DEAR] = vaddr;
2447 break;
2448 case POWERPC_MMU_BOOKE:
2449 case POWERPC_MMU_BOOKE206:
2450 env->spr[SPR_BOOKE_DEAR] = vaddr;
2451 break;
2452 default:
2453 env->spr[SPR_DAR] = vaddr;
2454 break;
2455 }
2456
2457 cs->exception_index = POWERPC_EXCP_ALIGN;
2458 env->error_code = insn & 0x03FF0000;
2459 cpu_loop_exit(cs);
2460 }
2461 #endif /* CONFIG_TCG */
2462 #endif /* !CONFIG_USER_ONLY */
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