2 * ARM Generic/Distributed Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 /* This file contains implementation code for the RealView EB interrupt
11 controller, MPCore distributed interrupt controller and ARMv7-M
12 Nested Vectored Interrupt Controller. */
16 /* Maximum number of possible interrupts, determined by the GIC architecture */
17 #define GIC_MAXIRQ 1020
18 /* First 32 are private to each CPU (SGIs and PPIs). */
19 #define GIC_INTERNAL 32
20 /* Maximum number of possible CPU interfaces, determined by GIC architecture */
30 #define DPRINTF(fmt, ...) \
31 do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0)
33 #define DPRINTF(fmt, ...) do {} while(0)
37 static const uint8_t gic_id
[] =
38 { 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 };
39 /* The NVIC has 16 internal vectors. However these are not exposed
40 through the normal GIC interface. */
41 #define GIC_BASE_IRQ 32
43 static const uint8_t gic_id
[] =
44 { 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
45 #define GIC_BASE_IRQ 0
48 #define FROM_SYSBUSGIC(type, dev) \
49 DO_UPCAST(type, gic, FROM_SYSBUS(gic_state, dev))
51 typedef struct gic_irq_state
53 /* The enable bits are only banked for per-cpu interrupts. */
54 unsigned enabled
:NCPU
;
55 unsigned pending
:NCPU
;
58 unsigned model
:1; /* 0 = N:N, 1 = 1:N */
59 unsigned trigger
:1; /* nonzero = edge triggered. */
62 #define ALL_CPU_MASK ((unsigned)(((1 << NCPU) - 1)))
64 #define NUM_CPU(s) ((s)->num_cpu)
69 #define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
70 #define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
71 #define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
72 #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
73 #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
74 #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0)
75 #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
76 #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
77 #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
78 #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1
79 #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0
80 #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
81 #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
82 #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
83 #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
84 #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
85 #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
86 #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
87 #define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \
88 s->priority1[irq][cpu] : \
89 s->priority2[(irq) - GIC_INTERNAL])
91 #define GIC_TARGET(irq) 1
93 #define GIC_TARGET(irq) s->irq_target[irq]
96 typedef struct gic_state
99 qemu_irq parent_irq
[NCPU
];
101 int cpu_enabled
[NCPU
];
103 gic_irq_state irq_state
[GIC_MAXIRQ
];
105 int irq_target
[GIC_MAXIRQ
];
107 int priority1
[GIC_INTERNAL
][NCPU
];
108 int priority2
[GIC_MAXIRQ
- GIC_INTERNAL
];
109 int last_active
[GIC_MAXIRQ
][NCPU
];
111 int priority_mask
[NCPU
];
112 int running_irq
[NCPU
];
113 int running_priority
[NCPU
];
114 int current_pending
[NCPU
];
120 MemoryRegion iomem
; /* Distributor */
122 /* This is just so we can have an opaque pointer which identifies
123 * both this GIC and which CPU interface we should be accessing.
125 struct gic_state
*backref
[NCPU
];
126 MemoryRegion cpuiomem
[NCPU
+1]; /* CPU interfaces */
131 static inline int gic_get_current_cpu(gic_state
*s
)
134 if (s
->num_cpu
> 1) {
135 return cpu_single_env
->cpu_index
;
141 /* TODO: Many places that call this routine could be optimized. */
142 /* Update interrupt status after enabled or pending bits have been changed. */
143 static void gic_update(gic_state
*s
)
152 for (cpu
= 0; cpu
< NUM_CPU(s
); cpu
++) {
154 s
->current_pending
[cpu
] = 1023;
155 if (!s
->enabled
|| !s
->cpu_enabled
[cpu
]) {
156 qemu_irq_lower(s
->parent_irq
[cpu
]);
161 for (irq
= 0; irq
< s
->num_irq
; irq
++) {
162 if (GIC_TEST_ENABLED(irq
, cm
) && GIC_TEST_PENDING(irq
, cm
)) {
163 if (GIC_GET_PRIORITY(irq
, cpu
) < best_prio
) {
164 best_prio
= GIC_GET_PRIORITY(irq
, cpu
);
170 if (best_prio
<= s
->priority_mask
[cpu
]) {
171 s
->current_pending
[cpu
] = best_irq
;
172 if (best_prio
< s
->running_priority
[cpu
]) {
173 DPRINTF("Raised pending IRQ %d\n", best_irq
);
177 qemu_set_irq(s
->parent_irq
[cpu
], level
);
181 static void __attribute__((unused
))
182 gic_set_pending_private(gic_state
*s
, int cpu
, int irq
)
186 if (GIC_TEST_PENDING(irq
, cm
))
189 DPRINTF("Set %d pending cpu %d\n", irq
, cpu
);
190 GIC_SET_PENDING(irq
, cm
);
194 /* Process a change in an external IRQ input. */
195 static void gic_set_irq(void *opaque
, int irq
, int level
)
197 /* Meaning of the 'irq' parameter:
198 * [0..N-1] : external interrupts
199 * [N..N+31] : PPI (internal) interrupts for CPU 0
200 * [N+32..N+63] : PPI (internal interrupts for CPU 1
203 gic_state
*s
= (gic_state
*)opaque
;
205 if (irq
< (s
->num_irq
- GIC_INTERNAL
)) {
206 /* The first external input line is internal interrupt 32. */
209 target
= GIC_TARGET(irq
);
212 irq
-= (s
->num_irq
- GIC_INTERNAL
);
213 cpu
= irq
/ GIC_INTERNAL
;
219 if (level
== GIC_TEST_LEVEL(irq
, cm
)) {
224 GIC_SET_LEVEL(irq
, cm
);
225 if (GIC_TEST_TRIGGER(irq
) || GIC_TEST_ENABLED(irq
, cm
)) {
226 DPRINTF("Set %d pending mask %x\n", irq
, target
);
227 GIC_SET_PENDING(irq
, target
);
230 GIC_CLEAR_LEVEL(irq
, cm
);
235 static void gic_set_running_irq(gic_state
*s
, int cpu
, int irq
)
237 s
->running_irq
[cpu
] = irq
;
239 s
->running_priority
[cpu
] = 0x100;
241 s
->running_priority
[cpu
] = GIC_GET_PRIORITY(irq
, cpu
);
246 static uint32_t gic_acknowledge_irq(gic_state
*s
, int cpu
)
250 new_irq
= s
->current_pending
[cpu
];
252 || GIC_GET_PRIORITY(new_irq
, cpu
) >= s
->running_priority
[cpu
]) {
253 DPRINTF("ACK no pending IRQ\n");
256 s
->last_active
[new_irq
][cpu
] = s
->running_irq
[cpu
];
257 /* Clear pending flags for both level and edge triggered interrupts.
258 Level triggered IRQs will be reasserted once they become inactive. */
259 GIC_CLEAR_PENDING(new_irq
, GIC_TEST_MODEL(new_irq
) ? ALL_CPU_MASK
: cm
);
260 gic_set_running_irq(s
, cpu
, new_irq
);
261 DPRINTF("ACK %d\n", new_irq
);
265 static void gic_complete_irq(gic_state
* s
, int cpu
, int irq
)
269 DPRINTF("EOI %d\n", irq
);
270 if (irq
>= s
->num_irq
) {
271 /* This handles two cases:
272 * 1. If software writes the ID of a spurious interrupt [ie 1023]
273 * to the GICC_EOIR, the GIC ignores that write.
274 * 2. If software writes the number of a non-existent interrupt
275 * this must be a subcase of "value written does not match the last
276 * valid interrupt value read from the Interrupt Acknowledge
277 * register" and so this is UNPREDICTABLE. We choose to ignore it.
281 if (s
->running_irq
[cpu
] == 1023)
282 return; /* No active IRQ. */
283 /* Mark level triggered interrupts as pending if they are still
285 if (!GIC_TEST_TRIGGER(irq
) && GIC_TEST_ENABLED(irq
, cm
)
286 && GIC_TEST_LEVEL(irq
, cm
) && (GIC_TARGET(irq
) & cm
) != 0) {
287 DPRINTF("Set %d pending mask %x\n", irq
, cm
);
288 GIC_SET_PENDING(irq
, cm
);
291 if (irq
!= s
->running_irq
[cpu
]) {
292 /* Complete an IRQ that is not currently running. */
293 int tmp
= s
->running_irq
[cpu
];
294 while (s
->last_active
[tmp
][cpu
] != 1023) {
295 if (s
->last_active
[tmp
][cpu
] == irq
) {
296 s
->last_active
[tmp
][cpu
] = s
->last_active
[irq
][cpu
];
299 tmp
= s
->last_active
[tmp
][cpu
];
305 /* Complete the current running IRQ. */
306 gic_set_running_irq(s
, cpu
, s
->last_active
[s
->running_irq
[cpu
]][cpu
]);
310 static uint32_t gic_dist_readb(void *opaque
, target_phys_addr_t offset
)
312 gic_state
*s
= (gic_state
*)opaque
;
320 cpu
= gic_get_current_cpu(s
);
322 if (offset
< 0x100) {
327 return ((s
->num_irq
/ 32) - 1) | ((NUM_CPU(s
) - 1) << 5);
330 if (offset
>= 0x80) {
331 /* Interrupt Security , RAZ/WI */
336 } else if (offset
< 0x200) {
337 /* Interrupt Set/Clear Enable. */
339 irq
= (offset
- 0x100) * 8;
341 irq
= (offset
- 0x180) * 8;
343 if (irq
>= s
->num_irq
)
346 for (i
= 0; i
< 8; i
++) {
347 if (GIC_TEST_ENABLED(irq
+ i
, cm
)) {
351 } else if (offset
< 0x300) {
352 /* Interrupt Set/Clear Pending. */
354 irq
= (offset
- 0x200) * 8;
356 irq
= (offset
- 0x280) * 8;
358 if (irq
>= s
->num_irq
)
361 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
362 for (i
= 0; i
< 8; i
++) {
363 if (GIC_TEST_PENDING(irq
+ i
, mask
)) {
367 } else if (offset
< 0x400) {
368 /* Interrupt Active. */
369 irq
= (offset
- 0x300) * 8 + GIC_BASE_IRQ
;
370 if (irq
>= s
->num_irq
)
373 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
374 for (i
= 0; i
< 8; i
++) {
375 if (GIC_TEST_ACTIVE(irq
+ i
, mask
)) {
379 } else if (offset
< 0x800) {
380 /* Interrupt Priority. */
381 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
382 if (irq
>= s
->num_irq
)
384 res
= GIC_GET_PRIORITY(irq
, cpu
);
386 } else if (offset
< 0xc00) {
387 /* Interrupt CPU Target. */
388 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
389 if (irq
>= s
->num_irq
)
391 if (irq
>= 29 && irq
<= 31) {
394 res
= GIC_TARGET(irq
);
396 } else if (offset
< 0xf00) {
397 /* Interrupt Configuration. */
398 irq
= (offset
- 0xc00) * 2 + GIC_BASE_IRQ
;
399 if (irq
>= s
->num_irq
)
402 for (i
= 0; i
< 4; i
++) {
403 if (GIC_TEST_MODEL(irq
+ i
))
404 res
|= (1 << (i
* 2));
405 if (GIC_TEST_TRIGGER(irq
+ i
))
406 res
|= (2 << (i
* 2));
409 } else if (offset
< 0xfe0) {
411 } else /* offset >= 0xfe0 */ {
415 res
= gic_id
[(offset
- 0xfe0) >> 2];
420 hw_error("gic_dist_readb: Bad offset %x\n", (int)offset
);
424 static uint32_t gic_dist_readw(void *opaque
, target_phys_addr_t offset
)
427 val
= gic_dist_readb(opaque
, offset
);
428 val
|= gic_dist_readb(opaque
, offset
+ 1) << 8;
432 static uint32_t gic_dist_readl(void *opaque
, target_phys_addr_t offset
)
436 gic_state
*s
= (gic_state
*)opaque
;
439 if (addr
< 0x100 || addr
> 0xd00)
440 return nvic_readl(s
, addr
);
442 val
= gic_dist_readw(opaque
, offset
);
443 val
|= gic_dist_readw(opaque
, offset
+ 2) << 16;
447 static void gic_dist_writeb(void *opaque
, target_phys_addr_t offset
,
450 gic_state
*s
= (gic_state
*)opaque
;
455 cpu
= gic_get_current_cpu(s
);
456 if (offset
< 0x100) {
461 s
->enabled
= (value
& 1);
462 DPRINTF("Distribution %sabled\n", s
->enabled
? "En" : "Dis");
463 } else if (offset
< 4) {
465 } else if (offset
>= 0x80) {
466 /* Interrupt Security Registers, RAZ/WI */
471 } else if (offset
< 0x180) {
472 /* Interrupt Set Enable. */
473 irq
= (offset
- 0x100) * 8 + GIC_BASE_IRQ
;
474 if (irq
>= s
->num_irq
)
478 for (i
= 0; i
< 8; i
++) {
479 if (value
& (1 << i
)) {
480 int mask
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : GIC_TARGET(irq
);
481 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
483 if (!GIC_TEST_ENABLED(irq
+ i
, cm
)) {
484 DPRINTF("Enabled IRQ %d\n", irq
+ i
);
486 GIC_SET_ENABLED(irq
+ i
, cm
);
487 /* If a raised level triggered IRQ enabled then mark
489 if (GIC_TEST_LEVEL(irq
+ i
, mask
)
490 && !GIC_TEST_TRIGGER(irq
+ i
)) {
491 DPRINTF("Set %d pending mask %x\n", irq
+ i
, mask
);
492 GIC_SET_PENDING(irq
+ i
, mask
);
496 } else if (offset
< 0x200) {
497 /* Interrupt Clear Enable. */
498 irq
= (offset
- 0x180) * 8 + GIC_BASE_IRQ
;
499 if (irq
>= s
->num_irq
)
503 for (i
= 0; i
< 8; i
++) {
504 if (value
& (1 << i
)) {
505 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
507 if (GIC_TEST_ENABLED(irq
+ i
, cm
)) {
508 DPRINTF("Disabled IRQ %d\n", irq
+ i
);
510 GIC_CLEAR_ENABLED(irq
+ i
, cm
);
513 } else if (offset
< 0x280) {
514 /* Interrupt Set Pending. */
515 irq
= (offset
- 0x200) * 8 + GIC_BASE_IRQ
;
516 if (irq
>= s
->num_irq
)
521 for (i
= 0; i
< 8; i
++) {
522 if (value
& (1 << i
)) {
523 GIC_SET_PENDING(irq
+ i
, GIC_TARGET(irq
));
526 } else if (offset
< 0x300) {
527 /* Interrupt Clear Pending. */
528 irq
= (offset
- 0x280) * 8 + GIC_BASE_IRQ
;
529 if (irq
>= s
->num_irq
)
531 for (i
= 0; i
< 8; i
++) {
532 /* ??? This currently clears the pending bit for all CPUs, even
533 for per-CPU interrupts. It's unclear whether this is the
535 if (value
& (1 << i
)) {
536 GIC_CLEAR_PENDING(irq
+ i
, ALL_CPU_MASK
);
539 } else if (offset
< 0x400) {
540 /* Interrupt Active. */
542 } else if (offset
< 0x800) {
543 /* Interrupt Priority. */
544 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
545 if (irq
>= s
->num_irq
)
547 if (irq
< GIC_INTERNAL
) {
548 s
->priority1
[irq
][cpu
] = value
;
550 s
->priority2
[irq
- GIC_INTERNAL
] = value
;
553 } else if (offset
< 0xc00) {
554 /* Interrupt CPU Target. */
555 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
556 if (irq
>= s
->num_irq
)
560 else if (irq
< GIC_INTERNAL
)
561 value
= ALL_CPU_MASK
;
562 s
->irq_target
[irq
] = value
& ALL_CPU_MASK
;
563 } else if (offset
< 0xf00) {
564 /* Interrupt Configuration. */
565 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
566 if (irq
>= s
->num_irq
)
568 if (irq
< GIC_INTERNAL
)
570 for (i
= 0; i
< 4; i
++) {
571 if (value
& (1 << (i
* 2))) {
572 GIC_SET_MODEL(irq
+ i
);
574 GIC_CLEAR_MODEL(irq
+ i
);
576 if (value
& (2 << (i
* 2))) {
577 GIC_SET_TRIGGER(irq
+ i
);
579 GIC_CLEAR_TRIGGER(irq
+ i
);
584 /* 0xf00 is only handled for 32-bit writes. */
590 hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset
);
593 static void gic_dist_writew(void *opaque
, target_phys_addr_t offset
,
596 gic_dist_writeb(opaque
, offset
, value
& 0xff);
597 gic_dist_writeb(opaque
, offset
+ 1, value
>> 8);
600 static void gic_dist_writel(void *opaque
, target_phys_addr_t offset
,
603 gic_state
*s
= (gic_state
*)opaque
;
607 if (addr
< 0x100 || (addr
> 0xd00 && addr
!= 0xf00)) {
608 nvic_writel(s
, addr
, value
);
612 if (offset
== 0xf00) {
617 cpu
= gic_get_current_cpu(s
);
619 switch ((value
>> 24) & 3) {
621 mask
= (value
>> 16) & ALL_CPU_MASK
;
624 mask
= ALL_CPU_MASK
^ (1 << cpu
);
630 DPRINTF("Bad Soft Int target filter\n");
634 GIC_SET_PENDING(irq
, mask
);
638 gic_dist_writew(opaque
, offset
, value
& 0xffff);
639 gic_dist_writew(opaque
, offset
+ 2, value
>> 16);
642 static const MemoryRegionOps gic_dist_ops
= {
644 .read
= { gic_dist_readb
, gic_dist_readw
, gic_dist_readl
, },
645 .write
= { gic_dist_writeb
, gic_dist_writew
, gic_dist_writel
, },
647 .endianness
= DEVICE_NATIVE_ENDIAN
,
651 static uint32_t gic_cpu_read(gic_state
*s
, int cpu
, int offset
)
654 case 0x00: /* Control */
655 return s
->cpu_enabled
[cpu
];
656 case 0x04: /* Priority mask */
657 return s
->priority_mask
[cpu
];
658 case 0x08: /* Binary Point */
659 /* ??? Not implemented. */
661 case 0x0c: /* Acknowledge */
662 return gic_acknowledge_irq(s
, cpu
);
663 case 0x14: /* Running Priority */
664 return s
->running_priority
[cpu
];
665 case 0x18: /* Highest Pending Interrupt */
666 return s
->current_pending
[cpu
];
668 hw_error("gic_cpu_read: Bad offset %x\n", (int)offset
);
673 static void gic_cpu_write(gic_state
*s
, int cpu
, int offset
, uint32_t value
)
676 case 0x00: /* Control */
677 s
->cpu_enabled
[cpu
] = (value
& 1);
678 DPRINTF("CPU %d %sabled\n", cpu
, s
->cpu_enabled
? "En" : "Dis");
680 case 0x04: /* Priority mask */
681 s
->priority_mask
[cpu
] = (value
& 0xff);
683 case 0x08: /* Binary Point */
684 /* ??? Not implemented. */
686 case 0x10: /* End Of Interrupt */
687 return gic_complete_irq(s
, cpu
, value
& 0x3ff);
689 hw_error("gic_cpu_write: Bad offset %x\n", (int)offset
);
695 /* Wrappers to read/write the GIC CPU interface for the current CPU */
696 static uint64_t gic_thiscpu_read(void *opaque
, target_phys_addr_t addr
,
699 gic_state
*s
= (gic_state
*)opaque
;
700 return gic_cpu_read(s
, gic_get_current_cpu(s
), addr
);
703 static void gic_thiscpu_write(void *opaque
, target_phys_addr_t addr
,
704 uint64_t value
, unsigned size
)
706 gic_state
*s
= (gic_state
*)opaque
;
707 gic_cpu_write(s
, gic_get_current_cpu(s
), addr
, value
);
710 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
711 * These just decode the opaque pointer into gic_state* + cpu id.
713 static uint64_t gic_do_cpu_read(void *opaque
, target_phys_addr_t addr
,
716 gic_state
**backref
= (gic_state
**)opaque
;
717 gic_state
*s
= *backref
;
718 int id
= (backref
- s
->backref
);
719 return gic_cpu_read(s
, id
, addr
);
722 static void gic_do_cpu_write(void *opaque
, target_phys_addr_t addr
,
723 uint64_t value
, unsigned size
)
725 gic_state
**backref
= (gic_state
**)opaque
;
726 gic_state
*s
= *backref
;
727 int id
= (backref
- s
->backref
);
728 gic_cpu_write(s
, id
, addr
, value
);
731 static const MemoryRegionOps gic_thiscpu_ops
= {
732 .read
= gic_thiscpu_read
,
733 .write
= gic_thiscpu_write
,
734 .endianness
= DEVICE_NATIVE_ENDIAN
,
737 static const MemoryRegionOps gic_cpu_ops
= {
738 .read
= gic_do_cpu_read
,
739 .write
= gic_do_cpu_write
,
740 .endianness
= DEVICE_NATIVE_ENDIAN
,
744 static void gic_reset(DeviceState
*dev
)
746 gic_state
*s
= FROM_SYSBUS(gic_state
, sysbus_from_qdev(dev
));
748 memset(s
->irq_state
, 0, GIC_MAXIRQ
* sizeof(gic_irq_state
));
749 for (i
= 0 ; i
< NUM_CPU(s
); i
++) {
750 s
->priority_mask
[i
] = 0xf0;
751 s
->current_pending
[i
] = 1023;
752 s
->running_irq
[i
] = 1023;
753 s
->running_priority
[i
] = 0x100;
755 /* The NVIC doesn't have per-cpu interfaces, so enable by default. */
756 s
->cpu_enabled
[i
] = 1;
758 s
->cpu_enabled
[i
] = 0;
761 for (i
= 0; i
< 16; i
++) {
762 GIC_SET_ENABLED(i
, ALL_CPU_MASK
);
766 /* The NVIC is always enabled. */
773 static void gic_save(QEMUFile
*f
, void *opaque
)
775 gic_state
*s
= (gic_state
*)opaque
;
779 qemu_put_be32(f
, s
->enabled
);
780 for (i
= 0; i
< NUM_CPU(s
); i
++) {
781 qemu_put_be32(f
, s
->cpu_enabled
[i
]);
782 for (j
= 0; j
< GIC_INTERNAL
; j
++)
783 qemu_put_be32(f
, s
->priority1
[j
][i
]);
784 for (j
= 0; j
< s
->num_irq
; j
++)
785 qemu_put_be32(f
, s
->last_active
[j
][i
]);
786 qemu_put_be32(f
, s
->priority_mask
[i
]);
787 qemu_put_be32(f
, s
->running_irq
[i
]);
788 qemu_put_be32(f
, s
->running_priority
[i
]);
789 qemu_put_be32(f
, s
->current_pending
[i
]);
791 for (i
= 0; i
< s
->num_irq
- GIC_INTERNAL
; i
++) {
792 qemu_put_be32(f
, s
->priority2
[i
]);
794 for (i
= 0; i
< s
->num_irq
; i
++) {
796 qemu_put_be32(f
, s
->irq_target
[i
]);
798 qemu_put_byte(f
, s
->irq_state
[i
].enabled
);
799 qemu_put_byte(f
, s
->irq_state
[i
].pending
);
800 qemu_put_byte(f
, s
->irq_state
[i
].active
);
801 qemu_put_byte(f
, s
->irq_state
[i
].level
);
802 qemu_put_byte(f
, s
->irq_state
[i
].model
);
803 qemu_put_byte(f
, s
->irq_state
[i
].trigger
);
807 static int gic_load(QEMUFile
*f
, void *opaque
, int version_id
)
809 gic_state
*s
= (gic_state
*)opaque
;
816 s
->enabled
= qemu_get_be32(f
);
817 for (i
= 0; i
< NUM_CPU(s
); i
++) {
818 s
->cpu_enabled
[i
] = qemu_get_be32(f
);
819 for (j
= 0; j
< GIC_INTERNAL
; j
++)
820 s
->priority1
[j
][i
] = qemu_get_be32(f
);
821 for (j
= 0; j
< s
->num_irq
; j
++)
822 s
->last_active
[j
][i
] = qemu_get_be32(f
);
823 s
->priority_mask
[i
] = qemu_get_be32(f
);
824 s
->running_irq
[i
] = qemu_get_be32(f
);
825 s
->running_priority
[i
] = qemu_get_be32(f
);
826 s
->current_pending
[i
] = qemu_get_be32(f
);
828 for (i
= 0; i
< s
->num_irq
- GIC_INTERNAL
; i
++) {
829 s
->priority2
[i
] = qemu_get_be32(f
);
831 for (i
= 0; i
< s
->num_irq
; i
++) {
833 s
->irq_target
[i
] = qemu_get_be32(f
);
835 s
->irq_state
[i
].enabled
= qemu_get_byte(f
);
836 s
->irq_state
[i
].pending
= qemu_get_byte(f
);
837 s
->irq_state
[i
].active
= qemu_get_byte(f
);
838 s
->irq_state
[i
].level
= qemu_get_byte(f
);
839 s
->irq_state
[i
].model
= qemu_get_byte(f
);
840 s
->irq_state
[i
].trigger
= qemu_get_byte(f
);
847 static void gic_init(gic_state
*s
, int num_cpu
, int num_irq
)
849 static void gic_init(gic_state
*s
, int num_irq
)
855 s
->num_cpu
= num_cpu
;
856 if (s
->num_cpu
> NCPU
) {
857 hw_error("requested %u CPUs exceeds GIC maximum %d\n",
861 s
->num_irq
= num_irq
+ GIC_BASE_IRQ
;
862 if (s
->num_irq
> GIC_MAXIRQ
) {
863 hw_error("requested %u interrupt lines exceeds GIC maximum %d\n",
864 num_irq
, GIC_MAXIRQ
);
866 /* ITLinesNumber is represented as (N / 32) - 1 (see
867 * gic_dist_readb) so this is an implementation imposed
868 * restriction, not an architectural one:
870 if (s
->num_irq
< 32 || (s
->num_irq
% 32)) {
871 hw_error("%d interrupt lines unsupported: not divisible by 32\n",
875 i
= s
->num_irq
- GIC_INTERNAL
;
877 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
878 * GPIO array layout is thus:
880 * [N..N+31] PPIs for CPU 0
881 * [N+32..N+63] PPIs for CPU 1
884 i
+= (GIC_INTERNAL
* num_cpu
);
886 qdev_init_gpio_in(&s
->busdev
.qdev
, gic_set_irq
, i
);
887 for (i
= 0; i
< NUM_CPU(s
); i
++) {
888 sysbus_init_irq(&s
->busdev
, &s
->parent_irq
[i
]);
890 memory_region_init_io(&s
->iomem
, &gic_dist_ops
, s
, "gic_dist", 0x1000);
892 /* Memory regions for the CPU interfaces (NVIC doesn't have these):
893 * a region for "CPU interface for this core", then a region for
894 * "CPU interface for core 0", "for core 1", ...
895 * NB that the memory region size of 0x100 applies for the 11MPCore
896 * and also cores following the GIC v1 spec (ie A9).
897 * GIC v2 defines a larger memory region (0x1000) so this will need
898 * to be extended when we implement A15.
900 memory_region_init_io(&s
->cpuiomem
[0], &gic_thiscpu_ops
, s
,
902 for (i
= 0; i
< NUM_CPU(s
); i
++) {
904 memory_region_init_io(&s
->cpuiomem
[i
+1], &gic_cpu_ops
, &s
->backref
[i
],
909 register_savevm(NULL
, "arm_gic", -1, 2, gic_save
, gic_load
, s
);
912 #ifndef LEGACY_INCLUDED_GIC
914 static int arm_gic_init(SysBusDevice
*dev
)
916 /* Device instance init function for the GIC sysbus device */
918 gic_state
*s
= FROM_SYSBUS(gic_state
, dev
);
919 gic_init(s
, s
->num_cpu
, s
->num_irq
);
921 sysbus_init_mmio(dev
, &s
->iomem
);
922 /* cpu interfaces (one for "current cpu" plus one per cpu) */
923 for (i
= 0; i
<= NUM_CPU(s
); i
++) {
924 sysbus_init_mmio(dev
, &s
->cpuiomem
[i
]);
929 static Property arm_gic_properties
[] = {
930 DEFINE_PROP_UINT32("num-cpu", gic_state
, num_cpu
, 1),
931 DEFINE_PROP_UINT32("num-irq", gic_state
, num_irq
, 32),
932 DEFINE_PROP_END_OF_LIST(),
935 static void arm_gic_class_init(ObjectClass
*klass
, void *data
)
937 DeviceClass
*dc
= DEVICE_CLASS(klass
);
938 SysBusDeviceClass
*sbc
= SYS_BUS_DEVICE_CLASS(klass
);
939 sbc
->init
= arm_gic_init
;
940 dc
->props
= arm_gic_properties
;
941 dc
->reset
= gic_reset
;
945 static TypeInfo arm_gic_info
= {
947 .parent
= TYPE_SYS_BUS_DEVICE
,
948 .instance_size
= sizeof(gic_state
),
949 .class_init
= arm_gic_class_init
,
952 static void arm_gic_register_types(void)
954 type_register_static(&arm_gic_info
);
957 type_init(arm_gic_register_types
)