include/hw/arm/armsse.h

   1 /*
   2  * ARM SSE (Subsystems for Embedded): IoTKit
   3  *
   4  * Copyright (c) 2018 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 or
   9  * (at your option) any later version.
  10  */
  11
  12 /*
  13  * This is a model of the Arm "Subsystems for Embedded" family of
  14  * hardware, which include the IoT Kit and the SSE-050, SSE-100 and
  15  * SSE-200. Currently we model only the Arm IoT Kit which is documented in
  16  * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
  17  * It contains:
  18  *  a Cortex-M33
  19  *  the IDAU
  20  *  some timers and watchdogs
  21  *  two peripheral protection controllers
  22  *  a memory protection controller
  23  *  a security controller
  24  *  a bus fabric which arranges that some parts of the address
  25  *  space are secure and non-secure aliases of each other
  26  *
  27  * QEMU interface:
  28  *  + QOM property "memory" is a MemoryRegion containing the devices provided
  29  *    by the board model.
  30  *  + QOM property "MAINCLK" is the frequency of the main system clock
  31  *  + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
  32  *    (In hardware, the SSE-200 permits the number of expansion interrupts
  33  *    for the two CPUs to be configured separately, but we restrict it to
  34  *    being the same for both, to avoid having to have separate Property
  35  *    lists for different variants. This restriction can be relaxed later
  36  *    if necessary.)
  37  *  + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
  38  *    which are wired to its NVIC lines 32 .. n+32
  39  *  + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
  40  *    CPU 1, which are wired to its NVIC lines 32 .. n+32
  41  *  + sysbus MMIO region 0 is the "AHB Slave Expansion" which allows
  42  *    bus master devices in the board model to make transactions into
  43  *    all the devices and memory areas in the IoTKit
  44  * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit
  45  * might provide:
  46  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
  47  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
  48  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
  49  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
  50  *  + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
  51  * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
  52  * might provide:
  53  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
  54  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
  55  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
  56  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
  57  *  + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
  58  * Controlling each of the 16 expansion MPCs which a system using the IoTKit
  59  * might provide:
  60  *  + named GPIO inputs mpcexp_status[0..15]
  61  * Controlling each of the 16 expansion MSCs which a system using the IoTKit
  62  * might provide:
  63  *  + named GPIO inputs mscexp_status[0..15]
  64  *  + named GPIO outputs mscexp_clear[0..15]
  65  *  + named GPIO outputs mscexp_ns[0..15]
  66  */
  67
  68 #ifndef ARMSSE_H
  69 #define ARMSSE_H
  70
  71 #include "hw/sysbus.h"
  72 #include "hw/arm/armv7m.h"
  73 #include "hw/misc/iotkit-secctl.h"
  74 #include "hw/misc/tz-ppc.h"
  75 #include "hw/misc/tz-mpc.h"
  76 #include "hw/timer/cmsdk-apb-timer.h"
  77 #include "hw/timer/cmsdk-apb-dualtimer.h"
  78 #include "hw/watchdog/cmsdk-apb-watchdog.h"
  79 #include "hw/misc/iotkit-sysctl.h"
  80 #include "hw/misc/iotkit-sysinfo.h"
  81 #include "hw/misc/armsse-cpuid.h"
  82 #include "hw/misc/unimp.h"
  83 #include "hw/or-irq.h"
  84 #include "hw/core/split-irq.h"
  85 #include "hw/cpu/cluster.h"
  86
  87 #define TYPE_ARMSSE "arm-sse"
  88 #define ARMSSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARMSSE)
  89
  90 /*
  91  * These type names are for specific IoTKit subsystems; other than
  92  * instantiating them, code using these devices should always handle
  93  * them via the ARMSSE base class, so they have no IOTKIT() etc macros.
  94  */
  95 #define TYPE_IOTKIT "iotkit"
  96
  97 /* We have an IRQ splitter and an OR gate input for each external PPC
  98  * and the 2 internal PPCs
  99  */
 100 #define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC)
 101 #define NUM_PPCS (NUM_EXTERNAL_PPCS + 2)
 102
 103 #define MAX_SRAM_BANKS 4
 104 #if MAX_SRAM_BANKS > IOTS_NUM_MPC
 105 #error Too many SRAM banks
 106 #endif
 107
 108 #define SSE_MAX_CPUS 2
 109
 110 /* These define what each PPU in the ppu[] index is for */
 111 #define CPU0CORE_PPU 0
 112 #define CPU1CORE_PPU 1
 113 #define DBG_PPU 2
 114 #define RAM0_PPU 3
 115 #define RAM1_PPU 4
 116 #define RAM2_PPU 5
 117 #define RAM3_PPU 6
 118 #define NUM_PPUS 7
 119
 120 typedef struct ARMSSE {
 121     /*< private >*/
 122     SysBusDevice parent_obj;
 123
 124     /*< public >*/
 125     ARMv7MState armv7m[SSE_MAX_CPUS];
 126     CPUClusterState cluster[SSE_MAX_CPUS];
 127     IoTKitSecCtl secctl;
 128     TZPPC apb_ppc0;
 129     TZPPC apb_ppc1;
 130     TZMPC mpc[IOTS_NUM_MPC];
 131     CMSDKAPBTIMER timer0;
 132     CMSDKAPBTIMER timer1;
 133     CMSDKAPBTIMER s32ktimer;
 134     qemu_or_irq ppc_irq_orgate;
 135     SplitIRQ sec_resp_splitter;
 136     SplitIRQ ppc_irq_splitter[NUM_PPCS];
 137     SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC];
 138     qemu_or_irq mpc_irq_orgate;
 139     qemu_or_irq nmi_orgate;
 140
 141     SplitIRQ cpu_irq_splitter[32];
 142
 143     CMSDKAPBDualTimer dualtimer;
 144
 145     CMSDKAPBWatchdog s32kwatchdog;
 146     CMSDKAPBWatchdog nswatchdog;
 147     CMSDKAPBWatchdog swatchdog;
 148
 149     IoTKitSysCtl sysctl;
 150     IoTKitSysCtl sysinfo;
 151
 152     UnimplementedDeviceState mhu[2];
 153     UnimplementedDeviceState ppu[NUM_PPUS];
 154     UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
 155     UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS];
 156
 157     ARMSSECPUID cpuid[SSE_MAX_CPUS];
 158
 159     /*
 160      * 'container' holds all devices seen by all CPUs.
 161      * 'cpu_container[i]' is the view that CPU i has: this has the
 162      * per-CPU devices of that CPU, plus as the background 'container'
 163      * (or an alias of it, since we can only use it directly once).
 164      * container_alias[i] is the alias of 'container' used by CPU i+1;
 165      * CPU 0 can use 'container' directly.
 166      */
 167     MemoryRegion container;
 168     MemoryRegion container_alias[SSE_MAX_CPUS - 1];
 169     MemoryRegion cpu_container[SSE_MAX_CPUS];
 170     MemoryRegion alias1;
 171     MemoryRegion alias2;
 172     MemoryRegion alias3;
 173     MemoryRegion sram[MAX_SRAM_BANKS];
 174
 175     qemu_irq *exp_irqs[SSE_MAX_CPUS];
 176     qemu_irq ppc0_irq;
 177     qemu_irq ppc1_irq;
 178     qemu_irq sec_resp_cfg;
 179     qemu_irq sec_resp_cfg_in;
 180     qemu_irq nsc_cfg_in;
 181
 182     qemu_irq irq_status_in[NUM_EXTERNAL_PPCS];
 183     qemu_irq mpcexp_status_in[IOTS_NUM_EXP_MPC];
 184
 185     uint32_t nsccfg;
 186
 187     /* Properties */
 188     MemoryRegion *board_memory;
 189     uint32_t exp_numirq;
 190     uint32_t mainclk_frq;
 191     uint32_t sram_addr_width;
 192 } ARMSSE;
 193
 194 typedef struct ARMSSEInfo ARMSSEInfo;
 195
 196 typedef struct ARMSSEClass {
 197     DeviceClass parent_class;
 198     const ARMSSEInfo *info;
 199 } ARMSSEClass;
 200
 201 #define ARMSSE_CLASS(klass) \
 202     OBJECT_CLASS_CHECK(ARMSSEClass, (klass), TYPE_ARMSSE)
 203 #define ARMSSE_GET_CLASS(obj) \
 204     OBJECT_GET_CLASS(ARMSSEClass, (obj), TYPE_ARMSSE)
 205
 206 #endif