util/mmap-alloc: Factor out calculation of the pagesize for the guard page
[qemu/kevin.git] / target / nios2 / cpu.c
blob5e37defef805dafeb512ff2bd4396bdefec7ed28
1 /*
2 * QEMU Nios II CPU
4 * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
21 #include "qemu/osdep.h"
22 #include "qemu/module.h"
23 #include "qapi/error.h"
24 #include "cpu.h"
25 #include "exec/log.h"
26 #include "exec/gdbstub.h"
27 #include "hw/qdev-properties.h"
29 static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
31 Nios2CPU *cpu = NIOS2_CPU(cs);
32 CPUNios2State *env = &cpu->env;
34 env->regs[R_PC] = value;
37 static bool nios2_cpu_has_work(CPUState *cs)
39 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
42 static void nios2_cpu_reset(DeviceState *dev)
44 CPUState *cs = CPU(dev);
45 Nios2CPU *cpu = NIOS2_CPU(cs);
46 Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(cpu);
47 CPUNios2State *env = &cpu->env;
49 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
50 qemu_log("CPU Reset (CPU %d)\n", cs->cpu_index);
51 log_cpu_state(cs, 0);
54 ncc->parent_reset(dev);
56 memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS);
57 env->regs[R_PC] = cpu->reset_addr;
59 #if defined(CONFIG_USER_ONLY)
60 /* Start in user mode with interrupts enabled. */
61 env->regs[CR_STATUS] = CR_STATUS_U | CR_STATUS_PIE;
62 #else
63 env->regs[CR_STATUS] = 0;
64 #endif
67 #ifndef CONFIG_USER_ONLY
68 static void nios2_cpu_set_irq(void *opaque, int irq, int level)
70 Nios2CPU *cpu = opaque;
71 CPUNios2State *env = &cpu->env;
72 CPUState *cs = CPU(cpu);
74 env->regs[CR_IPENDING] = deposit32(env->regs[CR_IPENDING], irq, 1, !!level);
76 env->irq_pending = env->regs[CR_IPENDING] & env->regs[CR_IENABLE];
78 if (env->irq_pending && (env->regs[CR_STATUS] & CR_STATUS_PIE)) {
79 env->irq_pending = 0;
80 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
81 } else if (!env->irq_pending) {
82 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
85 #endif
87 static void nios2_cpu_initfn(Object *obj)
89 Nios2CPU *cpu = NIOS2_CPU(obj);
91 cpu_set_cpustate_pointers(cpu);
93 #if !defined(CONFIG_USER_ONLY)
94 mmu_init(&cpu->env);
97 * These interrupt lines model the IIC (internal interrupt
98 * controller). QEMU does not currently support the EIC
99 * (external interrupt controller) -- if we did it would be
100 * a separate device in hw/intc with a custom interface to
101 * the CPU, and boards using it would not wire up these IRQ lines.
103 qdev_init_gpio_in_named(DEVICE(cpu), nios2_cpu_set_irq, "IRQ", 32);
104 #endif
107 static ObjectClass *nios2_cpu_class_by_name(const char *cpu_model)
109 return object_class_by_name(TYPE_NIOS2_CPU);
112 static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
114 CPUState *cs = CPU(dev);
115 Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev);
116 Error *local_err = NULL;
118 cpu_exec_realizefn(cs, &local_err);
119 if (local_err != NULL) {
120 error_propagate(errp, local_err);
121 return;
124 qemu_init_vcpu(cs);
125 cpu_reset(cs);
127 ncc->parent_realize(dev, errp);
130 static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
132 Nios2CPU *cpu = NIOS2_CPU(cs);
133 CPUNios2State *env = &cpu->env;
135 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
136 (env->regs[CR_STATUS] & CR_STATUS_PIE)) {
137 cs->exception_index = EXCP_IRQ;
138 nios2_cpu_do_interrupt(cs);
139 return true;
141 return false;
145 static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
147 /* NOTE: NiosII R2 is not supported yet. */
148 info->mach = bfd_arch_nios2;
149 #ifdef TARGET_WORDS_BIGENDIAN
150 info->print_insn = print_insn_big_nios2;
151 #else
152 info->print_insn = print_insn_little_nios2;
153 #endif
156 static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
158 Nios2CPU *cpu = NIOS2_CPU(cs);
159 CPUClass *cc = CPU_GET_CLASS(cs);
160 CPUNios2State *env = &cpu->env;
162 if (n > cc->gdb_num_core_regs) {
163 return 0;
166 if (n < 32) { /* GP regs */
167 return gdb_get_reg32(mem_buf, env->regs[n]);
168 } else if (n == 32) { /* PC */
169 return gdb_get_reg32(mem_buf, env->regs[R_PC]);
170 } else if (n < 49) { /* Status regs */
171 return gdb_get_reg32(mem_buf, env->regs[n - 1]);
174 /* Invalid regs */
175 return 0;
178 static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
180 Nios2CPU *cpu = NIOS2_CPU(cs);
181 CPUClass *cc = CPU_GET_CLASS(cs);
182 CPUNios2State *env = &cpu->env;
184 if (n > cc->gdb_num_core_regs) {
185 return 0;
188 if (n < 32) { /* GP regs */
189 env->regs[n] = ldl_p(mem_buf);
190 } else if (n == 32) { /* PC */
191 env->regs[R_PC] = ldl_p(mem_buf);
192 } else if (n < 49) { /* Status regs */
193 env->regs[n - 1] = ldl_p(mem_buf);
196 return 4;
199 static Property nios2_properties[] = {
200 DEFINE_PROP_BOOL("mmu_present", Nios2CPU, mmu_present, true),
201 /* ALTR,pid-num-bits */
202 DEFINE_PROP_UINT32("mmu_pid_num_bits", Nios2CPU, pid_num_bits, 8),
203 /* ALTR,tlb-num-ways */
204 DEFINE_PROP_UINT32("mmu_tlb_num_ways", Nios2CPU, tlb_num_ways, 16),
205 /* ALTR,tlb-num-entries */
206 DEFINE_PROP_UINT32("mmu_pid_num_entries", Nios2CPU, tlb_num_entries, 256),
207 DEFINE_PROP_END_OF_LIST(),
210 #ifndef CONFIG_USER_ONLY
211 #include "hw/core/sysemu-cpu-ops.h"
213 static const struct SysemuCPUOps nios2_sysemu_ops = {
214 .get_phys_page_debug = nios2_cpu_get_phys_page_debug,
216 #endif
218 #include "hw/core/tcg-cpu-ops.h"
220 static const struct TCGCPUOps nios2_tcg_ops = {
221 .initialize = nios2_tcg_init,
222 .cpu_exec_interrupt = nios2_cpu_exec_interrupt,
223 .tlb_fill = nios2_cpu_tlb_fill,
225 #ifndef CONFIG_USER_ONLY
226 .do_interrupt = nios2_cpu_do_interrupt,
227 .do_unaligned_access = nios2_cpu_do_unaligned_access,
228 #endif /* !CONFIG_USER_ONLY */
231 static void nios2_cpu_class_init(ObjectClass *oc, void *data)
233 DeviceClass *dc = DEVICE_CLASS(oc);
234 CPUClass *cc = CPU_CLASS(oc);
235 Nios2CPUClass *ncc = NIOS2_CPU_CLASS(oc);
237 device_class_set_parent_realize(dc, nios2_cpu_realizefn,
238 &ncc->parent_realize);
239 device_class_set_props(dc, nios2_properties);
240 device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset);
242 cc->class_by_name = nios2_cpu_class_by_name;
243 cc->has_work = nios2_cpu_has_work;
244 cc->dump_state = nios2_cpu_dump_state;
245 cc->set_pc = nios2_cpu_set_pc;
246 cc->disas_set_info = nios2_cpu_disas_set_info;
247 #ifndef CONFIG_USER_ONLY
248 cc->sysemu_ops = &nios2_sysemu_ops;
249 #endif
250 cc->gdb_read_register = nios2_cpu_gdb_read_register;
251 cc->gdb_write_register = nios2_cpu_gdb_write_register;
252 cc->gdb_num_core_regs = 49;
253 cc->tcg_ops = &nios2_tcg_ops;
256 static const TypeInfo nios2_cpu_type_info = {
257 .name = TYPE_NIOS2_CPU,
258 .parent = TYPE_CPU,
259 .instance_size = sizeof(Nios2CPU),
260 .instance_init = nios2_cpu_initfn,
261 .class_size = sizeof(Nios2CPUClass),
262 .class_init = nios2_cpu_class_init,
265 static void nios2_cpu_register_types(void)
267 type_register_static(&nios2_cpu_type_info);
270 type_init(nios2_cpu_register_types)