target/arm/psci.c

   1 /*
   2  * Copyright (C) 2014 - Linaro
   3  * Author: Rob Herring <rob.herring@linaro.org>
   4  *
   5  *  This program is free software; you can redistribute it and/or modify
   6  *  it under the terms of the GNU General Public License as published by
   7  *  the Free Software Foundation; either version 2 of the License, or
   8  *  (at your option) any later version.
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22 #include "kvm-consts.h"
  23 #include "qemu/main-loop.h"
  24 #include "sysemu/runstate.h"
  25 #include "internals.h"
  26 #include "arm-powerctl.h"
  27
  28 bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
  29 {
  30     /* Return true if the r0/x0 value indicates a PSCI call and
  31      * the exception type matches the configured PSCI conduit. This is
  32      * called before the SMC/HVC instruction is executed, to decide whether
  33      * we should treat it as a PSCI call or with the architecturally
  34      * defined behaviour for an SMC or HVC (which might be UNDEF or trap
  35      * to EL2 or to EL3).
  36      */
  37     CPUARMState *env = &cpu->env;
  38     uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0];
  39
  40     switch (excp_type) {
  41     case EXCP_HVC:
  42         if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_HVC) {
  43             return false;
  44         }
  45         break;
  46     case EXCP_SMC:
  47         if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
  48             return false;
  49         }
  50         break;
  51     default:
  52         return false;
  53     }
  54
  55     switch (param) {
  56     case QEMU_PSCI_0_2_FN_PSCI_VERSION:
  57     case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
  58     case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
  59     case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
  60     case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
  61     case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
  62     case QEMU_PSCI_0_1_FN_CPU_ON:
  63     case QEMU_PSCI_0_2_FN_CPU_ON:
  64     case QEMU_PSCI_0_2_FN64_CPU_ON:
  65     case QEMU_PSCI_0_1_FN_CPU_OFF:
  66     case QEMU_PSCI_0_2_FN_CPU_OFF:
  67     case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
  68     case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
  69     case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
  70     case QEMU_PSCI_0_1_FN_MIGRATE:
  71     case QEMU_PSCI_0_2_FN_MIGRATE:
  72         return true;
  73     default:
  74         return false;
  75     }
  76 }
  77
  78 void arm_handle_psci_call(ARMCPU *cpu)
  79 {
  80     /*
  81      * This function partially implements the logic for dispatching Power State
  82      * Coordination Interface (PSCI) calls (as described in ARM DEN 0022B.b),
  83      * to the extent required for bringing up and taking down secondary cores,
  84      * and for handling reset and poweroff requests.
  85      * Additional information about the calling convention used is available in
  86      * the document 'SMC Calling Convention' (ARM DEN 0028)
  87      */
  88     CPUARMState *env = &cpu->env;
  89     uint64_t param[4];
  90     uint64_t context_id, mpidr;
  91     target_ulong entry;
  92     int32_t ret = 0;
  93     int i;
  94
  95     for (i = 0; i < 4; i++) {
  96         /*
  97          * All PSCI functions take explicit 32-bit or native int sized
  98          * arguments so we can simply zero-extend all arguments regardless
  99          * of which exact function we are about to call.
 100          */
 101         param[i] = is_a64(env) ? env->xregs[i] : env->regs[i];
 102     }
 103
 104     if ((param[0] & QEMU_PSCI_0_2_64BIT) && !is_a64(env)) {
 105         ret = QEMU_PSCI_RET_INVALID_PARAMS;
 106         goto err;
 107     }
 108
 109     switch (param[0]) {
 110         CPUState *target_cpu_state;
 111         ARMCPU *target_cpu;
 112
 113     case QEMU_PSCI_0_2_FN_PSCI_VERSION:
 114         ret = QEMU_PSCI_0_2_RET_VERSION_0_2;
 115         break;
 116     case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
 117         ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */
 118         break;
 119     case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
 120     case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
 121         mpidr = param[1];
 122
 123         switch (param[2]) {
 124         case 0:
 125             target_cpu_state = arm_get_cpu_by_id(mpidr);
 126             if (!target_cpu_state) {
 127                 ret = QEMU_PSCI_RET_INVALID_PARAMS;
 128                 break;
 129             }
 130             target_cpu = ARM_CPU(target_cpu_state);
 131
 132             g_assert(qemu_mutex_iothread_locked());
 133             ret = target_cpu->power_state;
 134             break;
 135         default:
 136             /* Everything above affinity level 0 is always on. */
 137             ret = 0;
 138         }
 139         break;
 140     case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
 141         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 142         /* QEMU reset and shutdown are async requests, but PSCI
 143          * mandates that we never return from the reset/shutdown
 144          * call, so power the CPU off now so it doesn't execute
 145          * anything further.
 146          */
 147         goto cpu_off;
 148     case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
 149         qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 150         goto cpu_off;
 151     case QEMU_PSCI_0_1_FN_CPU_ON:
 152     case QEMU_PSCI_0_2_FN_CPU_ON:
 153     case QEMU_PSCI_0_2_FN64_CPU_ON:
 154     {
 155         /* The PSCI spec mandates that newly brought up CPUs start
 156          * in the highest exception level which exists and is enabled
 157          * on the calling CPU. Since the QEMU PSCI implementation is
 158          * acting as a "fake EL3" or "fake EL2" firmware, this for us
 159          * means that we want to start at the highest NS exception level
 160          * that we are providing to the guest.
 161          * The execution mode should be that which is currently in use
 162          * by the same exception level on the calling CPU.
 163          * The CPU should be started with the context_id value
 164          * in x0 (if AArch64) or r0 (if AArch32).
 165          */
 166         int target_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1;
 167         bool target_aarch64 = arm_el_is_aa64(env, target_el);
 168
 169         mpidr = param[1];
 170         entry = param[2];
 171         context_id = param[3];
 172         ret = arm_set_cpu_on(mpidr, entry, context_id,
 173                              target_el, target_aarch64);
 174         break;
 175     }
 176     case QEMU_PSCI_0_1_FN_CPU_OFF:
 177     case QEMU_PSCI_0_2_FN_CPU_OFF:
 178         goto cpu_off;
 179     case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
 180     case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
 181     case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
 182         /* Affinity levels are not supported in QEMU */
 183         if (param[1] & 0xfffe0000) {
 184             ret = QEMU_PSCI_RET_INVALID_PARAMS;
 185             break;
 186         }
 187         /* Powerdown is not supported, we always go into WFI */
 188         if (is_a64(env)) {
 189             env->xregs[0] = 0;
 190         } else {
 191             env->regs[0] = 0;
 192         }
 193         helper_wfi(env, 4);
 194         break;
 195     case QEMU_PSCI_0_1_FN_MIGRATE:
 196     case QEMU_PSCI_0_2_FN_MIGRATE:
 197         ret = QEMU_PSCI_RET_NOT_SUPPORTED;
 198         break;
 199     default:
 200         g_assert_not_reached();
 201     }
 202
 203 err:
 204     if (is_a64(env)) {
 205         env->xregs[0] = ret;
 206     } else {
 207         env->regs[0] = ret;
 208     }
 209     return;
 210
 211 cpu_off:
 212     ret = arm_set_cpu_off(cpu->mp_affinity);
 213     /* notreached */
 214     /* sanity check in case something failed */
 215     assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS);
 216 }