4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu-common.h"
24 #include "target/arm/idau.h"
25 #include "qemu/module.h"
26 #include "qapi/error.h"
27 #include "qapi/visitor.h"
30 #include "hw/core/tcg-cpu-ops.h"
31 #endif /* CONFIG_TCG */
32 #include "internals.h"
33 #include "exec/exec-all.h"
34 #include "hw/qdev-properties.h"
35 #if !defined(CONFIG_USER_ONLY)
36 #include "hw/loader.h"
37 #include "hw/boards.h"
39 #include "sysemu/tcg.h"
40 #include "sysemu/hw_accel.h"
42 #include "disas/capstone.h"
43 #include "fpu/softfloat.h"
45 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
47 ARMCPU
*cpu
= ARM_CPU(cs
);
48 CPUARMState
*env
= &cpu
->env
;
54 env
->regs
[15] = value
& ~1;
55 env
->thumb
= value
& 1;
60 void arm_cpu_synchronize_from_tb(CPUState
*cs
,
61 const TranslationBlock
*tb
)
63 ARMCPU
*cpu
= ARM_CPU(cs
);
64 CPUARMState
*env
= &cpu
->env
;
67 * It's OK to look at env for the current mode here, because it's
68 * never possible for an AArch64 TB to chain to an AArch32 TB.
73 env
->regs
[15] = tb
->pc
;
76 #endif /* CONFIG_TCG */
78 static bool arm_cpu_has_work(CPUState
*cs
)
80 ARMCPU
*cpu
= ARM_CPU(cs
);
82 return (cpu
->power_state
!= PSCI_OFF
)
83 && cs
->interrupt_request
&
84 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
85 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
86 | CPU_INTERRUPT_EXITTB
);
89 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
92 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
95 entry
->opaque
= opaque
;
97 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
100 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
103 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
106 entry
->opaque
= opaque
;
108 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
111 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
113 /* Reset a single ARMCPRegInfo register */
114 ARMCPRegInfo
*ri
= value
;
115 ARMCPU
*cpu
= opaque
;
117 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
122 ri
->resetfn(&cpu
->env
, ri
);
126 /* A zero offset is never possible as it would be regs[0]
127 * so we use it to indicate that reset is being handled elsewhere.
128 * This is basically only used for fields in non-core coprocessors
129 * (like the pxa2xx ones).
131 if (!ri
->fieldoffset
) {
135 if (cpreg_field_is_64bit(ri
)) {
136 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
138 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
142 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
144 /* Purely an assertion check: we've already done reset once,
145 * so now check that running the reset for the cpreg doesn't
146 * change its value. This traps bugs where two different cpregs
147 * both try to reset the same state field but to different values.
149 ARMCPRegInfo
*ri
= value
;
150 ARMCPU
*cpu
= opaque
;
151 uint64_t oldvalue
, newvalue
;
153 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
157 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
158 cp_reg_reset(key
, value
, opaque
);
159 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
160 assert(oldvalue
== newvalue
);
163 static void arm_cpu_reset(DeviceState
*dev
)
165 CPUState
*s
= CPU(dev
);
166 ARMCPU
*cpu
= ARM_CPU(s
);
167 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
168 CPUARMState
*env
= &cpu
->env
;
170 acc
->parent_reset(dev
);
172 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
174 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
175 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
177 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
178 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
179 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
180 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
182 cpu
->power_state
= s
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
184 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
185 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
188 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
189 /* 64 bit CPUs always start in 64 bit mode */
191 #if defined(CONFIG_USER_ONLY)
192 env
->pstate
= PSTATE_MODE_EL0t
;
193 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
194 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
195 /* Enable all PAC keys. */
196 env
->cp15
.sctlr_el
[1] |= (SCTLR_EnIA
| SCTLR_EnIB
|
197 SCTLR_EnDA
| SCTLR_EnDB
);
198 /* and to the FP/Neon instructions */
199 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
200 /* and to the SVE instructions */
201 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 16, 2, 3);
202 /* with reasonable vector length */
203 if (cpu_isar_feature(aa64_sve
, cpu
)) {
204 env
->vfp
.zcr_el
[1] = MIN(cpu
->sve_max_vq
- 1, 3);
207 * Enable TBI0 but not TBI1.
208 * Note that this must match useronly_clean_ptr.
210 env
->cp15
.tcr_el
[1].raw_tcr
= (1ULL << 37);
213 if (cpu_isar_feature(aa64_mte
, cpu
)) {
214 /* Enable tag access, but leave TCF0 as No Effect (0). */
215 env
->cp15
.sctlr_el
[1] |= SCTLR_ATA0
;
217 * Exclude all tags, so that tag 0 is always used.
218 * This corresponds to Linux current->thread.gcr_incl = 0.
220 * Set RRND, so that helper_irg() will generate a seed later.
221 * Here in cpu_reset(), the crypto subsystem has not yet been
224 env
->cp15
.gcr_el1
= 0x1ffff;
227 /* Reset into the highest available EL */
228 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
229 env
->pstate
= PSTATE_MODE_EL3h
;
230 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
231 env
->pstate
= PSTATE_MODE_EL2h
;
233 env
->pstate
= PSTATE_MODE_EL1h
;
235 env
->pc
= cpu
->rvbar
;
238 #if defined(CONFIG_USER_ONLY)
239 /* Userspace expects access to cp10 and cp11 for FP/Neon */
240 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
244 #if defined(CONFIG_USER_ONLY)
245 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
246 /* For user mode we must enable access to coprocessors */
247 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
248 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
249 env
->cp15
.c15_cpar
= 3;
250 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
251 env
->cp15
.c15_cpar
= 1;
256 * If the highest available EL is EL2, AArch32 will start in Hyp
257 * mode; otherwise it starts in SVC. Note that if we start in
258 * AArch64 then these values in the uncached_cpsr will be ignored.
260 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
261 !arm_feature(env
, ARM_FEATURE_EL3
)) {
262 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
264 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
266 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
268 if (arm_feature(env
, ARM_FEATURE_M
)) {
269 uint32_t initial_msp
; /* Loaded from 0x0 */
270 uint32_t initial_pc
; /* Loaded from 0x4 */
274 if (cpu_isar_feature(aa32_lob
, cpu
)) {
276 * LTPSIZE is constant 4 if MVE not implemented, and resets
277 * to an UNKNOWN value if MVE is implemented. We choose to
280 env
->v7m
.ltpsize
= 4;
281 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
282 env
->v7m
.fpdscr
[M_REG_NS
] = 4 << FPCR_LTPSIZE_SHIFT
;
283 env
->v7m
.fpdscr
[M_REG_S
] = 4 << FPCR_LTPSIZE_SHIFT
;
286 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
287 env
->v7m
.secure
= true;
289 /* This bit resets to 0 if security is supported, but 1 if
290 * it is not. The bit is not present in v7M, but we set it
291 * here so we can avoid having to make checks on it conditional
292 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
294 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
296 * Set NSACR to indicate "NS access permitted to everything";
297 * this avoids having to have all the tests of it being
298 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
299 * v8.1M the guest-visible value of NSACR in a CPU without the
300 * Security Extension is 0xcff.
302 env
->v7m
.nsacr
= 0xcff;
305 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
306 * that it resets to 1, so QEMU always does that rather than making
307 * it dependent on CPU model. In v8M it is RES1.
309 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
310 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
311 if (arm_feature(env
, ARM_FEATURE_V8
)) {
312 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
313 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
314 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
316 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
317 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
318 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
321 if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
322 env
->v7m
.fpccr
[M_REG_NS
] = R_V7M_FPCCR_ASPEN_MASK
;
323 env
->v7m
.fpccr
[M_REG_S
] = R_V7M_FPCCR_ASPEN_MASK
|
324 R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
;
326 /* Unlike A/R profile, M profile defines the reset LR value */
327 env
->regs
[14] = 0xffffffff;
329 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
330 env
->v7m
.vecbase
[M_REG_NS
] = cpu
->init_nsvtor
& 0xffffff80;
332 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
333 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
334 rom
= rom_ptr_for_as(s
->as
, vecbase
, 8);
336 /* Address zero is covered by ROM which hasn't yet been
337 * copied into physical memory.
339 initial_msp
= ldl_p(rom
);
340 initial_pc
= ldl_p(rom
+ 4);
342 /* Address zero not covered by a ROM blob, or the ROM blob
343 * is in non-modifiable memory and this is a second reset after
344 * it got copied into memory. In the latter case, rom_ptr
345 * will return a NULL pointer and we should use ldl_phys instead.
347 initial_msp
= ldl_phys(s
->as
, vecbase
);
348 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
351 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
352 env
->regs
[15] = initial_pc
& ~1;
353 env
->thumb
= initial_pc
& 1;
356 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
357 * executing as AArch32 then check if highvecs are enabled and
358 * adjust the PC accordingly.
360 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
361 env
->regs
[15] = 0xFFFF0000;
364 /* M profile requires that reset clears the exclusive monitor;
365 * A profile does not, but clearing it makes more sense than having it
366 * set with an exclusive access on address zero.
368 arm_clear_exclusive(env
);
370 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
373 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
374 if (cpu
->pmsav7_dregion
> 0) {
375 if (arm_feature(env
, ARM_FEATURE_V8
)) {
376 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
377 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
378 * cpu
->pmsav7_dregion
);
379 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
380 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
381 * cpu
->pmsav7_dregion
);
382 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
383 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
384 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
385 * cpu
->pmsav7_dregion
);
386 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
387 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
388 * cpu
->pmsav7_dregion
);
390 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
391 memset(env
->pmsav7
.drbar
, 0,
392 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
393 memset(env
->pmsav7
.drsr
, 0,
394 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
395 memset(env
->pmsav7
.dracr
, 0,
396 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
399 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
400 env
->pmsav7
.rnr
[M_REG_S
] = 0;
401 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
402 env
->pmsav8
.mair0
[M_REG_S
] = 0;
403 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
404 env
->pmsav8
.mair1
[M_REG_S
] = 0;
407 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
408 if (cpu
->sau_sregion
> 0) {
409 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
410 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
413 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
414 * the Cortex-M33 does.
419 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
420 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
421 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
422 set_default_nan_mode(1, &env
->vfp
.standard_fp_status_f16
);
423 set_float_detect_tininess(float_tininess_before_rounding
,
424 &env
->vfp
.fp_status
);
425 set_float_detect_tininess(float_tininess_before_rounding
,
426 &env
->vfp
.standard_fp_status
);
427 set_float_detect_tininess(float_tininess_before_rounding
,
428 &env
->vfp
.fp_status_f16
);
429 set_float_detect_tininess(float_tininess_before_rounding
,
430 &env
->vfp
.standard_fp_status_f16
);
431 #ifndef CONFIG_USER_ONLY
433 kvm_arm_reset_vcpu(cpu
);
437 hw_breakpoint_update_all(cpu
);
438 hw_watchpoint_update_all(cpu
);
439 arm_rebuild_hflags(env
);
442 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
443 unsigned int target_el
,
444 unsigned int cur_el
, bool secure
,
447 CPUARMState
*env
= cs
->env_ptr
;
448 bool pstate_unmasked
;
449 bool unmasked
= false;
452 * Don't take exceptions if they target a lower EL.
453 * This check should catch any exceptions that would not be taken
456 if (cur_el
> target_el
) {
462 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
466 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
470 if (!(hcr_el2
& HCR_FMO
) || (hcr_el2
& HCR_TGE
)) {
471 /* VFIQs are only taken when hypervized. */
474 return !(env
->daif
& PSTATE_F
);
476 if (!(hcr_el2
& HCR_IMO
) || (hcr_el2
& HCR_TGE
)) {
477 /* VIRQs are only taken when hypervized. */
480 return !(env
->daif
& PSTATE_I
);
482 g_assert_not_reached();
486 * Use the target EL, current execution state and SCR/HCR settings to
487 * determine whether the corresponding CPSR bit is used to mask the
490 if ((target_el
> cur_el
) && (target_el
!= 1)) {
491 /* Exceptions targeting a higher EL may not be maskable */
492 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
494 * 64-bit masking rules are simple: exceptions to EL3
495 * can't be masked, and exceptions to EL2 can only be
496 * masked from Secure state. The HCR and SCR settings
497 * don't affect the masking logic, only the interrupt routing.
499 if (target_el
== 3 || !secure
|| (env
->cp15
.scr_el3
& SCR_EEL2
)) {
504 * The old 32-bit-only environment has a more complicated
505 * masking setup. HCR and SCR bits not only affect interrupt
506 * routing but also change the behaviour of masking.
513 * If FIQs are routed to EL3 or EL2 then there are cases where
514 * we override the CPSR.F in determining if the exception is
515 * masked or not. If neither of these are set then we fall back
516 * to the CPSR.F setting otherwise we further assess the state
519 hcr
= hcr_el2
& HCR_FMO
;
520 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
523 * When EL3 is 32-bit, the SCR.FW bit controls whether the
524 * CPSR.F bit masks FIQ interrupts when taken in non-secure
525 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
526 * when non-secure but only when FIQs are only routed to EL3.
528 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
532 * When EL3 execution state is 32-bit, if HCR.IMO is set then
533 * we may override the CPSR.I masking when in non-secure state.
534 * The SCR.IRQ setting has already been taken into consideration
535 * when setting the target EL, so it does not have a further
538 hcr
= hcr_el2
& HCR_IMO
;
542 g_assert_not_reached();
545 if ((scr
|| hcr
) && !secure
) {
552 * The PSTATE bits only mask the interrupt if we have not overriden the
555 return unmasked
|| pstate_unmasked
;
558 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
560 CPUClass
*cc
= CPU_GET_CLASS(cs
);
561 CPUARMState
*env
= cs
->env_ptr
;
562 uint32_t cur_el
= arm_current_el(env
);
563 bool secure
= arm_is_secure(env
);
564 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
568 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
570 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
572 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
573 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
574 cur_el
, secure
, hcr_el2
)) {
578 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
580 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
581 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
582 cur_el
, secure
, hcr_el2
)) {
586 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
587 excp_idx
= EXCP_VIRQ
;
589 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
590 cur_el
, secure
, hcr_el2
)) {
594 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
595 excp_idx
= EXCP_VFIQ
;
597 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
598 cur_el
, secure
, hcr_el2
)) {
605 cs
->exception_index
= excp_idx
;
606 env
->exception
.target_el
= target_el
;
607 cc
->tcg_ops
->do_interrupt(cs
);
611 void arm_cpu_update_virq(ARMCPU
*cpu
)
614 * Update the interrupt level for VIRQ, which is the logical OR of
615 * the HCR_EL2.VI bit and the input line level from the GIC.
617 CPUARMState
*env
= &cpu
->env
;
618 CPUState
*cs
= CPU(cpu
);
620 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
621 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
623 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
625 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
627 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
632 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
635 * Update the interrupt level for VFIQ, which is the logical OR of
636 * the HCR_EL2.VF bit and the input line level from the GIC.
638 CPUARMState
*env
= &cpu
->env
;
639 CPUState
*cs
= CPU(cpu
);
641 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
642 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
644 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
646 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
648 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
653 #ifndef CONFIG_USER_ONLY
654 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
656 ARMCPU
*cpu
= opaque
;
657 CPUARMState
*env
= &cpu
->env
;
658 CPUState
*cs
= CPU(cpu
);
659 static const int mask
[] = {
660 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
661 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
662 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
663 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
667 env
->irq_line_state
|= mask
[irq
];
669 env
->irq_line_state
&= ~mask
[irq
];
674 assert(arm_feature(env
, ARM_FEATURE_EL2
));
675 arm_cpu_update_virq(cpu
);
678 assert(arm_feature(env
, ARM_FEATURE_EL2
));
679 arm_cpu_update_vfiq(cpu
);
684 cpu_interrupt(cs
, mask
[irq
]);
686 cpu_reset_interrupt(cs
, mask
[irq
]);
690 g_assert_not_reached();
694 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
697 ARMCPU
*cpu
= opaque
;
698 CPUARMState
*env
= &cpu
->env
;
699 CPUState
*cs
= CPU(cpu
);
700 uint32_t linestate_bit
;
705 irq_id
= KVM_ARM_IRQ_CPU_IRQ
;
706 linestate_bit
= CPU_INTERRUPT_HARD
;
709 irq_id
= KVM_ARM_IRQ_CPU_FIQ
;
710 linestate_bit
= CPU_INTERRUPT_FIQ
;
713 g_assert_not_reached();
717 env
->irq_line_state
|= linestate_bit
;
719 env
->irq_line_state
&= ~linestate_bit
;
721 kvm_arm_set_irq(cs
->cpu_index
, KVM_ARM_IRQ_TYPE_CPU
, irq_id
, !!level
);
725 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
727 ARMCPU
*cpu
= ARM_CPU(cs
);
728 CPUARMState
*env
= &cpu
->env
;
730 cpu_synchronize_state(cs
);
731 return arm_cpu_data_is_big_endian(env
);
737 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
739 return print_insn_arm(pc
| 1, info
);
742 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
744 ARMCPU
*ac
= ARM_CPU(cpu
);
745 CPUARMState
*env
= &ac
->env
;
749 /* We might not be compiled with the A64 disassembler
750 * because it needs a C++ compiler. Leave print_insn
751 * unset in this case to use the caller default behaviour.
753 #if defined(CONFIG_ARM_A64_DIS)
754 info
->print_insn
= print_insn_arm_a64
;
756 info
->cap_arch
= CS_ARCH_ARM64
;
757 info
->cap_insn_unit
= 4;
758 info
->cap_insn_split
= 4;
762 info
->print_insn
= print_insn_thumb1
;
763 info
->cap_insn_unit
= 2;
764 info
->cap_insn_split
= 4;
765 cap_mode
= CS_MODE_THUMB
;
767 info
->print_insn
= print_insn_arm
;
768 info
->cap_insn_unit
= 4;
769 info
->cap_insn_split
= 4;
770 cap_mode
= CS_MODE_ARM
;
772 if (arm_feature(env
, ARM_FEATURE_V8
)) {
773 cap_mode
|= CS_MODE_V8
;
775 if (arm_feature(env
, ARM_FEATURE_M
)) {
776 cap_mode
|= CS_MODE_MCLASS
;
778 info
->cap_arch
= CS_ARCH_ARM
;
779 info
->cap_mode
= cap_mode
;
782 sctlr_b
= arm_sctlr_b(env
);
783 if (bswap_code(sctlr_b
)) {
784 #ifdef TARGET_WORDS_BIGENDIAN
785 info
->endian
= BFD_ENDIAN_LITTLE
;
787 info
->endian
= BFD_ENDIAN_BIG
;
790 info
->flags
&= ~INSN_ARM_BE32
;
791 #ifndef CONFIG_USER_ONLY
793 info
->flags
|= INSN_ARM_BE32
;
798 #ifdef TARGET_AARCH64
800 static void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
802 ARMCPU
*cpu
= ARM_CPU(cs
);
803 CPUARMState
*env
= &cpu
->env
;
804 uint32_t psr
= pstate_read(env
);
806 int el
= arm_current_el(env
);
807 const char *ns_status
;
809 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
810 for (i
= 0; i
< 32; i
++) {
812 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
814 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
815 (i
+ 2) % 3 ? " " : "\n");
819 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
820 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
824 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
826 psr
& PSTATE_N
? 'N' : '-',
827 psr
& PSTATE_Z
? 'Z' : '-',
828 psr
& PSTATE_C
? 'C' : '-',
829 psr
& PSTATE_V
? 'V' : '-',
832 psr
& PSTATE_SP
? 'h' : 't');
834 if (cpu_isar_feature(aa64_bti
, cpu
)) {
835 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
837 if (!(flags
& CPU_DUMP_FPU
)) {
838 qemu_fprintf(f
, "\n");
841 if (fp_exception_el(env
, el
) != 0) {
842 qemu_fprintf(f
, " FPU disabled\n");
845 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
846 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
848 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
849 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
851 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
853 if (i
== FFR_PRED_NUM
) {
854 qemu_fprintf(f
, "FFR=");
855 /* It's last, so end the line. */
858 qemu_fprintf(f
, "P%02d=", i
);
871 /* More than one quadword per predicate. */
876 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
878 if (j
* 4 + 4 <= zcr_len
+ 1) {
881 digits
= (zcr_len
% 4 + 1) * 4;
883 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
884 env
->vfp
.pregs
[i
].p
[j
],
885 j
? ":" : eol
? "\n" : " ");
889 for (i
= 0; i
< 32; i
++) {
891 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
892 i
, env
->vfp
.zregs
[i
].d
[1],
893 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
894 } else if (zcr_len
== 1) {
895 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
896 ":%016" PRIx64
":%016" PRIx64
"\n",
897 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
898 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
900 for (j
= zcr_len
; j
>= 0; j
--) {
901 bool odd
= (zcr_len
- j
) % 2 != 0;
903 qemu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
906 qemu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
908 qemu_fprintf(f
, " [%x]=", j
);
911 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
912 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
913 env
->vfp
.zregs
[i
].d
[j
* 2],
914 odd
|| j
== 0 ? "\n" : ":");
919 for (i
= 0; i
< 32; i
++) {
920 uint64_t *q
= aa64_vfp_qreg(env
, i
);
921 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
922 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
929 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
931 g_assert_not_reached();
936 static void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
938 ARMCPU
*cpu
= ARM_CPU(cs
);
939 CPUARMState
*env
= &cpu
->env
;
943 aarch64_cpu_dump_state(cs
, f
, flags
);
947 for (i
= 0; i
< 16; i
++) {
948 qemu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
950 qemu_fprintf(f
, "\n");
952 qemu_fprintf(f
, " ");
956 if (arm_feature(env
, ARM_FEATURE_M
)) {
957 uint32_t xpsr
= xpsr_read(env
);
959 const char *ns_status
= "";
961 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
962 ns_status
= env
->v7m
.secure
? "S " : "NS ";
965 if (xpsr
& XPSR_EXCP
) {
968 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_NPRIV_MASK
) {
969 mode
= "unpriv-thread";
971 mode
= "priv-thread";
975 qemu_fprintf(f
, "XPSR=%08x %c%c%c%c %c %s%s\n",
977 xpsr
& XPSR_N
? 'N' : '-',
978 xpsr
& XPSR_Z
? 'Z' : '-',
979 xpsr
& XPSR_C
? 'C' : '-',
980 xpsr
& XPSR_V
? 'V' : '-',
981 xpsr
& XPSR_T
? 'T' : 'A',
985 uint32_t psr
= cpsr_read(env
);
986 const char *ns_status
= "";
988 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
989 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
990 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
993 qemu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
995 psr
& CPSR_N
? 'N' : '-',
996 psr
& CPSR_Z
? 'Z' : '-',
997 psr
& CPSR_C
? 'C' : '-',
998 psr
& CPSR_V
? 'V' : '-',
999 psr
& CPSR_T
? 'T' : 'A',
1001 aarch32_mode_name(psr
), (psr
& 0x10) ? 32 : 26);
1004 if (flags
& CPU_DUMP_FPU
) {
1006 if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
1008 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
1011 for (i
= 0; i
< numvfpregs
; i
++) {
1012 uint64_t v
= *aa32_vfp_dreg(env
, i
);
1013 qemu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
1015 i
* 2 + 1, (uint32_t)(v
>> 32),
1018 qemu_fprintf(f
, "FPSCR: %08x\n", vfp_get_fpscr(env
));
1022 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
1024 uint32_t Aff1
= idx
/ clustersz
;
1025 uint32_t Aff0
= idx
% clustersz
;
1026 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
1029 static void cpreg_hashtable_data_destroy(gpointer data
)
1032 * Destroy function for cpu->cp_regs hashtable data entries.
1033 * We must free the name string because it was g_strdup()ed in
1034 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
1035 * from r->name because we know we definitely allocated it.
1037 ARMCPRegInfo
*r
= data
;
1039 g_free((void *)r
->name
);
1043 static void arm_cpu_initfn(Object
*obj
)
1045 ARMCPU
*cpu
= ARM_CPU(obj
);
1047 cpu_set_cpustate_pointers(cpu
);
1048 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
1049 g_free
, cpreg_hashtable_data_destroy
);
1051 QLIST_INIT(&cpu
->pre_el_change_hooks
);
1052 QLIST_INIT(&cpu
->el_change_hooks
);
1054 #ifndef CONFIG_USER_ONLY
1055 /* Our inbound IRQ and FIQ lines */
1056 if (kvm_enabled()) {
1057 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1058 * the same interface as non-KVM CPUs.
1060 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
1062 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
1065 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
1066 ARRAY_SIZE(cpu
->gt_timer_outputs
));
1068 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
1069 "gicv3-maintenance-interrupt", 1);
1070 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
1071 "pmu-interrupt", 1);
1074 /* DTB consumers generally don't in fact care what the 'compatible'
1075 * string is, so always provide some string and trust that a hypothetical
1076 * picky DTB consumer will also provide a helpful error message.
1078 cpu
->dtb_compatible
= "qemu,unknown";
1079 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
1080 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
1082 if (tcg_enabled()) {
1083 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
1087 static Property arm_cpu_gt_cntfrq_property
=
1088 DEFINE_PROP_UINT64("cntfrq", ARMCPU
, gt_cntfrq_hz
,
1089 NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
);
1091 static Property arm_cpu_reset_cbar_property
=
1092 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
1094 static Property arm_cpu_reset_hivecs_property
=
1095 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
1097 static Property arm_cpu_rvbar_property
=
1098 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
1100 #ifndef CONFIG_USER_ONLY
1101 static Property arm_cpu_has_el2_property
=
1102 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
1104 static Property arm_cpu_has_el3_property
=
1105 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
1108 static Property arm_cpu_cfgend_property
=
1109 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
1111 static Property arm_cpu_has_vfp_property
=
1112 DEFINE_PROP_BOOL("vfp", ARMCPU
, has_vfp
, true);
1114 static Property arm_cpu_has_neon_property
=
1115 DEFINE_PROP_BOOL("neon", ARMCPU
, has_neon
, true);
1117 static Property arm_cpu_has_dsp_property
=
1118 DEFINE_PROP_BOOL("dsp", ARMCPU
, has_dsp
, true);
1120 static Property arm_cpu_has_mpu_property
=
1121 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
1123 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1124 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1125 * the right value for that particular CPU type, and we don't want
1126 * to override that with an incorrect constant value.
1128 static Property arm_cpu_pmsav7_dregion_property
=
1129 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
1131 qdev_prop_uint32
, uint32_t);
1133 static bool arm_get_pmu(Object
*obj
, Error
**errp
)
1135 ARMCPU
*cpu
= ARM_CPU(obj
);
1137 return cpu
->has_pmu
;
1140 static void arm_set_pmu(Object
*obj
, bool value
, Error
**errp
)
1142 ARMCPU
*cpu
= ARM_CPU(obj
);
1145 if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1146 error_setg(errp
, "'pmu' feature not supported by KVM on this host");
1149 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1151 unset_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1153 cpu
->has_pmu
= value
;
1156 unsigned int gt_cntfrq_period_ns(ARMCPU
*cpu
)
1159 * The exact approach to calculating guest ticks is:
1161 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1162 * NANOSECONDS_PER_SECOND);
1164 * We don't do that. Rather we intentionally use integer division
1165 * truncation below and in the caller for the conversion of host monotonic
1166 * time to guest ticks to provide the exact inverse for the semantics of
1167 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1168 * it loses precision when representing frequencies where
1169 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1170 * provide an exact inverse leads to scheduling timers with negative
1171 * periods, which in turn leads to sticky behaviour in the guest.
1173 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1174 * cannot become zero.
1176 return NANOSECONDS_PER_SECOND
> cpu
->gt_cntfrq_hz
?
1177 NANOSECONDS_PER_SECOND
/ cpu
->gt_cntfrq_hz
: 1;
1180 void arm_cpu_post_init(Object
*obj
)
1182 ARMCPU
*cpu
= ARM_CPU(obj
);
1184 /* M profile implies PMSA. We have to do this here rather than
1185 * in realize with the other feature-implication checks because
1186 * we look at the PMSA bit to see if we should add some properties.
1188 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1189 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1192 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
1193 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
1194 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
);
1197 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1198 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
);
1201 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1202 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
);
1205 #ifndef CONFIG_USER_ONLY
1206 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1207 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1208 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1210 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
);
1212 object_property_add_link(obj
, "secure-memory",
1214 (Object
**)&cpu
->secure_memory
,
1215 qdev_prop_allow_set_link_before_realize
,
1216 OBJ_PROP_LINK_STRONG
);
1219 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
1220 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
);
1224 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
1225 cpu
->has_pmu
= true;
1226 object_property_add_bool(obj
, "pmu", arm_get_pmu
, arm_set_pmu
);
1230 * Allow user to turn off VFP and Neon support, but only for TCG --
1231 * KVM does not currently allow us to lie to the guest about its
1232 * ID/feature registers, so the guest always sees what the host has.
1234 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)
1235 ? cpu_isar_feature(aa64_fp_simd
, cpu
)
1236 : cpu_isar_feature(aa32_vfp
, cpu
)) {
1237 cpu
->has_vfp
= true;
1238 if (!kvm_enabled()) {
1239 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_vfp_property
);
1243 if (arm_feature(&cpu
->env
, ARM_FEATURE_NEON
)) {
1244 cpu
->has_neon
= true;
1245 if (!kvm_enabled()) {
1246 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_neon_property
);
1250 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
) &&
1251 arm_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
)) {
1252 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_dsp_property
);
1255 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
1256 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
);
1257 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1258 qdev_property_add_static(DEVICE(obj
),
1259 &arm_cpu_pmsav7_dregion_property
);
1263 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1264 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
1265 qdev_prop_allow_set_link_before_realize
,
1266 OBJ_PROP_LINK_STRONG
);
1268 * M profile: initial value of the Secure VTOR. We can't just use
1269 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1270 * the property to be set after realize.
1272 object_property_add_uint32_ptr(obj
, "init-svtor",
1274 OBJ_PROP_FLAG_READWRITE
);
1276 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1278 * Initial value of the NS VTOR (for cores without the Security
1279 * extension, this is the only VTOR)
1281 object_property_add_uint32_ptr(obj
, "init-nsvtor",
1283 OBJ_PROP_FLAG_READWRITE
);
1286 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
);
1288 if (arm_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
)) {
1289 qdev_property_add_static(DEVICE(cpu
), &arm_cpu_gt_cntfrq_property
);
1292 if (kvm_enabled()) {
1293 kvm_arm_add_vcpu_properties(obj
);
1296 #ifndef CONFIG_USER_ONLY
1297 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) &&
1298 cpu_isar_feature(aa64_mte
, cpu
)) {
1299 object_property_add_link(obj
, "tag-memory",
1301 (Object
**)&cpu
->tag_memory
,
1302 qdev_prop_allow_set_link_before_realize
,
1303 OBJ_PROP_LINK_STRONG
);
1305 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1306 object_property_add_link(obj
, "secure-tag-memory",
1308 (Object
**)&cpu
->secure_tag_memory
,
1309 qdev_prop_allow_set_link_before_realize
,
1310 OBJ_PROP_LINK_STRONG
);
1316 static void arm_cpu_finalizefn(Object
*obj
)
1318 ARMCPU
*cpu
= ARM_CPU(obj
);
1319 ARMELChangeHook
*hook
, *next
;
1321 g_hash_table_destroy(cpu
->cp_regs
);
1323 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
1324 QLIST_REMOVE(hook
, node
);
1327 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
1328 QLIST_REMOVE(hook
, node
);
1331 #ifndef CONFIG_USER_ONLY
1332 if (cpu
->pmu_timer
) {
1333 timer_free(cpu
->pmu_timer
);
1338 void arm_cpu_finalize_features(ARMCPU
*cpu
, Error
**errp
)
1340 Error
*local_err
= NULL
;
1342 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1343 arm_cpu_sve_finalize(cpu
, &local_err
);
1344 if (local_err
!= NULL
) {
1345 error_propagate(errp
, local_err
);
1350 * KVM does not support modifications to this feature.
1351 * We have not registered the cpu properties when KVM
1352 * is in use, so the user will not be able to set them.
1354 if (!kvm_enabled()) {
1355 arm_cpu_pauth_finalize(cpu
, &local_err
);
1356 if (local_err
!= NULL
) {
1357 error_propagate(errp
, local_err
);
1363 if (kvm_enabled()) {
1364 kvm_arm_steal_time_finalize(cpu
, &local_err
);
1365 if (local_err
!= NULL
) {
1366 error_propagate(errp
, local_err
);
1372 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
1374 CPUState
*cs
= CPU(dev
);
1375 ARMCPU
*cpu
= ARM_CPU(dev
);
1376 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
1377 CPUARMState
*env
= &cpu
->env
;
1379 Error
*local_err
= NULL
;
1380 bool no_aa32
= false;
1382 /* If we needed to query the host kernel for the CPU features
1383 * then it's possible that might have failed in the initfn, but
1384 * this is the first point where we can report it.
1386 if (cpu
->host_cpu_probe_failed
) {
1387 if (!kvm_enabled()) {
1388 error_setg(errp
, "The 'host' CPU type can only be used with KVM");
1390 error_setg(errp
, "Failed to retrieve host CPU features");
1395 #ifndef CONFIG_USER_ONLY
1396 /* The NVIC and M-profile CPU are two halves of a single piece of
1397 * hardware; trying to use one without the other is a command line
1398 * error and will result in segfaults if not caught here.
1400 if (arm_feature(env
, ARM_FEATURE_M
)) {
1402 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
1407 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
1415 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1416 if (!cpu
->gt_cntfrq_hz
) {
1417 error_setg(errp
, "Invalid CNTFRQ: %"PRId64
"Hz",
1421 scale
= gt_cntfrq_period_ns(cpu
);
1423 scale
= GTIMER_SCALE
;
1426 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1427 arm_gt_ptimer_cb
, cpu
);
1428 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1429 arm_gt_vtimer_cb
, cpu
);
1430 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1431 arm_gt_htimer_cb
, cpu
);
1432 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1433 arm_gt_stimer_cb
, cpu
);
1434 cpu
->gt_timer
[GTIMER_HYPVIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1435 arm_gt_hvtimer_cb
, cpu
);
1439 cpu_exec_realizefn(cs
, &local_err
);
1440 if (local_err
!= NULL
) {
1441 error_propagate(errp
, local_err
);
1445 arm_cpu_finalize_features(cpu
, &local_err
);
1446 if (local_err
!= NULL
) {
1447 error_propagate(errp
, local_err
);
1451 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1452 cpu
->has_vfp
!= cpu
->has_neon
) {
1454 * This is an architectural requirement for AArch64; AArch32 is
1455 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1458 "AArch64 CPUs must have both VFP and Neon or neither");
1462 if (!cpu
->has_vfp
) {
1466 t
= cpu
->isar
.id_aa64isar1
;
1467 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 0);
1468 cpu
->isar
.id_aa64isar1
= t
;
1470 t
= cpu
->isar
.id_aa64pfr0
;
1471 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 0xf);
1472 cpu
->isar
.id_aa64pfr0
= t
;
1474 u
= cpu
->isar
.id_isar6
;
1475 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 0);
1476 u
= FIELD_DP32(u
, ID_ISAR6
, BF16
, 0);
1477 cpu
->isar
.id_isar6
= u
;
1479 u
= cpu
->isar
.mvfr0
;
1480 u
= FIELD_DP32(u
, MVFR0
, FPSP
, 0);
1481 u
= FIELD_DP32(u
, MVFR0
, FPDP
, 0);
1482 u
= FIELD_DP32(u
, MVFR0
, FPDIVIDE
, 0);
1483 u
= FIELD_DP32(u
, MVFR0
, FPSQRT
, 0);
1484 u
= FIELD_DP32(u
, MVFR0
, FPROUND
, 0);
1485 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1486 u
= FIELD_DP32(u
, MVFR0
, FPTRAP
, 0);
1487 u
= FIELD_DP32(u
, MVFR0
, FPSHVEC
, 0);
1489 cpu
->isar
.mvfr0
= u
;
1491 u
= cpu
->isar
.mvfr1
;
1492 u
= FIELD_DP32(u
, MVFR1
, FPFTZ
, 0);
1493 u
= FIELD_DP32(u
, MVFR1
, FPDNAN
, 0);
1494 u
= FIELD_DP32(u
, MVFR1
, FPHP
, 0);
1495 if (arm_feature(env
, ARM_FEATURE_M
)) {
1496 u
= FIELD_DP32(u
, MVFR1
, FP16
, 0);
1498 cpu
->isar
.mvfr1
= u
;
1500 u
= cpu
->isar
.mvfr2
;
1501 u
= FIELD_DP32(u
, MVFR2
, FPMISC
, 0);
1502 cpu
->isar
.mvfr2
= u
;
1505 if (!cpu
->has_neon
) {
1509 unset_feature(env
, ARM_FEATURE_NEON
);
1511 t
= cpu
->isar
.id_aa64isar0
;
1512 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 0);
1513 cpu
->isar
.id_aa64isar0
= t
;
1515 t
= cpu
->isar
.id_aa64isar1
;
1516 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 0);
1517 t
= FIELD_DP64(t
, ID_AA64ISAR1
, BF16
, 0);
1518 t
= FIELD_DP64(t
, ID_AA64ISAR1
, I8MM
, 0);
1519 cpu
->isar
.id_aa64isar1
= t
;
1521 t
= cpu
->isar
.id_aa64pfr0
;
1522 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 0xf);
1523 cpu
->isar
.id_aa64pfr0
= t
;
1525 u
= cpu
->isar
.id_isar5
;
1526 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 0);
1527 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 0);
1528 cpu
->isar
.id_isar5
= u
;
1530 u
= cpu
->isar
.id_isar6
;
1531 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 0);
1532 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 0);
1533 u
= FIELD_DP32(u
, ID_ISAR6
, BF16
, 0);
1534 u
= FIELD_DP32(u
, ID_ISAR6
, I8MM
, 0);
1535 cpu
->isar
.id_isar6
= u
;
1537 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1538 u
= cpu
->isar
.mvfr1
;
1539 u
= FIELD_DP32(u
, MVFR1
, SIMDLS
, 0);
1540 u
= FIELD_DP32(u
, MVFR1
, SIMDINT
, 0);
1541 u
= FIELD_DP32(u
, MVFR1
, SIMDSP
, 0);
1542 u
= FIELD_DP32(u
, MVFR1
, SIMDHP
, 0);
1543 cpu
->isar
.mvfr1
= u
;
1545 u
= cpu
->isar
.mvfr2
;
1546 u
= FIELD_DP32(u
, MVFR2
, SIMDMISC
, 0);
1547 cpu
->isar
.mvfr2
= u
;
1551 if (!cpu
->has_neon
&& !cpu
->has_vfp
) {
1555 t
= cpu
->isar
.id_aa64isar0
;
1556 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 0);
1557 cpu
->isar
.id_aa64isar0
= t
;
1559 t
= cpu
->isar
.id_aa64isar1
;
1560 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 0);
1561 cpu
->isar
.id_aa64isar1
= t
;
1563 u
= cpu
->isar
.mvfr0
;
1564 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 0);
1565 cpu
->isar
.mvfr0
= u
;
1567 /* Despite the name, this field covers both VFP and Neon */
1568 u
= cpu
->isar
.mvfr1
;
1569 u
= FIELD_DP32(u
, MVFR1
, SIMDFMAC
, 0);
1570 cpu
->isar
.mvfr1
= u
;
1573 if (arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_dsp
) {
1576 unset_feature(env
, ARM_FEATURE_THUMB_DSP
);
1578 u
= cpu
->isar
.id_isar1
;
1579 u
= FIELD_DP32(u
, ID_ISAR1
, EXTEND
, 1);
1580 cpu
->isar
.id_isar1
= u
;
1582 u
= cpu
->isar
.id_isar2
;
1583 u
= FIELD_DP32(u
, ID_ISAR2
, MULTU
, 1);
1584 u
= FIELD_DP32(u
, ID_ISAR2
, MULTS
, 1);
1585 cpu
->isar
.id_isar2
= u
;
1587 u
= cpu
->isar
.id_isar3
;
1588 u
= FIELD_DP32(u
, ID_ISAR3
, SIMD
, 1);
1589 u
= FIELD_DP32(u
, ID_ISAR3
, SATURATE
, 0);
1590 cpu
->isar
.id_isar3
= u
;
1593 /* Some features automatically imply others: */
1594 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1595 if (arm_feature(env
, ARM_FEATURE_M
)) {
1596 set_feature(env
, ARM_FEATURE_V7
);
1598 set_feature(env
, ARM_FEATURE_V7VE
);
1603 * There exist AArch64 cpus without AArch32 support. When KVM
1604 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1605 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1606 * As a general principle, we also do not make ID register
1607 * consistency checks anywhere unless using TCG, because only
1608 * for TCG would a consistency-check failure be a QEMU bug.
1610 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1611 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
1614 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
1615 /* v7 Virtualization Extensions. In real hardware this implies
1616 * EL2 and also the presence of the Security Extensions.
1617 * For QEMU, for backwards-compatibility we implement some
1618 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1619 * include the various other features that V7VE implies.
1620 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1621 * Security Extensions is ARM_FEATURE_EL3.
1623 assert(!tcg_enabled() || no_aa32
||
1624 cpu_isar_feature(aa32_arm_div
, cpu
));
1625 set_feature(env
, ARM_FEATURE_LPAE
);
1626 set_feature(env
, ARM_FEATURE_V7
);
1628 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1629 set_feature(env
, ARM_FEATURE_VAPA
);
1630 set_feature(env
, ARM_FEATURE_THUMB2
);
1631 set_feature(env
, ARM_FEATURE_MPIDR
);
1632 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1633 set_feature(env
, ARM_FEATURE_V6K
);
1635 set_feature(env
, ARM_FEATURE_V6
);
1638 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1639 * non-EL3 configs. This is needed by some legacy boards.
1641 set_feature(env
, ARM_FEATURE_VBAR
);
1643 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1644 set_feature(env
, ARM_FEATURE_V6
);
1645 set_feature(env
, ARM_FEATURE_MVFR
);
1647 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1648 set_feature(env
, ARM_FEATURE_V5
);
1649 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1650 assert(!tcg_enabled() || no_aa32
||
1651 cpu_isar_feature(aa32_jazelle
, cpu
));
1652 set_feature(env
, ARM_FEATURE_AUXCR
);
1655 if (arm_feature(env
, ARM_FEATURE_V5
)) {
1656 set_feature(env
, ARM_FEATURE_V4T
);
1658 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1659 set_feature(env
, ARM_FEATURE_V7MP
);
1661 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
1662 set_feature(env
, ARM_FEATURE_CBAR
);
1664 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
1665 !arm_feature(env
, ARM_FEATURE_M
)) {
1666 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
1670 * We rely on no XScale CPU having VFP so we can use the same bits in the
1671 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1673 assert(arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) ||
1674 !cpu_isar_feature(aa32_vfp_simd
, cpu
) ||
1675 !arm_feature(env
, ARM_FEATURE_XSCALE
));
1677 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1678 !arm_feature(env
, ARM_FEATURE_M
) &&
1679 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
1680 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1685 /* For CPUs which might have tiny 1K pages, or which have an
1686 * MPU and might have small region sizes, stick with 1K pages.
1690 if (!set_preferred_target_page_bits(pagebits
)) {
1691 /* This can only ever happen for hotplugging a CPU, or if
1692 * the board code incorrectly creates a CPU which it has
1693 * promised via minimum_page_size that it will not.
1695 error_setg(errp
, "This CPU requires a smaller page size than the "
1700 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1701 * We don't support setting cluster ID ([16..23]) (known as Aff2
1702 * in later ARM ARM versions), or any of the higher affinity level fields,
1703 * so these bits always RAZ.
1705 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
1706 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
1707 ARM_DEFAULT_CPUS_PER_CLUSTER
);
1710 if (cpu
->reset_hivecs
) {
1711 cpu
->reset_sctlr
|= (1 << 13);
1715 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1716 cpu
->reset_sctlr
|= SCTLR_EE
;
1718 cpu
->reset_sctlr
|= SCTLR_B
;
1722 if (!arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_el3
) {
1723 /* If the has_el3 CPU property is disabled then we need to disable the
1726 unset_feature(env
, ARM_FEATURE_EL3
);
1728 /* Disable the security extension feature bits in the processor feature
1729 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1731 cpu
->isar
.id_pfr1
&= ~0xf0;
1732 cpu
->isar
.id_aa64pfr0
&= ~0xf000;
1735 if (!cpu
->has_el2
) {
1736 unset_feature(env
, ARM_FEATURE_EL2
);
1739 if (!cpu
->has_pmu
) {
1740 unset_feature(env
, ARM_FEATURE_PMU
);
1742 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
1745 if (!kvm_enabled()) {
1746 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
1747 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
1750 #ifndef CONFIG_USER_ONLY
1751 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, arm_pmu_timer_cb
,
1755 cpu
->isar
.id_aa64dfr0
=
1756 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMUVER
, 0);
1757 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, PERFMON
, 0);
1762 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1763 /* Disable the hypervisor feature bits in the processor feature
1764 * registers if we don't have EL2. These are id_pfr1[15:12] and
1765 * id_aa64pfr0_el1[11:8].
1767 cpu
->isar
.id_aa64pfr0
&= ~0xf00;
1768 cpu
->isar
.id_pfr1
&= ~0xf000;
1771 #ifndef CONFIG_USER_ONLY
1772 if (cpu
->tag_memory
== NULL
&& cpu_isar_feature(aa64_mte
, cpu
)) {
1774 * Disable the MTE feature bits if we do not have tag-memory
1775 * provided by the machine.
1777 cpu
->isar
.id_aa64pfr1
=
1778 FIELD_DP64(cpu
->isar
.id_aa64pfr1
, ID_AA64PFR1
, MTE
, 0);
1782 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1783 * to false or by setting pmsav7-dregion to 0.
1785 if (!cpu
->has_mpu
) {
1786 cpu
->pmsav7_dregion
= 0;
1788 if (cpu
->pmsav7_dregion
== 0) {
1789 cpu
->has_mpu
= false;
1792 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
1793 arm_feature(env
, ARM_FEATURE_V7
)) {
1794 uint32_t nr
= cpu
->pmsav7_dregion
;
1797 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
1802 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1804 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1805 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1806 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1807 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
1808 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
1811 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
1812 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
1813 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
1818 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1819 uint32_t nr
= cpu
->sau_sregion
;
1822 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
1827 env
->sau
.rbar
= g_new0(uint32_t, nr
);
1828 env
->sau
.rlar
= g_new0(uint32_t, nr
);
1832 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1833 set_feature(env
, ARM_FEATURE_VBAR
);
1836 register_cp_regs_for_features(cpu
);
1837 arm_cpu_register_gdb_regs_for_features(cpu
);
1839 init_cpreg_list(cpu
);
1841 #ifndef CONFIG_USER_ONLY
1842 MachineState
*ms
= MACHINE(qdev_get_machine());
1843 unsigned int smp_cpus
= ms
->smp
.cpus
;
1844 bool has_secure
= cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
);
1847 * We must set cs->num_ases to the final value before
1848 * the first call to cpu_address_space_init.
1850 if (cpu
->tag_memory
!= NULL
) {
1851 cs
->num_ases
= 3 + has_secure
;
1853 cs
->num_ases
= 1 + has_secure
;
1857 if (!cpu
->secure_memory
) {
1858 cpu
->secure_memory
= cs
->memory
;
1860 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
1861 cpu
->secure_memory
);
1864 if (cpu
->tag_memory
!= NULL
) {
1865 cpu_address_space_init(cs
, ARMASIdx_TagNS
, "cpu-tag-memory",
1868 cpu_address_space_init(cs
, ARMASIdx_TagS
, "cpu-tag-memory",
1869 cpu
->secure_tag_memory
);
1873 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
1875 /* No core_count specified, default to smp_cpus. */
1876 if (cpu
->core_count
== -1) {
1877 cpu
->core_count
= smp_cpus
;
1881 if (tcg_enabled()) {
1882 int dcz_blocklen
= 4 << cpu
->dcz_blocksize
;
1885 * We only support DCZ blocklen that fits on one page.
1887 * Architectually this is always true. However TARGET_PAGE_SIZE
1888 * is variable and, for compatibility with -machine virt-2.7,
1889 * is only 1KiB, as an artifact of legacy ARMv5 subpage support.
1890 * But even then, while the largest architectural DCZ blocklen
1891 * is 2KiB, no cpu actually uses such a large blocklen.
1893 assert(dcz_blocklen
<= TARGET_PAGE_SIZE
);
1896 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
1897 * both nibbles of each byte storing tag data may be written at once.
1898 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
1900 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1901 assert(dcz_blocklen
>= 2 * TAG_GRANULE
);
1908 acc
->parent_realize(dev
, errp
);
1911 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
1916 const char *cpunamestr
;
1918 cpuname
= g_strsplit(cpu_model
, ",", 1);
1919 cpunamestr
= cpuname
[0];
1920 #ifdef CONFIG_USER_ONLY
1921 /* For backwards compatibility usermode emulation allows "-cpu any",
1922 * which has the same semantics as "-cpu max".
1924 if (!strcmp(cpunamestr
, "any")) {
1928 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
1929 oc
= object_class_by_name(typename
);
1930 g_strfreev(cpuname
);
1932 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
1933 object_class_is_abstract(oc
)) {
1939 static Property arm_cpu_properties
[] = {
1940 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
1941 DEFINE_PROP_UINT64("midr", ARMCPU
, midr
, 0),
1942 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
1943 mp_affinity
, ARM64_AFFINITY_INVALID
),
1944 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
1945 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
1946 DEFINE_PROP_END_OF_LIST()
1949 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
1951 ARMCPU
*cpu
= ARM_CPU(cs
);
1952 CPUARMState
*env
= &cpu
->env
;
1954 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
1955 return g_strdup("iwmmxt");
1957 return g_strdup("arm");
1960 #ifndef CONFIG_USER_ONLY
1961 #include "hw/core/sysemu-cpu-ops.h"
1963 static const struct SysemuCPUOps arm_sysemu_ops
= {
1964 .get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
,
1965 .asidx_from_attrs
= arm_asidx_from_attrs
,
1966 .write_elf32_note
= arm_cpu_write_elf32_note
,
1967 .write_elf64_note
= arm_cpu_write_elf64_note
,
1968 .virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
,
1969 .legacy_vmsd
= &vmstate_arm_cpu
,
1974 static const struct TCGCPUOps arm_tcg_ops
= {
1975 .initialize
= arm_translate_init
,
1976 .synchronize_from_tb
= arm_cpu_synchronize_from_tb
,
1977 .cpu_exec_interrupt
= arm_cpu_exec_interrupt
,
1978 .tlb_fill
= arm_cpu_tlb_fill
,
1979 .debug_excp_handler
= arm_debug_excp_handler
,
1981 #if !defined(CONFIG_USER_ONLY)
1982 .do_interrupt
= arm_cpu_do_interrupt
,
1983 .do_transaction_failed
= arm_cpu_do_transaction_failed
,
1984 .do_unaligned_access
= arm_cpu_do_unaligned_access
,
1985 .adjust_watchpoint_address
= arm_adjust_watchpoint_address
,
1986 .debug_check_watchpoint
= arm_debug_check_watchpoint
,
1987 #endif /* !CONFIG_USER_ONLY */
1989 #endif /* CONFIG_TCG */
1991 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
1993 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
1994 CPUClass
*cc
= CPU_CLASS(acc
);
1995 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1997 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
1998 &acc
->parent_realize
);
2000 device_class_set_props(dc
, arm_cpu_properties
);
2001 device_class_set_parent_reset(dc
, arm_cpu_reset
, &acc
->parent_reset
);
2003 cc
->class_by_name
= arm_cpu_class_by_name
;
2004 cc
->has_work
= arm_cpu_has_work
;
2005 cc
->dump_state
= arm_cpu_dump_state
;
2006 cc
->set_pc
= arm_cpu_set_pc
;
2007 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2008 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2009 #ifndef CONFIG_USER_ONLY
2010 cc
->sysemu_ops
= &arm_sysemu_ops
;
2012 cc
->gdb_num_core_regs
= 26;
2013 cc
->gdb_core_xml_file
= "arm-core.xml";
2014 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2015 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
2016 cc
->gdb_stop_before_watchpoint
= true;
2017 cc
->disas_set_info
= arm_disas_set_info
;
2020 cc
->tcg_ops
= &arm_tcg_ops
;
2021 #endif /* CONFIG_TCG */
2025 static void arm_host_initfn(Object
*obj
)
2027 ARMCPU
*cpu
= ARM_CPU(obj
);
2029 kvm_arm_set_cpu_features_from_host(cpu
);
2030 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
2031 aarch64_add_sve_properties(obj
);
2033 arm_cpu_post_init(obj
);
2036 static const TypeInfo host_arm_cpu_type_info
= {
2037 .name
= TYPE_ARM_HOST_CPU
,
2038 .parent
= TYPE_AARCH64_CPU
,
2039 .instance_init
= arm_host_initfn
,
2044 static void arm_cpu_instance_init(Object
*obj
)
2046 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2048 acc
->info
->initfn(obj
);
2049 arm_cpu_post_init(obj
);
2052 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2054 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2059 void arm_cpu_register(const ARMCPUInfo
*info
)
2061 TypeInfo type_info
= {
2062 .parent
= TYPE_ARM_CPU
,
2063 .instance_size
= sizeof(ARMCPU
),
2064 .instance_align
= __alignof__(ARMCPU
),
2065 .instance_init
= arm_cpu_instance_init
,
2066 .class_size
= sizeof(ARMCPUClass
),
2067 .class_init
= info
->class_init
?: cpu_register_class_init
,
2068 .class_data
= (void *)info
,
2071 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2072 type_register(&type_info
);
2073 g_free((void *)type_info
.name
);
2076 static const TypeInfo arm_cpu_type_info
= {
2077 .name
= TYPE_ARM_CPU
,
2079 .instance_size
= sizeof(ARMCPU
),
2080 .instance_align
= __alignof__(ARMCPU
),
2081 .instance_init
= arm_cpu_initfn
,
2082 .instance_finalize
= arm_cpu_finalizefn
,
2084 .class_size
= sizeof(ARMCPUClass
),
2085 .class_init
= arm_cpu_class_init
,
2088 static void arm_cpu_register_types(void)
2090 type_register_static(&arm_cpu_type_info
);
2093 type_register_static(&host_arm_cpu_type_info
);
2097 type_init(arm_cpu_register_types
)