hw/arm/xlnx-zynqmp.c

   1 /*
   2  * Xilinx Zynq MPSoC emulation
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qapi/error.h"
  20 #include "qemu-common.h"
  21 #include "cpu.h"
  22 #include "hw/arm/xlnx-zynqmp.h"
  23 #include "hw/intc/arm_gic_common.h"
  24 #include "exec/address-spaces.h"
  25 #include "sysemu/kvm.h"
  26 #include "kvm_arm.h"
  27
  28 #define GIC_NUM_SPI_INTR 160
  29
  30 #define ARM_PHYS_TIMER_PPI  30
  31 #define ARM_VIRT_TIMER_PPI  27
  32
  33 #define GEM_REVISION        0x40070106
  34
  35 #define GIC_BASE_ADDR       0xf9000000
  36 #define GIC_DIST_ADDR       0xf9010000
  37 #define GIC_CPU_ADDR        0xf9020000
  38
  39 #define SATA_INTR           133
  40 #define SATA_ADDR           0xFD0C0000
  41 #define SATA_NUM_PORTS      2
  42
  43 #define DP_ADDR             0xfd4a0000
  44 #define DP_IRQ              113
  45
  46 #define DPDMA_ADDR          0xfd4c0000
  47 #define DPDMA_IRQ           116
  48
  49 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
  50     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
  51 };
  52
  53 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
  54     57, 59, 61, 63,
  55 };
  56
  57 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
  58     0xFF000000, 0xFF010000,
  59 };
  60
  61 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
  62     21, 22,
  63 };
  64
  65 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
  66     0xFF160000, 0xFF170000,
  67 };
  68
  69 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
  70     48, 49,
  71 };
  72
  73 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
  74     0xFF040000, 0xFF050000,
  75 };
  76
  77 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
  78     19, 20,
  79 };
  80
  81 typedef struct XlnxZynqMPGICRegion {
  82     int region_index;
  83     uint32_t address;
  84 } XlnxZynqMPGICRegion;
  85
  86 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
  87     { .region_index = 0, .address = GIC_DIST_ADDR, },
  88     { .region_index = 1, .address = GIC_CPU_ADDR,  },
  89 };
  90
  91 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
  92 {
  93     return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
  94 }
  95
  96 static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu,
  97                                    Error **errp)
  98 {
  99     Error *err = NULL;
 100     int i;
 101
 102     for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
 103         char *name;
 104
 105         object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
 106                           "cortex-r5-" TYPE_ARM_CPU);
 107         object_property_add_child(OBJECT(s), "rpu-cpu[*]",
 108                                   OBJECT(&s->rpu_cpu[i]), &error_abort);
 109
 110         name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
 111         if (strcmp(name, boot_cpu)) {
 112             /* Secondary CPUs start in PSCI powered-down state */
 113             object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
 114                                      "start-powered-off", &error_abort);
 115         } else {
 116             s->boot_cpu_ptr = &s->rpu_cpu[i];
 117         }
 118         g_free(name);
 119
 120         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
 121                                  &error_abort);
 122         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
 123                                  &err);
 124         if (err) {
 125             error_propagate(errp, err);
 126             return;
 127         }
 128     }
 129 }
 130
 131 static void xlnx_zynqmp_init(Object *obj)
 132 {
 133     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
 134     int i;
 135
 136     for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
 137         object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
 138                           "cortex-a53-" TYPE_ARM_CPU);
 139         object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
 140                                   &error_abort);
 141     }
 142
 143     object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION,
 144                              (Object **)&s->ddr_ram,
 145                              qdev_prop_allow_set_link_before_realize,
 146                              OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
 147
 148     object_initialize(&s->gic, sizeof(s->gic), gic_class_name());
 149     qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
 150
 151     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 152         object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
 153         qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
 154     }
 155
 156     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 157         object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
 158         qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
 159     }
 160
 161     object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
 162     qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
 163
 164     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 165         object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
 166                           TYPE_SYSBUS_SDHCI);
 167         qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
 168                             sysbus_get_default());
 169     }
 170
 171     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 172         object_initialize(&s->spi[i], sizeof(s->spi[i]),
 173                           TYPE_XILINX_SPIPS);
 174         qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
 175     }
 176
 177     object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP);
 178     qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());
 179
 180     object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA);
 181     qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
 182 }
 183
 184 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
 185 {
 186     XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
 187     MemoryRegion *system_memory = get_system_memory();
 188     uint8_t i;
 189     uint64_t ram_size;
 190     const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
 191     ram_addr_t ddr_low_size, ddr_high_size;
 192     qemu_irq gic_spi[GIC_NUM_SPI_INTR];
 193     Error *err = NULL;
 194
 195     ram_size = memory_region_size(s->ddr_ram);
 196
 197     /* Create the DDR Memory Regions. User friendly checks should happen at
 198      * the board level
 199      */
 200     if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
 201         /* The RAM size is above the maximum available for the low DDR.
 202          * Create the high DDR memory region as well.
 203          */
 204         assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
 205         ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 206         ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 207
 208         memory_region_init_alias(&s->ddr_ram_high, NULL,
 209                                  "ddr-ram-high", s->ddr_ram,
 210                                   ddr_low_size, ddr_high_size);
 211         memory_region_add_subregion(get_system_memory(),
 212                                     XLNX_ZYNQMP_HIGH_RAM_START,
 213                                     &s->ddr_ram_high);
 214     } else {
 215         /* RAM must be non-zero */
 216         assert(ram_size);
 217         ddr_low_size = ram_size;
 218     }
 219
 220     memory_region_init_alias(&s->ddr_ram_low, NULL,
 221                              "ddr-ram-low", s->ddr_ram,
 222                               0, ddr_low_size);
 223     memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
 224
 225     /* Create the four OCM banks */
 226     for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
 227         char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
 228
 229         memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
 230                                XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
 231         memory_region_add_subregion(get_system_memory(),
 232                                     XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
 233                                         i * XLNX_ZYNQMP_OCM_RAM_SIZE,
 234                                     &s->ocm_ram[i]);
 235
 236         g_free(ocm_name);
 237     }
 238
 239     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
 240     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
 241     qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
 242
 243     /* Realize APUs before realizing the GIC. KVM requires this.  */
 244     for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
 245         char *name;
 246
 247         object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
 248                                 "psci-conduit", &error_abort);
 249
 250         name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
 251         if (strcmp(name, boot_cpu)) {
 252             /* Secondary CPUs start in PSCI powered-down state */
 253             object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
 254                                      "start-powered-off", &error_abort);
 255         } else {
 256             s->boot_cpu_ptr = &s->apu_cpu[i];
 257         }
 258         g_free(name);
 259
 260         object_property_set_bool(OBJECT(&s->apu_cpu[i]),
 261                                  s->secure, "has_el3", NULL);
 262         object_property_set_bool(OBJECT(&s->apu_cpu[i]),
 263                                  false, "has_el2", NULL);
 264         object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
 265                                 "reset-cbar", &error_abort);
 266         object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
 267                                  &err);
 268         if (err) {
 269             error_propagate(errp, err);
 270             return;
 271         }
 272     }
 273
 274     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
 275     if (err) {
 276         error_propagate(errp, err);
 277         return;
 278     }
 279
 280     assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
 281     for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
 282         SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
 283         const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
 284         MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
 285         uint32_t addr = r->address;
 286         int j;
 287
 288         sysbus_mmio_map(gic, r->region_index, addr);
 289
 290         for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
 291             MemoryRegion *alias = &s->gic_mr[i][j];
 292
 293             addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
 294             memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
 295                                      0, XLNX_ZYNQMP_GIC_REGION_SIZE);
 296             memory_region_add_subregion(system_memory, addr, alias);
 297         }
 298     }
 299
 300     for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
 301         qemu_irq irq;
 302
 303         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
 304                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 305                                             ARM_CPU_IRQ));
 306         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 307                                arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
 308         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
 309         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 310                                arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
 311         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
 312     }
 313
 314     if (s->has_rpu) {
 315         xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
 316         if (err) {
 317             error_propagate(errp, err);
 318             return;
 319         }
 320     }
 321
 322     if (!s->boot_cpu_ptr) {
 323         error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
 324         return;
 325     }
 326
 327     for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
 328         gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
 329     }
 330
 331     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 332         NICInfo *nd = &nd_table[i];
 333
 334         if (nd->used) {
 335             qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 336             qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
 337         }
 338         object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
 339                                 &error_abort);
 340         object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
 341                                 &error_abort);
 342         object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
 343         if (err) {
 344             error_propagate(errp, err);
 345             return;
 346         }
 347         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
 348         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
 349                            gic_spi[gem_intr[i]]);
 350     }
 351
 352     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 353         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]);
 354         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
 355         if (err) {
 356             error_propagate(errp, err);
 357             return;
 358         }
 359         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
 360         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 361                            gic_spi[uart_intr[i]]);
 362     }
 363
 364     object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
 365                             &error_abort);
 366     object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
 367     if (err) {
 368         error_propagate(errp, err);
 369         return;
 370     }
 371
 372     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
 373     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
 374
 375     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 376         char *bus_name;
 377
 378         object_property_set_bool(OBJECT(&s->sdhci[i]), true,
 379                                  "realized", &err);
 380         if (err) {
 381             error_propagate(errp, err);
 382             return;
 383         }
 384         sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
 385                         sdhci_addr[i]);
 386         sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
 387                            gic_spi[sdhci_intr[i]]);
 388         /* Alias controller SD bus to the SoC itself */
 389         bus_name = g_strdup_printf("sd-bus%d", i);
 390         object_property_add_alias(OBJECT(s), bus_name,
 391                                   OBJECT(&s->sdhci[i]), "sd-bus",
 392                                   &error_abort);
 393         g_free(bus_name);
 394     }
 395
 396     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 397         gchar *bus_name;
 398
 399         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
 400
 401         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
 402         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 403                            gic_spi[spi_intr[i]]);
 404
 405         /* Alias controller SPI bus to the SoC itself */
 406         bus_name = g_strdup_printf("spi%d", i);
 407         object_property_add_alias(OBJECT(s), bus_name,
 408                                   OBJECT(&s->spi[i]), "spi0",
 409                                   &error_abort);
 410         g_free(bus_name);
 411     }
 412
 413     object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
 414     if (err) {
 415         error_propagate(errp, err);
 416         return;
 417     }
 418     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
 419     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
 420
 421     object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
 422     if (err) {
 423         error_propagate(errp, err);
 424         return;
 425     }
 426     object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
 427                              &error_abort);
 428     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
 429     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
 430 }
 431
 432 static Property xlnx_zynqmp_props[] = {
 433     DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
 434     DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
 435     DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
 436     DEFINE_PROP_END_OF_LIST()
 437 };
 438
 439 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
 440 {
 441     DeviceClass *dc = DEVICE_CLASS(oc);
 442
 443     dc->props = xlnx_zynqmp_props;
 444     dc->realize = xlnx_zynqmp_realize;
 445 }
 446
 447 static const TypeInfo xlnx_zynqmp_type_info = {
 448     .name = TYPE_XLNX_ZYNQMP,
 449     .parent = TYPE_DEVICE,
 450     .instance_size = sizeof(XlnxZynqMPState),
 451     .instance_init = xlnx_zynqmp_init,
 452     .class_init = xlnx_zynqmp_class_init,
 453 };
 454
 455 static void xlnx_zynqmp_register_types(void)
 456 {
 457     type_register_static(&xlnx_zynqmp_type_info);
 458 }
 459
 460 type_init(xlnx_zynqmp_register_types)