target/cris/cpu.c

   1 /*
   2  * QEMU CRIS CPU
   3  *
   4  * Copyright (c) 2008 AXIS Communications AB
   5  * Written by Edgar E. Iglesias.
   6  *
   7  * Copyright (c) 2012 SUSE LINUX Products GmbH
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2.1 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see
  21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "qemu/qemu-print.h"
  27 #include "cpu.h"
  28 #include "mmu.h"
  29
  30
  31 static void cris_cpu_set_pc(CPUState *cs, vaddr value)
  32 {
  33     CRISCPU *cpu = CRIS_CPU(cs);
  34
  35     cpu->env.pc = value;
  36 }
  37
  38 static vaddr cris_cpu_get_pc(CPUState *cs)
  39 {
  40     CRISCPU *cpu = CRIS_CPU(cs);
  41
  42     return cpu->env.pc;
  43 }
  44
  45 static void cris_restore_state_to_opc(CPUState *cs,
  46                                       const TranslationBlock *tb,
  47                                       const uint64_t *data)
  48 {
  49     CRISCPU *cpu = CRIS_CPU(cs);
  50
  51     cpu->env.pc = data[0];
  52 }
  53
  54 static bool cris_cpu_has_work(CPUState *cs)
  55 {
  56     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
  57 }
  58
  59 static void cris_cpu_reset_hold(Object *obj)
  60 {
  61     CPUState *s = CPU(obj);
  62     CRISCPU *cpu = CRIS_CPU(s);
  63     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
  64     CPUCRISState *env = &cpu->env;
  65     uint32_t vr;
  66
  67     if (ccc->parent_phases.hold) {
  68         ccc->parent_phases.hold(obj);
  69     }
  70
  71     vr = env->pregs[PR_VR];
  72     memset(env, 0, offsetof(CPUCRISState, end_reset_fields));
  73     env->pregs[PR_VR] = vr;
  74
  75 #if defined(CONFIG_USER_ONLY)
  76     /* start in user mode with interrupts enabled.  */
  77     env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
  78 #else
  79     cris_mmu_init(env);
  80     env->pregs[PR_CCS] = 0;
  81 #endif
  82 }
  83
  84 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
  85 {
  86     ObjectClass *oc;
  87     char *typename;
  88
  89 #if defined(CONFIG_USER_ONLY)
  90     if (strcasecmp(cpu_model, "any") == 0) {
  91         return object_class_by_name(CRIS_CPU_TYPE_NAME("crisv32"));
  92     }
  93 #endif
  94
  95     typename = g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model);
  96     oc = object_class_by_name(typename);
  97     g_free(typename);
  98     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) ||
  99                        object_class_is_abstract(oc))) {
 100         oc = NULL;
 101     }
 102     return oc;
 103 }
 104
 105 /* Sort alphabetically by VR. */
 106 static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
 107 {
 108     CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a);
 109     CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b);
 110
 111     /*  */
 112     if (ccc_a->vr > ccc_b->vr) {
 113         return 1;
 114     } else if (ccc_a->vr < ccc_b->vr) {
 115         return -1;
 116     } else {
 117         return 0;
 118     }
 119 }
 120
 121 static void cris_cpu_list_entry(gpointer data, gpointer user_data)
 122 {
 123     ObjectClass *oc = data;
 124     const char *typename = object_class_get_name(oc);
 125     char *name;
 126
 127     name = g_strndup(typename, strlen(typename) - strlen(CRIS_CPU_TYPE_SUFFIX));
 128     qemu_printf("  %s\n", name);
 129     g_free(name);
 130 }
 131
 132 void cris_cpu_list(void)
 133 {
 134     GSList *list;
 135
 136     list = object_class_get_list(TYPE_CRIS_CPU, false);
 137     list = g_slist_sort(list, cris_cpu_list_compare);
 138     qemu_printf("Available CPUs:\n");
 139     g_slist_foreach(list, cris_cpu_list_entry, NULL);
 140     g_slist_free(list);
 141 }
 142
 143 static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
 144 {
 145     CPUState *cs = CPU(dev);
 146     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
 147     Error *local_err = NULL;
 148
 149     cpu_exec_realizefn(cs, &local_err);
 150     if (local_err != NULL) {
 151         error_propagate(errp, local_err);
 152         return;
 153     }
 154
 155     cpu_reset(cs);
 156     qemu_init_vcpu(cs);
 157
 158     ccc->parent_realize(dev, errp);
 159 }
 160
 161 #ifndef CONFIG_USER_ONLY
 162 static void cris_cpu_set_irq(void *opaque, int irq, int level)
 163 {
 164     CRISCPU *cpu = opaque;
 165     CPUState *cs = CPU(cpu);
 166     int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI;
 167
 168     if (irq == CRIS_CPU_IRQ) {
 169         /*
 170          * The PIC passes us the vector for the IRQ as the value it sends
 171          * over the qemu_irq line
 172          */
 173         cpu->env.interrupt_vector = level;
 174     }
 175
 176     if (level) {
 177         cpu_interrupt(cs, type);
 178     } else {
 179         cpu_reset_interrupt(cs, type);
 180     }
 181 }
 182 #endif
 183
 184 static void cris_disas_set_info(CPUState *cpu, disassemble_info *info)
 185 {
 186     CRISCPU *cc = CRIS_CPU(cpu);
 187     CPUCRISState *env = &cc->env;
 188
 189     if (env->pregs[PR_VR] != 32) {
 190         info->mach = bfd_mach_cris_v0_v10;
 191         info->print_insn = print_insn_crisv10;
 192     } else {
 193         info->mach = bfd_mach_cris_v32;
 194         info->print_insn = print_insn_crisv32;
 195     }
 196 }
 197
 198 static void cris_cpu_initfn(Object *obj)
 199 {
 200     CRISCPU *cpu = CRIS_CPU(obj);
 201     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
 202     CPUCRISState *env = &cpu->env;
 203
 204     cpu_set_cpustate_pointers(cpu);
 205
 206     env->pregs[PR_VR] = ccc->vr;
 207
 208 #ifndef CONFIG_USER_ONLY
 209     /* IRQ and NMI lines.  */
 210     qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2);
 211 #endif
 212 }
 213
 214 #ifndef CONFIG_USER_ONLY
 215 #include "hw/core/sysemu-cpu-ops.h"
 216
 217 static const struct SysemuCPUOps cris_sysemu_ops = {
 218     .get_phys_page_debug = cris_cpu_get_phys_page_debug,
 219 };
 220 #endif
 221
 222 #include "hw/core/tcg-cpu-ops.h"
 223
 224 static const struct TCGCPUOps crisv10_tcg_ops = {
 225     .initialize = cris_initialize_crisv10_tcg,
 226     .restore_state_to_opc = cris_restore_state_to_opc,
 227
 228 #ifndef CONFIG_USER_ONLY
 229     .tlb_fill = cris_cpu_tlb_fill,
 230     .cpu_exec_interrupt = cris_cpu_exec_interrupt,
 231     .do_interrupt = crisv10_cpu_do_interrupt,
 232 #endif /* !CONFIG_USER_ONLY */
 233 };
 234
 235 static const struct TCGCPUOps crisv32_tcg_ops = {
 236     .initialize = cris_initialize_tcg,
 237     .restore_state_to_opc = cris_restore_state_to_opc,
 238
 239 #ifndef CONFIG_USER_ONLY
 240     .tlb_fill = cris_cpu_tlb_fill,
 241     .cpu_exec_interrupt = cris_cpu_exec_interrupt,
 242     .do_interrupt = cris_cpu_do_interrupt,
 243 #endif /* !CONFIG_USER_ONLY */
 244 };
 245
 246 static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
 247 {
 248     CPUClass *cc = CPU_CLASS(oc);
 249     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 250
 251     ccc->vr = 8;
 252     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 253     cc->tcg_ops = &crisv10_tcg_ops;
 254 }
 255
 256 static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
 257 {
 258     CPUClass *cc = CPU_CLASS(oc);
 259     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 260
 261     ccc->vr = 9;
 262     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 263     cc->tcg_ops = &crisv10_tcg_ops;
 264 }
 265
 266 static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
 267 {
 268     CPUClass *cc = CPU_CLASS(oc);
 269     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 270
 271     ccc->vr = 10;
 272     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 273     cc->tcg_ops = &crisv10_tcg_ops;
 274 }
 275
 276 static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
 277 {
 278     CPUClass *cc = CPU_CLASS(oc);
 279     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 280
 281     ccc->vr = 11;
 282     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 283     cc->tcg_ops = &crisv10_tcg_ops;
 284 }
 285
 286 static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
 287 {
 288     CPUClass *cc = CPU_CLASS(oc);
 289     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 290
 291     ccc->vr = 17;
 292     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 293     cc->tcg_ops = &crisv10_tcg_ops;
 294 }
 295
 296 static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
 297 {
 298     CPUClass *cc = CPU_CLASS(oc);
 299     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 300
 301     ccc->vr = 32;
 302     cc->tcg_ops = &crisv32_tcg_ops;
 303 }
 304
 305 static void cris_cpu_class_init(ObjectClass *oc, void *data)
 306 {
 307     DeviceClass *dc = DEVICE_CLASS(oc);
 308     CPUClass *cc = CPU_CLASS(oc);
 309     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 310     ResettableClass *rc = RESETTABLE_CLASS(oc);
 311
 312     device_class_set_parent_realize(dc, cris_cpu_realizefn,
 313                                     &ccc->parent_realize);
 314
 315     resettable_class_set_parent_phases(rc, NULL, cris_cpu_reset_hold, NULL,
 316                                        &ccc->parent_phases);
 317
 318     cc->class_by_name = cris_cpu_class_by_name;
 319     cc->has_work = cris_cpu_has_work;
 320     cc->dump_state = cris_cpu_dump_state;
 321     cc->set_pc = cris_cpu_set_pc;
 322     cc->get_pc = cris_cpu_get_pc;
 323     cc->gdb_read_register = cris_cpu_gdb_read_register;
 324     cc->gdb_write_register = cris_cpu_gdb_write_register;
 325 #ifndef CONFIG_USER_ONLY
 326     dc->vmsd = &vmstate_cris_cpu;
 327     cc->sysemu_ops = &cris_sysemu_ops;
 328 #endif
 329
 330     cc->gdb_num_core_regs = 49;
 331     cc->gdb_stop_before_watchpoint = true;
 332
 333     cc->disas_set_info = cris_disas_set_info;
 334 }
 335
 336 #define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \
 337      {                                          \
 338          .parent = TYPE_CRIS_CPU,               \
 339          .class_init = initfn,                  \
 340          .name = CRIS_CPU_TYPE_NAME(cpu_model), \
 341      }
 342
 343 static const TypeInfo cris_cpu_model_type_infos[] = {
 344     {
 345         .name = TYPE_CRIS_CPU,
 346         .parent = TYPE_CPU,
 347         .instance_size = sizeof(CRISCPU),
 348         .instance_init = cris_cpu_initfn,
 349         .abstract = true,
 350         .class_size = sizeof(CRISCPUClass),
 351         .class_init = cris_cpu_class_init,
 352     },
 353     DEFINE_CRIS_CPU_TYPE("crisv8", crisv8_cpu_class_init),
 354     DEFINE_CRIS_CPU_TYPE("crisv9", crisv9_cpu_class_init),
 355     DEFINE_CRIS_CPU_TYPE("crisv10", crisv10_cpu_class_init),
 356     DEFINE_CRIS_CPU_TYPE("crisv11", crisv11_cpu_class_init),
 357     DEFINE_CRIS_CPU_TYPE("crisv17", crisv17_cpu_class_init),
 358     DEFINE_CRIS_CPU_TYPE("crisv32", crisv32_cpu_class_init),
 359 };
 360
 361 DEFINE_TYPES(cris_cpu_model_type_infos)